lsq_unit_impl.hh revision 2669
12292SN/A/* 22292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272292SN/A */ 282292SN/A 292316SN/A#include "cpu/checker/cpu.hh" 302292SN/A#include "cpu/o3/lsq_unit.hh" 312292SN/A#include "base/str.hh" 322669Sktlim@umich.edu#include "mem/request.hh" 332292SN/A 342669Sktlim@umich.edutemplate<class Impl> 352669Sktlim@umich.eduvoid 362669Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 372292SN/A{ 382669Sktlim@umich.edu/* 392669Sktlim@umich.edu DPRINTF(IEW, "Load writeback event [sn:%lli]\n", inst->seqNum); 402669Sktlim@umich.edu DPRINTF(Activity, "Activity: Ld Writeback event [sn:%lli]\n", inst->seqNum); 412669Sktlim@umich.edu 422669Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 432669Sktlim@umich.edu 442669Sktlim@umich.edu if (iewStage->isSwitchedOut()) { 452669Sktlim@umich.edu inst = NULL; 462669Sktlim@umich.edu return; 472669Sktlim@umich.edu } else if (inst->isSquashed()) { 482669Sktlim@umich.edu iewStage->wakeCPU(); 492669Sktlim@umich.edu inst = NULL; 502669Sktlim@umich.edu return; 512669Sktlim@umich.edu } 522669Sktlim@umich.edu 532669Sktlim@umich.edu iewStage->wakeCPU(); 542669Sktlim@umich.edu 552669Sktlim@umich.edu if (!inst->isExecuted()) { 562669Sktlim@umich.edu inst->setExecuted(); 572669Sktlim@umich.edu 582669Sktlim@umich.edu // Complete access to copy data to proper place. 592669Sktlim@umich.edu inst->completeAcc(); 602669Sktlim@umich.edu } 612669Sktlim@umich.edu 622669Sktlim@umich.edu // Need to insert instruction into queue to commit 632669Sktlim@umich.edu iewStage->instToCommit(inst); 642669Sktlim@umich.edu 652669Sktlim@umich.edu iewStage->activityThisCycle(); 662669Sktlim@umich.edu 672669Sktlim@umich.edu inst = NULL; 682669Sktlim@umich.edu*/ 692292SN/A} 702292SN/A 712669Sktlim@umich.edutemplate<class Impl> 722292SN/Avoid 732669Sktlim@umich.eduLSQUnit<Impl>::completeStoreDataAccess(DynInstPtr &inst) 742292SN/A{ 752669Sktlim@umich.edu/* 762292SN/A DPRINTF(LSQ, "Cache miss complete for store idx:%i\n", storeIdx); 772292SN/A DPRINTF(Activity, "Activity: st writeback event idx:%i\n", storeIdx); 782292SN/A 792292SN/A //lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum); 802292SN/A 812307SN/A if (lsqPtr->isSwitchedOut()) 822307SN/A return; 832307SN/A 842292SN/A lsqPtr->cpu->wakeCPU(); 852669Sktlim@umich.edu 862669Sktlim@umich.edu if (wb) 872669Sktlim@umich.edu lsqPtr->completeDataAccess(storeIdx); 882292SN/A lsqPtr->completeStore(storeIdx); 892669Sktlim@umich.edu*/ 902292SN/A} 912292SN/A 922292SN/Atemplate <class Impl> 932669Sktlim@umich.eduTick 942669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvAtomic(PacketPtr pkt) 952292SN/A{ 962669Sktlim@umich.edu panic("O3CPU model does not work with atomic mode!"); 972669Sktlim@umich.edu return curTick; 982669Sktlim@umich.edu} 992669Sktlim@umich.edu 1002669Sktlim@umich.edutemplate <class Impl> 1012669Sktlim@umich.eduvoid 1022669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvFunctional(PacketPtr pkt) 1032669Sktlim@umich.edu{ 1042669Sktlim@umich.edu panic("O3CPU doesn't expect recvFunctional callback!"); 1052669Sktlim@umich.edu} 1062669Sktlim@umich.edu 1072669Sktlim@umich.edutemplate <class Impl> 1082669Sktlim@umich.eduvoid 1092669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvStatusChange(Status status) 1102669Sktlim@umich.edu{ 1112669Sktlim@umich.edu if (status == RangeChange) 1122669Sktlim@umich.edu return; 1132669Sktlim@umich.edu 1142669Sktlim@umich.edu panic("O3CPU doesn't expect recvStatusChange callback!"); 1152669Sktlim@umich.edu} 1162669Sktlim@umich.edu 1172669Sktlim@umich.edutemplate <class Impl> 1182669Sktlim@umich.edubool 1192669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvTiming(PacketPtr pkt) 1202669Sktlim@umich.edu{ 1212669Sktlim@umich.edu lsq->completeDataAccess(pkt); 1222669Sktlim@umich.edu return true; 1232669Sktlim@umich.edu} 1242669Sktlim@umich.edu 1252669Sktlim@umich.edutemplate <class Impl> 1262669Sktlim@umich.eduvoid 1272669Sktlim@umich.eduLSQUnit<Impl>::DcachePort::recvRetry() 1282669Sktlim@umich.edu{ 1292669Sktlim@umich.edu panic("Retry unsupported for now!"); 1302669Sktlim@umich.edu // we shouldn't get a retry unless we have a packet that we're 1312669Sktlim@umich.edu // waiting to transmit 1322669Sktlim@umich.edu/* 1332669Sktlim@umich.edu assert(cpu->dcache_pkt != NULL); 1342669Sktlim@umich.edu assert(cpu->_status == DcacheRetry); 1352669Sktlim@umich.edu PacketPtr tmp = cpu->dcache_pkt; 1362669Sktlim@umich.edu if (sendTiming(tmp)) { 1372669Sktlim@umich.edu cpu->_status = DcacheWaitResponse; 1382669Sktlim@umich.edu cpu->dcache_pkt = NULL; 1392669Sktlim@umich.edu } 1402669Sktlim@umich.edu*/ 1412292SN/A} 1422292SN/A 1432292SN/Atemplate <class Impl> 1442292SN/ALSQUnit<Impl>::LSQUnit() 1452292SN/A : loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false), 1462292SN/A loadBlockedHandled(false) 1472292SN/A{ 1482292SN/A} 1492292SN/A 1502292SN/Atemplate<class Impl> 1512292SN/Avoid 1522292SN/ALSQUnit<Impl>::init(Params *params, unsigned maxLQEntries, 1532292SN/A unsigned maxSQEntries, unsigned id) 1542292SN/A{ 1552292SN/A DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1562292SN/A 1572307SN/A switchedOut = false; 1582307SN/A 1592292SN/A lsqID = id; 1602292SN/A 1612329SN/A // Add 1 for the sentinel entry (they are circular queues). 1622329SN/A LQEntries = maxLQEntries + 1; 1632329SN/A SQEntries = maxSQEntries + 1; 1642292SN/A 1652292SN/A loadQueue.resize(LQEntries); 1662292SN/A storeQueue.resize(SQEntries); 1672292SN/A 1682292SN/A loadHead = loadTail = 0; 1692292SN/A 1702292SN/A storeHead = storeWBIdx = storeTail = 0; 1712292SN/A 1722292SN/A usedPorts = 0; 1732292SN/A cachePorts = params->cachePorts; 1742292SN/A 1752669Sktlim@umich.edu Port *mem_dport = params->mem->getPort(""); 1762669Sktlim@umich.edu dcachePort->setPeer(mem_dport); 1772669Sktlim@umich.edu mem_dport->setPeer(dcachePort); 1782292SN/A 1792329SN/A memDepViolator = NULL; 1802292SN/A 1812292SN/A blockedLoadSeqNum = 0; 1822292SN/A} 1832292SN/A 1842292SN/Atemplate<class Impl> 1852669Sktlim@umich.eduvoid 1862669Sktlim@umich.eduLSQUnit<Impl>::setCPU(FullCPU *cpu_ptr) 1872669Sktlim@umich.edu{ 1882669Sktlim@umich.edu cpu = cpu_ptr; 1892669Sktlim@umich.edu dcachePort = new DcachePort(cpu, this); 1902669Sktlim@umich.edu} 1912669Sktlim@umich.edu 1922669Sktlim@umich.edutemplate<class Impl> 1932292SN/Astd::string 1942292SN/ALSQUnit<Impl>::name() const 1952292SN/A{ 1962292SN/A if (Impl::MaxThreads == 1) { 1972292SN/A return iewStage->name() + ".lsq"; 1982292SN/A } else { 1992292SN/A return iewStage->name() + ".lsq.thread." + to_string(lsqID); 2002292SN/A } 2012292SN/A} 2022292SN/A 2032292SN/Atemplate<class Impl> 2042292SN/Avoid 2052292SN/ALSQUnit<Impl>::clearLQ() 2062292SN/A{ 2072292SN/A loadQueue.clear(); 2082292SN/A} 2092292SN/A 2102292SN/Atemplate<class Impl> 2112292SN/Avoid 2122292SN/ALSQUnit<Impl>::clearSQ() 2132292SN/A{ 2142292SN/A storeQueue.clear(); 2152292SN/A} 2162292SN/A 2172292SN/A#if 0 2182292SN/Atemplate<class Impl> 2192292SN/Avoid 2202292SN/ALSQUnit<Impl>::setPageTable(PageTable *pt_ptr) 2212292SN/A{ 2222292SN/A DPRINTF(LSQUnit, "Setting the page table pointer.\n"); 2232292SN/A pTable = pt_ptr; 2242292SN/A} 2252292SN/A#endif 2262292SN/A 2272292SN/Atemplate<class Impl> 2282292SN/Avoid 2292307SN/ALSQUnit<Impl>::switchOut() 2302307SN/A{ 2312307SN/A switchedOut = true; 2322307SN/A for (int i = 0; i < loadQueue.size(); ++i) 2332307SN/A loadQueue[i] = NULL; 2342307SN/A 2352329SN/A assert(storesToWB == 0); 2362307SN/A} 2372307SN/A 2382307SN/Atemplate<class Impl> 2392307SN/Avoid 2402307SN/ALSQUnit<Impl>::takeOverFrom() 2412307SN/A{ 2422307SN/A switchedOut = false; 2432307SN/A loads = stores = storesToWB = 0; 2442307SN/A 2452307SN/A loadHead = loadTail = 0; 2462307SN/A 2472307SN/A storeHead = storeWBIdx = storeTail = 0; 2482307SN/A 2492307SN/A usedPorts = 0; 2502307SN/A 2512329SN/A memDepViolator = NULL; 2522307SN/A 2532307SN/A blockedLoadSeqNum = 0; 2542307SN/A 2552307SN/A stalled = false; 2562307SN/A isLoadBlocked = false; 2572307SN/A loadBlockedHandled = false; 2582307SN/A} 2592307SN/A 2602307SN/Atemplate<class Impl> 2612307SN/Avoid 2622292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 2632292SN/A{ 2642329SN/A unsigned size_plus_sentinel = size + 1; 2652329SN/A assert(size_plus_sentinel >= LQEntries); 2662292SN/A 2672329SN/A if (size_plus_sentinel > LQEntries) { 2682329SN/A while (size_plus_sentinel > loadQueue.size()) { 2692292SN/A DynInstPtr dummy; 2702292SN/A loadQueue.push_back(dummy); 2712292SN/A LQEntries++; 2722292SN/A } 2732292SN/A } else { 2742329SN/A LQEntries = size_plus_sentinel; 2752292SN/A } 2762292SN/A 2772292SN/A} 2782292SN/A 2792292SN/Atemplate<class Impl> 2802292SN/Avoid 2812292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 2822292SN/A{ 2832329SN/A unsigned size_plus_sentinel = size + 1; 2842329SN/A if (size_plus_sentinel > SQEntries) { 2852329SN/A while (size_plus_sentinel > storeQueue.size()) { 2862292SN/A SQEntry dummy; 2872292SN/A storeQueue.push_back(dummy); 2882292SN/A SQEntries++; 2892292SN/A } 2902292SN/A } else { 2912329SN/A SQEntries = size_plus_sentinel; 2922292SN/A } 2932292SN/A} 2942292SN/A 2952292SN/Atemplate <class Impl> 2962292SN/Avoid 2972292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 2982292SN/A{ 2992292SN/A assert(inst->isMemRef()); 3002292SN/A 3012292SN/A assert(inst->isLoad() || inst->isStore()); 3022292SN/A 3032292SN/A if (inst->isLoad()) { 3042292SN/A insertLoad(inst); 3052292SN/A } else { 3062292SN/A insertStore(inst); 3072292SN/A } 3082292SN/A 3092292SN/A inst->setInLSQ(); 3102292SN/A} 3112292SN/A 3122292SN/Atemplate <class Impl> 3132292SN/Avoid 3142292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3152292SN/A{ 3162329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3172329SN/A assert(loads < LQEntries); 3182292SN/A 3192292SN/A DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n", 3202292SN/A load_inst->readPC(), loadTail, load_inst->seqNum); 3212292SN/A 3222292SN/A load_inst->lqIdx = loadTail; 3232292SN/A 3242292SN/A if (stores == 0) { 3252292SN/A load_inst->sqIdx = -1; 3262292SN/A } else { 3272292SN/A load_inst->sqIdx = storeTail; 3282292SN/A } 3292292SN/A 3302292SN/A loadQueue[loadTail] = load_inst; 3312292SN/A 3322292SN/A incrLdIdx(loadTail); 3332292SN/A 3342292SN/A ++loads; 3352292SN/A} 3362292SN/A 3372292SN/Atemplate <class Impl> 3382292SN/Avoid 3392292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3402292SN/A{ 3412292SN/A // Make sure it is not full before inserting an instruction. 3422292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3432292SN/A assert(stores < SQEntries); 3442292SN/A 3452292SN/A DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n", 3462292SN/A store_inst->readPC(), storeTail, store_inst->seqNum); 3472292SN/A 3482292SN/A store_inst->sqIdx = storeTail; 3492292SN/A store_inst->lqIdx = loadTail; 3502292SN/A 3512292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3522292SN/A 3532292SN/A incrStIdx(storeTail); 3542292SN/A 3552292SN/A ++stores; 3562292SN/A} 3572292SN/A 3582292SN/Atemplate <class Impl> 3592292SN/Atypename Impl::DynInstPtr 3602292SN/ALSQUnit<Impl>::getMemDepViolator() 3612292SN/A{ 3622292SN/A DynInstPtr temp = memDepViolator; 3632292SN/A 3642292SN/A memDepViolator = NULL; 3652292SN/A 3662292SN/A return temp; 3672292SN/A} 3682292SN/A 3692292SN/Atemplate <class Impl> 3702292SN/Aunsigned 3712292SN/ALSQUnit<Impl>::numFreeEntries() 3722292SN/A{ 3732292SN/A unsigned free_lq_entries = LQEntries - loads; 3742292SN/A unsigned free_sq_entries = SQEntries - stores; 3752292SN/A 3762292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 3772292SN/A // empty/full conditions. Subtract 1 from the free entries. 3782292SN/A if (free_lq_entries < free_sq_entries) { 3792292SN/A return free_lq_entries - 1; 3802292SN/A } else { 3812292SN/A return free_sq_entries - 1; 3822292SN/A } 3832292SN/A} 3842292SN/A 3852292SN/Atemplate <class Impl> 3862292SN/Aint 3872292SN/ALSQUnit<Impl>::numLoadsReady() 3882292SN/A{ 3892292SN/A int load_idx = loadHead; 3902292SN/A int retval = 0; 3912292SN/A 3922292SN/A while (load_idx != loadTail) { 3932292SN/A assert(loadQueue[load_idx]); 3942292SN/A 3952292SN/A if (loadQueue[load_idx]->readyToIssue()) { 3962292SN/A ++retval; 3972292SN/A } 3982292SN/A } 3992292SN/A 4002292SN/A return retval; 4012292SN/A} 4022292SN/A 4032292SN/Atemplate <class Impl> 4042292SN/AFault 4052292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 4062292SN/A{ 4072292SN/A // Execute a specific load. 4082292SN/A Fault load_fault = NoFault; 4092292SN/A 4102292SN/A DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n", 4112292SN/A inst->readPC(),inst->seqNum); 4122292SN/A 4132669Sktlim@umich.edu load_fault = inst->initiateAcc(); 4142292SN/A 4152292SN/A // If the instruction faulted, then we need to send it along to commit 4162292SN/A // without the instruction completing. 4172292SN/A if (load_fault != NoFault) { 4182329SN/A // Send this instruction to commit, also make sure iew stage 4192329SN/A // realizes there is activity. 4202292SN/A iewStage->instToCommit(inst); 4212292SN/A iewStage->activityThisCycle(); 4222292SN/A } 4232292SN/A 4242292SN/A return load_fault; 4252292SN/A} 4262292SN/A 4272292SN/Atemplate <class Impl> 4282292SN/AFault 4292292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 4302292SN/A{ 4312292SN/A using namespace TheISA; 4322292SN/A // Make sure that a store exists. 4332292SN/A assert(stores != 0); 4342292SN/A 4352292SN/A int store_idx = store_inst->sqIdx; 4362292SN/A 4372292SN/A DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n", 4382292SN/A store_inst->readPC(), store_inst->seqNum); 4392292SN/A 4402292SN/A // Check the recently completed loads to see if any match this store's 4412292SN/A // address. If so, then we have a memory ordering violation. 4422292SN/A int load_idx = store_inst->lqIdx; 4432292SN/A 4442292SN/A Fault store_fault = store_inst->initiateAcc(); 4452292SN/A// Fault store_fault = store_inst->execute(); 4462292SN/A 4472329SN/A if (storeQueue[store_idx].size == 0) { 4482292SN/A DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n", 4492292SN/A store_inst->readPC(),store_inst->seqNum); 4502292SN/A 4512292SN/A return store_fault; 4522292SN/A } 4532292SN/A 4542292SN/A assert(store_fault == NoFault); 4552292SN/A 4562336SN/A if (store_inst->isStoreConditional()) { 4572336SN/A // Store conditionals need to set themselves as able to 4582336SN/A // writeback if we haven't had a fault by here. 4592329SN/A storeQueue[store_idx].canWB = true; 4602292SN/A 4612329SN/A ++storesToWB; 4622292SN/A } 4632292SN/A 4642292SN/A if (!memDepViolator) { 4652292SN/A while (load_idx != loadTail) { 4662329SN/A // Really only need to check loads that have actually executed 4672329SN/A // It's safe to check all loads because effAddr is set to 4682329SN/A // InvalAddr when the dyn inst is created. 4692292SN/A 4702329SN/A // @todo: For now this is extra conservative, detecting a 4712329SN/A // violation if the addresses match assuming all accesses 4722329SN/A // are quad word accesses. 4732329SN/A 4742292SN/A // @todo: Fix this, magic number being used here 4752292SN/A if ((loadQueue[load_idx]->effAddr >> 8) == 4762292SN/A (store_inst->effAddr >> 8)) { 4772292SN/A // A load incorrectly passed this store. Squash and refetch. 4782292SN/A // For now return a fault to show that it was unsuccessful. 4792292SN/A memDepViolator = loadQueue[load_idx]; 4802292SN/A 4812292SN/A return genMachineCheckFault(); 4822292SN/A } 4832292SN/A 4842292SN/A incrLdIdx(load_idx); 4852292SN/A } 4862292SN/A 4872292SN/A // If we've reached this point, there was no violation. 4882292SN/A memDepViolator = NULL; 4892292SN/A } 4902292SN/A 4912292SN/A return store_fault; 4922292SN/A} 4932292SN/A 4942292SN/Atemplate <class Impl> 4952292SN/Avoid 4962292SN/ALSQUnit<Impl>::commitLoad() 4972292SN/A{ 4982292SN/A assert(loadQueue[loadHead]); 4992292SN/A 5002292SN/A DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n", 5012292SN/A loadQueue[loadHead]->readPC()); 5022292SN/A 5032292SN/A 5042292SN/A loadQueue[loadHead] = NULL; 5052292SN/A 5062292SN/A incrLdIdx(loadHead); 5072292SN/A 5082292SN/A --loads; 5092292SN/A} 5102292SN/A 5112292SN/Atemplate <class Impl> 5122292SN/Avoid 5132292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 5142292SN/A{ 5152292SN/A assert(loads == 0 || loadQueue[loadHead]); 5162292SN/A 5172292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 5182292SN/A commitLoad(); 5192292SN/A } 5202292SN/A} 5212292SN/A 5222292SN/Atemplate <class Impl> 5232292SN/Avoid 5242292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 5252292SN/A{ 5262292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 5272292SN/A 5282292SN/A int store_idx = storeHead; 5292292SN/A 5302292SN/A while (store_idx != storeTail) { 5312292SN/A assert(storeQueue[store_idx].inst); 5322329SN/A // Mark any stores that are now committed and have not yet 5332329SN/A // been marked as able to write back. 5342292SN/A if (!storeQueue[store_idx].canWB) { 5352292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 5362292SN/A break; 5372292SN/A } 5382292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 5392292SN/A "%#x [sn:%lli]\n", 5402292SN/A storeQueue[store_idx].inst->readPC(), 5412292SN/A storeQueue[store_idx].inst->seqNum); 5422292SN/A 5432292SN/A storeQueue[store_idx].canWB = true; 5442292SN/A 5452292SN/A ++storesToWB; 5462292SN/A } 5472292SN/A 5482292SN/A incrStIdx(store_idx); 5492292SN/A } 5502292SN/A} 5512292SN/A 5522292SN/Atemplate <class Impl> 5532292SN/Avoid 5542292SN/ALSQUnit<Impl>::writebackStores() 5552292SN/A{ 5562292SN/A while (storesToWB > 0 && 5572292SN/A storeWBIdx != storeTail && 5582292SN/A storeQueue[storeWBIdx].inst && 5592292SN/A storeQueue[storeWBIdx].canWB && 5602292SN/A usedPorts < cachePorts) { 5612292SN/A 5622329SN/A // Store didn't write any data so no need to write it back to 5632329SN/A // memory. 5642292SN/A if (storeQueue[storeWBIdx].size == 0) { 5652292SN/A completeStore(storeWBIdx); 5662292SN/A 5672292SN/A incrStIdx(storeWBIdx); 5682292SN/A 5692292SN/A continue; 5702292SN/A } 5712669Sktlim@umich.edu/* 5722292SN/A if (dcacheInterface && dcacheInterface->isBlocked()) { 5732292SN/A DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 5742292SN/A " is blocked!\n"); 5752292SN/A break; 5762292SN/A } 5772669Sktlim@umich.edu*/ 5782292SN/A ++usedPorts; 5792292SN/A 5802292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 5812292SN/A incrStIdx(storeWBIdx); 5822292SN/A 5832292SN/A continue; 5842292SN/A } 5852292SN/A 5862292SN/A assert(storeQueue[storeWBIdx].req); 5872292SN/A assert(!storeQueue[storeWBIdx].committed); 5882292SN/A 5892669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 5902669Sktlim@umich.edu 5912669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 5922292SN/A storeQueue[storeWBIdx].committed = true; 5932292SN/A 5942669Sktlim@umich.edu assert(!inst->memData); 5952669Sktlim@umich.edu inst->memData = new uint8_t[64]; 5962669Sktlim@umich.edu memcpy(inst->memData, (uint8_t *)&storeQueue[storeWBIdx].data, req->getSize()); 5972669Sktlim@umich.edu 5982669Sktlim@umich.edu PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 5992669Sktlim@umich.edu data_pkt->dataStatic(inst->memData); 6002292SN/A 6012292SN/A DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x " 6022292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 6032669Sktlim@umich.edu storeWBIdx, storeQueue[storeWBIdx].inst->readPC(), 6042669Sktlim@umich.edu req->getPaddr(), *(inst->memData), 6052292SN/A storeQueue[storeWBIdx].inst->seqNum); 6062292SN/A 6072669Sktlim@umich.edu if (!dcachePort->sendTiming(data_pkt)) { 6082669Sktlim@umich.edu // Need to handle becoming blocked on a store. 6092669Sktlim@umich.edu } else { 6102669Sktlim@umich.edu /* 6112310SN/A StoreCompletionEvent *store_event = new 6122310SN/A StoreCompletionEvent(storeWBIdx, NULL, this); 6132669Sktlim@umich.edu */ 6142292SN/A if (isStalled() && 6152292SN/A storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 6162292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 6172292SN/A "load idx:%i\n", 6182292SN/A stallingStoreIsn, stallingLoadIdx); 6192292SN/A stalled = false; 6202292SN/A stallingStoreIsn = 0; 6212292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 6222292SN/A } 6232669Sktlim@umich.edu/* 6242669Sktlim@umich.edu typename LdWritebackEvent *wb = NULL; 6252329SN/A if (req->flags & LOCKED) { 6262329SN/A // Stx_C should not generate a system port transaction 6272329SN/A // if it misses in the cache, but that might be hard 6282329SN/A // to accomplish without explicit cache support. 6292329SN/A wb = new typename 6302669Sktlim@umich.edu LdWritebackEvent(storeQueue[storeWBIdx].inst, 6312669Sktlim@umich.edu iewStage); 6322329SN/A store_event->wbEvent = wb; 6332329SN/A } 6342669Sktlim@umich.edu*/ 6352669Sktlim@umich.edu if (data_pkt->result != Packet::Success) { 6362329SN/A DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n", 6372329SN/A storeWBIdx); 6382292SN/A 6392292SN/A DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n", 6402292SN/A storeQueue[storeWBIdx].inst->seqNum); 6412292SN/A 6422292SN/A //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum); 6432292SN/A 6442292SN/A //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size()); 6452292SN/A 6462329SN/A // @todo: Increment stat here. 6472292SN/A } else { 6482292SN/A DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n", 6492292SN/A storeWBIdx); 6502292SN/A 6512292SN/A DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n", 6522292SN/A storeQueue[storeWBIdx].inst->seqNum); 6532292SN/A } 6542292SN/A 6552292SN/A incrStIdx(storeWBIdx); 6562292SN/A } 6572292SN/A } 6582292SN/A 6592292SN/A // Not sure this should set it to 0. 6602292SN/A usedPorts = 0; 6612292SN/A 6622292SN/A assert(stores >= 0 && storesToWB >= 0); 6632292SN/A} 6642292SN/A 6652292SN/A/*template <class Impl> 6662292SN/Avoid 6672292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 6682292SN/A{ 6692292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 6702292SN/A mshrSeqNums.end(), 6712292SN/A seqNum); 6722292SN/A 6732292SN/A if (mshr_it != mshrSeqNums.end()) { 6742292SN/A mshrSeqNums.erase(mshr_it); 6752292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 6762292SN/A } 6772292SN/A}*/ 6782292SN/A 6792292SN/Atemplate <class Impl> 6802292SN/Avoid 6812292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 6822292SN/A{ 6832292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 6842329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 6852292SN/A 6862292SN/A int load_idx = loadTail; 6872292SN/A decrLdIdx(load_idx); 6882292SN/A 6892292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 6902292SN/A DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, " 6912292SN/A "[sn:%lli]\n", 6922292SN/A loadQueue[load_idx]->readPC(), 6932292SN/A loadQueue[load_idx]->seqNum); 6942292SN/A 6952292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 6962292SN/A stalled = false; 6972292SN/A stallingStoreIsn = 0; 6982292SN/A stallingLoadIdx = 0; 6992292SN/A } 7002292SN/A 7012329SN/A // Clear the smart pointer to make sure it is decremented. 7022292SN/A loadQueue[load_idx]->squashed = true; 7032292SN/A loadQueue[load_idx] = NULL; 7042292SN/A --loads; 7052292SN/A 7062292SN/A // Inefficient! 7072292SN/A loadTail = load_idx; 7082292SN/A 7092292SN/A decrLdIdx(load_idx); 7102292SN/A } 7112292SN/A 7122292SN/A if (isLoadBlocked) { 7132292SN/A if (squashed_num < blockedLoadSeqNum) { 7142292SN/A isLoadBlocked = false; 7152292SN/A loadBlockedHandled = false; 7162292SN/A blockedLoadSeqNum = 0; 7172292SN/A } 7182292SN/A } 7192292SN/A 7202292SN/A int store_idx = storeTail; 7212292SN/A decrStIdx(store_idx); 7222292SN/A 7232292SN/A while (stores != 0 && 7242292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 7252329SN/A // Instructions marked as can WB are already committed. 7262292SN/A if (storeQueue[store_idx].canWB) { 7272292SN/A break; 7282292SN/A } 7292292SN/A 7302292SN/A DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, " 7312292SN/A "idx:%i [sn:%lli]\n", 7322292SN/A storeQueue[store_idx].inst->readPC(), 7332292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 7342292SN/A 7352329SN/A // I don't think this can happen. It should have been cleared 7362329SN/A // by the stalling load. 7372292SN/A if (isStalled() && 7382292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 7392292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 7402292SN/A stalled = false; 7412292SN/A stallingStoreIsn = 0; 7422292SN/A } 7432292SN/A 7442329SN/A // Clear the smart pointer to make sure it is decremented. 7452292SN/A storeQueue[store_idx].inst->squashed = true; 7462292SN/A storeQueue[store_idx].inst = NULL; 7472292SN/A storeQueue[store_idx].canWB = 0; 7482292SN/A 7492292SN/A storeQueue[store_idx].req = NULL; 7502292SN/A --stores; 7512292SN/A 7522292SN/A // Inefficient! 7532292SN/A storeTail = store_idx; 7542292SN/A 7552292SN/A decrStIdx(store_idx); 7562292SN/A } 7572292SN/A} 7582292SN/A 7592292SN/Atemplate <class Impl> 7602292SN/Avoid 7612292SN/ALSQUnit<Impl>::completeStore(int store_idx) 7622292SN/A{ 7632292SN/A assert(storeQueue[store_idx].inst); 7642292SN/A storeQueue[store_idx].completed = true; 7652292SN/A --storesToWB; 7662292SN/A // A bit conservative because a store completion may not free up entries, 7672292SN/A // but hopefully avoids two store completions in one cycle from making 7682292SN/A // the CPU tick twice. 7692292SN/A cpu->activityThisCycle(); 7702292SN/A 7712292SN/A if (store_idx == storeHead) { 7722292SN/A do { 7732292SN/A incrStIdx(storeHead); 7742292SN/A 7752292SN/A --stores; 7762292SN/A } while (storeQueue[storeHead].completed && 7772292SN/A storeHead != storeTail); 7782292SN/A 7792292SN/A iewStage->updateLSQNextCycle = true; 7802292SN/A } 7812292SN/A 7822329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 7832329SN/A "idx:%i\n", 7842329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 7852292SN/A 7862292SN/A if (isStalled() && 7872292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 7882292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 7892292SN/A "load idx:%i\n", 7902292SN/A stallingStoreIsn, stallingLoadIdx); 7912292SN/A stalled = false; 7922292SN/A stallingStoreIsn = 0; 7932292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 7942292SN/A } 7952316SN/A 7962316SN/A storeQueue[store_idx].inst->setCompleted(); 7972329SN/A 7982329SN/A // Tell the checker we've completed this instruction. Some stores 7992329SN/A // may get reported twice to the checker, but the checker can 8002329SN/A // handle that case. 8012316SN/A if (cpu->checker) { 8022316SN/A cpu->checker->tick(storeQueue[store_idx].inst); 8032316SN/A } 8042292SN/A} 8052292SN/A 8062292SN/Atemplate <class Impl> 8072292SN/Ainline void 8082292SN/ALSQUnit<Impl>::incrStIdx(int &store_idx) 8092292SN/A{ 8102292SN/A if (++store_idx >= SQEntries) 8112292SN/A store_idx = 0; 8122292SN/A} 8132292SN/A 8142292SN/Atemplate <class Impl> 8152292SN/Ainline void 8162292SN/ALSQUnit<Impl>::decrStIdx(int &store_idx) 8172292SN/A{ 8182292SN/A if (--store_idx < 0) 8192292SN/A store_idx += SQEntries; 8202292SN/A} 8212292SN/A 8222292SN/Atemplate <class Impl> 8232292SN/Ainline void 8242292SN/ALSQUnit<Impl>::incrLdIdx(int &load_idx) 8252292SN/A{ 8262292SN/A if (++load_idx >= LQEntries) 8272292SN/A load_idx = 0; 8282292SN/A} 8292292SN/A 8302292SN/Atemplate <class Impl> 8312292SN/Ainline void 8322292SN/ALSQUnit<Impl>::decrLdIdx(int &load_idx) 8332292SN/A{ 8342292SN/A if (--load_idx < 0) 8352292SN/A load_idx += LQEntries; 8362292SN/A} 8372329SN/A 8382329SN/Atemplate <class Impl> 8392329SN/Avoid 8402329SN/ALSQUnit<Impl>::dumpInsts() 8412329SN/A{ 8422329SN/A cprintf("Load store queue: Dumping instructions.\n"); 8432329SN/A cprintf("Load queue size: %i\n", loads); 8442329SN/A cprintf("Load queue: "); 8452329SN/A 8462329SN/A int load_idx = loadHead; 8472329SN/A 8482329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 8492329SN/A cprintf("%#x ", loadQueue[load_idx]->readPC()); 8502329SN/A 8512329SN/A incrLdIdx(load_idx); 8522329SN/A } 8532329SN/A 8542329SN/A cprintf("Store queue size: %i\n", stores); 8552329SN/A cprintf("Store queue: "); 8562329SN/A 8572329SN/A int store_idx = storeHead; 8582329SN/A 8592329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 8602329SN/A cprintf("%#x ", storeQueue[store_idx].inst->readPC()); 8612329SN/A 8622329SN/A incrStIdx(store_idx); 8632329SN/A } 8642329SN/A 8652329SN/A cprintf("\n"); 8662329SN/A} 867