lsq_unit_impl.hh revision 2344 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#include "cpu/checker/cpu.hh"
30#include "cpu/o3/lsq_unit.hh"
31#include "base/str.hh"
32
33template <class Impl>
34LSQUnit<Impl>::StoreCompletionEvent::StoreCompletionEvent(int store_idx,
35                                                          Event *wb_event,
36                                                          LSQUnit<Impl> *lsq_ptr)
37    : Event(&mainEventQueue),
38      wbEvent(wb_event),
39      storeIdx(store_idx),
40      lsqPtr(lsq_ptr)
41{
42    this->setFlags(Event::AutoDelete);
43}
44
45template <class Impl>
46void
47LSQUnit<Impl>::StoreCompletionEvent::process()
48{
49    DPRINTF(LSQ, "Cache miss complete for store idx:%i\n", storeIdx);
50    DPRINTF(Activity, "Activity: st writeback event idx:%i\n", storeIdx);
51
52    //lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum);
53
54    if (lsqPtr->isSwitchedOut()) {
55        if (wbEvent)
56            delete wbEvent;
57
58        return;
59    }
60
61    lsqPtr->cpu->wakeCPU();
62    if (wbEvent) {
63        wbEvent->process();
64        delete wbEvent;
65    }
66    lsqPtr->completeStore(storeIdx);
67}
68
69template <class Impl>
70const char *
71LSQUnit<Impl>::StoreCompletionEvent::description()
72{
73    return "LSQ store completion event";
74}
75
76template <class Impl>
77LSQUnit<Impl>::LSQUnit()
78    : loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false),
79      loadBlockedHandled(false)
80{
81}
82
83template<class Impl>
84void
85LSQUnit<Impl>::init(Params *params, unsigned maxLQEntries,
86                    unsigned maxSQEntries, unsigned id)
87
88{
89    DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id);
90
91    switchedOut = false;
92
93    lsqID = id;
94
95    // Add 1 for the sentinel entry (they are circular queues).
96    LQEntries = maxLQEntries + 1;
97    SQEntries = maxSQEntries + 1;
98
99    loadQueue.resize(LQEntries);
100    storeQueue.resize(SQEntries);
101
102    loadHead = loadTail = 0;
103
104    storeHead = storeWBIdx = storeTail = 0;
105
106    usedPorts = 0;
107    cachePorts = params->cachePorts;
108
109    dcacheInterface = params->dcacheInterface;
110
111    memDepViolator = NULL;
112
113    blockedLoadSeqNum = 0;
114}
115
116template<class Impl>
117std::string
118LSQUnit<Impl>::name() const
119{
120    if (Impl::MaxThreads == 1) {
121        return iewStage->name() + ".lsq";
122    } else {
123        return iewStage->name() + ".lsq.thread." + to_string(lsqID);
124    }
125}
126
127template<class Impl>
128void
129LSQUnit<Impl>::clearLQ()
130{
131    loadQueue.clear();
132}
133
134template<class Impl>
135void
136LSQUnit<Impl>::clearSQ()
137{
138    storeQueue.clear();
139}
140
141#if 0
142template<class Impl>
143void
144LSQUnit<Impl>::setPageTable(PageTable *pt_ptr)
145{
146    DPRINTF(LSQUnit, "Setting the page table pointer.\n");
147    pTable = pt_ptr;
148}
149#endif
150
151template<class Impl>
152void
153LSQUnit<Impl>::switchOut()
154{
155    switchedOut = true;
156    for (int i = 0; i < loadQueue.size(); ++i)
157        loadQueue[i] = NULL;
158
159    assert(storesToWB == 0);
160
161    while (storesToWB > 0 &&
162           storeWBIdx != storeTail &&
163           storeQueue[storeWBIdx].inst &&
164           storeQueue[storeWBIdx].canWB) {
165
166        if (storeQueue[storeWBIdx].size == 0 ||
167            storeQueue[storeWBIdx].inst->isDataPrefetch() ||
168            storeQueue[storeWBIdx].committed ||
169            storeQueue[storeWBIdx].req->flags & LOCKED) {
170            incrStIdx(storeWBIdx);
171
172            continue;
173        }
174
175        assert(storeQueue[storeWBIdx].req);
176        assert(!storeQueue[storeWBIdx].committed);
177
178        MemReqPtr req = storeQueue[storeWBIdx].req;
179        storeQueue[storeWBIdx].committed = true;
180
181        req->cmd = Write;
182        req->completionEvent = NULL;
183        req->time = curTick;
184        assert(!req->data);
185        req->data = new uint8_t[64];
186        memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
187
188        DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
189                "to Addr:%#x, data:%#x [sn:%lli]\n",
190                storeWBIdx,storeQueue[storeWBIdx].inst->readPC(),
191                req->paddr, *(req->data),
192                storeQueue[storeWBIdx].inst->seqNum);
193
194        switch(storeQueue[storeWBIdx].size) {
195          case 1:
196            cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data);
197            break;
198          case 2:
199            cpu->write(req, (uint16_t &)storeQueue[storeWBIdx].data);
200            break;
201          case 4:
202            cpu->write(req, (uint32_t &)storeQueue[storeWBIdx].data);
203            break;
204          case 8:
205            cpu->write(req, (uint64_t &)storeQueue[storeWBIdx].data);
206            break;
207          default:
208            panic("Unexpected store size!\n");
209        }
210        incrStIdx(storeWBIdx);
211    }
212}
213
214template<class Impl>
215void
216LSQUnit<Impl>::takeOverFrom()
217{
218    switchedOut = false;
219    loads = stores = storesToWB = 0;
220
221    loadHead = loadTail = 0;
222
223    storeHead = storeWBIdx = storeTail = 0;
224
225    usedPorts = 0;
226
227    memDepViolator = NULL;
228
229    blockedLoadSeqNum = 0;
230
231    stalled = false;
232    isLoadBlocked = false;
233    loadBlockedHandled = false;
234}
235
236template<class Impl>
237void
238LSQUnit<Impl>::resizeLQ(unsigned size)
239{
240    unsigned size_plus_sentinel = size + 1;
241    assert(size_plus_sentinel >= LQEntries);
242
243    if (size_plus_sentinel > LQEntries) {
244        while (size_plus_sentinel > loadQueue.size()) {
245            DynInstPtr dummy;
246            loadQueue.push_back(dummy);
247            LQEntries++;
248        }
249    } else {
250        LQEntries = size_plus_sentinel;
251    }
252
253}
254
255template<class Impl>
256void
257LSQUnit<Impl>::resizeSQ(unsigned size)
258{
259    unsigned size_plus_sentinel = size + 1;
260    if (size_plus_sentinel > SQEntries) {
261        while (size_plus_sentinel > storeQueue.size()) {
262            SQEntry dummy;
263            storeQueue.push_back(dummy);
264            SQEntries++;
265        }
266    } else {
267        SQEntries = size_plus_sentinel;
268    }
269}
270
271template <class Impl>
272void
273LSQUnit<Impl>::insert(DynInstPtr &inst)
274{
275    assert(inst->isMemRef());
276
277    assert(inst->isLoad() || inst->isStore());
278
279    if (inst->isLoad()) {
280        insertLoad(inst);
281    } else {
282        insertStore(inst);
283    }
284
285    inst->setInLSQ();
286}
287
288template <class Impl>
289void
290LSQUnit<Impl>::insertLoad(DynInstPtr &load_inst)
291{
292    assert((loadTail + 1) % LQEntries != loadHead);
293    assert(loads < LQEntries);
294
295    DPRINTF(LSQUnit, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
296            load_inst->readPC(), loadTail, load_inst->seqNum);
297
298    load_inst->lqIdx = loadTail;
299
300    if (stores == 0) {
301        load_inst->sqIdx = -1;
302    } else {
303        load_inst->sqIdx = storeTail;
304    }
305
306    loadQueue[loadTail] = load_inst;
307
308    incrLdIdx(loadTail);
309
310    ++loads;
311}
312
313template <class Impl>
314void
315LSQUnit<Impl>::insertStore(DynInstPtr &store_inst)
316{
317    // Make sure it is not full before inserting an instruction.
318    assert((storeTail + 1) % SQEntries != storeHead);
319    assert(stores < SQEntries);
320
321    DPRINTF(LSQUnit, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
322            store_inst->readPC(), storeTail, store_inst->seqNum);
323
324    store_inst->sqIdx = storeTail;
325    store_inst->lqIdx = loadTail;
326
327    storeQueue[storeTail] = SQEntry(store_inst);
328
329    incrStIdx(storeTail);
330
331    ++stores;
332}
333
334template <class Impl>
335typename Impl::DynInstPtr
336LSQUnit<Impl>::getMemDepViolator()
337{
338    DynInstPtr temp = memDepViolator;
339
340    memDepViolator = NULL;
341
342    return temp;
343}
344
345template <class Impl>
346unsigned
347LSQUnit<Impl>::numFreeEntries()
348{
349    unsigned free_lq_entries = LQEntries - loads;
350    unsigned free_sq_entries = SQEntries - stores;
351
352    // Both the LQ and SQ entries have an extra dummy entry to differentiate
353    // empty/full conditions.  Subtract 1 from the free entries.
354    if (free_lq_entries < free_sq_entries) {
355        return free_lq_entries - 1;
356    } else {
357        return free_sq_entries - 1;
358    }
359}
360
361template <class Impl>
362int
363LSQUnit<Impl>::numLoadsReady()
364{
365    int load_idx = loadHead;
366    int retval = 0;
367
368    while (load_idx != loadTail) {
369        assert(loadQueue[load_idx]);
370
371        if (loadQueue[load_idx]->readyToIssue()) {
372            ++retval;
373        }
374    }
375
376    return retval;
377}
378
379template <class Impl>
380Fault
381LSQUnit<Impl>::executeLoad(DynInstPtr &inst)
382{
383    // Execute a specific load.
384    Fault load_fault = NoFault;
385
386    DPRINTF(LSQUnit, "Executing load PC %#x, [sn:%lli]\n",
387            inst->readPC(),inst->seqNum);
388
389//    load_fault = inst->initiateAcc();
390    load_fault = inst->execute();
391
392    // If the instruction faulted, then we need to send it along to commit
393    // without the instruction completing.
394    if (load_fault != NoFault) {
395        // Send this instruction to commit, also make sure iew stage
396        // realizes there is activity.
397        iewStage->instToCommit(inst);
398        iewStage->activityThisCycle();
399    }
400
401    return load_fault;
402}
403
404template <class Impl>
405Fault
406LSQUnit<Impl>::executeStore(DynInstPtr &store_inst)
407{
408    using namespace TheISA;
409    // Make sure that a store exists.
410    assert(stores != 0);
411
412    int store_idx = store_inst->sqIdx;
413
414    DPRINTF(LSQUnit, "Executing store PC %#x [sn:%lli]\n",
415            store_inst->readPC(), store_inst->seqNum);
416
417    // Check the recently completed loads to see if any match this store's
418    // address.  If so, then we have a memory ordering violation.
419    int load_idx = store_inst->lqIdx;
420
421    Fault store_fault = store_inst->initiateAcc();
422//    Fault store_fault = store_inst->execute();
423
424    if (storeQueue[store_idx].size == 0) {
425        DPRINTF(LSQUnit,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
426                store_inst->readPC(),store_inst->seqNum);
427
428        return store_fault;
429    }
430
431    assert(store_fault == NoFault);
432
433    if (store_inst->isStoreConditional()) {
434        // Store conditionals need to set themselves as able to
435        // writeback if we haven't had a fault by here.
436        storeQueue[store_idx].canWB = true;
437
438        ++storesToWB;
439    }
440
441    if (!memDepViolator) {
442        while (load_idx != loadTail) {
443            // Really only need to check loads that have actually executed
444            // It's safe to check all loads because effAddr is set to
445            // InvalAddr when the dyn inst is created.
446
447            // @todo: For now this is extra conservative, detecting a
448            // violation if the addresses match assuming all accesses
449            // are quad word accesses.
450
451            // @todo: Fix this, magic number being used here
452            if ((loadQueue[load_idx]->effAddr >> 8) ==
453                (store_inst->effAddr >> 8)) {
454                // A load incorrectly passed this store.  Squash and refetch.
455                // For now return a fault to show that it was unsuccessful.
456                memDepViolator = loadQueue[load_idx];
457
458                return genMachineCheckFault();
459            }
460
461            incrLdIdx(load_idx);
462        }
463
464        // If we've reached this point, there was no violation.
465        memDepViolator = NULL;
466    }
467
468    return store_fault;
469}
470
471template <class Impl>
472void
473LSQUnit<Impl>::commitLoad()
474{
475    assert(loadQueue[loadHead]);
476
477    DPRINTF(LSQUnit, "Committing head load instruction, PC %#x\n",
478            loadQueue[loadHead]->readPC());
479
480
481    loadQueue[loadHead] = NULL;
482
483    incrLdIdx(loadHead);
484
485    --loads;
486}
487
488template <class Impl>
489void
490LSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst)
491{
492    assert(loads == 0 || loadQueue[loadHead]);
493
494    while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) {
495        commitLoad();
496    }
497}
498
499template <class Impl>
500void
501LSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst)
502{
503    assert(stores == 0 || storeQueue[storeHead].inst);
504
505    int store_idx = storeHead;
506
507    while (store_idx != storeTail) {
508        assert(storeQueue[store_idx].inst);
509        // Mark any stores that are now committed and have not yet
510        // been marked as able to write back.
511        if (!storeQueue[store_idx].canWB) {
512            if (storeQueue[store_idx].inst->seqNum > youngest_inst) {
513                break;
514            }
515            DPRINTF(LSQUnit, "Marking store as able to write back, PC "
516                    "%#x [sn:%lli]\n",
517                    storeQueue[store_idx].inst->readPC(),
518                    storeQueue[store_idx].inst->seqNum);
519
520            storeQueue[store_idx].canWB = true;
521
522            ++storesToWB;
523        }
524
525        incrStIdx(store_idx);
526    }
527}
528
529template <class Impl>
530void
531LSQUnit<Impl>::writebackStores()
532{
533    while (storesToWB > 0 &&
534           storeWBIdx != storeTail &&
535           storeQueue[storeWBIdx].inst &&
536           storeQueue[storeWBIdx].canWB &&
537           usedPorts < cachePorts) {
538
539        // Store didn't write any data so no need to write it back to
540        // memory.
541        if (storeQueue[storeWBIdx].size == 0) {
542            completeStore(storeWBIdx);
543
544            incrStIdx(storeWBIdx);
545
546            continue;
547        }
548
549        if (dcacheInterface && dcacheInterface->isBlocked()) {
550            DPRINTF(LSQUnit, "Unable to write back any more stores, cache"
551                    " is blocked!\n");
552            break;
553        }
554
555        ++usedPorts;
556
557        if (storeQueue[storeWBIdx].inst->isDataPrefetch()) {
558            incrStIdx(storeWBIdx);
559
560            continue;
561        }
562
563        assert(storeQueue[storeWBIdx].req);
564        assert(!storeQueue[storeWBIdx].committed);
565
566        MemReqPtr req = storeQueue[storeWBIdx].req;
567        storeQueue[storeWBIdx].committed = true;
568
569        req->cmd = Write;
570        req->completionEvent = NULL;
571        req->time = curTick;
572        assert(!req->data);
573        req->data = new uint8_t[64];
574        memcpy(req->data, (uint8_t *)&storeQueue[storeWBIdx].data, req->size);
575
576        DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%#x "
577                "to Addr:%#x, data:%#x [sn:%lli]\n",
578                storeWBIdx,storeQueue[storeWBIdx].inst->readPC(),
579                req->paddr, *(req->data),
580                storeQueue[storeWBIdx].inst->seqNum);
581
582        switch(storeQueue[storeWBIdx].size) {
583          case 1:
584            cpu->write(req, (uint8_t &)storeQueue[storeWBIdx].data);
585            break;
586          case 2:
587            cpu->write(req, (uint16_t &)storeQueue[storeWBIdx].data);
588            break;
589          case 4:
590            cpu->write(req, (uint32_t &)storeQueue[storeWBIdx].data);
591            break;
592          case 8:
593            cpu->write(req, (uint64_t &)storeQueue[storeWBIdx].data);
594            break;
595          default:
596            panic("Unexpected store size!\n");
597        }
598
599        // Stores other than store conditionals are completed at this
600        // time.  Mark them as completed and, if we have a checker,
601        // tell it that the instruction is completed.
602        // @todo: Figure out what time I can say stores are complete in
603        // the timing memory.
604        if (!(req->flags & LOCKED)) {
605            storeQueue[storeWBIdx].inst->setCompleted();
606            if (cpu->checker) {
607                cpu->checker->tick(storeQueue[storeWBIdx].inst);
608            }
609        }
610
611        if (dcacheInterface) {
612            assert(!req->completionEvent);
613            StoreCompletionEvent *store_event = new
614                StoreCompletionEvent(storeWBIdx, NULL, this);
615            req->completionEvent = store_event;
616
617            MemAccessResult result = dcacheInterface->access(req);
618
619            if (isStalled() &&
620                storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) {
621                DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
622                        "load idx:%i\n",
623                        stallingStoreIsn, stallingLoadIdx);
624                stalled = false;
625                stallingStoreIsn = 0;
626                iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
627            }
628
629            typename IEW::LdWritebackEvent *wb = NULL;
630            if (req->flags & LOCKED) {
631                // Stx_C should not generate a system port transaction
632                // if it misses in the cache, but that might be hard
633                // to accomplish without explicit cache support.
634                wb = new typename
635                    IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
636                                              iewStage);
637                store_event->wbEvent = wb;
638            }
639
640            if (result != MA_HIT && dcacheInterface->doEvents()) {
641                DPRINTF(LSQUnit,"D-Cache Write Miss on idx:%i!\n",
642                        storeWBIdx);
643
644                DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
645                        storeQueue[storeWBIdx].inst->seqNum);
646
647                //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
648
649                //DPRINTF(LSQUnit, "Added MSHR. count = %i\n",mshrSeqNums.size());
650
651                // @todo: Increment stat here.
652            } else {
653                DPRINTF(LSQUnit,"D-Cache: Write Hit on idx:%i !\n",
654                        storeWBIdx);
655
656                DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
657                        storeQueue[storeWBIdx].inst->seqNum);
658            }
659
660            incrStIdx(storeWBIdx);
661        } else {
662            panic("Must HAVE DCACHE!!!!!\n");
663        }
664    }
665
666    // Not sure this should set it to 0.
667    usedPorts = 0;
668
669    assert(stores >= 0 && storesToWB >= 0);
670}
671
672/*template <class Impl>
673void
674LSQUnit<Impl>::removeMSHR(InstSeqNum seqNum)
675{
676    list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(),
677                                              mshrSeqNums.end(),
678                                              seqNum);
679
680    if (mshr_it != mshrSeqNums.end()) {
681        mshrSeqNums.erase(mshr_it);
682        DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size());
683    }
684}*/
685
686template <class Impl>
687void
688LSQUnit<Impl>::squash(const InstSeqNum &squashed_num)
689{
690    DPRINTF(LSQUnit, "Squashing until [sn:%lli]!"
691            "(Loads:%i Stores:%i)\n", squashed_num, loads, stores);
692
693    int load_idx = loadTail;
694    decrLdIdx(load_idx);
695
696    while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) {
697        DPRINTF(LSQUnit,"Load Instruction PC %#x squashed, "
698                "[sn:%lli]\n",
699                loadQueue[load_idx]->readPC(),
700                loadQueue[load_idx]->seqNum);
701
702        if (isStalled() && load_idx == stallingLoadIdx) {
703            stalled = false;
704            stallingStoreIsn = 0;
705            stallingLoadIdx = 0;
706        }
707
708        // Clear the smart pointer to make sure it is decremented.
709        loadQueue[load_idx]->squashed = true;
710        loadQueue[load_idx] = NULL;
711        --loads;
712
713        // Inefficient!
714        loadTail = load_idx;
715
716        decrLdIdx(load_idx);
717    }
718
719    if (isLoadBlocked) {
720        if (squashed_num < blockedLoadSeqNum) {
721            isLoadBlocked = false;
722            loadBlockedHandled = false;
723            blockedLoadSeqNum = 0;
724        }
725    }
726
727    int store_idx = storeTail;
728    decrStIdx(store_idx);
729
730    while (stores != 0 &&
731           storeQueue[store_idx].inst->seqNum > squashed_num) {
732        // Instructions marked as can WB are already committed.
733        if (storeQueue[store_idx].canWB) {
734            break;
735        }
736
737        DPRINTF(LSQUnit,"Store Instruction PC %#x squashed, "
738                "idx:%i [sn:%lli]\n",
739                storeQueue[store_idx].inst->readPC(),
740                store_idx, storeQueue[store_idx].inst->seqNum);
741
742        // I don't think this can happen.  It should have been cleared
743        // by the stalling load.
744        if (isStalled() &&
745            storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
746            panic("Is stalled should have been cleared by stalling load!\n");
747            stalled = false;
748            stallingStoreIsn = 0;
749        }
750
751        // Clear the smart pointer to make sure it is decremented.
752        storeQueue[store_idx].inst->squashed = true;
753        storeQueue[store_idx].inst = NULL;
754        storeQueue[store_idx].canWB = 0;
755
756        if (storeQueue[store_idx].req) {
757            // There should not be a completion event if the store has
758            // not yet committed.
759            assert(!storeQueue[store_idx].req->completionEvent);
760        }
761
762        storeQueue[store_idx].req = NULL;
763        --stores;
764
765        // Inefficient!
766        storeTail = store_idx;
767
768        decrStIdx(store_idx);
769    }
770}
771
772template <class Impl>
773void
774LSQUnit<Impl>::completeStore(int store_idx)
775{
776    assert(storeQueue[store_idx].inst);
777    storeQueue[store_idx].completed = true;
778    --storesToWB;
779    // A bit conservative because a store completion may not free up entries,
780    // but hopefully avoids two store completions in one cycle from making
781    // the CPU tick twice.
782    cpu->activityThisCycle();
783
784    if (store_idx == storeHead) {
785        do {
786            incrStIdx(storeHead);
787
788            --stores;
789        } while (storeQueue[storeHead].completed &&
790                 storeHead != storeTail);
791
792        iewStage->updateLSQNextCycle = true;
793    }
794
795    DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head "
796            "idx:%i\n",
797            storeQueue[store_idx].inst->seqNum, store_idx, storeHead);
798
799    if (isStalled() &&
800        storeQueue[store_idx].inst->seqNum == stallingStoreIsn) {
801        DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] "
802                "load idx:%i\n",
803                stallingStoreIsn, stallingLoadIdx);
804        stalled = false;
805        stallingStoreIsn = 0;
806        iewStage->replayMemInst(loadQueue[stallingLoadIdx]);
807    }
808
809    storeQueue[store_idx].inst->setCompleted();
810
811    // Tell the checker we've completed this instruction.  Some stores
812    // may get reported twice to the checker, but the checker can
813    // handle that case.
814    if (cpu->checker) {
815        cpu->checker->tick(storeQueue[store_idx].inst);
816    }
817}
818
819template <class Impl>
820inline void
821LSQUnit<Impl>::incrStIdx(int &store_idx)
822{
823    if (++store_idx >= SQEntries)
824        store_idx = 0;
825}
826
827template <class Impl>
828inline void
829LSQUnit<Impl>::decrStIdx(int &store_idx)
830{
831    if (--store_idx < 0)
832        store_idx += SQEntries;
833}
834
835template <class Impl>
836inline void
837LSQUnit<Impl>::incrLdIdx(int &load_idx)
838{
839    if (++load_idx >= LQEntries)
840        load_idx = 0;
841}
842
843template <class Impl>
844inline void
845LSQUnit<Impl>::decrLdIdx(int &load_idx)
846{
847    if (--load_idx < 0)
848        load_idx += LQEntries;
849}
850
851template <class Impl>
852void
853LSQUnit<Impl>::dumpInsts()
854{
855    cprintf("Load store queue: Dumping instructions.\n");
856    cprintf("Load queue size: %i\n", loads);
857    cprintf("Load queue: ");
858
859    int load_idx = loadHead;
860
861    while (load_idx != loadTail && loadQueue[load_idx]) {
862        cprintf("%#x ", loadQueue[load_idx]->readPC());
863
864        incrLdIdx(load_idx);
865    }
866
867    cprintf("Store queue size: %i\n", stores);
868    cprintf("Store queue: ");
869
870    int store_idx = storeHead;
871
872    while (store_idx != storeTail && storeQueue[store_idx].inst) {
873        cprintf("%#x ", storeQueue[store_idx].inst->readPC());
874
875        incrStIdx(store_idx);
876    }
877
878    cprintf("\n");
879}
880