lsq_unit_impl.hh revision 13953
19814Sandreas.hansson@arm.com 22292SN/A/* 313590Srekai.gonzalezalberquilla@arm.com * Copyright (c) 2010-2014, 2017-2018 ARM Limited 410239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 57597Sminkyu.jeong@arm.com * All rights reserved 67597Sminkyu.jeong@arm.com * 77597Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 87597Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 97597Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 107597Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 117597Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 127597Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 137597Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 147597Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 157597Sminkyu.jeong@arm.com * 162292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 172292SN/A * All rights reserved. 182292SN/A * 192292SN/A * Redistribution and use in source and binary forms, with or without 202292SN/A * modification, are permitted provided that the following conditions are 212292SN/A * met: redistributions of source code must retain the above copyright 222292SN/A * notice, this list of conditions and the following disclaimer; 232292SN/A * redistributions in binary form must reproduce the above copyright 242292SN/A * notice, this list of conditions and the following disclaimer in the 252292SN/A * documentation and/or other materials provided with the distribution; 262292SN/A * neither the name of the copyright holders nor the names of its 272292SN/A * contributors may be used to endorse or promote products derived from 282292SN/A * this software without specific prior written permission. 292292SN/A * 302292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 312292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 322292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 332292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 342292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 352292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 362292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 372292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 382292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 392292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 402292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412689Sktlim@umich.edu * 422689Sktlim@umich.edu * Authors: Kevin Lim 432689Sktlim@umich.edu * Korey Sewell 442292SN/A */ 452292SN/A 469944Smatt.horsnell@ARM.com#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__ 479944Smatt.horsnell@ARM.com#define __CPU_O3_LSQ_UNIT_IMPL_HH__ 489944Smatt.horsnell@ARM.com 498591Sgblack@eecs.umich.edu#include "arch/generic/debugfaults.hh" 503326Sktlim@umich.edu#include "arch/locked_mem.hh" 518229Snate@binkert.org#include "base/str.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 538887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 542907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 552292SN/A#include "cpu/o3/lsq_unit.hh" 568232Snate@binkert.org#include "debug/Activity.hh" 578232Snate@binkert.org#include "debug/IEW.hh" 588232Snate@binkert.org#include "debug/LSQUnit.hh" 599527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 602722Sktlim@umich.edu#include "mem/packet.hh" 612669Sktlim@umich.edu#include "mem/request.hh" 622292SN/A 632669Sktlim@umich.edutemplate<class Impl> 6413429Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::WritebackEvent::WritebackEvent(const DynInstPtr &_inst, 6513429Srekai.gonzalezalberquilla@arm.com PacketPtr _pkt, LSQUnit *lsq_ptr) 668581Ssteve.reinhardt@amd.com : Event(Default_Pri, AutoDelete), 678581Ssteve.reinhardt@amd.com inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 682292SN/A{ 6913590Srekai.gonzalezalberquilla@arm.com assert(_inst->savedReq); 7013590Srekai.gonzalezalberquilla@arm.com _inst->savedReq->writebackScheduled(); 712292SN/A} 722292SN/A 732669Sktlim@umich.edutemplate<class Impl> 742292SN/Avoid 752678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 762292SN/A{ 779444SAndreas.Sandberg@ARM.com assert(!lsqPtr->cpu->switchedOut()); 789444SAndreas.Sandberg@ARM.com 799444SAndreas.Sandberg@ARM.com lsqPtr->writeback(inst, pkt); 804319Sktlim@umich.edu 8113590Srekai.gonzalezalberquilla@arm.com assert(inst->savedReq); 8213590Srekai.gonzalezalberquilla@arm.com inst->savedReq->writebackDone(); 832678Sktlim@umich.edu delete pkt; 842678Sktlim@umich.edu} 852292SN/A 862678Sktlim@umich.edutemplate<class Impl> 872678Sktlim@umich.educonst char * 885336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 892678Sktlim@umich.edu{ 904873Sstever@eecs.umich.edu return "Store writeback"; 912678Sktlim@umich.edu} 922292SN/A 9313590Srekai.gonzalezalberquilla@arm.comtemplate <class Impl> 9413590Srekai.gonzalezalberquilla@arm.combool 9513590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::recvTimingResp(PacketPtr pkt) 9613590Srekai.gonzalezalberquilla@arm.com{ 9713590Srekai.gonzalezalberquilla@arm.com auto senderState = dynamic_cast<LSQSenderState*>(pkt->senderState); 9813590Srekai.gonzalezalberquilla@arm.com LSQRequest* req = senderState->request(); 9913590Srekai.gonzalezalberquilla@arm.com assert(req != nullptr); 10013590Srekai.gonzalezalberquilla@arm.com bool ret = true; 10113590Srekai.gonzalezalberquilla@arm.com /* Check that the request is still alive before any further action. */ 10213590Srekai.gonzalezalberquilla@arm.com if (senderState->alive()) { 10313590Srekai.gonzalezalberquilla@arm.com ret = req->recvTimingResp(pkt); 10413590Srekai.gonzalezalberquilla@arm.com } else { 10513590Srekai.gonzalezalberquilla@arm.com senderState->outstanding--; 10613590Srekai.gonzalezalberquilla@arm.com } 10713590Srekai.gonzalezalberquilla@arm.com return ret; 10813590Srekai.gonzalezalberquilla@arm.com 10913590Srekai.gonzalezalberquilla@arm.com} 11013590Srekai.gonzalezalberquilla@arm.com 1112678Sktlim@umich.edutemplate<class Impl> 1122678Sktlim@umich.eduvoid 1132678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 1142678Sktlim@umich.edu{ 1152678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 1162678Sktlim@umich.edu DynInstPtr inst = state->inst; 1172344SN/A 11813590Srekai.gonzalezalberquilla@arm.com cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt)); 1192678Sktlim@umich.edu 12013590Srekai.gonzalezalberquilla@arm.com /* Notify the sender state that the access is complete (for ownership 12113590Srekai.gonzalezalberquilla@arm.com * tracking). */ 12213590Srekai.gonzalezalberquilla@arm.com state->complete(); 1236974Stjones1@inf.ed.ac.uk 1249444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 12510327Smitch.hayenga@arm.com if (!inst->isSquashed()) { 12613590Srekai.gonzalezalberquilla@arm.com if (state->needWB) { 12713652Sqtt2@cornell.edu // Only loads, store conditionals and atomics perform the writeback 12812216Snikos.nikoleris@arm.com // after receving the response from the memory 12913652Sqtt2@cornell.edu assert(inst->isLoad() || inst->isStoreConditional() || 13013652Sqtt2@cornell.edu inst->isAtomic()); 13113590Srekai.gonzalezalberquilla@arm.com writeback(inst, state->request()->mainPacket()); 13213652Sqtt2@cornell.edu if (inst->isStore() || inst->isAtomic()) { 13313590Srekai.gonzalezalberquilla@arm.com auto ss = dynamic_cast<SQSenderState*>(state); 13413590Srekai.gonzalezalberquilla@arm.com ss->writebackDone(); 13513590Srekai.gonzalezalberquilla@arm.com completeStore(ss->idx); 1366974Stjones1@inf.ed.ac.uk } 13713590Srekai.gonzalezalberquilla@arm.com } else if (inst->isStore()) { 13813652Sqtt2@cornell.edu // This is a regular store (i.e., not store conditionals and 13913652Sqtt2@cornell.edu // atomics), so it can complete without writing back 14013590Srekai.gonzalezalberquilla@arm.com completeStore(dynamic_cast<SQSenderState*>(state)->idx); 1412678Sktlim@umich.edu } 1422344SN/A } 1432292SN/A} 1442292SN/A 1452292SN/Atemplate <class Impl> 14613472Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::LSQUnit(uint32_t lqEntries, uint32_t sqEntries) 14713472Srekai.gonzalezalberquilla@arm.com : lsqID(-1), storeQueue(sqEntries+1), loadQueue(lqEntries+1), 14813472Srekai.gonzalezalberquilla@arm.com loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 14913590Srekai.gonzalezalberquilla@arm.com isStoreBlocked(false), storeInFlight(false), hasPendingRequest(false), 15013590Srekai.gonzalezalberquilla@arm.com pendingRequest(nullptr) 1512292SN/A{ 1522292SN/A} 1532292SN/A 1542292SN/Atemplate<class Impl> 1552292SN/Avoid 1565529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 15713472Srekai.gonzalezalberquilla@arm.com LSQ *lsq_ptr, unsigned id) 1582292SN/A{ 15913472Srekai.gonzalezalberquilla@arm.com lsqID = id; 16013472Srekai.gonzalezalberquilla@arm.com 1614329Sktlim@umich.edu cpu = cpu_ptr; 1624329Sktlim@umich.edu iewStage = iew_ptr; 1634329Sktlim@umich.edu 1642907Sktlim@umich.edu lsq = lsq_ptr; 1652907Sktlim@umich.edu 16613472Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",lsqID); 1672292SN/A 1688199SAli.Saidi@ARM.com depCheckShift = params->LSQDepCheckShift; 1698199SAli.Saidi@ARM.com checkLoads = params->LSQCheckLoads; 1709444SAndreas.Sandberg@ARM.com needsTSO = params->needsTSO; 1719444SAndreas.Sandberg@ARM.com 1729444SAndreas.Sandberg@ARM.com resetState(); 1739444SAndreas.Sandberg@ARM.com} 1749444SAndreas.Sandberg@ARM.com 1759444SAndreas.Sandberg@ARM.com 1769444SAndreas.Sandberg@ARM.comtemplate<class Impl> 1779444SAndreas.Sandberg@ARM.comvoid 1789444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::resetState() 1799444SAndreas.Sandberg@ARM.com{ 1809444SAndreas.Sandberg@ARM.com loads = stores = storesToWB = 0; 1818199SAli.Saidi@ARM.com 1822292SN/A 18313590Srekai.gonzalezalberquilla@arm.com storeWBIt = storeQueue.begin(); 1842292SN/A 1853492Sktlim@umich.edu retryPkt = NULL; 1862329SN/A memDepViolator = NULL; 1872292SN/A 1889444SAndreas.Sandberg@ARM.com stalled = false; 1899444SAndreas.Sandberg@ARM.com 1909814Sandreas.hansson@arm.com cacheBlockMask = ~(cpu->cacheLineSize() - 1); 1912292SN/A} 1922292SN/A 1932292SN/Atemplate<class Impl> 1942292SN/Astd::string 1952292SN/ALSQUnit<Impl>::name() const 1962292SN/A{ 1972292SN/A if (Impl::MaxThreads == 1) { 1982292SN/A return iewStage->name() + ".lsq"; 1992292SN/A } else { 20010386Sandreas.hansson@arm.com return iewStage->name() + ".lsq.thread" + std::to_string(lsqID); 2012292SN/A } 2022292SN/A} 2032292SN/A 2042292SN/Atemplate<class Impl> 2052292SN/Avoid 2062727Sktlim@umich.eduLSQUnit<Impl>::regStats() 2072727Sktlim@umich.edu{ 2082727Sktlim@umich.edu lsqForwLoads 2092727Sktlim@umich.edu .name(name() + ".forwLoads") 2102727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 2112727Sktlim@umich.edu 2122727Sktlim@umich.edu invAddrLoads 2132727Sktlim@umich.edu .name(name() + ".invAddrLoads") 2142727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 2152727Sktlim@umich.edu 2162727Sktlim@umich.edu lsqSquashedLoads 2172727Sktlim@umich.edu .name(name() + ".squashedLoads") 2182727Sktlim@umich.edu .desc("Number of loads squashed"); 2192727Sktlim@umich.edu 2202727Sktlim@umich.edu lsqIgnoredResponses 2212727Sktlim@umich.edu .name(name() + ".ignoredResponses") 2222727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2232727Sktlim@umich.edu 2242361SN/A lsqMemOrderViolation 2252361SN/A .name(name() + ".memOrderViolation") 2262361SN/A .desc("Number of memory ordering violations"); 2272361SN/A 2282727Sktlim@umich.edu lsqSquashedStores 2292727Sktlim@umich.edu .name(name() + ".squashedStores") 2302727Sktlim@umich.edu .desc("Number of stores squashed"); 2312727Sktlim@umich.edu 2322727Sktlim@umich.edu invAddrSwpfs 2332727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2342727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2352727Sktlim@umich.edu 2362727Sktlim@umich.edu lsqBlockedLoads 2372727Sktlim@umich.edu .name(name() + ".blockedLoads") 2382727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2392727Sktlim@umich.edu 2402727Sktlim@umich.edu lsqRescheduledLoads 2412727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2422727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2432727Sktlim@umich.edu 2442727Sktlim@umich.edu lsqCacheBlocked 2452727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2462727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2472727Sktlim@umich.edu} 2482727Sktlim@umich.edu 2492727Sktlim@umich.edutemplate<class Impl> 2502727Sktlim@umich.eduvoid 2518922Swilliam.wang@arm.comLSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 2524329Sktlim@umich.edu{ 2534329Sktlim@umich.edu dcachePort = dcache_port; 2544329Sktlim@umich.edu} 2554329Sktlim@umich.edu 2564329Sktlim@umich.edutemplate<class Impl> 2574329Sktlim@umich.eduvoid 2589444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::drainSanityCheck() const 2592307SN/A{ 26013590Srekai.gonzalezalberquilla@arm.com for (int i = 0; i < loadQueue.capacity(); ++i) 26113590Srekai.gonzalezalberquilla@arm.com assert(!loadQueue[i].valid()); 2622307SN/A 2632329SN/A assert(storesToWB == 0); 2649444SAndreas.Sandberg@ARM.com assert(!retryPkt); 2652307SN/A} 2662307SN/A 2672307SN/Atemplate<class Impl> 2682307SN/Avoid 2692307SN/ALSQUnit<Impl>::takeOverFrom() 2702307SN/A{ 2719444SAndreas.Sandberg@ARM.com resetState(); 2722307SN/A} 2732307SN/A 2742292SN/Atemplate <class Impl> 2752292SN/Avoid 27613429Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::insert(const DynInstPtr &inst) 2772292SN/A{ 2782292SN/A assert(inst->isMemRef()); 2792292SN/A 28013652Sqtt2@cornell.edu assert(inst->isLoad() || inst->isStore() || inst->isAtomic()); 2812292SN/A 2822292SN/A if (inst->isLoad()) { 2832292SN/A insertLoad(inst); 2842292SN/A } else { 2852292SN/A insertStore(inst); 2862292SN/A } 2872292SN/A 2882292SN/A inst->setInLSQ(); 2892292SN/A} 2902292SN/A 2912292SN/Atemplate <class Impl> 2922292SN/Avoid 29313429Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::insertLoad(const DynInstPtr &load_inst) 2942292SN/A{ 29513590Srekai.gonzalezalberquilla@arm.com assert(!loadQueue.full()); 29613590Srekai.gonzalezalberquilla@arm.com assert(loads < loadQueue.capacity()); 2972292SN/A 2987720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 29913590Srekai.gonzalezalberquilla@arm.com load_inst->pcState(), loadQueue.tail(), load_inst->seqNum); 3002292SN/A 30113590Srekai.gonzalezalberquilla@arm.com /* Grow the queue. */ 30213590Srekai.gonzalezalberquilla@arm.com loadQueue.advance_tail(); 3032292SN/A 30413590Srekai.gonzalezalberquilla@arm.com load_inst->sqIt = storeQueue.end(); 3052292SN/A 30613590Srekai.gonzalezalberquilla@arm.com assert(!loadQueue.back().valid()); 30713590Srekai.gonzalezalberquilla@arm.com loadQueue.back().set(load_inst); 30813590Srekai.gonzalezalberquilla@arm.com load_inst->lqIdx = loadQueue.tail(); 30913590Srekai.gonzalezalberquilla@arm.com load_inst->lqIt = loadQueue.getIterator(load_inst->lqIdx); 3102292SN/A 3112292SN/A ++loads; 3122292SN/A} 3132292SN/A 3142292SN/Atemplate <class Impl> 3152292SN/Avoid 31613590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::insertStore(const DynInstPtr& store_inst) 3172292SN/A{ 3182292SN/A // Make sure it is not full before inserting an instruction. 31913590Srekai.gonzalezalberquilla@arm.com assert(!storeQueue.full()); 32013590Srekai.gonzalezalberquilla@arm.com assert(stores < storeQueue.capacity()); 3212292SN/A 3227720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 32313590Srekai.gonzalezalberquilla@arm.com store_inst->pcState(), storeQueue.tail(), store_inst->seqNum); 32413590Srekai.gonzalezalberquilla@arm.com storeQueue.advance_tail(); 3252292SN/A 32613590Srekai.gonzalezalberquilla@arm.com store_inst->sqIdx = storeQueue.tail(); 32713590Srekai.gonzalezalberquilla@arm.com store_inst->lqIdx = loadQueue.moduloAdd(loadQueue.tail(), 1); 32813590Srekai.gonzalezalberquilla@arm.com store_inst->lqIt = loadQueue.end(); 3292292SN/A 33013590Srekai.gonzalezalberquilla@arm.com storeQueue.back().set(store_inst); 3312292SN/A 3322292SN/A ++stores; 3332292SN/A} 3342292SN/A 3352292SN/Atemplate <class Impl> 3362292SN/Atypename Impl::DynInstPtr 3372292SN/ALSQUnit<Impl>::getMemDepViolator() 3382292SN/A{ 3392292SN/A DynInstPtr temp = memDepViolator; 3402292SN/A 3412292SN/A memDepViolator = NULL; 3422292SN/A 3432292SN/A return temp; 3442292SN/A} 3452292SN/A 3462292SN/Atemplate <class Impl> 3472292SN/Aunsigned 34810239Sbinhpham@cs.rutgers.eduLSQUnit<Impl>::numFreeLoadEntries() 3492292SN/A{ 35010239Sbinhpham@cs.rutgers.edu //LQ has an extra dummy entry to differentiate 35110239Sbinhpham@cs.rutgers.edu //empty/full conditions. Subtract 1 from the free entries. 35213590Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "LQ size: %d, #loads occupied: %d\n", 35313590Srekai.gonzalezalberquilla@arm.com 1 + loadQueue.capacity(), loads); 35413590Srekai.gonzalezalberquilla@arm.com return loadQueue.capacity() - loads; 35510239Sbinhpham@cs.rutgers.edu} 3562292SN/A 35710239Sbinhpham@cs.rutgers.edutemplate <class Impl> 35810239Sbinhpham@cs.rutgers.eduunsigned 35910239Sbinhpham@cs.rutgers.eduLSQUnit<Impl>::numFreeStoreEntries() 36010239Sbinhpham@cs.rutgers.edu{ 36110239Sbinhpham@cs.rutgers.edu //SQ has an extra dummy entry to differentiate 36210239Sbinhpham@cs.rutgers.edu //empty/full conditions. Subtract 1 from the free entries. 36313590Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n", 36413590Srekai.gonzalezalberquilla@arm.com 1 + storeQueue.capacity(), stores); 36513590Srekai.gonzalezalberquilla@arm.com return storeQueue.capacity() - stores; 36610239Sbinhpham@cs.rutgers.edu 36710239Sbinhpham@cs.rutgers.edu } 3682292SN/A 3692292SN/Atemplate <class Impl> 3708545Ssaidi@eecs.umich.eduvoid 3718545Ssaidi@eecs.umich.eduLSQUnit<Impl>::checkSnoop(PacketPtr pkt) 3728545Ssaidi@eecs.umich.edu{ 37311357Sstephan.diestelhorst@arm.com // Should only ever get invalidations in here 37411357Sstephan.diestelhorst@arm.com assert(pkt->isInvalidate()); 37511357Sstephan.diestelhorst@arm.com 37610030SAli.Saidi@ARM.com DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 3778545Ssaidi@eecs.umich.edu 37810030SAli.Saidi@ARM.com for (int x = 0; x < cpu->numContexts(); x++) { 3799383SAli.Saidi@ARM.com ThreadContext *tc = cpu->getContext(x); 3809383SAli.Saidi@ARM.com bool no_squash = cpu->thread[x]->noSquashFromTC; 3819383SAli.Saidi@ARM.com cpu->thread[x]->noSquashFromTC = true; 3829383SAli.Saidi@ARM.com TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 3839383SAli.Saidi@ARM.com cpu->thread[x]->noSquashFromTC = no_squash; 3849383SAli.Saidi@ARM.com } 3859383SAli.Saidi@ARM.com 38613590Srekai.gonzalezalberquilla@arm.com if (loadQueue.empty()) 38713590Srekai.gonzalezalberquilla@arm.com return; 38813590Srekai.gonzalezalberquilla@arm.com 38913590Srekai.gonzalezalberquilla@arm.com auto iter = loadQueue.begin(); 39013590Srekai.gonzalezalberquilla@arm.com 39110030SAli.Saidi@ARM.com Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 39210030SAli.Saidi@ARM.com 39313590Srekai.gonzalezalberquilla@arm.com DynInstPtr ld_inst = iter->instruction(); 39413590Srekai.gonzalezalberquilla@arm.com assert(ld_inst); 39513590Srekai.gonzalezalberquilla@arm.com LSQRequest *req = iter->request(); 39611097Songal@cs.wisc.edu 39713590Srekai.gonzalezalberquilla@arm.com // Check that this snoop didn't just invalidate our lock flag 39813590Srekai.gonzalezalberquilla@arm.com if (ld_inst->effAddrValid() && 39913590Srekai.gonzalezalberquilla@arm.com req->isCacheBlockHit(invalidate_addr, cacheBlockMask) 40013590Srekai.gonzalezalberquilla@arm.com && ld_inst->memReqFlags & Request::LLSC) 40113590Srekai.gonzalezalberquilla@arm.com TheISA::handleLockedSnoopHit(ld_inst.get()); 4028545Ssaidi@eecs.umich.edu 40310149Smarco.elver@ed.ac.uk bool force_squash = false; 40410149Smarco.elver@ed.ac.uk 40513590Srekai.gonzalezalberquilla@arm.com while (++iter != loadQueue.end()) { 40613590Srekai.gonzalezalberquilla@arm.com ld_inst = iter->instruction(); 40713590Srekai.gonzalezalberquilla@arm.com assert(ld_inst); 40813590Srekai.gonzalezalberquilla@arm.com req = iter->request(); 40913590Srekai.gonzalezalberquilla@arm.com if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) 41013590Srekai.gonzalezalberquilla@arm.com continue; 4118545Ssaidi@eecs.umich.edu 41213590Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "-- inst [sn:%lli] to pktAddr:%#x\n", 41313590Srekai.gonzalezalberquilla@arm.com ld_inst->seqNum, invalidate_addr); 4148545Ssaidi@eecs.umich.edu 41513590Srekai.gonzalezalberquilla@arm.com if (force_squash || 41613590Srekai.gonzalezalberquilla@arm.com req->isCacheBlockHit(invalidate_addr, cacheBlockMask)) { 41710149Smarco.elver@ed.ac.uk if (needsTSO) { 41810149Smarco.elver@ed.ac.uk // If we have a TSO system, as all loads must be ordered with 41910149Smarco.elver@ed.ac.uk // all other loads, this load as well as *all* subsequent loads 42010149Smarco.elver@ed.ac.uk // need to be squashed to prevent possible load reordering. 42110149Smarco.elver@ed.ac.uk force_squash = true; 42210149Smarco.elver@ed.ac.uk } 42310149Smarco.elver@ed.ac.uk if (ld_inst->possibleLoadViolation() || force_squash) { 4248545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 42510030SAli.Saidi@ARM.com pkt->getAddr(), ld_inst->seqNum); 4268545Ssaidi@eecs.umich.edu 4278545Ssaidi@eecs.umich.edu // Mark the load for re-execution 42810474Sandreas.hansson@arm.com ld_inst->fault = std::make_shared<ReExec>(); 4298545Ssaidi@eecs.umich.edu } else { 43010030SAli.Saidi@ARM.com DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n", 43110030SAli.Saidi@ARM.com pkt->getAddr(), ld_inst->seqNum); 43210030SAli.Saidi@ARM.com 43310030SAli.Saidi@ARM.com // Make sure that we don't lose a snoop hitting a LOCKED 43410030SAli.Saidi@ARM.com // address since the LOCK* flags don't get updated until 43510030SAli.Saidi@ARM.com // commit. 43610030SAli.Saidi@ARM.com if (ld_inst->memReqFlags & Request::LLSC) 43710030SAli.Saidi@ARM.com TheISA::handleLockedSnoopHit(ld_inst.get()); 43810030SAli.Saidi@ARM.com 4398545Ssaidi@eecs.umich.edu // If a older load checks this and it's true 4408545Ssaidi@eecs.umich.edu // then we might have missed the snoop 4418545Ssaidi@eecs.umich.edu // in which case we need to invalidate to be sure 4429046SAli.Saidi@ARM.com ld_inst->hitExternalSnoop(true); 4438545Ssaidi@eecs.umich.edu } 4448545Ssaidi@eecs.umich.edu } 4458545Ssaidi@eecs.umich.edu } 4468545Ssaidi@eecs.umich.edu return; 4478545Ssaidi@eecs.umich.edu} 4488545Ssaidi@eecs.umich.edu 4498545Ssaidi@eecs.umich.edutemplate <class Impl> 4502292SN/AFault 45113590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::checkViolations(typename LoadQueue::iterator& loadIt, 45213590Srekai.gonzalezalberquilla@arm.com const DynInstPtr& inst) 4538199SAli.Saidi@ARM.com{ 4548199SAli.Saidi@ARM.com Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 4558199SAli.Saidi@ARM.com Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 4568199SAli.Saidi@ARM.com 4578199SAli.Saidi@ARM.com /** @todo in theory you only need to check an instruction that has executed 4588199SAli.Saidi@ARM.com * however, there isn't a good way in the pipeline at the moment to check 4598199SAli.Saidi@ARM.com * all instructions that will execute before the store writes back. Thus, 4608199SAli.Saidi@ARM.com * like the implementation that came before it, we're overly conservative. 4618199SAli.Saidi@ARM.com */ 46213590Srekai.gonzalezalberquilla@arm.com while (loadIt != loadQueue.end()) { 46313590Srekai.gonzalezalberquilla@arm.com DynInstPtr ld_inst = loadIt->instruction(); 46410824SAndreas.Sandberg@ARM.com if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) { 46513590Srekai.gonzalezalberquilla@arm.com ++loadIt; 4668199SAli.Saidi@ARM.com continue; 4678199SAli.Saidi@ARM.com } 4688199SAli.Saidi@ARM.com 4698199SAli.Saidi@ARM.com Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 4708199SAli.Saidi@ARM.com Addr ld_eff_addr2 = 4718199SAli.Saidi@ARM.com (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 4728199SAli.Saidi@ARM.com 4738272SAli.Saidi@ARM.com if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 4748545Ssaidi@eecs.umich.edu if (inst->isLoad()) { 4758545Ssaidi@eecs.umich.edu // If this load is to the same block as an external snoop 4768545Ssaidi@eecs.umich.edu // invalidate that we've observed then the load needs to be 4778545Ssaidi@eecs.umich.edu // squashed as it could have newer data 4789046SAli.Saidi@ARM.com if (ld_inst->hitExternalSnoop()) { 4798545Ssaidi@eecs.umich.edu if (!memDepViolator || 4808545Ssaidi@eecs.umich.edu ld_inst->seqNum < memDepViolator->seqNum) { 4818545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 4828592Sgblack@eecs.umich.edu "and [sn:%lli] at address %#x\n", 4838592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 4848545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 4858199SAli.Saidi@ARM.com 4868545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 4878199SAli.Saidi@ARM.com 48810474Sandreas.hansson@arm.com return std::make_shared<GenericISA::M5PanicFault>( 48910474Sandreas.hansson@arm.com "Detected fault with inst [sn:%lli] and " 49010474Sandreas.hansson@arm.com "[sn:%lli] at address %#x\n", 49110474Sandreas.hansson@arm.com inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 4928545Ssaidi@eecs.umich.edu } 4938545Ssaidi@eecs.umich.edu } 4948199SAli.Saidi@ARM.com 4958545Ssaidi@eecs.umich.edu // Otherwise, mark the load has a possible load violation 4968545Ssaidi@eecs.umich.edu // and if we see a snoop before it's commited, we need to squash 4979046SAli.Saidi@ARM.com ld_inst->possibleLoadViolation(true); 49810575SMarco.Elver@ARM.com DPRINTF(LSQUnit, "Found possible load violation at addr: %#x" 4998545Ssaidi@eecs.umich.edu " between instructions [sn:%lli] and [sn:%lli]\n", 5008545Ssaidi@eecs.umich.edu inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 5018545Ssaidi@eecs.umich.edu } else { 5028545Ssaidi@eecs.umich.edu // A load/store incorrectly passed this store. 5038545Ssaidi@eecs.umich.edu // Check if we already have a violator, or if it's newer 5048545Ssaidi@eecs.umich.edu // squash and refetch. 5058545Ssaidi@eecs.umich.edu if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 5068545Ssaidi@eecs.umich.edu break; 5078545Ssaidi@eecs.umich.edu 5088592Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 5098592Sgblack@eecs.umich.edu "[sn:%lli] at address %#x\n", 5108592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5118545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5128545Ssaidi@eecs.umich.edu 5138545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5148545Ssaidi@eecs.umich.edu 51510474Sandreas.hansson@arm.com return std::make_shared<GenericISA::M5PanicFault>( 51610474Sandreas.hansson@arm.com "Detected fault with " 51710474Sandreas.hansson@arm.com "inst [sn:%lli] and [sn:%lli] at address %#x\n", 51810474Sandreas.hansson@arm.com inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5198545Ssaidi@eecs.umich.edu } 5208199SAli.Saidi@ARM.com } 5218199SAli.Saidi@ARM.com 52213590Srekai.gonzalezalberquilla@arm.com ++loadIt; 5238199SAli.Saidi@ARM.com } 5248199SAli.Saidi@ARM.com return NoFault; 5258199SAli.Saidi@ARM.com} 5268199SAli.Saidi@ARM.com 5278199SAli.Saidi@ARM.com 5288199SAli.Saidi@ARM.com 5298199SAli.Saidi@ARM.com 5308199SAli.Saidi@ARM.comtemplate <class Impl> 5318199SAli.Saidi@ARM.comFault 53213429Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::executeLoad(const DynInstPtr &inst) 5332292SN/A{ 5344032Sktlim@umich.edu using namespace TheISA; 5352292SN/A // Execute a specific load. 5362292SN/A Fault load_fault = NoFault; 5372292SN/A 5387720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 5397944SGiacomo.Gabrielli@arm.com inst->pcState(), inst->seqNum); 5402292SN/A 5414032Sktlim@umich.edu assert(!inst->isSquashed()); 5424032Sktlim@umich.edu 5432669Sktlim@umich.edu load_fault = inst->initiateAcc(); 5442292SN/A 54513953Sgiacomo.gabrielli@arm.com if (!inst->readMemAccPredicate()) { 54613953Sgiacomo.gabrielli@arm.com assert(load_fault == NoFault); 54713953Sgiacomo.gabrielli@arm.com assert(inst->readPredicate()); 54813953Sgiacomo.gabrielli@arm.com inst->setExecuted(); 54913953Sgiacomo.gabrielli@arm.com inst->completeAcc(nullptr); 55013953Sgiacomo.gabrielli@arm.com iewStage->instToCommit(inst); 55113953Sgiacomo.gabrielli@arm.com iewStage->activityThisCycle(); 55213953Sgiacomo.gabrielli@arm.com return NoFault; 55313953Sgiacomo.gabrielli@arm.com } 55413953Sgiacomo.gabrielli@arm.com 55513590Srekai.gonzalezalberquilla@arm.com if (inst->isTranslationDelayed() && load_fault == NoFault) 5567944SGiacomo.Gabrielli@arm.com return load_fault; 5577944SGiacomo.Gabrielli@arm.com 5587597Sminkyu.jeong@arm.com // If the instruction faulted or predicated false, then we need to send it 5597597Sminkyu.jeong@arm.com // along to commit without the instruction completing. 56010231Ssteve.reinhardt@amd.com if (load_fault != NoFault || !inst->readPredicate()) { 5612329SN/A // Send this instruction to commit, also make sure iew stage 56210824SAndreas.Sandberg@ARM.com // realizes there is activity. Mark it as executed unless it 56310824SAndreas.Sandberg@ARM.com // is a strictly ordered load that needs to hit the head of 56410824SAndreas.Sandberg@ARM.com // commit. 56510231Ssteve.reinhardt@amd.com if (!inst->readPredicate()) 5667848SAli.Saidi@ARM.com inst->forwardOldRegs(); 5677600Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 5687600Sminkyu.jeong@arm.com inst->seqNum, 5697600Sminkyu.jeong@arm.com (load_fault != NoFault ? "fault" : "predication")); 57010824SAndreas.Sandberg@ARM.com if (!(inst->hasRequest() && inst->strictlyOrdered()) || 5713731Sktlim@umich.edu inst->isAtCommit()) { 5722367SN/A inst->setExecuted(); 5732367SN/A } 5742292SN/A iewStage->instToCommit(inst); 5752292SN/A iewStage->activityThisCycle(); 57610333Smitch.hayenga@arm.com } else { 57713590Srekai.gonzalezalberquilla@arm.com if (inst->effAddrValid()) { 57813590Srekai.gonzalezalberquilla@arm.com auto it = inst->lqIt; 57913590Srekai.gonzalezalberquilla@arm.com ++it; 5804032Sktlim@umich.edu 58113590Srekai.gonzalezalberquilla@arm.com if (checkLoads) 58213590Srekai.gonzalezalberquilla@arm.com return checkViolations(it, inst); 58313590Srekai.gonzalezalberquilla@arm.com } 5842292SN/A } 5852292SN/A 5862292SN/A return load_fault; 5872292SN/A} 5882292SN/A 5892292SN/Atemplate <class Impl> 5902292SN/AFault 59113429Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::executeStore(const DynInstPtr &store_inst) 5922292SN/A{ 5932292SN/A using namespace TheISA; 5942292SN/A // Make sure that a store exists. 5952292SN/A assert(stores != 0); 5962292SN/A 5972292SN/A int store_idx = store_inst->sqIdx; 5982292SN/A 5997720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 6007720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6012292SN/A 6024032Sktlim@umich.edu assert(!store_inst->isSquashed()); 6034032Sktlim@umich.edu 6042292SN/A // Check the recently completed loads to see if any match this store's 6052292SN/A // address. If so, then we have a memory ordering violation. 60613590Srekai.gonzalezalberquilla@arm.com typename LoadQueue::iterator loadIt = store_inst->lqIt; 6072292SN/A 6082292SN/A Fault store_fault = store_inst->initiateAcc(); 6092292SN/A 6107944SGiacomo.Gabrielli@arm.com if (store_inst->isTranslationDelayed() && 6117944SGiacomo.Gabrielli@arm.com store_fault == NoFault) 6127944SGiacomo.Gabrielli@arm.com return store_fault; 6137944SGiacomo.Gabrielli@arm.com 61412217Snikos.nikoleris@arm.com if (!store_inst->readPredicate()) { 61512217Snikos.nikoleris@arm.com DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 61612217Snikos.nikoleris@arm.com store_inst->seqNum); 6177848SAli.Saidi@ARM.com store_inst->forwardOldRegs(); 61812217Snikos.nikoleris@arm.com return store_fault; 61912217Snikos.nikoleris@arm.com } 6207848SAli.Saidi@ARM.com 62113590Srekai.gonzalezalberquilla@arm.com if (storeQueue[store_idx].size() == 0) { 6227782Sminkyu.jeong@arm.com DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 6237720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6242292SN/A 6252292SN/A return store_fault; 6262292SN/A } 6272292SN/A 6282292SN/A assert(store_fault == NoFault); 6292292SN/A 63013652Sqtt2@cornell.edu if (store_inst->isStoreConditional() || store_inst->isAtomic()) { 63113652Sqtt2@cornell.edu // Store conditionals and Atomics need to set themselves as able to 6322336SN/A // writeback if we haven't had a fault by here. 63313590Srekai.gonzalezalberquilla@arm.com storeQueue[store_idx].canWB() = true; 6342292SN/A 6352329SN/A ++storesToWB; 6362292SN/A } 6372292SN/A 63813590Srekai.gonzalezalberquilla@arm.com return checkViolations(loadIt, store_inst); 6392292SN/A 6402292SN/A} 6412292SN/A 6422292SN/Atemplate <class Impl> 6432292SN/Avoid 6442292SN/ALSQUnit<Impl>::commitLoad() 6452292SN/A{ 64613590Srekai.gonzalezalberquilla@arm.com assert(loadQueue.front().valid()); 6472292SN/A 6487720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 64913590Srekai.gonzalezalberquilla@arm.com loadQueue.front().instruction()->pcState()); 6502292SN/A 65113590Srekai.gonzalezalberquilla@arm.com loadQueue.front().clear(); 65213590Srekai.gonzalezalberquilla@arm.com loadQueue.pop_front(); 6532292SN/A 6542292SN/A --loads; 6552292SN/A} 6562292SN/A 6572292SN/Atemplate <class Impl> 6582292SN/Avoid 6592292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 6602292SN/A{ 66113590Srekai.gonzalezalberquilla@arm.com assert(loads == 0 || loadQueue.front().valid()); 6622292SN/A 66313590Srekai.gonzalezalberquilla@arm.com while (loads != 0 && loadQueue.front().instruction()->seqNum 66413590Srekai.gonzalezalberquilla@arm.com <= youngest_inst) { 6652292SN/A commitLoad(); 6662292SN/A } 6672292SN/A} 6682292SN/A 6692292SN/Atemplate <class Impl> 6702292SN/Avoid 6712292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 6722292SN/A{ 67313590Srekai.gonzalezalberquilla@arm.com assert(stores == 0 || storeQueue.front().valid()); 6742292SN/A 67513590Srekai.gonzalezalberquilla@arm.com /* Forward iterate the store queue (age order). */ 67613590Srekai.gonzalezalberquilla@arm.com for (auto& x : storeQueue) { 67713590Srekai.gonzalezalberquilla@arm.com assert(x.valid()); 6782329SN/A // Mark any stores that are now committed and have not yet 6792329SN/A // been marked as able to write back. 68013590Srekai.gonzalezalberquilla@arm.com if (!x.canWB()) { 68113590Srekai.gonzalezalberquilla@arm.com if (x.instruction()->seqNum > youngest_inst) { 6822292SN/A break; 6832292SN/A } 6842292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 6857720Sgblack@eecs.umich.edu "%s [sn:%lli]\n", 68613590Srekai.gonzalezalberquilla@arm.com x.instruction()->pcState(), 68713590Srekai.gonzalezalberquilla@arm.com x.instruction()->seqNum); 6882292SN/A 68913590Srekai.gonzalezalberquilla@arm.com x.canWB() = true; 6902292SN/A 6912292SN/A ++storesToWB; 6922292SN/A } 6932292SN/A } 6942292SN/A} 6952292SN/A 6962292SN/Atemplate <class Impl> 6972292SN/Avoid 69813590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::writebackBlockedStore() 6996974Stjones1@inf.ed.ac.uk{ 70013590Srekai.gonzalezalberquilla@arm.com assert(isStoreBlocked); 70113590Srekai.gonzalezalberquilla@arm.com storeWBIt->request()->sendPacketToCache(); 70213590Srekai.gonzalezalberquilla@arm.com if (storeWBIt->request()->isSent()){ 70313590Srekai.gonzalezalberquilla@arm.com storePostSend(); 7046974Stjones1@inf.ed.ac.uk } 7056974Stjones1@inf.ed.ac.uk} 7066974Stjones1@inf.ed.ac.uk 7076974Stjones1@inf.ed.ac.uktemplate <class Impl> 7086974Stjones1@inf.ed.ac.ukvoid 7092292SN/ALSQUnit<Impl>::writebackStores() 7102292SN/A{ 71113590Srekai.gonzalezalberquilla@arm.com if (isStoreBlocked) { 71213590Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "Writing back blocked store\n"); 71313590Srekai.gonzalezalberquilla@arm.com writebackBlockedStore(); 7146974Stjones1@inf.ed.ac.uk } 7156974Stjones1@inf.ed.ac.uk 7162292SN/A while (storesToWB > 0 && 71713590Srekai.gonzalezalberquilla@arm.com storeWBIt.dereferenceable() && 71813590Srekai.gonzalezalberquilla@arm.com storeWBIt->valid() && 71913590Srekai.gonzalezalberquilla@arm.com storeWBIt->canWB() && 7208727Snilay@cs.wisc.edu ((!needsTSO) || (!storeInFlight)) && 72113710Sgabor.dozsa@arm.com lsq->cachePortAvailable(false)) { 7222292SN/A 72310333Smitch.hayenga@arm.com if (isStoreBlocked) { 7242678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 7252678Sktlim@umich.edu " is blocked!\n"); 7262678Sktlim@umich.edu break; 7272678Sktlim@umich.edu } 7282678Sktlim@umich.edu 7292329SN/A // Store didn't write any data so no need to write it back to 7302329SN/A // memory. 73113590Srekai.gonzalezalberquilla@arm.com if (storeWBIt->size() == 0) { 73213590Srekai.gonzalezalberquilla@arm.com /* It is important that the preincrement happens at (or before) 73313590Srekai.gonzalezalberquilla@arm.com * the call, as the the code of completeStore checks 73413590Srekai.gonzalezalberquilla@arm.com * storeWBIt. */ 73513590Srekai.gonzalezalberquilla@arm.com completeStore(storeWBIt++); 7362292SN/A continue; 7372292SN/A } 7382678Sktlim@umich.edu 73913590Srekai.gonzalezalberquilla@arm.com if (storeWBIt->instruction()->isDataPrefetch()) { 74013590Srekai.gonzalezalberquilla@arm.com storeWBIt++; 7412292SN/A continue; 7422292SN/A } 7432292SN/A 74413590Srekai.gonzalezalberquilla@arm.com assert(storeWBIt->hasRequest()); 74513590Srekai.gonzalezalberquilla@arm.com assert(!storeWBIt->committed()); 7462292SN/A 74713590Srekai.gonzalezalberquilla@arm.com DynInstPtr inst = storeWBIt->instruction(); 74813590Srekai.gonzalezalberquilla@arm.com LSQRequest* req = storeWBIt->request(); 74913590Srekai.gonzalezalberquilla@arm.com storeWBIt->committed() = true; 7502292SN/A 7512669Sktlim@umich.edu assert(!inst->memData); 75213590Srekai.gonzalezalberquilla@arm.com inst->memData = new uint8_t[req->_size]; 7533772Sgblack@eecs.umich.edu 75413590Srekai.gonzalezalberquilla@arm.com if (storeWBIt->isAllZeros()) 75513590Srekai.gonzalezalberquilla@arm.com memset(inst->memData, 0, req->_size); 75610031SAli.Saidi@ARM.com else 75713590Srekai.gonzalezalberquilla@arm.com memcpy(inst->memData, storeWBIt->data(), req->_size); 7582669Sktlim@umich.edu 7592292SN/A 76013590Srekai.gonzalezalberquilla@arm.com if (req->senderState() == nullptr) { 76113590Srekai.gonzalezalberquilla@arm.com SQSenderState *state = new SQSenderState(storeWBIt); 76213590Srekai.gonzalezalberquilla@arm.com state->isLoad = false; 76313590Srekai.gonzalezalberquilla@arm.com state->needWB = false; 76413590Srekai.gonzalezalberquilla@arm.com state->inst = inst; 7656974Stjones1@inf.ed.ac.uk 76613590Srekai.gonzalezalberquilla@arm.com req->senderState(state); 76713652Sqtt2@cornell.edu if (inst->isStoreConditional() || inst->isAtomic()) { 76813652Sqtt2@cornell.edu /* Only store conditionals and atomics need a writeback. */ 76913590Srekai.gonzalezalberquilla@arm.com state->needWB = true; 77013590Srekai.gonzalezalberquilla@arm.com } 7716974Stjones1@inf.ed.ac.uk } 77213590Srekai.gonzalezalberquilla@arm.com req->buildPackets(); 7732678Sktlim@umich.edu 7747720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 7752292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 77613590Srekai.gonzalezalberquilla@arm.com storeWBIt.idx(), inst->pcState(), 77713590Srekai.gonzalezalberquilla@arm.com req->request()->getPaddr(), (int)*(inst->memData), 7783221Sktlim@umich.edu inst->seqNum); 7792292SN/A 7802693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 7814350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 7823326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 7833326Sktlim@umich.edu // misc regs normally updates the result, but this is not 7843326Sktlim@umich.edu // the desired behavior when handling store conditionals. 7859046SAli.Saidi@ARM.com inst->recordResult(false); 78613590Srekai.gonzalezalberquilla@arm.com bool success = TheISA::handleLockedWrite(inst.get(), 78713590Srekai.gonzalezalberquilla@arm.com req->request(), cacheBlockMask); 7889046SAli.Saidi@ARM.com inst->recordResult(true); 78913590Srekai.gonzalezalberquilla@arm.com req->packetSent(); 7903326Sktlim@umich.edu 7913326Sktlim@umich.edu if (!success) { 79213590Srekai.gonzalezalberquilla@arm.com req->complete(); 7933326Sktlim@umich.edu // Instantly complete this store. 7943326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 7953326Sktlim@umich.edu "Instantly completing it.\n", 7963326Sktlim@umich.edu inst->seqNum); 79713590Srekai.gonzalezalberquilla@arm.com PacketPtr new_pkt = new Packet(*req->packet()); 79813590Srekai.gonzalezalberquilla@arm.com WritebackEvent *wb = new WritebackEvent(inst, 79913590Srekai.gonzalezalberquilla@arm.com new_pkt, this); 8007823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick() + 1); 80113590Srekai.gonzalezalberquilla@arm.com completeStore(storeWBIt); 80213590Srekai.gonzalezalberquilla@arm.com if (!storeQueue.empty()) 80313590Srekai.gonzalezalberquilla@arm.com storeWBIt++; 80413590Srekai.gonzalezalberquilla@arm.com else 80513590Srekai.gonzalezalberquilla@arm.com storeWBIt = storeQueue.end(); 8063326Sktlim@umich.edu continue; 8072693Sktlim@umich.edu } 8082693Sktlim@umich.edu } 8092693Sktlim@umich.edu 81013590Srekai.gonzalezalberquilla@arm.com if (req->request()->isMmappedIpr()) { 81113590Srekai.gonzalezalberquilla@arm.com assert(!inst->isStoreConditional()); 81213590Srekai.gonzalezalberquilla@arm.com ThreadContext *thread = cpu->tcBase(lsqID); 81313590Srekai.gonzalezalberquilla@arm.com PacketPtr main_pkt = new Packet(req->mainRequest(), 81413590Srekai.gonzalezalberquilla@arm.com MemCmd::WriteReq); 81513590Srekai.gonzalezalberquilla@arm.com main_pkt->dataStatic(inst->memData); 81613590Srekai.gonzalezalberquilla@arm.com req->handleIprWrite(thread, main_pkt); 81713590Srekai.gonzalezalberquilla@arm.com delete main_pkt; 81813590Srekai.gonzalezalberquilla@arm.com completeStore(storeWBIt); 81913590Srekai.gonzalezalberquilla@arm.com storeWBIt++; 82013590Srekai.gonzalezalberquilla@arm.com continue; 82113590Srekai.gonzalezalberquilla@arm.com } 82213590Srekai.gonzalezalberquilla@arm.com /* Send to cache */ 82313590Srekai.gonzalezalberquilla@arm.com req->sendPacketToCache(); 8248481Sgblack@eecs.umich.edu 82513590Srekai.gonzalezalberquilla@arm.com /* If successful, do the post send */ 82613590Srekai.gonzalezalberquilla@arm.com if (req->isSent()) { 82713590Srekai.gonzalezalberquilla@arm.com storePostSend(); 82813590Srekai.gonzalezalberquilla@arm.com } else { 82913590Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "D-Cache became blocked when writing [sn:%lli], " 83013590Srekai.gonzalezalberquilla@arm.com "will retry later\n", 8313221Sktlim@umich.edu inst->seqNum); 8322292SN/A } 8332292SN/A } 8342292SN/A assert(stores >= 0 && storesToWB >= 0); 8352292SN/A} 8362292SN/A 8372292SN/Atemplate <class Impl> 8382292SN/Avoid 8392292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 8402292SN/A{ 8412292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 8422329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 8432292SN/A 84413590Srekai.gonzalezalberquilla@arm.com while (loads != 0 && 84513590Srekai.gonzalezalberquilla@arm.com loadQueue.back().instruction()->seqNum > squashed_num) { 8467720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 8472292SN/A "[sn:%lli]\n", 84813590Srekai.gonzalezalberquilla@arm.com loadQueue.back().instruction()->pcState(), 84913590Srekai.gonzalezalberquilla@arm.com loadQueue.back().instruction()->seqNum); 8502292SN/A 85113590Srekai.gonzalezalberquilla@arm.com if (isStalled() && loadQueue.tail() == stallingLoadIdx) { 8522292SN/A stalled = false; 8532292SN/A stallingStoreIsn = 0; 8542292SN/A stallingLoadIdx = 0; 8552292SN/A } 8562292SN/A 8572329SN/A // Clear the smart pointer to make sure it is decremented. 85813590Srekai.gonzalezalberquilla@arm.com loadQueue.back().instruction()->setSquashed(); 85913590Srekai.gonzalezalberquilla@arm.com loadQueue.back().clear(); 86013590Srekai.gonzalezalberquilla@arm.com 8612292SN/A --loads; 8622292SN/A 86313590Srekai.gonzalezalberquilla@arm.com loadQueue.pop_back(); 8642727Sktlim@umich.edu ++lsqSquashedLoads; 8652292SN/A } 8662292SN/A 8674032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 8684032Sktlim@umich.edu memDepViolator = NULL; 8694032Sktlim@umich.edu } 8704032Sktlim@umich.edu 8712292SN/A while (stores != 0 && 87213590Srekai.gonzalezalberquilla@arm.com storeQueue.back().instruction()->seqNum > squashed_num) { 8732329SN/A // Instructions marked as can WB are already committed. 87413590Srekai.gonzalezalberquilla@arm.com if (storeQueue.back().canWB()) { 8752292SN/A break; 8762292SN/A } 8772292SN/A 8787720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 8792292SN/A "idx:%i [sn:%lli]\n", 88013590Srekai.gonzalezalberquilla@arm.com storeQueue.back().instruction()->pcState(), 88113590Srekai.gonzalezalberquilla@arm.com storeQueue.tail(), storeQueue.back().instruction()->seqNum); 8822292SN/A 8832329SN/A // I don't think this can happen. It should have been cleared 8842329SN/A // by the stalling load. 8852292SN/A if (isStalled() && 88613590Srekai.gonzalezalberquilla@arm.com storeQueue.back().instruction()->seqNum == stallingStoreIsn) { 8872292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 8882292SN/A stalled = false; 8892292SN/A stallingStoreIsn = 0; 8902292SN/A } 8912292SN/A 8922329SN/A // Clear the smart pointer to make sure it is decremented. 89313590Srekai.gonzalezalberquilla@arm.com storeQueue.back().instruction()->setSquashed(); 8942292SN/A 8954032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 8964032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 8974032Sktlim@umich.edu // place to really handle request deletes. 89813590Srekai.gonzalezalberquilla@arm.com storeQueue.back().clear(); 8992292SN/A --stores; 9002292SN/A 90113590Srekai.gonzalezalberquilla@arm.com storeQueue.pop_back(); 9022727Sktlim@umich.edu ++lsqSquashedStores; 9032292SN/A } 9042292SN/A} 9052292SN/A 9062292SN/Atemplate <class Impl> 9072292SN/Avoid 90813590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::storePostSend() 9092693Sktlim@umich.edu{ 9102693Sktlim@umich.edu if (isStalled() && 91113590Srekai.gonzalezalberquilla@arm.com storeWBIt->instruction()->seqNum == stallingStoreIsn) { 9122693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 9132693Sktlim@umich.edu "load idx:%i\n", 9142693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 9152693Sktlim@umich.edu stalled = false; 9162693Sktlim@umich.edu stallingStoreIsn = 0; 91713590Srekai.gonzalezalberquilla@arm.com iewStage->replayMemInst(loadQueue[stallingLoadIdx].instruction()); 9182693Sktlim@umich.edu } 9192693Sktlim@umich.edu 92013590Srekai.gonzalezalberquilla@arm.com if (!storeWBIt->instruction()->isStoreConditional()) { 9212693Sktlim@umich.edu // The store is basically completed at this time. This 9222693Sktlim@umich.edu // only works so long as the checker doesn't try to 9232693Sktlim@umich.edu // verify the value in memory for stores. 92413590Srekai.gonzalezalberquilla@arm.com storeWBIt->instruction()->setCompleted(); 9258887Sgeoffrey.blake@arm.com 9262693Sktlim@umich.edu if (cpu->checker) { 92713590Srekai.gonzalezalberquilla@arm.com cpu->checker->verify(storeWBIt->instruction()); 9282693Sktlim@umich.edu } 9292693Sktlim@umich.edu } 9302693Sktlim@umich.edu 9318727Snilay@cs.wisc.edu if (needsTSO) { 9328727Snilay@cs.wisc.edu storeInFlight = true; 9338727Snilay@cs.wisc.edu } 9348727Snilay@cs.wisc.edu 93513590Srekai.gonzalezalberquilla@arm.com storeWBIt++; 9362693Sktlim@umich.edu} 9372693Sktlim@umich.edu 9382693Sktlim@umich.edutemplate <class Impl> 9392693Sktlim@umich.eduvoid 94013429Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::writeback(const DynInstPtr &inst, PacketPtr pkt) 9412678Sktlim@umich.edu{ 9422678Sktlim@umich.edu iewStage->wakeCPU(); 9432678Sktlim@umich.edu 9442678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 9452678Sktlim@umich.edu if (inst->isSquashed()) { 9462678Sktlim@umich.edu assert(!inst->isStore()); 9472727Sktlim@umich.edu ++lsqIgnoredResponses; 9482678Sktlim@umich.edu return; 9492678Sktlim@umich.edu } 9502678Sktlim@umich.edu 9512678Sktlim@umich.edu if (!inst->isExecuted()) { 9522678Sktlim@umich.edu inst->setExecuted(); 9532678Sktlim@umich.edu 95410575SMarco.Elver@ARM.com if (inst->fault == NoFault) { 95510575SMarco.Elver@ARM.com // Complete access to copy data to proper place. 95610575SMarco.Elver@ARM.com inst->completeAcc(pkt); 95710575SMarco.Elver@ARM.com } else { 95810575SMarco.Elver@ARM.com // If the instruction has an outstanding fault, we cannot complete 95910575SMarco.Elver@ARM.com // the access as this discards the current fault. 96010575SMarco.Elver@ARM.com 96110575SMarco.Elver@ARM.com // If we have an outstanding fault, the fault should only be of 96210575SMarco.Elver@ARM.com // type ReExec. 96310575SMarco.Elver@ARM.com assert(dynamic_cast<ReExec*>(inst->fault.get()) != nullptr); 96410575SMarco.Elver@ARM.com 96510575SMarco.Elver@ARM.com DPRINTF(LSQUnit, "Not completing instruction [sn:%lli] access " 96610575SMarco.Elver@ARM.com "due to pending fault.\n", inst->seqNum); 96710575SMarco.Elver@ARM.com } 9682678Sktlim@umich.edu } 9692678Sktlim@umich.edu 9702678Sktlim@umich.edu // Need to insert instruction into queue to commit 9712678Sktlim@umich.edu iewStage->instToCommit(inst); 9722678Sktlim@umich.edu 9732678Sktlim@umich.edu iewStage->activityThisCycle(); 9747598Sminkyu.jeong@arm.com 9757598Sminkyu.jeong@arm.com // see if this load changed the PC 9767598Sminkyu.jeong@arm.com iewStage->checkMisprediction(inst); 9772678Sktlim@umich.edu} 9782678Sktlim@umich.edu 9792678Sktlim@umich.edutemplate <class Impl> 9802678Sktlim@umich.eduvoid 98113590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::completeStore(typename StoreQueue::iterator store_idx) 9822292SN/A{ 98313590Srekai.gonzalezalberquilla@arm.com assert(store_idx->valid()); 98413590Srekai.gonzalezalberquilla@arm.com store_idx->completed() = true; 9852292SN/A --storesToWB; 9862292SN/A // A bit conservative because a store completion may not free up entries, 9872292SN/A // but hopefully avoids two store completions in one cycle from making 9882292SN/A // the CPU tick twice. 9893126Sktlim@umich.edu cpu->wakeCPU(); 9902292SN/A cpu->activityThisCycle(); 9912292SN/A 99213590Srekai.gonzalezalberquilla@arm.com /* We 'need' a copy here because we may clear the entry from the 99313590Srekai.gonzalezalberquilla@arm.com * store queue. */ 99413590Srekai.gonzalezalberquilla@arm.com DynInstPtr store_inst = store_idx->instruction(); 99513590Srekai.gonzalezalberquilla@arm.com if (store_idx == storeQueue.begin()) { 9962292SN/A do { 99713590Srekai.gonzalezalberquilla@arm.com storeQueue.front().clear(); 99813590Srekai.gonzalezalberquilla@arm.com storeQueue.pop_front(); 9992292SN/A --stores; 100013590Srekai.gonzalezalberquilla@arm.com } while (storeQueue.front().completed() && 100113590Srekai.gonzalezalberquilla@arm.com !storeQueue.empty()); 10022292SN/A 10032292SN/A iewStage->updateLSQNextCycle = true; 10042292SN/A } 10052292SN/A 10062329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 10072329SN/A "idx:%i\n", 100813590Srekai.gonzalezalberquilla@arm.com store_inst->seqNum, store_idx.idx() - 1, storeQueue.head() - 1); 10092292SN/A 10109527SMatt.Horsnell@arm.com#if TRACING_ON 10119527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 101213734SAndrea.Mondelli@ucf.edu store_inst->storeTick = 101313734SAndrea.Mondelli@ucf.edu curTick() - store_inst->fetchTick; 10149527SMatt.Horsnell@arm.com } 10159527SMatt.Horsnell@arm.com#endif 10169527SMatt.Horsnell@arm.com 10172292SN/A if (isStalled() && 101813590Srekai.gonzalezalberquilla@arm.com store_inst->seqNum == stallingStoreIsn) { 10192292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10202292SN/A "load idx:%i\n", 10212292SN/A stallingStoreIsn, stallingLoadIdx); 10222292SN/A stalled = false; 10232292SN/A stallingStoreIsn = 0; 102413590Srekai.gonzalezalberquilla@arm.com iewStage->replayMemInst(loadQueue[stallingLoadIdx].instruction()); 10252292SN/A } 10262316SN/A 102713590Srekai.gonzalezalberquilla@arm.com store_inst->setCompleted(); 10282329SN/A 10298727Snilay@cs.wisc.edu if (needsTSO) { 10308727Snilay@cs.wisc.edu storeInFlight = false; 10318727Snilay@cs.wisc.edu } 10328727Snilay@cs.wisc.edu 10332329SN/A // Tell the checker we've completed this instruction. Some stores 10342329SN/A // may get reported twice to the checker, but the checker can 10352329SN/A // handle that case. 103612216Snikos.nikoleris@arm.com // Store conditionals cannot be sent to the checker yet, they have 103712216Snikos.nikoleris@arm.com // to update the misc registers first which should take place 103812216Snikos.nikoleris@arm.com // when they commit 103913590Srekai.gonzalezalberquilla@arm.com if (cpu->checker && !store_inst->isStoreConditional()) { 104013590Srekai.gonzalezalberquilla@arm.com cpu->checker->verify(store_inst); 10412316SN/A } 10422292SN/A} 10432292SN/A 10442292SN/Atemplate <class Impl> 10456974Stjones1@inf.ed.ac.ukbool 104613590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::trySendPacket(bool isLoad, PacketPtr data_pkt) 10476974Stjones1@inf.ed.ac.uk{ 104813590Srekai.gonzalezalberquilla@arm.com bool ret = true; 104913590Srekai.gonzalezalberquilla@arm.com bool cache_got_blocked = false; 105013590Srekai.gonzalezalberquilla@arm.com 105113590Srekai.gonzalezalberquilla@arm.com auto state = dynamic_cast<LSQSenderState*>(data_pkt->senderState); 105213590Srekai.gonzalezalberquilla@arm.com 105313710Sgabor.dozsa@arm.com if (!lsq->cacheBlocked() && 105413710Sgabor.dozsa@arm.com lsq->cachePortAvailable(isLoad)) { 105513590Srekai.gonzalezalberquilla@arm.com if (!dcachePort->sendTimingReq(data_pkt)) { 105613590Srekai.gonzalezalberquilla@arm.com ret = false; 105713590Srekai.gonzalezalberquilla@arm.com cache_got_blocked = true; 105813590Srekai.gonzalezalberquilla@arm.com } 105913590Srekai.gonzalezalberquilla@arm.com } else { 106013590Srekai.gonzalezalberquilla@arm.com ret = false; 10616974Stjones1@inf.ed.ac.uk } 106213590Srekai.gonzalezalberquilla@arm.com 106313590Srekai.gonzalezalberquilla@arm.com if (ret) { 106413590Srekai.gonzalezalberquilla@arm.com if (!isLoad) { 106513590Srekai.gonzalezalberquilla@arm.com isStoreBlocked = false; 106613590Srekai.gonzalezalberquilla@arm.com } 106713710Sgabor.dozsa@arm.com lsq->cachePortBusy(isLoad); 106813590Srekai.gonzalezalberquilla@arm.com state->outstanding++; 106913590Srekai.gonzalezalberquilla@arm.com state->request()->packetSent(); 107013590Srekai.gonzalezalberquilla@arm.com } else { 107113590Srekai.gonzalezalberquilla@arm.com if (cache_got_blocked) { 107213590Srekai.gonzalezalberquilla@arm.com lsq->cacheBlocked(true); 107313590Srekai.gonzalezalberquilla@arm.com ++lsqCacheBlocked; 107413590Srekai.gonzalezalberquilla@arm.com } 107513590Srekai.gonzalezalberquilla@arm.com if (!isLoad) { 107613590Srekai.gonzalezalberquilla@arm.com assert(state->request() == storeWBIt->request()); 107713590Srekai.gonzalezalberquilla@arm.com isStoreBlocked = true; 107813590Srekai.gonzalezalberquilla@arm.com } 107913590Srekai.gonzalezalberquilla@arm.com state->request()->packetNotSent(); 108013590Srekai.gonzalezalberquilla@arm.com } 108113590Srekai.gonzalezalberquilla@arm.com return ret; 10826974Stjones1@inf.ed.ac.uk} 10836974Stjones1@inf.ed.ac.uk 10846974Stjones1@inf.ed.ac.uktemplate <class Impl> 10852693Sktlim@umich.eduvoid 10862693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 10872693Sktlim@umich.edu{ 10882698Sktlim@umich.edu if (isStoreBlocked) { 108913590Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "Receiving retry: blocked store\n"); 109013590Srekai.gonzalezalberquilla@arm.com writebackBlockedStore(); 10912693Sktlim@umich.edu } 10922693Sktlim@umich.edu} 10932693Sktlim@umich.edu 10942693Sktlim@umich.edutemplate <class Impl> 10952329SN/Avoid 10969440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::dumpInsts() const 10972329SN/A{ 10982329SN/A cprintf("Load store queue: Dumping instructions.\n"); 10992329SN/A cprintf("Load queue size: %i\n", loads); 11002329SN/A cprintf("Load queue: "); 11012329SN/A 110213590Srekai.gonzalezalberquilla@arm.com for (const auto& e: loadQueue) { 110313590Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst(e.instruction()); 110413831SAndrea.Mondelli@ucf.edu cprintf("%s.[sn:%llu] ", inst->pcState(), inst->seqNum); 11052329SN/A } 11069440SAndreas.Sandberg@ARM.com cprintf("\n"); 11072329SN/A 11082329SN/A cprintf("Store queue size: %i\n", stores); 11092329SN/A cprintf("Store queue: "); 11102329SN/A 111113590Srekai.gonzalezalberquilla@arm.com for (const auto& e: storeQueue) { 111213590Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst(e.instruction()); 111313831SAndrea.Mondelli@ucf.edu cprintf("%s.[sn:%llu] ", inst->pcState(), inst->seqNum); 11142329SN/A } 11152329SN/A 11162329SN/A cprintf("\n"); 11172329SN/A} 11189944Smatt.horsnell@ARM.com 111913590Srekai.gonzalezalberquilla@arm.comtemplate <class Impl> 112013590Srekai.gonzalezalberquilla@arm.comunsigned int 112113590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::cacheLineSize() 112213590Srekai.gonzalezalberquilla@arm.com{ 112313590Srekai.gonzalezalberquilla@arm.com return cpu->cacheLineSize(); 112413590Srekai.gonzalezalberquilla@arm.com} 112513590Srekai.gonzalezalberquilla@arm.com 11269944Smatt.horsnell@ARM.com#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__ 1127