lsq_unit_impl.hh revision 13590
19814Sandreas.hansson@arm.com 22292SN/A/* 313590Srekai.gonzalezalberquilla@arm.com * Copyright (c) 2010-2014, 2017-2018 ARM Limited 410239Sbinhpham@cs.rutgers.edu * Copyright (c) 2013 Advanced Micro Devices, Inc. 57597Sminkyu.jeong@arm.com * All rights reserved 67597Sminkyu.jeong@arm.com * 77597Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 87597Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 97597Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 107597Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 117597Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 127597Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 137597Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 147597Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 157597Sminkyu.jeong@arm.com * 162292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 172292SN/A * All rights reserved. 182292SN/A * 192292SN/A * Redistribution and use in source and binary forms, with or without 202292SN/A * modification, are permitted provided that the following conditions are 212292SN/A * met: redistributions of source code must retain the above copyright 222292SN/A * notice, this list of conditions and the following disclaimer; 232292SN/A * redistributions in binary form must reproduce the above copyright 242292SN/A * notice, this list of conditions and the following disclaimer in the 252292SN/A * documentation and/or other materials provided with the distribution; 262292SN/A * neither the name of the copyright holders nor the names of its 272292SN/A * contributors may be used to endorse or promote products derived from 282292SN/A * this software without specific prior written permission. 292292SN/A * 302292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 312292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 322292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 332292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 342292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 352292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 362292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 372292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 382292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 392292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 402292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 412689Sktlim@umich.edu * 422689Sktlim@umich.edu * Authors: Kevin Lim 432689Sktlim@umich.edu * Korey Sewell 442292SN/A */ 452292SN/A 469944Smatt.horsnell@ARM.com#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__ 479944Smatt.horsnell@ARM.com#define __CPU_O3_LSQ_UNIT_IMPL_HH__ 489944Smatt.horsnell@ARM.com 498591Sgblack@eecs.umich.edu#include "arch/generic/debugfaults.hh" 503326Sktlim@umich.edu#include "arch/locked_mem.hh" 518229Snate@binkert.org#include "base/str.hh" 526658Snate@binkert.org#include "config/the_isa.hh" 538887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 542907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 552292SN/A#include "cpu/o3/lsq_unit.hh" 568232Snate@binkert.org#include "debug/Activity.hh" 578232Snate@binkert.org#include "debug/IEW.hh" 588232Snate@binkert.org#include "debug/LSQUnit.hh" 599527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 602722Sktlim@umich.edu#include "mem/packet.hh" 612669Sktlim@umich.edu#include "mem/request.hh" 622292SN/A 632669Sktlim@umich.edutemplate<class Impl> 6413429Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::WritebackEvent::WritebackEvent(const DynInstPtr &_inst, 6513429Srekai.gonzalezalberquilla@arm.com PacketPtr _pkt, LSQUnit *lsq_ptr) 668581Ssteve.reinhardt@amd.com : Event(Default_Pri, AutoDelete), 678581Ssteve.reinhardt@amd.com inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 682292SN/A{ 6913590Srekai.gonzalezalberquilla@arm.com assert(_inst->savedReq); 7013590Srekai.gonzalezalberquilla@arm.com _inst->savedReq->writebackScheduled(); 712292SN/A} 722292SN/A 732669Sktlim@umich.edutemplate<class Impl> 742292SN/Avoid 752678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 762292SN/A{ 779444SAndreas.Sandberg@ARM.com assert(!lsqPtr->cpu->switchedOut()); 789444SAndreas.Sandberg@ARM.com 799444SAndreas.Sandberg@ARM.com lsqPtr->writeback(inst, pkt); 804319Sktlim@umich.edu 8113590Srekai.gonzalezalberquilla@arm.com assert(inst->savedReq); 8213590Srekai.gonzalezalberquilla@arm.com inst->savedReq->writebackDone(); 832678Sktlim@umich.edu delete pkt; 842678Sktlim@umich.edu} 852292SN/A 862678Sktlim@umich.edutemplate<class Impl> 872678Sktlim@umich.educonst char * 885336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 892678Sktlim@umich.edu{ 904873Sstever@eecs.umich.edu return "Store writeback"; 912678Sktlim@umich.edu} 922292SN/A 9313590Srekai.gonzalezalberquilla@arm.comtemplate <class Impl> 9413590Srekai.gonzalezalberquilla@arm.combool 9513590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::recvTimingResp(PacketPtr pkt) 9613590Srekai.gonzalezalberquilla@arm.com{ 9713590Srekai.gonzalezalberquilla@arm.com auto senderState = dynamic_cast<LSQSenderState*>(pkt->senderState); 9813590Srekai.gonzalezalberquilla@arm.com LSQRequest* req = senderState->request(); 9913590Srekai.gonzalezalberquilla@arm.com assert(req != nullptr); 10013590Srekai.gonzalezalberquilla@arm.com bool ret = true; 10113590Srekai.gonzalezalberquilla@arm.com /* Check that the request is still alive before any further action. */ 10213590Srekai.gonzalezalberquilla@arm.com if (senderState->alive()) { 10313590Srekai.gonzalezalberquilla@arm.com ret = req->recvTimingResp(pkt); 10413590Srekai.gonzalezalberquilla@arm.com } else { 10513590Srekai.gonzalezalberquilla@arm.com senderState->outstanding--; 10613590Srekai.gonzalezalberquilla@arm.com } 10713590Srekai.gonzalezalberquilla@arm.com return ret; 10813590Srekai.gonzalezalberquilla@arm.com 10913590Srekai.gonzalezalberquilla@arm.com} 11013590Srekai.gonzalezalberquilla@arm.com 1112678Sktlim@umich.edutemplate<class Impl> 1122678Sktlim@umich.eduvoid 1132678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 1142678Sktlim@umich.edu{ 1152678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 1162678Sktlim@umich.edu DynInstPtr inst = state->inst; 1172344SN/A 11813590Srekai.gonzalezalberquilla@arm.com cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt)); 1192678Sktlim@umich.edu 12013590Srekai.gonzalezalberquilla@arm.com /* Notify the sender state that the access is complete (for ownership 12113590Srekai.gonzalezalberquilla@arm.com * tracking). */ 12213590Srekai.gonzalezalberquilla@arm.com state->complete(); 1236974Stjones1@inf.ed.ac.uk 1249444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 12510327Smitch.hayenga@arm.com if (!inst->isSquashed()) { 12613590Srekai.gonzalezalberquilla@arm.com if (state->needWB) { 12712216Snikos.nikoleris@arm.com // Only loads and store conditionals perform the writeback 12812216Snikos.nikoleris@arm.com // after receving the response from the memory 12912216Snikos.nikoleris@arm.com assert(inst->isLoad() || inst->isStoreConditional()); 13013590Srekai.gonzalezalberquilla@arm.com writeback(inst, state->request()->mainPacket()); 13113590Srekai.gonzalezalberquilla@arm.com if (inst->isStore()) { 13213590Srekai.gonzalezalberquilla@arm.com auto ss = dynamic_cast<SQSenderState*>(state); 13313590Srekai.gonzalezalberquilla@arm.com ss->writebackDone(); 13413590Srekai.gonzalezalberquilla@arm.com completeStore(ss->idx); 1356974Stjones1@inf.ed.ac.uk } 13613590Srekai.gonzalezalberquilla@arm.com } else if (inst->isStore()) { 13713590Srekai.gonzalezalberquilla@arm.com completeStore(dynamic_cast<SQSenderState*>(state)->idx); 1382678Sktlim@umich.edu } 1392344SN/A } 1402292SN/A} 1412292SN/A 1422292SN/Atemplate <class Impl> 14313472Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::LSQUnit(uint32_t lqEntries, uint32_t sqEntries) 14413472Srekai.gonzalezalberquilla@arm.com : lsqID(-1), storeQueue(sqEntries+1), loadQueue(lqEntries+1), 14513472Srekai.gonzalezalberquilla@arm.com loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 14613590Srekai.gonzalezalberquilla@arm.com isStoreBlocked(false), storeInFlight(false), hasPendingRequest(false), 14713590Srekai.gonzalezalberquilla@arm.com pendingRequest(nullptr) 1482292SN/A{ 1492292SN/A} 1502292SN/A 1512292SN/Atemplate<class Impl> 1522292SN/Avoid 1535529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 15413472Srekai.gonzalezalberquilla@arm.com LSQ *lsq_ptr, unsigned id) 1552292SN/A{ 15613472Srekai.gonzalezalberquilla@arm.com lsqID = id; 15713472Srekai.gonzalezalberquilla@arm.com 1584329Sktlim@umich.edu cpu = cpu_ptr; 1594329Sktlim@umich.edu iewStage = iew_ptr; 1604329Sktlim@umich.edu 1612907Sktlim@umich.edu lsq = lsq_ptr; 1622907Sktlim@umich.edu 16313472Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",lsqID); 1642292SN/A 1658199SAli.Saidi@ARM.com depCheckShift = params->LSQDepCheckShift; 1668199SAli.Saidi@ARM.com checkLoads = params->LSQCheckLoads; 1679444SAndreas.Sandberg@ARM.com needsTSO = params->needsTSO; 1689444SAndreas.Sandberg@ARM.com 1699444SAndreas.Sandberg@ARM.com resetState(); 1709444SAndreas.Sandberg@ARM.com} 1719444SAndreas.Sandberg@ARM.com 1729444SAndreas.Sandberg@ARM.com 1739444SAndreas.Sandberg@ARM.comtemplate<class Impl> 1749444SAndreas.Sandberg@ARM.comvoid 1759444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::resetState() 1769444SAndreas.Sandberg@ARM.com{ 1779444SAndreas.Sandberg@ARM.com loads = stores = storesToWB = 0; 1788199SAli.Saidi@ARM.com 1792292SN/A 18013590Srekai.gonzalezalberquilla@arm.com storeWBIt = storeQueue.begin(); 1812292SN/A 1823492Sktlim@umich.edu retryPkt = NULL; 1832329SN/A memDepViolator = NULL; 1842292SN/A 1859444SAndreas.Sandberg@ARM.com stalled = false; 1869444SAndreas.Sandberg@ARM.com 1879814Sandreas.hansson@arm.com cacheBlockMask = ~(cpu->cacheLineSize() - 1); 1882292SN/A} 1892292SN/A 1902292SN/Atemplate<class Impl> 1912292SN/Astd::string 1922292SN/ALSQUnit<Impl>::name() const 1932292SN/A{ 1942292SN/A if (Impl::MaxThreads == 1) { 1952292SN/A return iewStage->name() + ".lsq"; 1962292SN/A } else { 19710386Sandreas.hansson@arm.com return iewStage->name() + ".lsq.thread" + std::to_string(lsqID); 1982292SN/A } 1992292SN/A} 2002292SN/A 2012292SN/Atemplate<class Impl> 2022292SN/Avoid 2032727Sktlim@umich.eduLSQUnit<Impl>::regStats() 2042727Sktlim@umich.edu{ 2052727Sktlim@umich.edu lsqForwLoads 2062727Sktlim@umich.edu .name(name() + ".forwLoads") 2072727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 2082727Sktlim@umich.edu 2092727Sktlim@umich.edu invAddrLoads 2102727Sktlim@umich.edu .name(name() + ".invAddrLoads") 2112727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 2122727Sktlim@umich.edu 2132727Sktlim@umich.edu lsqSquashedLoads 2142727Sktlim@umich.edu .name(name() + ".squashedLoads") 2152727Sktlim@umich.edu .desc("Number of loads squashed"); 2162727Sktlim@umich.edu 2172727Sktlim@umich.edu lsqIgnoredResponses 2182727Sktlim@umich.edu .name(name() + ".ignoredResponses") 2192727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2202727Sktlim@umich.edu 2212361SN/A lsqMemOrderViolation 2222361SN/A .name(name() + ".memOrderViolation") 2232361SN/A .desc("Number of memory ordering violations"); 2242361SN/A 2252727Sktlim@umich.edu lsqSquashedStores 2262727Sktlim@umich.edu .name(name() + ".squashedStores") 2272727Sktlim@umich.edu .desc("Number of stores squashed"); 2282727Sktlim@umich.edu 2292727Sktlim@umich.edu invAddrSwpfs 2302727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2312727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2322727Sktlim@umich.edu 2332727Sktlim@umich.edu lsqBlockedLoads 2342727Sktlim@umich.edu .name(name() + ".blockedLoads") 2352727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2362727Sktlim@umich.edu 2372727Sktlim@umich.edu lsqRescheduledLoads 2382727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2392727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2402727Sktlim@umich.edu 2412727Sktlim@umich.edu lsqCacheBlocked 2422727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2432727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2442727Sktlim@umich.edu} 2452727Sktlim@umich.edu 2462727Sktlim@umich.edutemplate<class Impl> 2472727Sktlim@umich.eduvoid 2488922Swilliam.wang@arm.comLSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 2494329Sktlim@umich.edu{ 2504329Sktlim@umich.edu dcachePort = dcache_port; 2514329Sktlim@umich.edu} 2524329Sktlim@umich.edu 2534329Sktlim@umich.edutemplate<class Impl> 2544329Sktlim@umich.eduvoid 2559444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::drainSanityCheck() const 2562307SN/A{ 25713590Srekai.gonzalezalberquilla@arm.com for (int i = 0; i < loadQueue.capacity(); ++i) 25813590Srekai.gonzalezalberquilla@arm.com assert(!loadQueue[i].valid()); 2592307SN/A 2602329SN/A assert(storesToWB == 0); 2619444SAndreas.Sandberg@ARM.com assert(!retryPkt); 2622307SN/A} 2632307SN/A 2642307SN/Atemplate<class Impl> 2652307SN/Avoid 2662307SN/ALSQUnit<Impl>::takeOverFrom() 2672307SN/A{ 2689444SAndreas.Sandberg@ARM.com resetState(); 2692307SN/A} 2702307SN/A 2712292SN/Atemplate <class Impl> 2722292SN/Avoid 27313429Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::insert(const DynInstPtr &inst) 2742292SN/A{ 2752292SN/A assert(inst->isMemRef()); 2762292SN/A 2772292SN/A assert(inst->isLoad() || inst->isStore()); 2782292SN/A 2792292SN/A if (inst->isLoad()) { 2802292SN/A insertLoad(inst); 2812292SN/A } else { 2822292SN/A insertStore(inst); 2832292SN/A } 2842292SN/A 2852292SN/A inst->setInLSQ(); 2862292SN/A} 2872292SN/A 2882292SN/Atemplate <class Impl> 2892292SN/Avoid 29013429Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::insertLoad(const DynInstPtr &load_inst) 2912292SN/A{ 29213590Srekai.gonzalezalberquilla@arm.com assert(!loadQueue.full()); 29313590Srekai.gonzalezalberquilla@arm.com assert(loads < loadQueue.capacity()); 2942292SN/A 2957720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 29613590Srekai.gonzalezalberquilla@arm.com load_inst->pcState(), loadQueue.tail(), load_inst->seqNum); 2972292SN/A 29813590Srekai.gonzalezalberquilla@arm.com /* Grow the queue. */ 29913590Srekai.gonzalezalberquilla@arm.com loadQueue.advance_tail(); 3002292SN/A 30113590Srekai.gonzalezalberquilla@arm.com load_inst->sqIt = storeQueue.end(); 3022292SN/A 30313590Srekai.gonzalezalberquilla@arm.com assert(!loadQueue.back().valid()); 30413590Srekai.gonzalezalberquilla@arm.com loadQueue.back().set(load_inst); 30513590Srekai.gonzalezalberquilla@arm.com load_inst->lqIdx = loadQueue.tail(); 30613590Srekai.gonzalezalberquilla@arm.com load_inst->lqIt = loadQueue.getIterator(load_inst->lqIdx); 3072292SN/A 3082292SN/A ++loads; 3092292SN/A} 3102292SN/A 3112292SN/Atemplate <class Impl> 3122292SN/Avoid 31313590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::insertStore(const DynInstPtr& store_inst) 3142292SN/A{ 3152292SN/A // Make sure it is not full before inserting an instruction. 31613590Srekai.gonzalezalberquilla@arm.com assert(!storeQueue.full()); 31713590Srekai.gonzalezalberquilla@arm.com assert(stores < storeQueue.capacity()); 3182292SN/A 3197720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 32013590Srekai.gonzalezalberquilla@arm.com store_inst->pcState(), storeQueue.tail(), store_inst->seqNum); 32113590Srekai.gonzalezalberquilla@arm.com storeQueue.advance_tail(); 3222292SN/A 32313590Srekai.gonzalezalberquilla@arm.com store_inst->sqIdx = storeQueue.tail(); 32413590Srekai.gonzalezalberquilla@arm.com store_inst->lqIdx = loadQueue.moduloAdd(loadQueue.tail(), 1); 32513590Srekai.gonzalezalberquilla@arm.com store_inst->lqIt = loadQueue.end(); 3262292SN/A 32713590Srekai.gonzalezalberquilla@arm.com storeQueue.back().set(store_inst); 3282292SN/A 3292292SN/A ++stores; 3302292SN/A} 3312292SN/A 3322292SN/Atemplate <class Impl> 3332292SN/Atypename Impl::DynInstPtr 3342292SN/ALSQUnit<Impl>::getMemDepViolator() 3352292SN/A{ 3362292SN/A DynInstPtr temp = memDepViolator; 3372292SN/A 3382292SN/A memDepViolator = NULL; 3392292SN/A 3402292SN/A return temp; 3412292SN/A} 3422292SN/A 3432292SN/Atemplate <class Impl> 3442292SN/Aunsigned 34510239Sbinhpham@cs.rutgers.eduLSQUnit<Impl>::numFreeLoadEntries() 3462292SN/A{ 34710239Sbinhpham@cs.rutgers.edu //LQ has an extra dummy entry to differentiate 34810239Sbinhpham@cs.rutgers.edu //empty/full conditions. Subtract 1 from the free entries. 34913590Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "LQ size: %d, #loads occupied: %d\n", 35013590Srekai.gonzalezalberquilla@arm.com 1 + loadQueue.capacity(), loads); 35113590Srekai.gonzalezalberquilla@arm.com return loadQueue.capacity() - loads; 35210239Sbinhpham@cs.rutgers.edu} 3532292SN/A 35410239Sbinhpham@cs.rutgers.edutemplate <class Impl> 35510239Sbinhpham@cs.rutgers.eduunsigned 35610239Sbinhpham@cs.rutgers.eduLSQUnit<Impl>::numFreeStoreEntries() 35710239Sbinhpham@cs.rutgers.edu{ 35810239Sbinhpham@cs.rutgers.edu //SQ has an extra dummy entry to differentiate 35910239Sbinhpham@cs.rutgers.edu //empty/full conditions. Subtract 1 from the free entries. 36013590Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "SQ size: %d, #stores occupied: %d\n", 36113590Srekai.gonzalezalberquilla@arm.com 1 + storeQueue.capacity(), stores); 36213590Srekai.gonzalezalberquilla@arm.com return storeQueue.capacity() - stores; 36310239Sbinhpham@cs.rutgers.edu 36410239Sbinhpham@cs.rutgers.edu } 3652292SN/A 3662292SN/Atemplate <class Impl> 3678545Ssaidi@eecs.umich.eduvoid 3688545Ssaidi@eecs.umich.eduLSQUnit<Impl>::checkSnoop(PacketPtr pkt) 3698545Ssaidi@eecs.umich.edu{ 37011357Sstephan.diestelhorst@arm.com // Should only ever get invalidations in here 37111357Sstephan.diestelhorst@arm.com assert(pkt->isInvalidate()); 37211357Sstephan.diestelhorst@arm.com 37310030SAli.Saidi@ARM.com DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 3748545Ssaidi@eecs.umich.edu 37510030SAli.Saidi@ARM.com for (int x = 0; x < cpu->numContexts(); x++) { 3769383SAli.Saidi@ARM.com ThreadContext *tc = cpu->getContext(x); 3779383SAli.Saidi@ARM.com bool no_squash = cpu->thread[x]->noSquashFromTC; 3789383SAli.Saidi@ARM.com cpu->thread[x]->noSquashFromTC = true; 3799383SAli.Saidi@ARM.com TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 3809383SAli.Saidi@ARM.com cpu->thread[x]->noSquashFromTC = no_squash; 3819383SAli.Saidi@ARM.com } 3829383SAli.Saidi@ARM.com 38313590Srekai.gonzalezalberquilla@arm.com if (loadQueue.empty()) 38413590Srekai.gonzalezalberquilla@arm.com return; 38513590Srekai.gonzalezalberquilla@arm.com 38613590Srekai.gonzalezalberquilla@arm.com auto iter = loadQueue.begin(); 38713590Srekai.gonzalezalberquilla@arm.com 38810030SAli.Saidi@ARM.com Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 38910030SAli.Saidi@ARM.com 39013590Srekai.gonzalezalberquilla@arm.com DynInstPtr ld_inst = iter->instruction(); 39113590Srekai.gonzalezalberquilla@arm.com assert(ld_inst); 39213590Srekai.gonzalezalberquilla@arm.com LSQRequest *req = iter->request(); 39311097Songal@cs.wisc.edu 39413590Srekai.gonzalezalberquilla@arm.com // Check that this snoop didn't just invalidate our lock flag 39513590Srekai.gonzalezalberquilla@arm.com if (ld_inst->effAddrValid() && 39613590Srekai.gonzalezalberquilla@arm.com req->isCacheBlockHit(invalidate_addr, cacheBlockMask) 39713590Srekai.gonzalezalberquilla@arm.com && ld_inst->memReqFlags & Request::LLSC) 39813590Srekai.gonzalezalberquilla@arm.com TheISA::handleLockedSnoopHit(ld_inst.get()); 3998545Ssaidi@eecs.umich.edu 40010149Smarco.elver@ed.ac.uk bool force_squash = false; 40110149Smarco.elver@ed.ac.uk 40213590Srekai.gonzalezalberquilla@arm.com while (++iter != loadQueue.end()) { 40313590Srekai.gonzalezalberquilla@arm.com ld_inst = iter->instruction(); 40413590Srekai.gonzalezalberquilla@arm.com assert(ld_inst); 40513590Srekai.gonzalezalberquilla@arm.com req = iter->request(); 40613590Srekai.gonzalezalberquilla@arm.com if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) 40713590Srekai.gonzalezalberquilla@arm.com continue; 4088545Ssaidi@eecs.umich.edu 40913590Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "-- inst [sn:%lli] to pktAddr:%#x\n", 41013590Srekai.gonzalezalberquilla@arm.com ld_inst->seqNum, invalidate_addr); 4118545Ssaidi@eecs.umich.edu 41213590Srekai.gonzalezalberquilla@arm.com if (force_squash || 41313590Srekai.gonzalezalberquilla@arm.com req->isCacheBlockHit(invalidate_addr, cacheBlockMask)) { 41410149Smarco.elver@ed.ac.uk if (needsTSO) { 41510149Smarco.elver@ed.ac.uk // If we have a TSO system, as all loads must be ordered with 41610149Smarco.elver@ed.ac.uk // all other loads, this load as well as *all* subsequent loads 41710149Smarco.elver@ed.ac.uk // need to be squashed to prevent possible load reordering. 41810149Smarco.elver@ed.ac.uk force_squash = true; 41910149Smarco.elver@ed.ac.uk } 42010149Smarco.elver@ed.ac.uk if (ld_inst->possibleLoadViolation() || force_squash) { 4218545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 42210030SAli.Saidi@ARM.com pkt->getAddr(), ld_inst->seqNum); 4238545Ssaidi@eecs.umich.edu 4248545Ssaidi@eecs.umich.edu // Mark the load for re-execution 42510474Sandreas.hansson@arm.com ld_inst->fault = std::make_shared<ReExec>(); 4268545Ssaidi@eecs.umich.edu } else { 42710030SAli.Saidi@ARM.com DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n", 42810030SAli.Saidi@ARM.com pkt->getAddr(), ld_inst->seqNum); 42910030SAli.Saidi@ARM.com 43010030SAli.Saidi@ARM.com // Make sure that we don't lose a snoop hitting a LOCKED 43110030SAli.Saidi@ARM.com // address since the LOCK* flags don't get updated until 43210030SAli.Saidi@ARM.com // commit. 43310030SAli.Saidi@ARM.com if (ld_inst->memReqFlags & Request::LLSC) 43410030SAli.Saidi@ARM.com TheISA::handleLockedSnoopHit(ld_inst.get()); 43510030SAli.Saidi@ARM.com 4368545Ssaidi@eecs.umich.edu // If a older load checks this and it's true 4378545Ssaidi@eecs.umich.edu // then we might have missed the snoop 4388545Ssaidi@eecs.umich.edu // in which case we need to invalidate to be sure 4399046SAli.Saidi@ARM.com ld_inst->hitExternalSnoop(true); 4408545Ssaidi@eecs.umich.edu } 4418545Ssaidi@eecs.umich.edu } 4428545Ssaidi@eecs.umich.edu } 4438545Ssaidi@eecs.umich.edu return; 4448545Ssaidi@eecs.umich.edu} 4458545Ssaidi@eecs.umich.edu 4468545Ssaidi@eecs.umich.edutemplate <class Impl> 4472292SN/AFault 44813590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::checkViolations(typename LoadQueue::iterator& loadIt, 44913590Srekai.gonzalezalberquilla@arm.com const DynInstPtr& inst) 4508199SAli.Saidi@ARM.com{ 4518199SAli.Saidi@ARM.com Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 4528199SAli.Saidi@ARM.com Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 4538199SAli.Saidi@ARM.com 4548199SAli.Saidi@ARM.com /** @todo in theory you only need to check an instruction that has executed 4558199SAli.Saidi@ARM.com * however, there isn't a good way in the pipeline at the moment to check 4568199SAli.Saidi@ARM.com * all instructions that will execute before the store writes back. Thus, 4578199SAli.Saidi@ARM.com * like the implementation that came before it, we're overly conservative. 4588199SAli.Saidi@ARM.com */ 45913590Srekai.gonzalezalberquilla@arm.com while (loadIt != loadQueue.end()) { 46013590Srekai.gonzalezalberquilla@arm.com DynInstPtr ld_inst = loadIt->instruction(); 46110824SAndreas.Sandberg@ARM.com if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) { 46213590Srekai.gonzalezalberquilla@arm.com ++loadIt; 4638199SAli.Saidi@ARM.com continue; 4648199SAli.Saidi@ARM.com } 4658199SAli.Saidi@ARM.com 4668199SAli.Saidi@ARM.com Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 4678199SAli.Saidi@ARM.com Addr ld_eff_addr2 = 4688199SAli.Saidi@ARM.com (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 4698199SAli.Saidi@ARM.com 4708272SAli.Saidi@ARM.com if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 4718545Ssaidi@eecs.umich.edu if (inst->isLoad()) { 4728545Ssaidi@eecs.umich.edu // If this load is to the same block as an external snoop 4738545Ssaidi@eecs.umich.edu // invalidate that we've observed then the load needs to be 4748545Ssaidi@eecs.umich.edu // squashed as it could have newer data 4759046SAli.Saidi@ARM.com if (ld_inst->hitExternalSnoop()) { 4768545Ssaidi@eecs.umich.edu if (!memDepViolator || 4778545Ssaidi@eecs.umich.edu ld_inst->seqNum < memDepViolator->seqNum) { 4788545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 4798592Sgblack@eecs.umich.edu "and [sn:%lli] at address %#x\n", 4808592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 4818545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 4828199SAli.Saidi@ARM.com 4838545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 4848199SAli.Saidi@ARM.com 48510474Sandreas.hansson@arm.com return std::make_shared<GenericISA::M5PanicFault>( 48610474Sandreas.hansson@arm.com "Detected fault with inst [sn:%lli] and " 48710474Sandreas.hansson@arm.com "[sn:%lli] at address %#x\n", 48810474Sandreas.hansson@arm.com inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 4898545Ssaidi@eecs.umich.edu } 4908545Ssaidi@eecs.umich.edu } 4918199SAli.Saidi@ARM.com 4928545Ssaidi@eecs.umich.edu // Otherwise, mark the load has a possible load violation 4938545Ssaidi@eecs.umich.edu // and if we see a snoop before it's commited, we need to squash 4949046SAli.Saidi@ARM.com ld_inst->possibleLoadViolation(true); 49510575SMarco.Elver@ARM.com DPRINTF(LSQUnit, "Found possible load violation at addr: %#x" 4968545Ssaidi@eecs.umich.edu " between instructions [sn:%lli] and [sn:%lli]\n", 4978545Ssaidi@eecs.umich.edu inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 4988545Ssaidi@eecs.umich.edu } else { 4998545Ssaidi@eecs.umich.edu // A load/store incorrectly passed this store. 5008545Ssaidi@eecs.umich.edu // Check if we already have a violator, or if it's newer 5018545Ssaidi@eecs.umich.edu // squash and refetch. 5028545Ssaidi@eecs.umich.edu if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 5038545Ssaidi@eecs.umich.edu break; 5048545Ssaidi@eecs.umich.edu 5058592Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 5068592Sgblack@eecs.umich.edu "[sn:%lli] at address %#x\n", 5078592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5088545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5098545Ssaidi@eecs.umich.edu 5108545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5118545Ssaidi@eecs.umich.edu 51210474Sandreas.hansson@arm.com return std::make_shared<GenericISA::M5PanicFault>( 51310474Sandreas.hansson@arm.com "Detected fault with " 51410474Sandreas.hansson@arm.com "inst [sn:%lli] and [sn:%lli] at address %#x\n", 51510474Sandreas.hansson@arm.com inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5168545Ssaidi@eecs.umich.edu } 5178199SAli.Saidi@ARM.com } 5188199SAli.Saidi@ARM.com 51913590Srekai.gonzalezalberquilla@arm.com ++loadIt; 5208199SAli.Saidi@ARM.com } 5218199SAli.Saidi@ARM.com return NoFault; 5228199SAli.Saidi@ARM.com} 5238199SAli.Saidi@ARM.com 5248199SAli.Saidi@ARM.com 5258199SAli.Saidi@ARM.com 5268199SAli.Saidi@ARM.com 5278199SAli.Saidi@ARM.comtemplate <class Impl> 5288199SAli.Saidi@ARM.comFault 52913429Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::executeLoad(const DynInstPtr &inst) 5302292SN/A{ 5314032Sktlim@umich.edu using namespace TheISA; 5322292SN/A // Execute a specific load. 5332292SN/A Fault load_fault = NoFault; 5342292SN/A 5357720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 5367944SGiacomo.Gabrielli@arm.com inst->pcState(), inst->seqNum); 5372292SN/A 5384032Sktlim@umich.edu assert(!inst->isSquashed()); 5394032Sktlim@umich.edu 5402669Sktlim@umich.edu load_fault = inst->initiateAcc(); 5412292SN/A 54213590Srekai.gonzalezalberquilla@arm.com if (inst->isTranslationDelayed() && load_fault == NoFault) 5437944SGiacomo.Gabrielli@arm.com return load_fault; 5447944SGiacomo.Gabrielli@arm.com 5457597Sminkyu.jeong@arm.com // If the instruction faulted or predicated false, then we need to send it 5467597Sminkyu.jeong@arm.com // along to commit without the instruction completing. 54710231Ssteve.reinhardt@amd.com if (load_fault != NoFault || !inst->readPredicate()) { 5482329SN/A // Send this instruction to commit, also make sure iew stage 54910824SAndreas.Sandberg@ARM.com // realizes there is activity. Mark it as executed unless it 55010824SAndreas.Sandberg@ARM.com // is a strictly ordered load that needs to hit the head of 55110824SAndreas.Sandberg@ARM.com // commit. 55210231Ssteve.reinhardt@amd.com if (!inst->readPredicate()) 5537848SAli.Saidi@ARM.com inst->forwardOldRegs(); 5547600Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 5557600Sminkyu.jeong@arm.com inst->seqNum, 5567600Sminkyu.jeong@arm.com (load_fault != NoFault ? "fault" : "predication")); 55710824SAndreas.Sandberg@ARM.com if (!(inst->hasRequest() && inst->strictlyOrdered()) || 5583731Sktlim@umich.edu inst->isAtCommit()) { 5592367SN/A inst->setExecuted(); 5602367SN/A } 5612292SN/A iewStage->instToCommit(inst); 5622292SN/A iewStage->activityThisCycle(); 56310333Smitch.hayenga@arm.com } else { 56413590Srekai.gonzalezalberquilla@arm.com if (inst->effAddrValid()) { 56513590Srekai.gonzalezalberquilla@arm.com auto it = inst->lqIt; 56613590Srekai.gonzalezalberquilla@arm.com ++it; 5674032Sktlim@umich.edu 56813590Srekai.gonzalezalberquilla@arm.com if (checkLoads) 56913590Srekai.gonzalezalberquilla@arm.com return checkViolations(it, inst); 57013590Srekai.gonzalezalberquilla@arm.com } 5712292SN/A } 5722292SN/A 5732292SN/A return load_fault; 5742292SN/A} 5752292SN/A 5762292SN/Atemplate <class Impl> 5772292SN/AFault 57813429Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::executeStore(const DynInstPtr &store_inst) 5792292SN/A{ 5802292SN/A using namespace TheISA; 5812292SN/A // Make sure that a store exists. 5822292SN/A assert(stores != 0); 5832292SN/A 5842292SN/A int store_idx = store_inst->sqIdx; 5852292SN/A 5867720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 5877720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 5882292SN/A 5894032Sktlim@umich.edu assert(!store_inst->isSquashed()); 5904032Sktlim@umich.edu 5912292SN/A // Check the recently completed loads to see if any match this store's 5922292SN/A // address. If so, then we have a memory ordering violation. 59313590Srekai.gonzalezalberquilla@arm.com typename LoadQueue::iterator loadIt = store_inst->lqIt; 5942292SN/A 5952292SN/A Fault store_fault = store_inst->initiateAcc(); 5962292SN/A 5977944SGiacomo.Gabrielli@arm.com if (store_inst->isTranslationDelayed() && 5987944SGiacomo.Gabrielli@arm.com store_fault == NoFault) 5997944SGiacomo.Gabrielli@arm.com return store_fault; 6007944SGiacomo.Gabrielli@arm.com 60112217Snikos.nikoleris@arm.com if (!store_inst->readPredicate()) { 60212217Snikos.nikoleris@arm.com DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 60312217Snikos.nikoleris@arm.com store_inst->seqNum); 6047848SAli.Saidi@ARM.com store_inst->forwardOldRegs(); 60512217Snikos.nikoleris@arm.com return store_fault; 60612217Snikos.nikoleris@arm.com } 6077848SAli.Saidi@ARM.com 60813590Srekai.gonzalezalberquilla@arm.com if (storeQueue[store_idx].size() == 0) { 6097782Sminkyu.jeong@arm.com DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 6107720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6112292SN/A 6122292SN/A return store_fault; 6132292SN/A } 6142292SN/A 6152292SN/A assert(store_fault == NoFault); 6162292SN/A 6172336SN/A if (store_inst->isStoreConditional()) { 6182336SN/A // Store conditionals need to set themselves as able to 6192336SN/A // writeback if we haven't had a fault by here. 62013590Srekai.gonzalezalberquilla@arm.com storeQueue[store_idx].canWB() = true; 6212292SN/A 6222329SN/A ++storesToWB; 6232292SN/A } 6242292SN/A 62513590Srekai.gonzalezalberquilla@arm.com return checkViolations(loadIt, store_inst); 6262292SN/A 6272292SN/A} 6282292SN/A 6292292SN/Atemplate <class Impl> 6302292SN/Avoid 6312292SN/ALSQUnit<Impl>::commitLoad() 6322292SN/A{ 63313590Srekai.gonzalezalberquilla@arm.com assert(loadQueue.front().valid()); 6342292SN/A 6357720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 63613590Srekai.gonzalezalberquilla@arm.com loadQueue.front().instruction()->pcState()); 6372292SN/A 63813590Srekai.gonzalezalberquilla@arm.com loadQueue.front().clear(); 63913590Srekai.gonzalezalberquilla@arm.com loadQueue.pop_front(); 6402292SN/A 6412292SN/A --loads; 6422292SN/A} 6432292SN/A 6442292SN/Atemplate <class Impl> 6452292SN/Avoid 6462292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 6472292SN/A{ 64813590Srekai.gonzalezalberquilla@arm.com assert(loads == 0 || loadQueue.front().valid()); 6492292SN/A 65013590Srekai.gonzalezalberquilla@arm.com while (loads != 0 && loadQueue.front().instruction()->seqNum 65113590Srekai.gonzalezalberquilla@arm.com <= youngest_inst) { 6522292SN/A commitLoad(); 6532292SN/A } 6542292SN/A} 6552292SN/A 6562292SN/Atemplate <class Impl> 6572292SN/Avoid 6582292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 6592292SN/A{ 66013590Srekai.gonzalezalberquilla@arm.com assert(stores == 0 || storeQueue.front().valid()); 6612292SN/A 66213590Srekai.gonzalezalberquilla@arm.com /* Forward iterate the store queue (age order). */ 66313590Srekai.gonzalezalberquilla@arm.com for (auto& x : storeQueue) { 66413590Srekai.gonzalezalberquilla@arm.com assert(x.valid()); 6652329SN/A // Mark any stores that are now committed and have not yet 6662329SN/A // been marked as able to write back. 66713590Srekai.gonzalezalberquilla@arm.com if (!x.canWB()) { 66813590Srekai.gonzalezalberquilla@arm.com if (x.instruction()->seqNum > youngest_inst) { 6692292SN/A break; 6702292SN/A } 6712292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 6727720Sgblack@eecs.umich.edu "%s [sn:%lli]\n", 67313590Srekai.gonzalezalberquilla@arm.com x.instruction()->pcState(), 67413590Srekai.gonzalezalberquilla@arm.com x.instruction()->seqNum); 6752292SN/A 67613590Srekai.gonzalezalberquilla@arm.com x.canWB() = true; 6772292SN/A 6782292SN/A ++storesToWB; 6792292SN/A } 6802292SN/A } 6812292SN/A} 6822292SN/A 6832292SN/Atemplate <class Impl> 6842292SN/Avoid 68513590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::writebackBlockedStore() 6866974Stjones1@inf.ed.ac.uk{ 68713590Srekai.gonzalezalberquilla@arm.com assert(isStoreBlocked); 68813590Srekai.gonzalezalberquilla@arm.com storeWBIt->request()->sendPacketToCache(); 68913590Srekai.gonzalezalberquilla@arm.com if (storeWBIt->request()->isSent()){ 69013590Srekai.gonzalezalberquilla@arm.com storePostSend(); 6916974Stjones1@inf.ed.ac.uk } 6926974Stjones1@inf.ed.ac.uk} 6936974Stjones1@inf.ed.ac.uk 6946974Stjones1@inf.ed.ac.uktemplate <class Impl> 6956974Stjones1@inf.ed.ac.ukvoid 6962292SN/ALSQUnit<Impl>::writebackStores() 6972292SN/A{ 69813590Srekai.gonzalezalberquilla@arm.com if (isStoreBlocked) { 69913590Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "Writing back blocked store\n"); 70013590Srekai.gonzalezalberquilla@arm.com writebackBlockedStore(); 7016974Stjones1@inf.ed.ac.uk } 7026974Stjones1@inf.ed.ac.uk 7032292SN/A while (storesToWB > 0 && 70413590Srekai.gonzalezalberquilla@arm.com storeWBIt.dereferenceable() && 70513590Srekai.gonzalezalberquilla@arm.com storeWBIt->valid() && 70613590Srekai.gonzalezalberquilla@arm.com storeWBIt->canWB() && 7078727Snilay@cs.wisc.edu ((!needsTSO) || (!storeInFlight)) && 70813590Srekai.gonzalezalberquilla@arm.com lsq->storePortAvailable()) { 7092292SN/A 71010333Smitch.hayenga@arm.com if (isStoreBlocked) { 7112678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 7122678Sktlim@umich.edu " is blocked!\n"); 7132678Sktlim@umich.edu break; 7142678Sktlim@umich.edu } 7152678Sktlim@umich.edu 7162329SN/A // Store didn't write any data so no need to write it back to 7172329SN/A // memory. 71813590Srekai.gonzalezalberquilla@arm.com if (storeWBIt->size() == 0) { 71913590Srekai.gonzalezalberquilla@arm.com /* It is important that the preincrement happens at (or before) 72013590Srekai.gonzalezalberquilla@arm.com * the call, as the the code of completeStore checks 72113590Srekai.gonzalezalberquilla@arm.com * storeWBIt. */ 72213590Srekai.gonzalezalberquilla@arm.com completeStore(storeWBIt++); 7232292SN/A continue; 7242292SN/A } 7252678Sktlim@umich.edu 72613590Srekai.gonzalezalberquilla@arm.com if (storeWBIt->instruction()->isDataPrefetch()) { 72713590Srekai.gonzalezalberquilla@arm.com storeWBIt++; 7282292SN/A continue; 7292292SN/A } 7302292SN/A 73113590Srekai.gonzalezalberquilla@arm.com assert(storeWBIt->hasRequest()); 73213590Srekai.gonzalezalberquilla@arm.com assert(!storeWBIt->committed()); 7332292SN/A 73413590Srekai.gonzalezalberquilla@arm.com DynInstPtr inst = storeWBIt->instruction(); 73513590Srekai.gonzalezalberquilla@arm.com LSQRequest* req = storeWBIt->request(); 73613590Srekai.gonzalezalberquilla@arm.com storeWBIt->committed() = true; 7372292SN/A 7382669Sktlim@umich.edu assert(!inst->memData); 73913590Srekai.gonzalezalberquilla@arm.com inst->memData = new uint8_t[req->_size]; 7403772Sgblack@eecs.umich.edu 74113590Srekai.gonzalezalberquilla@arm.com if (storeWBIt->isAllZeros()) 74213590Srekai.gonzalezalberquilla@arm.com memset(inst->memData, 0, req->_size); 74310031SAli.Saidi@ARM.com else 74413590Srekai.gonzalezalberquilla@arm.com memcpy(inst->memData, storeWBIt->data(), req->_size); 7452669Sktlim@umich.edu 7462292SN/A 74713590Srekai.gonzalezalberquilla@arm.com if (req->senderState() == nullptr) { 74813590Srekai.gonzalezalberquilla@arm.com SQSenderState *state = new SQSenderState(storeWBIt); 74913590Srekai.gonzalezalberquilla@arm.com state->isLoad = false; 75013590Srekai.gonzalezalberquilla@arm.com state->needWB = false; 75113590Srekai.gonzalezalberquilla@arm.com state->inst = inst; 7526974Stjones1@inf.ed.ac.uk 75313590Srekai.gonzalezalberquilla@arm.com req->senderState(state); 75413590Srekai.gonzalezalberquilla@arm.com if (inst->isStoreConditional()) { 75513590Srekai.gonzalezalberquilla@arm.com /* Only store conditionals need a writeback. */ 75613590Srekai.gonzalezalberquilla@arm.com state->needWB = true; 75713590Srekai.gonzalezalberquilla@arm.com } 7586974Stjones1@inf.ed.ac.uk } 75913590Srekai.gonzalezalberquilla@arm.com req->buildPackets(); 7602678Sktlim@umich.edu 7617720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 7622292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 76313590Srekai.gonzalezalberquilla@arm.com storeWBIt.idx(), inst->pcState(), 76413590Srekai.gonzalezalberquilla@arm.com req->request()->getPaddr(), (int)*(inst->memData), 7653221Sktlim@umich.edu inst->seqNum); 7662292SN/A 7672693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 7684350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 7693326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 7703326Sktlim@umich.edu // misc regs normally updates the result, but this is not 7713326Sktlim@umich.edu // the desired behavior when handling store conditionals. 7729046SAli.Saidi@ARM.com inst->recordResult(false); 77313590Srekai.gonzalezalberquilla@arm.com bool success = TheISA::handleLockedWrite(inst.get(), 77413590Srekai.gonzalezalberquilla@arm.com req->request(), cacheBlockMask); 7759046SAli.Saidi@ARM.com inst->recordResult(true); 77613590Srekai.gonzalezalberquilla@arm.com req->packetSent(); 7773326Sktlim@umich.edu 7783326Sktlim@umich.edu if (!success) { 77913590Srekai.gonzalezalberquilla@arm.com req->complete(); 7803326Sktlim@umich.edu // Instantly complete this store. 7813326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 7823326Sktlim@umich.edu "Instantly completing it.\n", 7833326Sktlim@umich.edu inst->seqNum); 78413590Srekai.gonzalezalberquilla@arm.com PacketPtr new_pkt = new Packet(*req->packet()); 78513590Srekai.gonzalezalberquilla@arm.com WritebackEvent *wb = new WritebackEvent(inst, 78613590Srekai.gonzalezalberquilla@arm.com new_pkt, this); 7877823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick() + 1); 78813590Srekai.gonzalezalberquilla@arm.com completeStore(storeWBIt); 78913590Srekai.gonzalezalberquilla@arm.com if (!storeQueue.empty()) 79013590Srekai.gonzalezalberquilla@arm.com storeWBIt++; 79113590Srekai.gonzalezalberquilla@arm.com else 79213590Srekai.gonzalezalberquilla@arm.com storeWBIt = storeQueue.end(); 7933326Sktlim@umich.edu continue; 7942693Sktlim@umich.edu } 7952693Sktlim@umich.edu } 7962693Sktlim@umich.edu 79713590Srekai.gonzalezalberquilla@arm.com if (req->request()->isMmappedIpr()) { 79813590Srekai.gonzalezalberquilla@arm.com assert(!inst->isStoreConditional()); 79913590Srekai.gonzalezalberquilla@arm.com ThreadContext *thread = cpu->tcBase(lsqID); 80013590Srekai.gonzalezalberquilla@arm.com PacketPtr main_pkt = new Packet(req->mainRequest(), 80113590Srekai.gonzalezalberquilla@arm.com MemCmd::WriteReq); 80213590Srekai.gonzalezalberquilla@arm.com main_pkt->dataStatic(inst->memData); 80313590Srekai.gonzalezalberquilla@arm.com req->handleIprWrite(thread, main_pkt); 80413590Srekai.gonzalezalberquilla@arm.com delete main_pkt; 80513590Srekai.gonzalezalberquilla@arm.com completeStore(storeWBIt); 80613590Srekai.gonzalezalberquilla@arm.com storeWBIt++; 80713590Srekai.gonzalezalberquilla@arm.com continue; 80813590Srekai.gonzalezalberquilla@arm.com } 80913590Srekai.gonzalezalberquilla@arm.com /* Send to cache */ 81013590Srekai.gonzalezalberquilla@arm.com req->sendPacketToCache(); 8118481Sgblack@eecs.umich.edu 81213590Srekai.gonzalezalberquilla@arm.com /* If successful, do the post send */ 81313590Srekai.gonzalezalberquilla@arm.com if (req->isSent()) { 81413590Srekai.gonzalezalberquilla@arm.com storePostSend(); 81513590Srekai.gonzalezalberquilla@arm.com } else { 81613590Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "D-Cache became blocked when writing [sn:%lli], " 81713590Srekai.gonzalezalberquilla@arm.com "will retry later\n", 8183221Sktlim@umich.edu inst->seqNum); 8192292SN/A } 8202292SN/A } 8212292SN/A assert(stores >= 0 && storesToWB >= 0); 8222292SN/A} 8232292SN/A 8242292SN/Atemplate <class Impl> 8252292SN/Avoid 8262292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 8272292SN/A{ 8282292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 8292329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 8302292SN/A 83113590Srekai.gonzalezalberquilla@arm.com while (loads != 0 && 83213590Srekai.gonzalezalberquilla@arm.com loadQueue.back().instruction()->seqNum > squashed_num) { 8337720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 8342292SN/A "[sn:%lli]\n", 83513590Srekai.gonzalezalberquilla@arm.com loadQueue.back().instruction()->pcState(), 83613590Srekai.gonzalezalberquilla@arm.com loadQueue.back().instruction()->seqNum); 8372292SN/A 83813590Srekai.gonzalezalberquilla@arm.com if (isStalled() && loadQueue.tail() == stallingLoadIdx) { 8392292SN/A stalled = false; 8402292SN/A stallingStoreIsn = 0; 8412292SN/A stallingLoadIdx = 0; 8422292SN/A } 8432292SN/A 8442329SN/A // Clear the smart pointer to make sure it is decremented. 84513590Srekai.gonzalezalberquilla@arm.com loadQueue.back().instruction()->setSquashed(); 84613590Srekai.gonzalezalberquilla@arm.com loadQueue.back().clear(); 84713590Srekai.gonzalezalberquilla@arm.com 8482292SN/A --loads; 8492292SN/A 85013590Srekai.gonzalezalberquilla@arm.com loadQueue.pop_back(); 8512727Sktlim@umich.edu ++lsqSquashedLoads; 8522292SN/A } 8532292SN/A 8544032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 8554032Sktlim@umich.edu memDepViolator = NULL; 8564032Sktlim@umich.edu } 8574032Sktlim@umich.edu 8582292SN/A while (stores != 0 && 85913590Srekai.gonzalezalberquilla@arm.com storeQueue.back().instruction()->seqNum > squashed_num) { 8602329SN/A // Instructions marked as can WB are already committed. 86113590Srekai.gonzalezalberquilla@arm.com if (storeQueue.back().canWB()) { 8622292SN/A break; 8632292SN/A } 8642292SN/A 8657720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 8662292SN/A "idx:%i [sn:%lli]\n", 86713590Srekai.gonzalezalberquilla@arm.com storeQueue.back().instruction()->pcState(), 86813590Srekai.gonzalezalberquilla@arm.com storeQueue.tail(), storeQueue.back().instruction()->seqNum); 8692292SN/A 8702329SN/A // I don't think this can happen. It should have been cleared 8712329SN/A // by the stalling load. 8722292SN/A if (isStalled() && 87313590Srekai.gonzalezalberquilla@arm.com storeQueue.back().instruction()->seqNum == stallingStoreIsn) { 8742292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 8752292SN/A stalled = false; 8762292SN/A stallingStoreIsn = 0; 8772292SN/A } 8782292SN/A 8792329SN/A // Clear the smart pointer to make sure it is decremented. 88013590Srekai.gonzalezalberquilla@arm.com storeQueue.back().instruction()->setSquashed(); 8812292SN/A 8824032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 8834032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 8844032Sktlim@umich.edu // place to really handle request deletes. 88513590Srekai.gonzalezalberquilla@arm.com storeQueue.back().clear(); 8862292SN/A --stores; 8872292SN/A 88813590Srekai.gonzalezalberquilla@arm.com storeQueue.pop_back(); 8892727Sktlim@umich.edu ++lsqSquashedStores; 8902292SN/A } 8912292SN/A} 8922292SN/A 8932292SN/Atemplate <class Impl> 8942292SN/Avoid 89513590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::storePostSend() 8962693Sktlim@umich.edu{ 8972693Sktlim@umich.edu if (isStalled() && 89813590Srekai.gonzalezalberquilla@arm.com storeWBIt->instruction()->seqNum == stallingStoreIsn) { 8992693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 9002693Sktlim@umich.edu "load idx:%i\n", 9012693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 9022693Sktlim@umich.edu stalled = false; 9032693Sktlim@umich.edu stallingStoreIsn = 0; 90413590Srekai.gonzalezalberquilla@arm.com iewStage->replayMemInst(loadQueue[stallingLoadIdx].instruction()); 9052693Sktlim@umich.edu } 9062693Sktlim@umich.edu 90713590Srekai.gonzalezalberquilla@arm.com if (!storeWBIt->instruction()->isStoreConditional()) { 9082693Sktlim@umich.edu // The store is basically completed at this time. This 9092693Sktlim@umich.edu // only works so long as the checker doesn't try to 9102693Sktlim@umich.edu // verify the value in memory for stores. 91113590Srekai.gonzalezalberquilla@arm.com storeWBIt->instruction()->setCompleted(); 9128887Sgeoffrey.blake@arm.com 9132693Sktlim@umich.edu if (cpu->checker) { 91413590Srekai.gonzalezalberquilla@arm.com cpu->checker->verify(storeWBIt->instruction()); 9152693Sktlim@umich.edu } 9162693Sktlim@umich.edu } 9172693Sktlim@umich.edu 9188727Snilay@cs.wisc.edu if (needsTSO) { 9198727Snilay@cs.wisc.edu storeInFlight = true; 9208727Snilay@cs.wisc.edu } 9218727Snilay@cs.wisc.edu 92213590Srekai.gonzalezalberquilla@arm.com storeWBIt++; 9232693Sktlim@umich.edu} 9242693Sktlim@umich.edu 9252693Sktlim@umich.edutemplate <class Impl> 9262693Sktlim@umich.eduvoid 92713429Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::writeback(const DynInstPtr &inst, PacketPtr pkt) 9282678Sktlim@umich.edu{ 9292678Sktlim@umich.edu iewStage->wakeCPU(); 9302678Sktlim@umich.edu 9312678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 9322678Sktlim@umich.edu if (inst->isSquashed()) { 9332678Sktlim@umich.edu assert(!inst->isStore()); 9342727Sktlim@umich.edu ++lsqIgnoredResponses; 9352678Sktlim@umich.edu return; 9362678Sktlim@umich.edu } 9372678Sktlim@umich.edu 9382678Sktlim@umich.edu if (!inst->isExecuted()) { 9392678Sktlim@umich.edu inst->setExecuted(); 9402678Sktlim@umich.edu 94110575SMarco.Elver@ARM.com if (inst->fault == NoFault) { 94210575SMarco.Elver@ARM.com // Complete access to copy data to proper place. 94310575SMarco.Elver@ARM.com inst->completeAcc(pkt); 94410575SMarco.Elver@ARM.com } else { 94510575SMarco.Elver@ARM.com // If the instruction has an outstanding fault, we cannot complete 94610575SMarco.Elver@ARM.com // the access as this discards the current fault. 94710575SMarco.Elver@ARM.com 94810575SMarco.Elver@ARM.com // If we have an outstanding fault, the fault should only be of 94910575SMarco.Elver@ARM.com // type ReExec. 95010575SMarco.Elver@ARM.com assert(dynamic_cast<ReExec*>(inst->fault.get()) != nullptr); 95110575SMarco.Elver@ARM.com 95210575SMarco.Elver@ARM.com DPRINTF(LSQUnit, "Not completing instruction [sn:%lli] access " 95310575SMarco.Elver@ARM.com "due to pending fault.\n", inst->seqNum); 95410575SMarco.Elver@ARM.com } 9552678Sktlim@umich.edu } 9562678Sktlim@umich.edu 9572678Sktlim@umich.edu // Need to insert instruction into queue to commit 9582678Sktlim@umich.edu iewStage->instToCommit(inst); 9592678Sktlim@umich.edu 9602678Sktlim@umich.edu iewStage->activityThisCycle(); 9617598Sminkyu.jeong@arm.com 9627598Sminkyu.jeong@arm.com // see if this load changed the PC 9637598Sminkyu.jeong@arm.com iewStage->checkMisprediction(inst); 9642678Sktlim@umich.edu} 9652678Sktlim@umich.edu 9662678Sktlim@umich.edutemplate <class Impl> 9672678Sktlim@umich.eduvoid 96813590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::completeStore(typename StoreQueue::iterator store_idx) 9692292SN/A{ 97013590Srekai.gonzalezalberquilla@arm.com assert(store_idx->valid()); 97113590Srekai.gonzalezalberquilla@arm.com store_idx->completed() = true; 9722292SN/A --storesToWB; 9732292SN/A // A bit conservative because a store completion may not free up entries, 9742292SN/A // but hopefully avoids two store completions in one cycle from making 9752292SN/A // the CPU tick twice. 9763126Sktlim@umich.edu cpu->wakeCPU(); 9772292SN/A cpu->activityThisCycle(); 9782292SN/A 97913590Srekai.gonzalezalberquilla@arm.com /* We 'need' a copy here because we may clear the entry from the 98013590Srekai.gonzalezalberquilla@arm.com * store queue. */ 98113590Srekai.gonzalezalberquilla@arm.com DynInstPtr store_inst = store_idx->instruction(); 98213590Srekai.gonzalezalberquilla@arm.com if (store_idx == storeQueue.begin()) { 9832292SN/A do { 98413590Srekai.gonzalezalberquilla@arm.com storeQueue.front().clear(); 98513590Srekai.gonzalezalberquilla@arm.com storeQueue.pop_front(); 9862292SN/A --stores; 98713590Srekai.gonzalezalberquilla@arm.com } while (storeQueue.front().completed() && 98813590Srekai.gonzalezalberquilla@arm.com !storeQueue.empty()); 9892292SN/A 9902292SN/A iewStage->updateLSQNextCycle = true; 9912292SN/A } 9922292SN/A 9932329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 9942329SN/A "idx:%i\n", 99513590Srekai.gonzalezalberquilla@arm.com store_inst->seqNum, store_idx.idx() - 1, storeQueue.head() - 1); 9962292SN/A 9979527SMatt.Horsnell@arm.com#if TRACING_ON 9989527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 99913590Srekai.gonzalezalberquilla@arm.com store_idx->instruction()->storeTick = 100013590Srekai.gonzalezalberquilla@arm.com curTick() - store_idx->instruction()->fetchTick; 10019527SMatt.Horsnell@arm.com } 10029527SMatt.Horsnell@arm.com#endif 10039527SMatt.Horsnell@arm.com 10042292SN/A if (isStalled() && 100513590Srekai.gonzalezalberquilla@arm.com store_inst->seqNum == stallingStoreIsn) { 10062292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10072292SN/A "load idx:%i\n", 10082292SN/A stallingStoreIsn, stallingLoadIdx); 10092292SN/A stalled = false; 10102292SN/A stallingStoreIsn = 0; 101113590Srekai.gonzalezalberquilla@arm.com iewStage->replayMemInst(loadQueue[stallingLoadIdx].instruction()); 10122292SN/A } 10132316SN/A 101413590Srekai.gonzalezalberquilla@arm.com store_inst->setCompleted(); 10152329SN/A 10168727Snilay@cs.wisc.edu if (needsTSO) { 10178727Snilay@cs.wisc.edu storeInFlight = false; 10188727Snilay@cs.wisc.edu } 10198727Snilay@cs.wisc.edu 10202329SN/A // Tell the checker we've completed this instruction. Some stores 10212329SN/A // may get reported twice to the checker, but the checker can 10222329SN/A // handle that case. 102312216Snikos.nikoleris@arm.com // Store conditionals cannot be sent to the checker yet, they have 102412216Snikos.nikoleris@arm.com // to update the misc registers first which should take place 102512216Snikos.nikoleris@arm.com // when they commit 102613590Srekai.gonzalezalberquilla@arm.com if (cpu->checker && !store_inst->isStoreConditional()) { 102713590Srekai.gonzalezalberquilla@arm.com cpu->checker->verify(store_inst); 10282316SN/A } 10292292SN/A} 10302292SN/A 10312292SN/Atemplate <class Impl> 10326974Stjones1@inf.ed.ac.ukbool 103313590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::trySendPacket(bool isLoad, PacketPtr data_pkt) 10346974Stjones1@inf.ed.ac.uk{ 103513590Srekai.gonzalezalberquilla@arm.com bool ret = true; 103613590Srekai.gonzalezalberquilla@arm.com bool cache_got_blocked = false; 103713590Srekai.gonzalezalberquilla@arm.com 103813590Srekai.gonzalezalberquilla@arm.com auto state = dynamic_cast<LSQSenderState*>(data_pkt->senderState); 103913590Srekai.gonzalezalberquilla@arm.com 104013590Srekai.gonzalezalberquilla@arm.com if (!lsq->cacheBlocked() && (isLoad || lsq->storePortAvailable())) { 104113590Srekai.gonzalezalberquilla@arm.com if (!dcachePort->sendTimingReq(data_pkt)) { 104213590Srekai.gonzalezalberquilla@arm.com ret = false; 104313590Srekai.gonzalezalberquilla@arm.com cache_got_blocked = true; 104413590Srekai.gonzalezalberquilla@arm.com } 104513590Srekai.gonzalezalberquilla@arm.com } else { 104613590Srekai.gonzalezalberquilla@arm.com ret = false; 10476974Stjones1@inf.ed.ac.uk } 104813590Srekai.gonzalezalberquilla@arm.com 104913590Srekai.gonzalezalberquilla@arm.com if (ret) { 105013590Srekai.gonzalezalberquilla@arm.com if (!isLoad) { 105113590Srekai.gonzalezalberquilla@arm.com lsq->storePortBusy(); 105213590Srekai.gonzalezalberquilla@arm.com isStoreBlocked = false; 105313590Srekai.gonzalezalberquilla@arm.com } 105413590Srekai.gonzalezalberquilla@arm.com state->outstanding++; 105513590Srekai.gonzalezalberquilla@arm.com state->request()->packetSent(); 105613590Srekai.gonzalezalberquilla@arm.com } else { 105713590Srekai.gonzalezalberquilla@arm.com if (cache_got_blocked) { 105813590Srekai.gonzalezalberquilla@arm.com lsq->cacheBlocked(true); 105913590Srekai.gonzalezalberquilla@arm.com ++lsqCacheBlocked; 106013590Srekai.gonzalezalberquilla@arm.com } 106113590Srekai.gonzalezalberquilla@arm.com if (!isLoad) { 106213590Srekai.gonzalezalberquilla@arm.com assert(state->request() == storeWBIt->request()); 106313590Srekai.gonzalezalberquilla@arm.com isStoreBlocked = true; 106413590Srekai.gonzalezalberquilla@arm.com } 106513590Srekai.gonzalezalberquilla@arm.com state->request()->packetNotSent(); 106613590Srekai.gonzalezalberquilla@arm.com } 106713590Srekai.gonzalezalberquilla@arm.com 106813590Srekai.gonzalezalberquilla@arm.com return ret; 10696974Stjones1@inf.ed.ac.uk} 10706974Stjones1@inf.ed.ac.uk 10716974Stjones1@inf.ed.ac.uktemplate <class Impl> 10722693Sktlim@umich.eduvoid 10732693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 10742693Sktlim@umich.edu{ 10752698Sktlim@umich.edu if (isStoreBlocked) { 107613590Srekai.gonzalezalberquilla@arm.com DPRINTF(LSQUnit, "Receiving retry: blocked store\n"); 107713590Srekai.gonzalezalberquilla@arm.com writebackBlockedStore(); 10782693Sktlim@umich.edu } 10792693Sktlim@umich.edu} 10802693Sktlim@umich.edu 10812693Sktlim@umich.edutemplate <class Impl> 10822329SN/Avoid 10839440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::dumpInsts() const 10842329SN/A{ 10852329SN/A cprintf("Load store queue: Dumping instructions.\n"); 10862329SN/A cprintf("Load queue size: %i\n", loads); 10872329SN/A cprintf("Load queue: "); 10882329SN/A 108913590Srekai.gonzalezalberquilla@arm.com for (const auto& e: loadQueue) { 109013590Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst(e.instruction()); 10919440SAndreas.Sandberg@ARM.com cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 10922329SN/A } 10939440SAndreas.Sandberg@ARM.com cprintf("\n"); 10942329SN/A 10952329SN/A cprintf("Store queue size: %i\n", stores); 10962329SN/A cprintf("Store queue: "); 10972329SN/A 109813590Srekai.gonzalezalberquilla@arm.com for (const auto& e: storeQueue) { 109913590Srekai.gonzalezalberquilla@arm.com const DynInstPtr &inst(e.instruction()); 11009440SAndreas.Sandberg@ARM.com cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 11012329SN/A } 11022329SN/A 11032329SN/A cprintf("\n"); 11042329SN/A} 11059944Smatt.horsnell@ARM.com 110613590Srekai.gonzalezalberquilla@arm.comtemplate <class Impl> 110713590Srekai.gonzalezalberquilla@arm.comunsigned int 110813590Srekai.gonzalezalberquilla@arm.comLSQUnit<Impl>::cacheLineSize() 110913590Srekai.gonzalezalberquilla@arm.com{ 111013590Srekai.gonzalezalberquilla@arm.com return cpu->cacheLineSize(); 111113590Srekai.gonzalezalberquilla@arm.com} 111213590Srekai.gonzalezalberquilla@arm.com 11139944Smatt.horsnell@ARM.com#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__ 1114