lsq_unit_impl.hh revision 10149
19814Sandreas.hansson@arm.com 22292SN/A/* 310030SAli.Saidi@ARM.com * Copyright (c) 2010-2013 ARM Limited 47597Sminkyu.jeong@arm.com * All rights reserved 57597Sminkyu.jeong@arm.com * 67597Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 77597Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 87597Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 97597Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 107597Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 117597Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 127597Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 137597Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 147597Sminkyu.jeong@arm.com * 152292SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 162292SN/A * All rights reserved. 172292SN/A * 182292SN/A * Redistribution and use in source and binary forms, with or without 192292SN/A * modification, are permitted provided that the following conditions are 202292SN/A * met: redistributions of source code must retain the above copyright 212292SN/A * notice, this list of conditions and the following disclaimer; 222292SN/A * redistributions in binary form must reproduce the above copyright 232292SN/A * notice, this list of conditions and the following disclaimer in the 242292SN/A * documentation and/or other materials provided with the distribution; 252292SN/A * neither the name of the copyright holders nor the names of its 262292SN/A * contributors may be used to endorse or promote products derived from 272292SN/A * this software without specific prior written permission. 282292SN/A * 292292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 302292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 312292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 352292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 362292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 372292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 392292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402689Sktlim@umich.edu * 412689Sktlim@umich.edu * Authors: Kevin Lim 422689Sktlim@umich.edu * Korey Sewell 432292SN/A */ 442292SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_LSQ_UNIT_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_LSQ_UNIT_IMPL_HH__ 479944Smatt.horsnell@ARM.com 488591Sgblack@eecs.umich.edu#include "arch/generic/debugfaults.hh" 493326Sktlim@umich.edu#include "arch/locked_mem.hh" 508229Snate@binkert.org#include "base/str.hh" 516658Snate@binkert.org#include "config/the_isa.hh" 528887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 532907Sktlim@umich.edu#include "cpu/o3/lsq.hh" 542292SN/A#include "cpu/o3/lsq_unit.hh" 558232Snate@binkert.org#include "debug/Activity.hh" 568232Snate@binkert.org#include "debug/IEW.hh" 578232Snate@binkert.org#include "debug/LSQUnit.hh" 589527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 592722Sktlim@umich.edu#include "mem/packet.hh" 602669Sktlim@umich.edu#include "mem/request.hh" 612292SN/A 622669Sktlim@umich.edutemplate<class Impl> 632678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt, 642678Sktlim@umich.edu LSQUnit *lsq_ptr) 658581Ssteve.reinhardt@amd.com : Event(Default_Pri, AutoDelete), 668581Ssteve.reinhardt@amd.com inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr) 672292SN/A{ 682292SN/A} 692292SN/A 702669Sktlim@umich.edutemplate<class Impl> 712292SN/Avoid 722678Sktlim@umich.eduLSQUnit<Impl>::WritebackEvent::process() 732292SN/A{ 749444SAndreas.Sandberg@ARM.com assert(!lsqPtr->cpu->switchedOut()); 759444SAndreas.Sandberg@ARM.com 769444SAndreas.Sandberg@ARM.com lsqPtr->writeback(inst, pkt); 774319Sktlim@umich.edu 784319Sktlim@umich.edu if (pkt->senderState) 794319Sktlim@umich.edu delete pkt->senderState; 804319Sktlim@umich.edu 814319Sktlim@umich.edu delete pkt->req; 822678Sktlim@umich.edu delete pkt; 832678Sktlim@umich.edu} 842292SN/A 852678Sktlim@umich.edutemplate<class Impl> 862678Sktlim@umich.educonst char * 875336Shines@cs.fsu.eduLSQUnit<Impl>::WritebackEvent::description() const 882678Sktlim@umich.edu{ 894873Sstever@eecs.umich.edu return "Store writeback"; 902678Sktlim@umich.edu} 912292SN/A 922678Sktlim@umich.edutemplate<class Impl> 932678Sktlim@umich.eduvoid 942678Sktlim@umich.eduLSQUnit<Impl>::completeDataAccess(PacketPtr pkt) 952678Sktlim@umich.edu{ 962678Sktlim@umich.edu LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState); 972678Sktlim@umich.edu DynInstPtr inst = state->inst; 987852SMatt.Horsnell@arm.com DPRINTF(IEW, "Writeback event [sn:%lli].\n", inst->seqNum); 997852SMatt.Horsnell@arm.com DPRINTF(Activity, "Activity: Writeback event [sn:%lli].\n", inst->seqNum); 1002344SN/A 1012678Sktlim@umich.edu //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); 1022678Sktlim@umich.edu 1036974Stjones1@inf.ed.ac.uk // If this is a split access, wait until all packets are received. 1046974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && !state->complete()) { 1056974Stjones1@inf.ed.ac.uk delete pkt->req; 1066974Stjones1@inf.ed.ac.uk delete pkt; 1076974Stjones1@inf.ed.ac.uk return; 1086974Stjones1@inf.ed.ac.uk } 1096974Stjones1@inf.ed.ac.uk 1109444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 1119444SAndreas.Sandberg@ARM.com if (inst->isSquashed()) { 1122820Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 1132678Sktlim@umich.edu } else { 1142678Sktlim@umich.edu if (!state->noWB) { 1156974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !state->isSplit || 1166974Stjones1@inf.ed.ac.uk !state->isLoad) { 1176974Stjones1@inf.ed.ac.uk writeback(inst, pkt); 1186974Stjones1@inf.ed.ac.uk } else { 1196974Stjones1@inf.ed.ac.uk writeback(inst, state->mainPkt); 1206974Stjones1@inf.ed.ac.uk } 1212678Sktlim@umich.edu } 1222678Sktlim@umich.edu 1232678Sktlim@umich.edu if (inst->isStore()) { 1242678Sktlim@umich.edu completeStore(state->idx); 1252678Sktlim@umich.edu } 1262344SN/A } 1272307SN/A 1286974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->isSplit && state->isLoad) { 1296974Stjones1@inf.ed.ac.uk delete state->mainPkt->req; 1306974Stjones1@inf.ed.ac.uk delete state->mainPkt; 1316974Stjones1@inf.ed.ac.uk } 13210020Smatt.horsnell@ARM.com 13310020Smatt.horsnell@ARM.com pkt->req->setAccessLatency(); 13410023Smatt.horsnell@ARM.com cpu->ppDataAccessComplete->notify(std::make_pair(inst, pkt)); 13510023Smatt.horsnell@ARM.com 1362678Sktlim@umich.edu delete state; 1374032Sktlim@umich.edu delete pkt->req; 1382678Sktlim@umich.edu delete pkt; 1392292SN/A} 1402292SN/A 1412292SN/Atemplate <class Impl> 1422292SN/ALSQUnit<Impl>::LSQUnit() 1438545Ssaidi@eecs.umich.edu : loads(0), stores(0), storesToWB(0), cacheBlockMask(0), stalled(false), 1442678Sktlim@umich.edu isStoreBlocked(false), isLoadBlocked(false), 1458727Snilay@cs.wisc.edu loadBlockedHandled(false), storeInFlight(false), hasPendingPkt(false) 1462292SN/A{ 1472292SN/A} 1482292SN/A 1492292SN/Atemplate<class Impl> 1502292SN/Avoid 1515529Snate@binkert.orgLSQUnit<Impl>::init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 1525529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 1535529Snate@binkert.org unsigned id) 1542292SN/A{ 1554329Sktlim@umich.edu cpu = cpu_ptr; 1564329Sktlim@umich.edu iewStage = iew_ptr; 1574329Sktlim@umich.edu 1584329Sktlim@umich.edu DPRINTF(LSQUnit, "Creating LSQUnit%i object.\n",id); 1592292SN/A 1602907Sktlim@umich.edu lsq = lsq_ptr; 1612907Sktlim@umich.edu 1622292SN/A lsqID = id; 1632292SN/A 1642329SN/A // Add 1 for the sentinel entry (they are circular queues). 1652329SN/A LQEntries = maxLQEntries + 1; 1662329SN/A SQEntries = maxSQEntries + 1; 1672292SN/A 1689936SFaissal.Sleiman@arm.com //Due to uint8_t index in LSQSenderState 1699936SFaissal.Sleiman@arm.com assert(LQEntries <= 256); 1709936SFaissal.Sleiman@arm.com assert(SQEntries <= 256); 1719936SFaissal.Sleiman@arm.com 1722292SN/A loadQueue.resize(LQEntries); 1732292SN/A storeQueue.resize(SQEntries); 1742292SN/A 1758199SAli.Saidi@ARM.com depCheckShift = params->LSQDepCheckShift; 1768199SAli.Saidi@ARM.com checkLoads = params->LSQCheckLoads; 1779444SAndreas.Sandberg@ARM.com cachePorts = params->cachePorts; 1789444SAndreas.Sandberg@ARM.com needsTSO = params->needsTSO; 1799444SAndreas.Sandberg@ARM.com 1809444SAndreas.Sandberg@ARM.com resetState(); 1819444SAndreas.Sandberg@ARM.com} 1829444SAndreas.Sandberg@ARM.com 1839444SAndreas.Sandberg@ARM.com 1849444SAndreas.Sandberg@ARM.comtemplate<class Impl> 1859444SAndreas.Sandberg@ARM.comvoid 1869444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::resetState() 1879444SAndreas.Sandberg@ARM.com{ 1889444SAndreas.Sandberg@ARM.com loads = stores = storesToWB = 0; 1898199SAli.Saidi@ARM.com 1902292SN/A loadHead = loadTail = 0; 1912292SN/A 1922292SN/A storeHead = storeWBIdx = storeTail = 0; 1932292SN/A 1942292SN/A usedPorts = 0; 1952292SN/A 1963492Sktlim@umich.edu retryPkt = NULL; 1972329SN/A memDepViolator = NULL; 1982292SN/A 1992292SN/A blockedLoadSeqNum = 0; 2009444SAndreas.Sandberg@ARM.com 2019444SAndreas.Sandberg@ARM.com stalled = false; 2029444SAndreas.Sandberg@ARM.com isLoadBlocked = false; 2039444SAndreas.Sandberg@ARM.com loadBlockedHandled = false; 2049444SAndreas.Sandberg@ARM.com 2059814Sandreas.hansson@arm.com cacheBlockMask = ~(cpu->cacheLineSize() - 1); 2062292SN/A} 2072292SN/A 2082292SN/Atemplate<class Impl> 2092292SN/Astd::string 2102292SN/ALSQUnit<Impl>::name() const 2112292SN/A{ 2122292SN/A if (Impl::MaxThreads == 1) { 2132292SN/A return iewStage->name() + ".lsq"; 2142292SN/A } else { 2158247Snate@binkert.org return iewStage->name() + ".lsq.thread" + to_string(lsqID); 2162292SN/A } 2172292SN/A} 2182292SN/A 2192292SN/Atemplate<class Impl> 2202292SN/Avoid 2212727Sktlim@umich.eduLSQUnit<Impl>::regStats() 2222727Sktlim@umich.edu{ 2232727Sktlim@umich.edu lsqForwLoads 2242727Sktlim@umich.edu .name(name() + ".forwLoads") 2252727Sktlim@umich.edu .desc("Number of loads that had data forwarded from stores"); 2262727Sktlim@umich.edu 2272727Sktlim@umich.edu invAddrLoads 2282727Sktlim@umich.edu .name(name() + ".invAddrLoads") 2292727Sktlim@umich.edu .desc("Number of loads ignored due to an invalid address"); 2302727Sktlim@umich.edu 2312727Sktlim@umich.edu lsqSquashedLoads 2322727Sktlim@umich.edu .name(name() + ".squashedLoads") 2332727Sktlim@umich.edu .desc("Number of loads squashed"); 2342727Sktlim@umich.edu 2352727Sktlim@umich.edu lsqIgnoredResponses 2362727Sktlim@umich.edu .name(name() + ".ignoredResponses") 2372727Sktlim@umich.edu .desc("Number of memory responses ignored because the instruction is squashed"); 2382727Sktlim@umich.edu 2392361SN/A lsqMemOrderViolation 2402361SN/A .name(name() + ".memOrderViolation") 2412361SN/A .desc("Number of memory ordering violations"); 2422361SN/A 2432727Sktlim@umich.edu lsqSquashedStores 2442727Sktlim@umich.edu .name(name() + ".squashedStores") 2452727Sktlim@umich.edu .desc("Number of stores squashed"); 2462727Sktlim@umich.edu 2472727Sktlim@umich.edu invAddrSwpfs 2482727Sktlim@umich.edu .name(name() + ".invAddrSwpfs") 2492727Sktlim@umich.edu .desc("Number of software prefetches ignored due to an invalid address"); 2502727Sktlim@umich.edu 2512727Sktlim@umich.edu lsqBlockedLoads 2522727Sktlim@umich.edu .name(name() + ".blockedLoads") 2532727Sktlim@umich.edu .desc("Number of blocked loads due to partial load-store forwarding"); 2542727Sktlim@umich.edu 2552727Sktlim@umich.edu lsqRescheduledLoads 2562727Sktlim@umich.edu .name(name() + ".rescheduledLoads") 2572727Sktlim@umich.edu .desc("Number of loads that were rescheduled"); 2582727Sktlim@umich.edu 2592727Sktlim@umich.edu lsqCacheBlocked 2602727Sktlim@umich.edu .name(name() + ".cacheBlocked") 2612727Sktlim@umich.edu .desc("Number of times an access to memory failed due to the cache being blocked"); 2622727Sktlim@umich.edu} 2632727Sktlim@umich.edu 2642727Sktlim@umich.edutemplate<class Impl> 2652727Sktlim@umich.eduvoid 2668922Swilliam.wang@arm.comLSQUnit<Impl>::setDcachePort(MasterPort *dcache_port) 2674329Sktlim@umich.edu{ 2684329Sktlim@umich.edu dcachePort = dcache_port; 2694329Sktlim@umich.edu} 2704329Sktlim@umich.edu 2714329Sktlim@umich.edutemplate<class Impl> 2724329Sktlim@umich.eduvoid 2732292SN/ALSQUnit<Impl>::clearLQ() 2742292SN/A{ 2752292SN/A loadQueue.clear(); 2762292SN/A} 2772292SN/A 2782292SN/Atemplate<class Impl> 2792292SN/Avoid 2802292SN/ALSQUnit<Impl>::clearSQ() 2812292SN/A{ 2822292SN/A storeQueue.clear(); 2832292SN/A} 2842292SN/A 2852292SN/Atemplate<class Impl> 2862292SN/Avoid 2879444SAndreas.Sandberg@ARM.comLSQUnit<Impl>::drainSanityCheck() const 2882307SN/A{ 2899444SAndreas.Sandberg@ARM.com for (int i = 0; i < loadQueue.size(); ++i) 2902367SN/A assert(!loadQueue[i]); 2912307SN/A 2922329SN/A assert(storesToWB == 0); 2939444SAndreas.Sandberg@ARM.com assert(!retryPkt); 2942307SN/A} 2952307SN/A 2962307SN/Atemplate<class Impl> 2972307SN/Avoid 2982307SN/ALSQUnit<Impl>::takeOverFrom() 2992307SN/A{ 3009444SAndreas.Sandberg@ARM.com resetState(); 3012307SN/A} 3022307SN/A 3032307SN/Atemplate<class Impl> 3042307SN/Avoid 3052292SN/ALSQUnit<Impl>::resizeLQ(unsigned size) 3062292SN/A{ 3072329SN/A unsigned size_plus_sentinel = size + 1; 3082329SN/A assert(size_plus_sentinel >= LQEntries); 3092292SN/A 3102329SN/A if (size_plus_sentinel > LQEntries) { 3112329SN/A while (size_plus_sentinel > loadQueue.size()) { 3122292SN/A DynInstPtr dummy; 3132292SN/A loadQueue.push_back(dummy); 3142292SN/A LQEntries++; 3152292SN/A } 3162292SN/A } else { 3172329SN/A LQEntries = size_plus_sentinel; 3182292SN/A } 3192292SN/A 3209936SFaissal.Sleiman@arm.com assert(LQEntries <= 256); 3212292SN/A} 3222292SN/A 3232292SN/Atemplate<class Impl> 3242292SN/Avoid 3252292SN/ALSQUnit<Impl>::resizeSQ(unsigned size) 3262292SN/A{ 3272329SN/A unsigned size_plus_sentinel = size + 1; 3282329SN/A if (size_plus_sentinel > SQEntries) { 3292329SN/A while (size_plus_sentinel > storeQueue.size()) { 3302292SN/A SQEntry dummy; 3312292SN/A storeQueue.push_back(dummy); 3322292SN/A SQEntries++; 3332292SN/A } 3342292SN/A } else { 3352329SN/A SQEntries = size_plus_sentinel; 3362292SN/A } 3379936SFaissal.Sleiman@arm.com 3389936SFaissal.Sleiman@arm.com assert(SQEntries <= 256); 3392292SN/A} 3402292SN/A 3412292SN/Atemplate <class Impl> 3422292SN/Avoid 3432292SN/ALSQUnit<Impl>::insert(DynInstPtr &inst) 3442292SN/A{ 3452292SN/A assert(inst->isMemRef()); 3462292SN/A 3472292SN/A assert(inst->isLoad() || inst->isStore()); 3482292SN/A 3492292SN/A if (inst->isLoad()) { 3502292SN/A insertLoad(inst); 3512292SN/A } else { 3522292SN/A insertStore(inst); 3532292SN/A } 3542292SN/A 3552292SN/A inst->setInLSQ(); 3562292SN/A} 3572292SN/A 3582292SN/Atemplate <class Impl> 3592292SN/Avoid 3602292SN/ALSQUnit<Impl>::insertLoad(DynInstPtr &load_inst) 3612292SN/A{ 3622329SN/A assert((loadTail + 1) % LQEntries != loadHead); 3632329SN/A assert(loads < LQEntries); 3642292SN/A 3657720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting load PC %s, idx:%i [sn:%lli]\n", 3667720Sgblack@eecs.umich.edu load_inst->pcState(), loadTail, load_inst->seqNum); 3672292SN/A 3682292SN/A load_inst->lqIdx = loadTail; 3692292SN/A 3702292SN/A if (stores == 0) { 3712292SN/A load_inst->sqIdx = -1; 3722292SN/A } else { 3732292SN/A load_inst->sqIdx = storeTail; 3742292SN/A } 3752292SN/A 3762292SN/A loadQueue[loadTail] = load_inst; 3772292SN/A 3782292SN/A incrLdIdx(loadTail); 3792292SN/A 3802292SN/A ++loads; 3812292SN/A} 3822292SN/A 3832292SN/Atemplate <class Impl> 3842292SN/Avoid 3852292SN/ALSQUnit<Impl>::insertStore(DynInstPtr &store_inst) 3862292SN/A{ 3872292SN/A // Make sure it is not full before inserting an instruction. 3882292SN/A assert((storeTail + 1) % SQEntries != storeHead); 3892292SN/A assert(stores < SQEntries); 3902292SN/A 3917720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Inserting store PC %s, idx:%i [sn:%lli]\n", 3927720Sgblack@eecs.umich.edu store_inst->pcState(), storeTail, store_inst->seqNum); 3932292SN/A 3942292SN/A store_inst->sqIdx = storeTail; 3952292SN/A store_inst->lqIdx = loadTail; 3962292SN/A 3972292SN/A storeQueue[storeTail] = SQEntry(store_inst); 3982292SN/A 3992292SN/A incrStIdx(storeTail); 4002292SN/A 4012292SN/A ++stores; 4022292SN/A} 4032292SN/A 4042292SN/Atemplate <class Impl> 4052292SN/Atypename Impl::DynInstPtr 4062292SN/ALSQUnit<Impl>::getMemDepViolator() 4072292SN/A{ 4082292SN/A DynInstPtr temp = memDepViolator; 4092292SN/A 4102292SN/A memDepViolator = NULL; 4112292SN/A 4122292SN/A return temp; 4132292SN/A} 4142292SN/A 4152292SN/Atemplate <class Impl> 4162292SN/Aunsigned 4172292SN/ALSQUnit<Impl>::numFreeEntries() 4182292SN/A{ 4192292SN/A unsigned free_lq_entries = LQEntries - loads; 4202292SN/A unsigned free_sq_entries = SQEntries - stores; 4212292SN/A 4222292SN/A // Both the LQ and SQ entries have an extra dummy entry to differentiate 4232292SN/A // empty/full conditions. Subtract 1 from the free entries. 4242292SN/A if (free_lq_entries < free_sq_entries) { 4252292SN/A return free_lq_entries - 1; 4262292SN/A } else { 4272292SN/A return free_sq_entries - 1; 4282292SN/A } 4292292SN/A} 4302292SN/A 4312292SN/Atemplate <class Impl> 4328545Ssaidi@eecs.umich.eduvoid 4338545Ssaidi@eecs.umich.eduLSQUnit<Impl>::checkSnoop(PacketPtr pkt) 4348545Ssaidi@eecs.umich.edu{ 4358545Ssaidi@eecs.umich.edu int load_idx = loadHead; 43610030SAli.Saidi@ARM.com DPRINTF(LSQUnit, "Got snoop for address %#x\n", pkt->getAddr()); 4378545Ssaidi@eecs.umich.edu 4389383SAli.Saidi@ARM.com // Unlock the cpu-local monitor when the CPU sees a snoop to a locked 4399383SAli.Saidi@ARM.com // address. The CPU can speculatively execute a LL operation after a pending 4409383SAli.Saidi@ARM.com // SC operation in the pipeline and that can make the cache monitor the CPU 4419383SAli.Saidi@ARM.com // is connected to valid while it really shouldn't be. 44210030SAli.Saidi@ARM.com for (int x = 0; x < cpu->numContexts(); x++) { 4439383SAli.Saidi@ARM.com ThreadContext *tc = cpu->getContext(x); 4449383SAli.Saidi@ARM.com bool no_squash = cpu->thread[x]->noSquashFromTC; 4459383SAli.Saidi@ARM.com cpu->thread[x]->noSquashFromTC = true; 4469383SAli.Saidi@ARM.com TheISA::handleLockedSnoop(tc, pkt, cacheBlockMask); 4479383SAli.Saidi@ARM.com cpu->thread[x]->noSquashFromTC = no_squash; 4489383SAli.Saidi@ARM.com } 4499383SAli.Saidi@ARM.com 45010030SAli.Saidi@ARM.com Addr invalidate_addr = pkt->getAddr() & cacheBlockMask; 45110030SAli.Saidi@ARM.com 45210030SAli.Saidi@ARM.com DynInstPtr ld_inst = loadQueue[load_idx]; 45310030SAli.Saidi@ARM.com if (ld_inst) { 45410030SAli.Saidi@ARM.com Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 45510030SAli.Saidi@ARM.com // Check that this snoop didn't just invalidate our lock flag 45610030SAli.Saidi@ARM.com if (ld_inst->effAddrValid() && load_addr == invalidate_addr && 45710030SAli.Saidi@ARM.com ld_inst->memReqFlags & Request::LLSC) 45810030SAli.Saidi@ARM.com TheISA::handleLockedSnoopHit(ld_inst.get()); 45910030SAli.Saidi@ARM.com } 46010030SAli.Saidi@ARM.com 4618545Ssaidi@eecs.umich.edu // If this is the only load in the LSQ we don't care 4628545Ssaidi@eecs.umich.edu if (load_idx == loadTail) 4638545Ssaidi@eecs.umich.edu return; 46410030SAli.Saidi@ARM.com 4658545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4668545Ssaidi@eecs.umich.edu 46710149Smarco.elver@ed.ac.uk bool force_squash = false; 46810149Smarco.elver@ed.ac.uk 4698545Ssaidi@eecs.umich.edu while (load_idx != loadTail) { 4708545Ssaidi@eecs.umich.edu DynInstPtr ld_inst = loadQueue[load_idx]; 4718545Ssaidi@eecs.umich.edu 4729046SAli.Saidi@ARM.com if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 4738545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 4748545Ssaidi@eecs.umich.edu continue; 4758545Ssaidi@eecs.umich.edu } 4768545Ssaidi@eecs.umich.edu 4778545Ssaidi@eecs.umich.edu Addr load_addr = ld_inst->physEffAddr & cacheBlockMask; 4788545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "-- inst [sn:%lli] load_addr: %#x to pktAddr:%#x\n", 4798545Ssaidi@eecs.umich.edu ld_inst->seqNum, load_addr, invalidate_addr); 4808545Ssaidi@eecs.umich.edu 48110149Smarco.elver@ed.ac.uk if (load_addr == invalidate_addr || force_squash) { 48210149Smarco.elver@ed.ac.uk if (needsTSO) { 48310149Smarco.elver@ed.ac.uk // If we have a TSO system, as all loads must be ordered with 48410149Smarco.elver@ed.ac.uk // all other loads, this load as well as *all* subsequent loads 48510149Smarco.elver@ed.ac.uk // need to be squashed to prevent possible load reordering. 48610149Smarco.elver@ed.ac.uk force_squash = true; 48710149Smarco.elver@ed.ac.uk } 48810149Smarco.elver@ed.ac.uk if (ld_inst->possibleLoadViolation() || force_squash) { 4898545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Conflicting load at addr %#x [sn:%lli]\n", 49010030SAli.Saidi@ARM.com pkt->getAddr(), ld_inst->seqNum); 4918545Ssaidi@eecs.umich.edu 4928545Ssaidi@eecs.umich.edu // Mark the load for re-execution 4938545Ssaidi@eecs.umich.edu ld_inst->fault = new ReExec; 4948545Ssaidi@eecs.umich.edu } else { 49510030SAli.Saidi@ARM.com DPRINTF(LSQUnit, "HitExternal Snoop for addr %#x [sn:%lli]\n", 49610030SAli.Saidi@ARM.com pkt->getAddr(), ld_inst->seqNum); 49710030SAli.Saidi@ARM.com 49810030SAli.Saidi@ARM.com // Make sure that we don't lose a snoop hitting a LOCKED 49910030SAli.Saidi@ARM.com // address since the LOCK* flags don't get updated until 50010030SAli.Saidi@ARM.com // commit. 50110030SAli.Saidi@ARM.com if (ld_inst->memReqFlags & Request::LLSC) 50210030SAli.Saidi@ARM.com TheISA::handleLockedSnoopHit(ld_inst.get()); 50310030SAli.Saidi@ARM.com 5048545Ssaidi@eecs.umich.edu // If a older load checks this and it's true 5058545Ssaidi@eecs.umich.edu // then we might have missed the snoop 5068545Ssaidi@eecs.umich.edu // in which case we need to invalidate to be sure 5079046SAli.Saidi@ARM.com ld_inst->hitExternalSnoop(true); 5088545Ssaidi@eecs.umich.edu } 5098545Ssaidi@eecs.umich.edu } 5108545Ssaidi@eecs.umich.edu incrLdIdx(load_idx); 5118545Ssaidi@eecs.umich.edu } 5128545Ssaidi@eecs.umich.edu return; 5138545Ssaidi@eecs.umich.edu} 5148545Ssaidi@eecs.umich.edu 5158545Ssaidi@eecs.umich.edutemplate <class Impl> 5162292SN/AFault 5178199SAli.Saidi@ARM.comLSQUnit<Impl>::checkViolations(int load_idx, DynInstPtr &inst) 5188199SAli.Saidi@ARM.com{ 5198199SAli.Saidi@ARM.com Addr inst_eff_addr1 = inst->effAddr >> depCheckShift; 5208199SAli.Saidi@ARM.com Addr inst_eff_addr2 = (inst->effAddr + inst->effSize - 1) >> depCheckShift; 5218199SAli.Saidi@ARM.com 5228199SAli.Saidi@ARM.com /** @todo in theory you only need to check an instruction that has executed 5238199SAli.Saidi@ARM.com * however, there isn't a good way in the pipeline at the moment to check 5248199SAli.Saidi@ARM.com * all instructions that will execute before the store writes back. Thus, 5258199SAli.Saidi@ARM.com * like the implementation that came before it, we're overly conservative. 5268199SAli.Saidi@ARM.com */ 5278199SAli.Saidi@ARM.com while (load_idx != loadTail) { 5288199SAli.Saidi@ARM.com DynInstPtr ld_inst = loadQueue[load_idx]; 5299046SAli.Saidi@ARM.com if (!ld_inst->effAddrValid() || ld_inst->uncacheable()) { 5308199SAli.Saidi@ARM.com incrLdIdx(load_idx); 5318199SAli.Saidi@ARM.com continue; 5328199SAli.Saidi@ARM.com } 5338199SAli.Saidi@ARM.com 5348199SAli.Saidi@ARM.com Addr ld_eff_addr1 = ld_inst->effAddr >> depCheckShift; 5358199SAli.Saidi@ARM.com Addr ld_eff_addr2 = 5368199SAli.Saidi@ARM.com (ld_inst->effAddr + ld_inst->effSize - 1) >> depCheckShift; 5378199SAli.Saidi@ARM.com 5388272SAli.Saidi@ARM.com if (inst_eff_addr2 >= ld_eff_addr1 && inst_eff_addr1 <= ld_eff_addr2) { 5398545Ssaidi@eecs.umich.edu if (inst->isLoad()) { 5408545Ssaidi@eecs.umich.edu // If this load is to the same block as an external snoop 5418545Ssaidi@eecs.umich.edu // invalidate that we've observed then the load needs to be 5428545Ssaidi@eecs.umich.edu // squashed as it could have newer data 5439046SAli.Saidi@ARM.com if (ld_inst->hitExternalSnoop()) { 5448545Ssaidi@eecs.umich.edu if (!memDepViolator || 5458545Ssaidi@eecs.umich.edu ld_inst->seqNum < memDepViolator->seqNum) { 5468545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] " 5478592Sgblack@eecs.umich.edu "and [sn:%lli] at address %#x\n", 5488592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5498545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5508199SAli.Saidi@ARM.com 5518545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5528199SAli.Saidi@ARM.com 5538591Sgblack@eecs.umich.edu return new GenericISA::M5PanicFault( 5548591Sgblack@eecs.umich.edu "Detected fault with inst [sn:%lli] and " 5558591Sgblack@eecs.umich.edu "[sn:%lli] at address %#x\n", 5568591Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5578545Ssaidi@eecs.umich.edu } 5588545Ssaidi@eecs.umich.edu } 5598199SAli.Saidi@ARM.com 5608545Ssaidi@eecs.umich.edu // Otherwise, mark the load has a possible load violation 5618545Ssaidi@eecs.umich.edu // and if we see a snoop before it's commited, we need to squash 5629046SAli.Saidi@ARM.com ld_inst->possibleLoadViolation(true); 5638545Ssaidi@eecs.umich.edu DPRINTF(LSQUnit, "Found possible load violaiton at addr: %#x" 5648545Ssaidi@eecs.umich.edu " between instructions [sn:%lli] and [sn:%lli]\n", 5658545Ssaidi@eecs.umich.edu inst_eff_addr1, inst->seqNum, ld_inst->seqNum); 5668545Ssaidi@eecs.umich.edu } else { 5678545Ssaidi@eecs.umich.edu // A load/store incorrectly passed this store. 5688545Ssaidi@eecs.umich.edu // Check if we already have a violator, or if it's newer 5698545Ssaidi@eecs.umich.edu // squash and refetch. 5708545Ssaidi@eecs.umich.edu if (memDepViolator && ld_inst->seqNum > memDepViolator->seqNum) 5718545Ssaidi@eecs.umich.edu break; 5728545Ssaidi@eecs.umich.edu 5738592Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Detected fault with inst [sn:%lli] and " 5748592Sgblack@eecs.umich.edu "[sn:%lli] at address %#x\n", 5758592Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5768545Ssaidi@eecs.umich.edu memDepViolator = ld_inst; 5778545Ssaidi@eecs.umich.edu 5788545Ssaidi@eecs.umich.edu ++lsqMemOrderViolation; 5798545Ssaidi@eecs.umich.edu 5808591Sgblack@eecs.umich.edu return new GenericISA::M5PanicFault("Detected fault with " 5818591Sgblack@eecs.umich.edu "inst [sn:%lli] and [sn:%lli] at address %#x\n", 5828591Sgblack@eecs.umich.edu inst->seqNum, ld_inst->seqNum, ld_eff_addr1); 5838545Ssaidi@eecs.umich.edu } 5848199SAli.Saidi@ARM.com } 5858199SAli.Saidi@ARM.com 5868199SAli.Saidi@ARM.com incrLdIdx(load_idx); 5878199SAli.Saidi@ARM.com } 5888199SAli.Saidi@ARM.com return NoFault; 5898199SAli.Saidi@ARM.com} 5908199SAli.Saidi@ARM.com 5918199SAli.Saidi@ARM.com 5928199SAli.Saidi@ARM.com 5938199SAli.Saidi@ARM.com 5948199SAli.Saidi@ARM.comtemplate <class Impl> 5958199SAli.Saidi@ARM.comFault 5962292SN/ALSQUnit<Impl>::executeLoad(DynInstPtr &inst) 5972292SN/A{ 5984032Sktlim@umich.edu using namespace TheISA; 5992292SN/A // Execute a specific load. 6002292SN/A Fault load_fault = NoFault; 6012292SN/A 6027720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing load PC %s, [sn:%lli]\n", 6037944SGiacomo.Gabrielli@arm.com inst->pcState(), inst->seqNum); 6042292SN/A 6054032Sktlim@umich.edu assert(!inst->isSquashed()); 6064032Sktlim@umich.edu 6072669Sktlim@umich.edu load_fault = inst->initiateAcc(); 6082292SN/A 6097944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 6107944SGiacomo.Gabrielli@arm.com load_fault == NoFault) 6117944SGiacomo.Gabrielli@arm.com return load_fault; 6127944SGiacomo.Gabrielli@arm.com 6137597Sminkyu.jeong@arm.com // If the instruction faulted or predicated false, then we need to send it 6147597Sminkyu.jeong@arm.com // along to commit without the instruction completing. 6157597Sminkyu.jeong@arm.com if (load_fault != NoFault || inst->readPredicate() == false) { 6162329SN/A // Send this instruction to commit, also make sure iew stage 6172329SN/A // realizes there is activity. 6182367SN/A // Mark it as executed unless it is an uncached load that 6192367SN/A // needs to hit the head of commit. 6207848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 6217848SAli.Saidi@ARM.com inst->forwardOldRegs(); 6227600Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Load [sn:%lli] not executed from %s\n", 6237600Sminkyu.jeong@arm.com inst->seqNum, 6247600Sminkyu.jeong@arm.com (load_fault != NoFault ? "fault" : "predication")); 6254032Sktlim@umich.edu if (!(inst->hasRequest() && inst->uncacheable()) || 6263731Sktlim@umich.edu inst->isAtCommit()) { 6272367SN/A inst->setExecuted(); 6282367SN/A } 6292292SN/A iewStage->instToCommit(inst); 6302292SN/A iewStage->activityThisCycle(); 6314032Sktlim@umich.edu } else if (!loadBlocked()) { 6329046SAli.Saidi@ARM.com assert(inst->effAddrValid()); 6334032Sktlim@umich.edu int load_idx = inst->lqIdx; 6344032Sktlim@umich.edu incrLdIdx(load_idx); 6354032Sktlim@umich.edu 6368199SAli.Saidi@ARM.com if (checkLoads) 6378199SAli.Saidi@ARM.com return checkViolations(load_idx, inst); 6382292SN/A } 6392292SN/A 6402292SN/A return load_fault; 6412292SN/A} 6422292SN/A 6432292SN/Atemplate <class Impl> 6442292SN/AFault 6452292SN/ALSQUnit<Impl>::executeStore(DynInstPtr &store_inst) 6462292SN/A{ 6472292SN/A using namespace TheISA; 6482292SN/A // Make sure that a store exists. 6492292SN/A assert(stores != 0); 6502292SN/A 6512292SN/A int store_idx = store_inst->sqIdx; 6522292SN/A 6537720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Executing store PC %s [sn:%lli]\n", 6547720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6552292SN/A 6564032Sktlim@umich.edu assert(!store_inst->isSquashed()); 6574032Sktlim@umich.edu 6582292SN/A // Check the recently completed loads to see if any match this store's 6592292SN/A // address. If so, then we have a memory ordering violation. 6602292SN/A int load_idx = store_inst->lqIdx; 6612292SN/A 6622292SN/A Fault store_fault = store_inst->initiateAcc(); 6632292SN/A 6647944SGiacomo.Gabrielli@arm.com if (store_inst->isTranslationDelayed() && 6657944SGiacomo.Gabrielli@arm.com store_fault == NoFault) 6667944SGiacomo.Gabrielli@arm.com return store_fault; 6677944SGiacomo.Gabrielli@arm.com 6687848SAli.Saidi@ARM.com if (store_inst->readPredicate() == false) 6697848SAli.Saidi@ARM.com store_inst->forwardOldRegs(); 6707848SAli.Saidi@ARM.com 6712329SN/A if (storeQueue[store_idx].size == 0) { 6727782Sminkyu.jeong@arm.com DPRINTF(LSQUnit,"Fault on Store PC %s, [sn:%lli], Size = 0\n", 6737720Sgblack@eecs.umich.edu store_inst->pcState(), store_inst->seqNum); 6742292SN/A 6752292SN/A return store_fault; 6767782Sminkyu.jeong@arm.com } else if (store_inst->readPredicate() == false) { 6777782Sminkyu.jeong@arm.com DPRINTF(LSQUnit, "Store [sn:%lli] not executed from predication\n", 6787782Sminkyu.jeong@arm.com store_inst->seqNum); 6797782Sminkyu.jeong@arm.com return store_fault; 6802292SN/A } 6812292SN/A 6822292SN/A assert(store_fault == NoFault); 6832292SN/A 6842336SN/A if (store_inst->isStoreConditional()) { 6852336SN/A // Store conditionals need to set themselves as able to 6862336SN/A // writeback if we haven't had a fault by here. 6872329SN/A storeQueue[store_idx].canWB = true; 6882292SN/A 6892329SN/A ++storesToWB; 6902292SN/A } 6912292SN/A 6928199SAli.Saidi@ARM.com return checkViolations(load_idx, store_inst); 6932292SN/A 6942292SN/A} 6952292SN/A 6962292SN/Atemplate <class Impl> 6972292SN/Avoid 6982292SN/ALSQUnit<Impl>::commitLoad() 6992292SN/A{ 7002292SN/A assert(loadQueue[loadHead]); 7012292SN/A 7027720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Committing head load instruction, PC %s\n", 7037720Sgblack@eecs.umich.edu loadQueue[loadHead]->pcState()); 7042292SN/A 7052292SN/A loadQueue[loadHead] = NULL; 7062292SN/A 7072292SN/A incrLdIdx(loadHead); 7082292SN/A 7092292SN/A --loads; 7102292SN/A} 7112292SN/A 7122292SN/Atemplate <class Impl> 7132292SN/Avoid 7142292SN/ALSQUnit<Impl>::commitLoads(InstSeqNum &youngest_inst) 7152292SN/A{ 7162292SN/A assert(loads == 0 || loadQueue[loadHead]); 7172292SN/A 7182292SN/A while (loads != 0 && loadQueue[loadHead]->seqNum <= youngest_inst) { 7192292SN/A commitLoad(); 7202292SN/A } 7212292SN/A} 7222292SN/A 7232292SN/Atemplate <class Impl> 7242292SN/Avoid 7252292SN/ALSQUnit<Impl>::commitStores(InstSeqNum &youngest_inst) 7262292SN/A{ 7272292SN/A assert(stores == 0 || storeQueue[storeHead].inst); 7282292SN/A 7292292SN/A int store_idx = storeHead; 7302292SN/A 7312292SN/A while (store_idx != storeTail) { 7322292SN/A assert(storeQueue[store_idx].inst); 7332329SN/A // Mark any stores that are now committed and have not yet 7342329SN/A // been marked as able to write back. 7352292SN/A if (!storeQueue[store_idx].canWB) { 7362292SN/A if (storeQueue[store_idx].inst->seqNum > youngest_inst) { 7372292SN/A break; 7382292SN/A } 7392292SN/A DPRINTF(LSQUnit, "Marking store as able to write back, PC " 7407720Sgblack@eecs.umich.edu "%s [sn:%lli]\n", 7417720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 7422292SN/A storeQueue[store_idx].inst->seqNum); 7432292SN/A 7442292SN/A storeQueue[store_idx].canWB = true; 7452292SN/A 7462292SN/A ++storesToWB; 7472292SN/A } 7482292SN/A 7492292SN/A incrStIdx(store_idx); 7502292SN/A } 7512292SN/A} 7522292SN/A 7532292SN/Atemplate <class Impl> 7542292SN/Avoid 7556974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::writebackPendingStore() 7566974Stjones1@inf.ed.ac.uk{ 7576974Stjones1@inf.ed.ac.uk if (hasPendingPkt) { 7586974Stjones1@inf.ed.ac.uk assert(pendingPkt != NULL); 7596974Stjones1@inf.ed.ac.uk 7606974Stjones1@inf.ed.ac.uk // If the cache is blocked, this will store the packet for retry. 7616974Stjones1@inf.ed.ac.uk if (sendStore(pendingPkt)) { 7626974Stjones1@inf.ed.ac.uk storePostSend(pendingPkt); 7636974Stjones1@inf.ed.ac.uk } 7646974Stjones1@inf.ed.ac.uk pendingPkt = NULL; 7656974Stjones1@inf.ed.ac.uk hasPendingPkt = false; 7666974Stjones1@inf.ed.ac.uk } 7676974Stjones1@inf.ed.ac.uk} 7686974Stjones1@inf.ed.ac.uk 7696974Stjones1@inf.ed.ac.uktemplate <class Impl> 7706974Stjones1@inf.ed.ac.ukvoid 7712292SN/ALSQUnit<Impl>::writebackStores() 7722292SN/A{ 7736974Stjones1@inf.ed.ac.uk // First writeback the second packet from any split store that didn't 7746974Stjones1@inf.ed.ac.uk // complete last cycle because there weren't enough cache ports available. 7756974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc) { 7766974Stjones1@inf.ed.ac.uk writebackPendingStore(); 7776974Stjones1@inf.ed.ac.uk } 7786974Stjones1@inf.ed.ac.uk 7792292SN/A while (storesToWB > 0 && 7802292SN/A storeWBIdx != storeTail && 7812292SN/A storeQueue[storeWBIdx].inst && 7822292SN/A storeQueue[storeWBIdx].canWB && 7838727Snilay@cs.wisc.edu ((!needsTSO) || (!storeInFlight)) && 7842292SN/A usedPorts < cachePorts) { 7852292SN/A 7862907Sktlim@umich.edu if (isStoreBlocked || lsq->cacheBlocked()) { 7872678Sktlim@umich.edu DPRINTF(LSQUnit, "Unable to write back any more stores, cache" 7882678Sktlim@umich.edu " is blocked!\n"); 7892678Sktlim@umich.edu break; 7902678Sktlim@umich.edu } 7912678Sktlim@umich.edu 7922329SN/A // Store didn't write any data so no need to write it back to 7932329SN/A // memory. 7942292SN/A if (storeQueue[storeWBIdx].size == 0) { 7952292SN/A completeStore(storeWBIdx); 7962292SN/A 7972292SN/A incrStIdx(storeWBIdx); 7982292SN/A 7992292SN/A continue; 8002292SN/A } 8012678Sktlim@umich.edu 8022292SN/A ++usedPorts; 8032292SN/A 8042292SN/A if (storeQueue[storeWBIdx].inst->isDataPrefetch()) { 8052292SN/A incrStIdx(storeWBIdx); 8062292SN/A 8072292SN/A continue; 8082292SN/A } 8092292SN/A 8102292SN/A assert(storeQueue[storeWBIdx].req); 8112292SN/A assert(!storeQueue[storeWBIdx].committed); 8122292SN/A 8136974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit) { 8146974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqLow); 8156974Stjones1@inf.ed.ac.uk assert(storeQueue[storeWBIdx].sreqHigh); 8166974Stjones1@inf.ed.ac.uk } 8176974Stjones1@inf.ed.ac.uk 8182669Sktlim@umich.edu DynInstPtr inst = storeQueue[storeWBIdx].inst; 8192669Sktlim@umich.edu 8202669Sktlim@umich.edu Request *req = storeQueue[storeWBIdx].req; 8218481Sgblack@eecs.umich.edu RequestPtr sreqLow = storeQueue[storeWBIdx].sreqLow; 8228481Sgblack@eecs.umich.edu RequestPtr sreqHigh = storeQueue[storeWBIdx].sreqHigh; 8238481Sgblack@eecs.umich.edu 8242292SN/A storeQueue[storeWBIdx].committed = true; 8252292SN/A 8262669Sktlim@umich.edu assert(!inst->memData); 82710031SAli.Saidi@ARM.com inst->memData = new uint8_t[req->getSize()]; 8283772Sgblack@eecs.umich.edu 82910031SAli.Saidi@ARM.com if (storeQueue[storeWBIdx].isAllZeros) 83010031SAli.Saidi@ARM.com memset(inst->memData, 0, req->getSize()); 83110031SAli.Saidi@ARM.com else 83210031SAli.Saidi@ARM.com memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); 8332669Sktlim@umich.edu 8344878Sstever@eecs.umich.edu MemCmd command = 8354878Sstever@eecs.umich.edu req->isSwap() ? MemCmd::SwapReq : 8366102Sgblack@eecs.umich.edu (req->isLLSC() ? MemCmd::StoreCondReq : MemCmd::WriteReq); 8376974Stjones1@inf.ed.ac.uk PacketPtr data_pkt; 8386974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 8392292SN/A 8402678Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 8412678Sktlim@umich.edu state->isLoad = false; 8422678Sktlim@umich.edu state->idx = storeWBIdx; 8432678Sktlim@umich.edu state->inst = inst; 8446974Stjones1@inf.ed.ac.uk 8456974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !storeQueue[storeWBIdx].isSplit) { 8466974Stjones1@inf.ed.ac.uk 8476974Stjones1@inf.ed.ac.uk // Build a single data packet if the store isn't split. 8488949Sandreas.hansson@arm.com data_pkt = new Packet(req, command); 8496974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8506974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8516974Stjones1@inf.ed.ac.uk } else { 8526974Stjones1@inf.ed.ac.uk // Create two packets if the store is split in two. 8538949Sandreas.hansson@arm.com data_pkt = new Packet(sreqLow, command); 8548949Sandreas.hansson@arm.com snd_data_pkt = new Packet(sreqHigh, command); 8556974Stjones1@inf.ed.ac.uk 8566974Stjones1@inf.ed.ac.uk data_pkt->dataStatic(inst->memData); 8576974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(inst->memData + sreqLow->getSize()); 8586974Stjones1@inf.ed.ac.uk 8596974Stjones1@inf.ed.ac.uk data_pkt->senderState = state; 8606974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 8616974Stjones1@inf.ed.ac.uk 8626974Stjones1@inf.ed.ac.uk state->isSplit = true; 8636974Stjones1@inf.ed.ac.uk state->outstanding = 2; 8646974Stjones1@inf.ed.ac.uk 8656974Stjones1@inf.ed.ac.uk // Can delete the main request now. 8666974Stjones1@inf.ed.ac.uk delete req; 8676974Stjones1@inf.ed.ac.uk req = sreqLow; 8686974Stjones1@inf.ed.ac.uk } 8692678Sktlim@umich.edu 8707720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "D-Cache: Writing back store idx:%i PC:%s " 8712292SN/A "to Addr:%#x, data:%#x [sn:%lli]\n", 8727720Sgblack@eecs.umich.edu storeWBIdx, inst->pcState(), 8733797Sgblack@eecs.umich.edu req->getPaddr(), (int)*(inst->memData), 8743221Sktlim@umich.edu inst->seqNum); 8752292SN/A 8762693Sktlim@umich.edu // @todo: Remove this SC hack once the memory system handles it. 8774350Sgblack@eecs.umich.edu if (inst->isStoreConditional()) { 8786974Stjones1@inf.ed.ac.uk assert(!storeQueue[storeWBIdx].isSplit); 8793326Sktlim@umich.edu // Disable recording the result temporarily. Writing to 8803326Sktlim@umich.edu // misc regs normally updates the result, but this is not 8813326Sktlim@umich.edu // the desired behavior when handling store conditionals. 8829046SAli.Saidi@ARM.com inst->recordResult(false); 88310030SAli.Saidi@ARM.com bool success = TheISA::handleLockedWrite(inst.get(), req, cacheBlockMask); 8849046SAli.Saidi@ARM.com inst->recordResult(true); 8853326Sktlim@umich.edu 8863326Sktlim@umich.edu if (!success) { 8873326Sktlim@umich.edu // Instantly complete this store. 8883326Sktlim@umich.edu DPRINTF(LSQUnit, "Store conditional [sn:%lli] failed. " 8893326Sktlim@umich.edu "Instantly completing it.\n", 8903326Sktlim@umich.edu inst->seqNum); 8913326Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(inst, data_pkt, this); 8927823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick() + 1); 8938887Sgeoffrey.blake@arm.com if (cpu->checker) { 8948887Sgeoffrey.blake@arm.com // Make sure to set the LLSC data for verification 8958887Sgeoffrey.blake@arm.com // if checker is loaded 8968887Sgeoffrey.blake@arm.com inst->reqToVerify->setExtraData(0); 8978887Sgeoffrey.blake@arm.com inst->completeAcc(data_pkt); 8988887Sgeoffrey.blake@arm.com } 8993326Sktlim@umich.edu completeStore(storeWBIdx); 9003326Sktlim@umich.edu incrStIdx(storeWBIdx); 9013326Sktlim@umich.edu continue; 9022693Sktlim@umich.edu } 9032693Sktlim@umich.edu } else { 9042693Sktlim@umich.edu // Non-store conditionals do not need a writeback. 9052693Sktlim@umich.edu state->noWB = true; 9062693Sktlim@umich.edu } 9072693Sktlim@umich.edu 9088481Sgblack@eecs.umich.edu bool split = 9098481Sgblack@eecs.umich.edu TheISA::HasUnalignedMemAcc && storeQueue[storeWBIdx].isSplit; 9108481Sgblack@eecs.umich.edu 9118481Sgblack@eecs.umich.edu ThreadContext *thread = cpu->tcBase(lsqID); 9128481Sgblack@eecs.umich.edu 9138481Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 9148481Sgblack@eecs.umich.edu assert(!inst->isStoreConditional()); 9158481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, data_pkt); 9168481Sgblack@eecs.umich.edu delete data_pkt; 9178481Sgblack@eecs.umich.edu if (split) { 9188481Sgblack@eecs.umich.edu assert(snd_data_pkt->req->isMmappedIpr()); 9198481Sgblack@eecs.umich.edu TheISA::handleIprWrite(thread, snd_data_pkt); 9208481Sgblack@eecs.umich.edu delete snd_data_pkt; 9218481Sgblack@eecs.umich.edu delete sreqLow; 9228481Sgblack@eecs.umich.edu delete sreqHigh; 9238481Sgblack@eecs.umich.edu } 9248481Sgblack@eecs.umich.edu delete state; 9258481Sgblack@eecs.umich.edu delete req; 9268481Sgblack@eecs.umich.edu completeStore(storeWBIdx); 9278481Sgblack@eecs.umich.edu incrStIdx(storeWBIdx); 9288481Sgblack@eecs.umich.edu } else if (!sendStore(data_pkt)) { 9294032Sktlim@umich.edu DPRINTF(IEW, "D-Cache became blocked when writing [sn:%lli], will" 9303221Sktlim@umich.edu "retry later\n", 9313221Sktlim@umich.edu inst->seqNum); 9326974Stjones1@inf.ed.ac.uk 9336974Stjones1@inf.ed.ac.uk // Need to store the second packet, if split. 9348481Sgblack@eecs.umich.edu if (split) { 9356974Stjones1@inf.ed.ac.uk state->pktToSend = true; 9366974Stjones1@inf.ed.ac.uk state->pendingPacket = snd_data_pkt; 9376974Stjones1@inf.ed.ac.uk } 9382669Sktlim@umich.edu } else { 9396974Stjones1@inf.ed.ac.uk 9406974Stjones1@inf.ed.ac.uk // If split, try to send the second packet too 9418481Sgblack@eecs.umich.edu if (split) { 9426974Stjones1@inf.ed.ac.uk assert(snd_data_pkt); 9436974Stjones1@inf.ed.ac.uk 9446974Stjones1@inf.ed.ac.uk // Ensure there are enough ports to use. 9456974Stjones1@inf.ed.ac.uk if (usedPorts < cachePorts) { 9466974Stjones1@inf.ed.ac.uk ++usedPorts; 9476974Stjones1@inf.ed.ac.uk if (sendStore(snd_data_pkt)) { 9486974Stjones1@inf.ed.ac.uk storePostSend(snd_data_pkt); 9496974Stjones1@inf.ed.ac.uk } else { 9506974Stjones1@inf.ed.ac.uk DPRINTF(IEW, "D-Cache became blocked when writing" 9516974Stjones1@inf.ed.ac.uk " [sn:%lli] second packet, will retry later\n", 9526974Stjones1@inf.ed.ac.uk inst->seqNum); 9536974Stjones1@inf.ed.ac.uk } 9546974Stjones1@inf.ed.ac.uk } else { 9556974Stjones1@inf.ed.ac.uk 9566974Stjones1@inf.ed.ac.uk // Store the packet for when there's free ports. 9576974Stjones1@inf.ed.ac.uk assert(pendingPkt == NULL); 9586974Stjones1@inf.ed.ac.uk pendingPkt = snd_data_pkt; 9596974Stjones1@inf.ed.ac.uk hasPendingPkt = true; 9606974Stjones1@inf.ed.ac.uk } 9616974Stjones1@inf.ed.ac.uk } else { 9626974Stjones1@inf.ed.ac.uk 9636974Stjones1@inf.ed.ac.uk // Not a split store. 9646974Stjones1@inf.ed.ac.uk storePostSend(data_pkt); 9656974Stjones1@inf.ed.ac.uk } 9662292SN/A } 9672292SN/A } 9682292SN/A 9692292SN/A // Not sure this should set it to 0. 9702292SN/A usedPorts = 0; 9712292SN/A 9722292SN/A assert(stores >= 0 && storesToWB >= 0); 9732292SN/A} 9742292SN/A 9752292SN/A/*template <class Impl> 9762292SN/Avoid 9772292SN/ALSQUnit<Impl>::removeMSHR(InstSeqNum seqNum) 9782292SN/A{ 9792292SN/A list<InstSeqNum>::iterator mshr_it = find(mshrSeqNums.begin(), 9802292SN/A mshrSeqNums.end(), 9812292SN/A seqNum); 9822292SN/A 9832292SN/A if (mshr_it != mshrSeqNums.end()) { 9842292SN/A mshrSeqNums.erase(mshr_it); 9852292SN/A DPRINTF(LSQUnit, "Removing MSHR. count = %i\n",mshrSeqNums.size()); 9862292SN/A } 9872292SN/A}*/ 9882292SN/A 9892292SN/Atemplate <class Impl> 9902292SN/Avoid 9912292SN/ALSQUnit<Impl>::squash(const InstSeqNum &squashed_num) 9922292SN/A{ 9932292SN/A DPRINTF(LSQUnit, "Squashing until [sn:%lli]!" 9942329SN/A "(Loads:%i Stores:%i)\n", squashed_num, loads, stores); 9952292SN/A 9962292SN/A int load_idx = loadTail; 9972292SN/A decrLdIdx(load_idx); 9982292SN/A 9992292SN/A while (loads != 0 && loadQueue[load_idx]->seqNum > squashed_num) { 10007720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Load Instruction PC %s squashed, " 10012292SN/A "[sn:%lli]\n", 10027720Sgblack@eecs.umich.edu loadQueue[load_idx]->pcState(), 10032292SN/A loadQueue[load_idx]->seqNum); 10042292SN/A 10052292SN/A if (isStalled() && load_idx == stallingLoadIdx) { 10062292SN/A stalled = false; 10072292SN/A stallingStoreIsn = 0; 10082292SN/A stallingLoadIdx = 0; 10092292SN/A } 10102292SN/A 10112329SN/A // Clear the smart pointer to make sure it is decremented. 10122731Sktlim@umich.edu loadQueue[load_idx]->setSquashed(); 10132292SN/A loadQueue[load_idx] = NULL; 10142292SN/A --loads; 10152292SN/A 10162292SN/A // Inefficient! 10172292SN/A loadTail = load_idx; 10182292SN/A 10192292SN/A decrLdIdx(load_idx); 10202727Sktlim@umich.edu ++lsqSquashedLoads; 10212292SN/A } 10222292SN/A 10232292SN/A if (isLoadBlocked) { 10242292SN/A if (squashed_num < blockedLoadSeqNum) { 10252292SN/A isLoadBlocked = false; 10262292SN/A loadBlockedHandled = false; 10272292SN/A blockedLoadSeqNum = 0; 10282292SN/A } 10292292SN/A } 10302292SN/A 10314032Sktlim@umich.edu if (memDepViolator && squashed_num < memDepViolator->seqNum) { 10324032Sktlim@umich.edu memDepViolator = NULL; 10334032Sktlim@umich.edu } 10344032Sktlim@umich.edu 10352292SN/A int store_idx = storeTail; 10362292SN/A decrStIdx(store_idx); 10372292SN/A 10382292SN/A while (stores != 0 && 10392292SN/A storeQueue[store_idx].inst->seqNum > squashed_num) { 10402329SN/A // Instructions marked as can WB are already committed. 10412292SN/A if (storeQueue[store_idx].canWB) { 10422292SN/A break; 10432292SN/A } 10442292SN/A 10457720Sgblack@eecs.umich.edu DPRINTF(LSQUnit,"Store Instruction PC %s squashed, " 10462292SN/A "idx:%i [sn:%lli]\n", 10477720Sgblack@eecs.umich.edu storeQueue[store_idx].inst->pcState(), 10482292SN/A store_idx, storeQueue[store_idx].inst->seqNum); 10492292SN/A 10502329SN/A // I don't think this can happen. It should have been cleared 10512329SN/A // by the stalling load. 10522292SN/A if (isStalled() && 10532292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 10542292SN/A panic("Is stalled should have been cleared by stalling load!\n"); 10552292SN/A stalled = false; 10562292SN/A stallingStoreIsn = 0; 10572292SN/A } 10582292SN/A 10592329SN/A // Clear the smart pointer to make sure it is decremented. 10602731Sktlim@umich.edu storeQueue[store_idx].inst->setSquashed(); 10612292SN/A storeQueue[store_idx].inst = NULL; 10622292SN/A storeQueue[store_idx].canWB = 0; 10632292SN/A 10644032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 10654032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 10664032Sktlim@umich.edu // place to really handle request deletes. 10674032Sktlim@umich.edu delete storeQueue[store_idx].req; 10686974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && storeQueue[store_idx].isSplit) { 10696974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqLow; 10706974Stjones1@inf.ed.ac.uk delete storeQueue[store_idx].sreqHigh; 10716974Stjones1@inf.ed.ac.uk 10726974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = NULL; 10736974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = NULL; 10746974Stjones1@inf.ed.ac.uk } 10754032Sktlim@umich.edu 10762292SN/A storeQueue[store_idx].req = NULL; 10772292SN/A --stores; 10782292SN/A 10792292SN/A // Inefficient! 10802292SN/A storeTail = store_idx; 10812292SN/A 10822292SN/A decrStIdx(store_idx); 10832727Sktlim@umich.edu ++lsqSquashedStores; 10842292SN/A } 10852292SN/A} 10862292SN/A 10872292SN/Atemplate <class Impl> 10882292SN/Avoid 10893349Sbinkertn@umich.eduLSQUnit<Impl>::storePostSend(PacketPtr pkt) 10902693Sktlim@umich.edu{ 10912693Sktlim@umich.edu if (isStalled() && 10922693Sktlim@umich.edu storeQueue[storeWBIdx].inst->seqNum == stallingStoreIsn) { 10932693Sktlim@umich.edu DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 10942693Sktlim@umich.edu "load idx:%i\n", 10952693Sktlim@umich.edu stallingStoreIsn, stallingLoadIdx); 10962693Sktlim@umich.edu stalled = false; 10972693Sktlim@umich.edu stallingStoreIsn = 0; 10982693Sktlim@umich.edu iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 10992693Sktlim@umich.edu } 11002693Sktlim@umich.edu 11012693Sktlim@umich.edu if (!storeQueue[storeWBIdx].inst->isStoreConditional()) { 11022693Sktlim@umich.edu // The store is basically completed at this time. This 11032693Sktlim@umich.edu // only works so long as the checker doesn't try to 11042693Sktlim@umich.edu // verify the value in memory for stores. 11052693Sktlim@umich.edu storeQueue[storeWBIdx].inst->setCompleted(); 11068887Sgeoffrey.blake@arm.com 11072693Sktlim@umich.edu if (cpu->checker) { 11082732Sktlim@umich.edu cpu->checker->verify(storeQueue[storeWBIdx].inst); 11092693Sktlim@umich.edu } 11102693Sktlim@umich.edu } 11112693Sktlim@umich.edu 11128727Snilay@cs.wisc.edu if (needsTSO) { 11138727Snilay@cs.wisc.edu storeInFlight = true; 11148727Snilay@cs.wisc.edu } 11158727Snilay@cs.wisc.edu 11162693Sktlim@umich.edu incrStIdx(storeWBIdx); 11172693Sktlim@umich.edu} 11182693Sktlim@umich.edu 11192693Sktlim@umich.edutemplate <class Impl> 11202693Sktlim@umich.eduvoid 11212678Sktlim@umich.eduLSQUnit<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt) 11222678Sktlim@umich.edu{ 11232678Sktlim@umich.edu iewStage->wakeCPU(); 11242678Sktlim@umich.edu 11252678Sktlim@umich.edu // Squashed instructions do not need to complete their access. 11262678Sktlim@umich.edu if (inst->isSquashed()) { 11272927Sktlim@umich.edu iewStage->decrWb(inst->seqNum); 11282678Sktlim@umich.edu assert(!inst->isStore()); 11292727Sktlim@umich.edu ++lsqIgnoredResponses; 11302678Sktlim@umich.edu return; 11312678Sktlim@umich.edu } 11322678Sktlim@umich.edu 11332678Sktlim@umich.edu if (!inst->isExecuted()) { 11342678Sktlim@umich.edu inst->setExecuted(); 11352678Sktlim@umich.edu 11362678Sktlim@umich.edu // Complete access to copy data to proper place. 11372678Sktlim@umich.edu inst->completeAcc(pkt); 11382678Sktlim@umich.edu } 11392678Sktlim@umich.edu 11402678Sktlim@umich.edu // Need to insert instruction into queue to commit 11412678Sktlim@umich.edu iewStage->instToCommit(inst); 11422678Sktlim@umich.edu 11432678Sktlim@umich.edu iewStage->activityThisCycle(); 11447598Sminkyu.jeong@arm.com 11457598Sminkyu.jeong@arm.com // see if this load changed the PC 11467598Sminkyu.jeong@arm.com iewStage->checkMisprediction(inst); 11472678Sktlim@umich.edu} 11482678Sktlim@umich.edu 11492678Sktlim@umich.edutemplate <class Impl> 11502678Sktlim@umich.eduvoid 11512292SN/ALSQUnit<Impl>::completeStore(int store_idx) 11522292SN/A{ 11532292SN/A assert(storeQueue[store_idx].inst); 11542292SN/A storeQueue[store_idx].completed = true; 11552292SN/A --storesToWB; 11562292SN/A // A bit conservative because a store completion may not free up entries, 11572292SN/A // but hopefully avoids two store completions in one cycle from making 11582292SN/A // the CPU tick twice. 11593126Sktlim@umich.edu cpu->wakeCPU(); 11602292SN/A cpu->activityThisCycle(); 11612292SN/A 11622292SN/A if (store_idx == storeHead) { 11632292SN/A do { 11642292SN/A incrStIdx(storeHead); 11652292SN/A 11662292SN/A --stores; 11672292SN/A } while (storeQueue[storeHead].completed && 11682292SN/A storeHead != storeTail); 11692292SN/A 11702292SN/A iewStage->updateLSQNextCycle = true; 11712292SN/A } 11722292SN/A 11732329SN/A DPRINTF(LSQUnit, "Completing store [sn:%lli], idx:%i, store head " 11742329SN/A "idx:%i\n", 11752329SN/A storeQueue[store_idx].inst->seqNum, store_idx, storeHead); 11762292SN/A 11779527SMatt.Horsnell@arm.com#if TRACING_ON 11789527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 11799527SMatt.Horsnell@arm.com storeQueue[store_idx].inst->storeTick = 11809527SMatt.Horsnell@arm.com curTick() - storeQueue[store_idx].inst->fetchTick; 11819527SMatt.Horsnell@arm.com } 11829527SMatt.Horsnell@arm.com#endif 11839527SMatt.Horsnell@arm.com 11842292SN/A if (isStalled() && 11852292SN/A storeQueue[store_idx].inst->seqNum == stallingStoreIsn) { 11862292SN/A DPRINTF(LSQUnit, "Unstalling, stalling store [sn:%lli] " 11872292SN/A "load idx:%i\n", 11882292SN/A stallingStoreIsn, stallingLoadIdx); 11892292SN/A stalled = false; 11902292SN/A stallingStoreIsn = 0; 11912292SN/A iewStage->replayMemInst(loadQueue[stallingLoadIdx]); 11922292SN/A } 11932316SN/A 11942316SN/A storeQueue[store_idx].inst->setCompleted(); 11952329SN/A 11968727Snilay@cs.wisc.edu if (needsTSO) { 11978727Snilay@cs.wisc.edu storeInFlight = false; 11988727Snilay@cs.wisc.edu } 11998727Snilay@cs.wisc.edu 12002329SN/A // Tell the checker we've completed this instruction. Some stores 12012329SN/A // may get reported twice to the checker, but the checker can 12022329SN/A // handle that case. 12032316SN/A if (cpu->checker) { 12042732Sktlim@umich.edu cpu->checker->verify(storeQueue[store_idx].inst); 12052316SN/A } 12062292SN/A} 12072292SN/A 12082292SN/Atemplate <class Impl> 12096974Stjones1@inf.ed.ac.ukbool 12106974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::sendStore(PacketPtr data_pkt) 12116974Stjones1@inf.ed.ac.uk{ 12128975Sandreas.hansson@arm.com if (!dcachePort->sendTimingReq(data_pkt)) { 12136974Stjones1@inf.ed.ac.uk // Need to handle becoming blocked on a store. 12146974Stjones1@inf.ed.ac.uk isStoreBlocked = true; 12156974Stjones1@inf.ed.ac.uk ++lsqCacheBlocked; 12166974Stjones1@inf.ed.ac.uk assert(retryPkt == NULL); 12176974Stjones1@inf.ed.ac.uk retryPkt = data_pkt; 12186974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 12196974Stjones1@inf.ed.ac.uk return false; 12206974Stjones1@inf.ed.ac.uk } 12216974Stjones1@inf.ed.ac.uk return true; 12226974Stjones1@inf.ed.ac.uk} 12236974Stjones1@inf.ed.ac.uk 12246974Stjones1@inf.ed.ac.uktemplate <class Impl> 12252693Sktlim@umich.eduvoid 12262693Sktlim@umich.eduLSQUnit<Impl>::recvRetry() 12272693Sktlim@umich.edu{ 12282698Sktlim@umich.edu if (isStoreBlocked) { 12294985Sktlim@umich.edu DPRINTF(LSQUnit, "Receiving retry: store blocked\n"); 12302698Sktlim@umich.edu assert(retryPkt != NULL); 12312693Sktlim@umich.edu 12328587Snilay@cs.wisc.edu LSQSenderState *state = 12338587Snilay@cs.wisc.edu dynamic_cast<LSQSenderState *>(retryPkt->senderState); 12348587Snilay@cs.wisc.edu 12358975Sandreas.hansson@arm.com if (dcachePort->sendTimingReq(retryPkt)) { 12366974Stjones1@inf.ed.ac.uk // Don't finish the store unless this is the last packet. 12378133SAli.Saidi@ARM.com if (!TheISA::HasUnalignedMemAcc || !state->pktToSend || 12388133SAli.Saidi@ARM.com state->pendingPacket == retryPkt) { 12398133SAli.Saidi@ARM.com state->pktToSend = false; 12406974Stjones1@inf.ed.ac.uk storePostSend(retryPkt); 12416974Stjones1@inf.ed.ac.uk } 12422699Sktlim@umich.edu retryPkt = NULL; 12432693Sktlim@umich.edu isStoreBlocked = false; 12446221Snate@binkert.org lsq->setRetryTid(InvalidThreadID); 12456974Stjones1@inf.ed.ac.uk 12466974Stjones1@inf.ed.ac.uk // Send any outstanding packet. 12476974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && state->pktToSend) { 12486974Stjones1@inf.ed.ac.uk assert(state->pendingPacket); 12496974Stjones1@inf.ed.ac.uk if (sendStore(state->pendingPacket)) { 12506974Stjones1@inf.ed.ac.uk storePostSend(state->pendingPacket); 12516974Stjones1@inf.ed.ac.uk } 12526974Stjones1@inf.ed.ac.uk } 12532693Sktlim@umich.edu } else { 12542693Sktlim@umich.edu // Still blocked! 12552727Sktlim@umich.edu ++lsqCacheBlocked; 12562907Sktlim@umich.edu lsq->setRetryTid(lsqID); 12572693Sktlim@umich.edu } 12582693Sktlim@umich.edu } else if (isLoadBlocked) { 12592693Sktlim@umich.edu DPRINTF(LSQUnit, "Loads squash themselves and all younger insts, " 12602693Sktlim@umich.edu "no need to resend packet.\n"); 12612693Sktlim@umich.edu } else { 12622693Sktlim@umich.edu DPRINTF(LSQUnit, "Retry received but LSQ is no longer blocked.\n"); 12632693Sktlim@umich.edu } 12642693Sktlim@umich.edu} 12652693Sktlim@umich.edu 12662693Sktlim@umich.edutemplate <class Impl> 12672292SN/Ainline void 12689440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::incrStIdx(int &store_idx) const 12692292SN/A{ 12702292SN/A if (++store_idx >= SQEntries) 12712292SN/A store_idx = 0; 12722292SN/A} 12732292SN/A 12742292SN/Atemplate <class Impl> 12752292SN/Ainline void 12769440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::decrStIdx(int &store_idx) const 12772292SN/A{ 12782292SN/A if (--store_idx < 0) 12792292SN/A store_idx += SQEntries; 12802292SN/A} 12812292SN/A 12822292SN/Atemplate <class Impl> 12832292SN/Ainline void 12849440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::incrLdIdx(int &load_idx) const 12852292SN/A{ 12862292SN/A if (++load_idx >= LQEntries) 12872292SN/A load_idx = 0; 12882292SN/A} 12892292SN/A 12902292SN/Atemplate <class Impl> 12912292SN/Ainline void 12929440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::decrLdIdx(int &load_idx) const 12932292SN/A{ 12942292SN/A if (--load_idx < 0) 12952292SN/A load_idx += LQEntries; 12962292SN/A} 12972329SN/A 12982329SN/Atemplate <class Impl> 12992329SN/Avoid 13009440SAndreas.Sandberg@ARM.comLSQUnit<Impl>::dumpInsts() const 13012329SN/A{ 13022329SN/A cprintf("Load store queue: Dumping instructions.\n"); 13032329SN/A cprintf("Load queue size: %i\n", loads); 13042329SN/A cprintf("Load queue: "); 13052329SN/A 13062329SN/A int load_idx = loadHead; 13072329SN/A 13082329SN/A while (load_idx != loadTail && loadQueue[load_idx]) { 13099440SAndreas.Sandberg@ARM.com const DynInstPtr &inst(loadQueue[load_idx]); 13109440SAndreas.Sandberg@ARM.com cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 13112329SN/A 13122329SN/A incrLdIdx(load_idx); 13132329SN/A } 13149440SAndreas.Sandberg@ARM.com cprintf("\n"); 13152329SN/A 13162329SN/A cprintf("Store queue size: %i\n", stores); 13172329SN/A cprintf("Store queue: "); 13182329SN/A 13192329SN/A int store_idx = storeHead; 13202329SN/A 13212329SN/A while (store_idx != storeTail && storeQueue[store_idx].inst) { 13229440SAndreas.Sandberg@ARM.com const DynInstPtr &inst(storeQueue[store_idx].inst); 13239440SAndreas.Sandberg@ARM.com cprintf("%s.[sn:%i] ", inst->pcState(), inst->seqNum); 13242329SN/A 13252329SN/A incrStIdx(store_idx); 13262329SN/A } 13272329SN/A 13282329SN/A cprintf("\n"); 13292329SN/A} 13309944Smatt.horsnell@ARM.com 13319944Smatt.horsnell@ARM.com#endif//__CPU_O3_LSQ_UNIT_IMPL_HH__ 1332