lsq_unit.hh revision 9044
12292SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu * Korey Sewell 302292SN/A */ 312292SN/A 322292SN/A#ifndef __CPU_O3_LSQ_UNIT_HH__ 332292SN/A#define __CPU_O3_LSQ_UNIT_HH__ 342292SN/A 352329SN/A#include <algorithm> 364395Ssaidi@eecs.umich.edu#include <cstring> 372292SN/A#include <map> 382292SN/A#include <queue> 392292SN/A 408591Sgblack@eecs.umich.edu#include "arch/generic/debugfaults.hh" 418506Sgblack@eecs.umich.edu#include "arch/isa_traits.hh" 423326Sktlim@umich.edu#include "arch/locked_mem.hh" 438481Sgblack@eecs.umich.edu#include "arch/mmapped_ipr.hh" 448229Snate@binkert.org#include "base/hashmap.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 462292SN/A#include "cpu/inst_seq.hh" 478230Snate@binkert.org#include "cpu/timebuf.hh" 488232Snate@binkert.org#include "debug/LSQUnit.hh" 493348Sbinkertn@umich.edu#include "mem/packet.hh" 502669Sktlim@umich.edu#include "mem/port.hh" 518817Sgblack@eecs.umich.edu#include "sim/fault_fwd.hh" 522292SN/A 538737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 545529Snate@binkert.org 552292SN/A/** 562329SN/A * Class that implements the actual LQ and SQ for each specific 572329SN/A * thread. Both are circular queues; load entries are freed upon 582329SN/A * committing, while store entries are freed once they writeback. The 592329SN/A * LSQUnit tracks if there are memory ordering violations, and also 602329SN/A * detects partial load to store forwarding cases (a store only has 612329SN/A * part of a load's data) that requires the load to wait until the 622329SN/A * store writes back. In the former case it holds onto the instruction 632329SN/A * until the dependence unit looks at it, and in the latter it stalls 642329SN/A * the LSQ until the store writes back. At that point the load is 652329SN/A * replayed. 662292SN/A */ 672292SN/Atemplate <class Impl> 682292SN/Aclass LSQUnit { 692292SN/A public: 702733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 712292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 722292SN/A typedef typename Impl::CPUPol::IEW IEW; 732907Sktlim@umich.edu typedef typename Impl::CPUPol::LSQ LSQ; 742292SN/A typedef typename Impl::CPUPol::IssueStruct IssueStruct; 752292SN/A 762292SN/A public: 772292SN/A /** Constructs an LSQ unit. init() must be called prior to use. */ 782292SN/A LSQUnit(); 792292SN/A 802292SN/A /** Initializes the LSQ unit with the specified number of entries. */ 815529Snate@binkert.org void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 825529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 835529Snate@binkert.org unsigned id); 842292SN/A 852292SN/A /** Returns the name of the LSQ unit. */ 862292SN/A std::string name() const; 872292SN/A 882727Sktlim@umich.edu /** Registers statistics. */ 892727Sktlim@umich.edu void regStats(); 902727Sktlim@umich.edu 912907Sktlim@umich.edu /** Sets the pointer to the dcache port. */ 928922Swilliam.wang@arm.com void setDcachePort(MasterPort *dcache_port); 932907Sktlim@umich.edu 942348SN/A /** Switches out LSQ unit. */ 952307SN/A void switchOut(); 962307SN/A 972348SN/A /** Takes over from another CPU's thread. */ 982307SN/A void takeOverFrom(); 992307SN/A 1002348SN/A /** Returns if the LSQ is switched out. */ 1012307SN/A bool isSwitchedOut() { return switchedOut; } 1022307SN/A 1032292SN/A /** Ticks the LSQ unit, which in this case only resets the number of 1042292SN/A * used cache ports. 1052292SN/A * @todo: Move the number of used ports up to the LSQ level so it can 1062292SN/A * be shared by all LSQ units. 1072292SN/A */ 1082292SN/A void tick() { usedPorts = 0; } 1092292SN/A 1102292SN/A /** Inserts an instruction. */ 1112292SN/A void insert(DynInstPtr &inst); 1122292SN/A /** Inserts a load instruction. */ 1132292SN/A void insertLoad(DynInstPtr &load_inst); 1142292SN/A /** Inserts a store instruction. */ 1152292SN/A void insertStore(DynInstPtr &store_inst); 1162292SN/A 1178545Ssaidi@eecs.umich.edu /** Check for ordering violations in the LSQ. For a store squash if we 1188545Ssaidi@eecs.umich.edu * ever find a conflicting load. For a load, only squash if we 1198545Ssaidi@eecs.umich.edu * an external snoop invalidate has been seen for that load address 1208199SAli.Saidi@ARM.com * @param load_idx index to start checking at 1218199SAli.Saidi@ARM.com * @param inst the instruction to check 1228199SAli.Saidi@ARM.com */ 1238199SAli.Saidi@ARM.com Fault checkViolations(int load_idx, DynInstPtr &inst); 1248199SAli.Saidi@ARM.com 1258545Ssaidi@eecs.umich.edu /** Check if an incoming invalidate hits in the lsq on a load 1268545Ssaidi@eecs.umich.edu * that might have issued out of order wrt another load beacuse 1278545Ssaidi@eecs.umich.edu * of the intermediate invalidate. 1288545Ssaidi@eecs.umich.edu */ 1298545Ssaidi@eecs.umich.edu void checkSnoop(PacketPtr pkt); 1308545Ssaidi@eecs.umich.edu 1312292SN/A /** Executes a load instruction. */ 1322292SN/A Fault executeLoad(DynInstPtr &inst); 1332292SN/A 1342329SN/A Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; } 1352292SN/A /** Executes a store instruction. */ 1362292SN/A Fault executeStore(DynInstPtr &inst); 1372292SN/A 1382292SN/A /** Commits the head load. */ 1392292SN/A void commitLoad(); 1402292SN/A /** Commits loads older than a specific sequence number. */ 1412292SN/A void commitLoads(InstSeqNum &youngest_inst); 1422292SN/A 1432292SN/A /** Commits stores older than a specific sequence number. */ 1442292SN/A void commitStores(InstSeqNum &youngest_inst); 1452292SN/A 1462292SN/A /** Writes back stores. */ 1472292SN/A void writebackStores(); 1482292SN/A 1492790Sktlim@umich.edu /** Completes the data access that has been returned from the 1502790Sktlim@umich.edu * memory system. */ 1512669Sktlim@umich.edu void completeDataAccess(PacketPtr pkt); 1522669Sktlim@umich.edu 1532292SN/A /** Clears all the entries in the LQ. */ 1542292SN/A void clearLQ(); 1552292SN/A 1562292SN/A /** Clears all the entries in the SQ. */ 1572292SN/A void clearSQ(); 1582292SN/A 1592292SN/A /** Resizes the LQ to a given size. */ 1602292SN/A void resizeLQ(unsigned size); 1612292SN/A 1622292SN/A /** Resizes the SQ to a given size. */ 1632292SN/A void resizeSQ(unsigned size); 1642292SN/A 1652292SN/A /** Squashes all instructions younger than a specific sequence number. */ 1662292SN/A void squash(const InstSeqNum &squashed_num); 1672292SN/A 1682292SN/A /** Returns if there is a memory ordering violation. Value is reset upon 1692292SN/A * call to getMemDepViolator(). 1702292SN/A */ 1712292SN/A bool violation() { return memDepViolator; } 1722292SN/A 1732292SN/A /** Returns the memory ordering violator. */ 1742292SN/A DynInstPtr getMemDepViolator(); 1752292SN/A 1762329SN/A /** Returns if a load became blocked due to the memory system. */ 1772292SN/A bool loadBlocked() 1782292SN/A { return isLoadBlocked; } 1792292SN/A 1802348SN/A /** Clears the signal that a load became blocked. */ 1812292SN/A void clearLoadBlocked() 1822292SN/A { isLoadBlocked = false; } 1832292SN/A 1842348SN/A /** Returns if the blocked load was handled. */ 1852292SN/A bool isLoadBlockedHandled() 1862292SN/A { return loadBlockedHandled; } 1872292SN/A 1882348SN/A /** Records the blocked load as being handled. */ 1892292SN/A void setLoadBlockedHandled() 1902292SN/A { loadBlockedHandled = true; } 1912292SN/A 1922292SN/A /** Returns the number of free entries (min of free LQ and SQ entries). */ 1932292SN/A unsigned numFreeEntries(); 1942292SN/A 1952292SN/A /** Returns the number of loads ready to execute. */ 1962292SN/A int numLoadsReady(); 1972292SN/A 1982292SN/A /** Returns the number of loads in the LQ. */ 1992292SN/A int numLoads() { return loads; } 2002292SN/A 2012292SN/A /** Returns the number of stores in the SQ. */ 2022292SN/A int numStores() { return stores; } 2032292SN/A 2042292SN/A /** Returns if either the LQ or SQ is full. */ 2052292SN/A bool isFull() { return lqFull() || sqFull(); } 2062292SN/A 2072292SN/A /** Returns if the LQ is full. */ 2082292SN/A bool lqFull() { return loads >= (LQEntries - 1); } 2092292SN/A 2102292SN/A /** Returns if the SQ is full. */ 2112292SN/A bool sqFull() { return stores >= (SQEntries - 1); } 2122292SN/A 2132292SN/A /** Returns the number of instructions in the LSQ. */ 2142292SN/A unsigned getCount() { return loads + stores; } 2152292SN/A 2162292SN/A /** Returns if there are any stores to writeback. */ 2172292SN/A bool hasStoresToWB() { return storesToWB; } 2182292SN/A 2192292SN/A /** Returns the number of stores to writeback. */ 2202292SN/A int numStoresToWB() { return storesToWB; } 2212292SN/A 2222292SN/A /** Returns if the LSQ unit will writeback on this cycle. */ 2232292SN/A bool willWB() { return storeQueue[storeWBIdx].canWB && 2242678Sktlim@umich.edu !storeQueue[storeWBIdx].completed && 2252678Sktlim@umich.edu !isStoreBlocked; } 2262292SN/A 2272907Sktlim@umich.edu /** Handles doing the retry. */ 2282907Sktlim@umich.edu void recvRetry(); 2292907Sktlim@umich.edu 2302292SN/A private: 2312698Sktlim@umich.edu /** Writes back the instruction, sending it to IEW. */ 2322678Sktlim@umich.edu void writeback(DynInstPtr &inst, PacketPtr pkt); 2332678Sktlim@umich.edu 2346974Stjones1@inf.ed.ac.uk /** Writes back a store that couldn't be completed the previous cycle. */ 2356974Stjones1@inf.ed.ac.uk void writebackPendingStore(); 2366974Stjones1@inf.ed.ac.uk 2372698Sktlim@umich.edu /** Handles completing the send of a store to memory. */ 2383349Sbinkertn@umich.edu void storePostSend(PacketPtr pkt); 2392693Sktlim@umich.edu 2402292SN/A /** Completes the store at the specified index. */ 2412292SN/A void completeStore(int store_idx); 2422292SN/A 2436974Stjones1@inf.ed.ac.uk /** Attempts to send a store to the cache. */ 2446974Stjones1@inf.ed.ac.uk bool sendStore(PacketPtr data_pkt); 2456974Stjones1@inf.ed.ac.uk 2462292SN/A /** Increments the given store index (circular queue). */ 2472292SN/A inline void incrStIdx(int &store_idx); 2482292SN/A /** Decrements the given store index (circular queue). */ 2492292SN/A inline void decrStIdx(int &store_idx); 2502292SN/A /** Increments the given load index (circular queue). */ 2512292SN/A inline void incrLdIdx(int &load_idx); 2522292SN/A /** Decrements the given load index (circular queue). */ 2532292SN/A inline void decrLdIdx(int &load_idx); 2542292SN/A 2552329SN/A public: 2562329SN/A /** Debugging function to dump instructions in the LSQ. */ 2572329SN/A void dumpInsts(); 2582329SN/A 2592292SN/A private: 2602292SN/A /** Pointer to the CPU. */ 2612733Sktlim@umich.edu O3CPU *cpu; 2622292SN/A 2632292SN/A /** Pointer to the IEW stage. */ 2642292SN/A IEW *iewStage; 2652292SN/A 2662907Sktlim@umich.edu /** Pointer to the LSQ. */ 2672907Sktlim@umich.edu LSQ *lsq; 2682669Sktlim@umich.edu 2692907Sktlim@umich.edu /** Pointer to the dcache port. Used only for sending. */ 2708922Swilliam.wang@arm.com MasterPort *dcachePort; 2712292SN/A 2722698Sktlim@umich.edu /** Derived class to hold any sender state the LSQ needs. */ 2739044SAli.Saidi@ARM.com class LSQSenderState : public Packet::SenderState 2742678Sktlim@umich.edu { 2752678Sktlim@umich.edu public: 2762698Sktlim@umich.edu /** Default constructor. */ 2772678Sktlim@umich.edu LSQSenderState() 2786974Stjones1@inf.ed.ac.uk : noWB(false), isSplit(false), pktToSend(false), outstanding(1), 2796974Stjones1@inf.ed.ac.uk mainPkt(NULL), pendingPacket(NULL) 2802678Sktlim@umich.edu { } 2812678Sktlim@umich.edu 2822698Sktlim@umich.edu /** Instruction who initiated the access to memory. */ 2832678Sktlim@umich.edu DynInstPtr inst; 2842698Sktlim@umich.edu /** Whether or not it is a load. */ 2852678Sktlim@umich.edu bool isLoad; 2862698Sktlim@umich.edu /** The LQ/SQ index of the instruction. */ 2872678Sktlim@umich.edu int idx; 2882698Sktlim@umich.edu /** Whether or not the instruction will need to writeback. */ 2892678Sktlim@umich.edu bool noWB; 2906974Stjones1@inf.ed.ac.uk /** Whether or not this access is split in two. */ 2916974Stjones1@inf.ed.ac.uk bool isSplit; 2926974Stjones1@inf.ed.ac.uk /** Whether or not there is a packet that needs sending. */ 2936974Stjones1@inf.ed.ac.uk bool pktToSend; 2946974Stjones1@inf.ed.ac.uk /** Number of outstanding packets to complete. */ 2956974Stjones1@inf.ed.ac.uk int outstanding; 2966974Stjones1@inf.ed.ac.uk /** The main packet from a split load, used during writeback. */ 2976974Stjones1@inf.ed.ac.uk PacketPtr mainPkt; 2986974Stjones1@inf.ed.ac.uk /** A second packet from a split store that needs sending. */ 2996974Stjones1@inf.ed.ac.uk PacketPtr pendingPacket; 3006974Stjones1@inf.ed.ac.uk 3016974Stjones1@inf.ed.ac.uk /** Completes a packet and returns whether the access is finished. */ 3026974Stjones1@inf.ed.ac.uk inline bool complete() { return --outstanding == 0; } 3032678Sktlim@umich.edu }; 3042678Sktlim@umich.edu 3052698Sktlim@umich.edu /** Writeback event, specifically for when stores forward data to loads. */ 3062678Sktlim@umich.edu class WritebackEvent : public Event { 3072678Sktlim@umich.edu public: 3082678Sktlim@umich.edu /** Constructs a writeback event. */ 3092678Sktlim@umich.edu WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr); 3102678Sktlim@umich.edu 3112678Sktlim@umich.edu /** Processes the writeback event. */ 3122678Sktlim@umich.edu void process(); 3132678Sktlim@umich.edu 3142678Sktlim@umich.edu /** Returns the description of this event. */ 3155336Shines@cs.fsu.edu const char *description() const; 3162678Sktlim@umich.edu 3172678Sktlim@umich.edu private: 3182698Sktlim@umich.edu /** Instruction whose results are being written back. */ 3192678Sktlim@umich.edu DynInstPtr inst; 3202678Sktlim@umich.edu 3212698Sktlim@umich.edu /** The packet that would have been sent to memory. */ 3222678Sktlim@umich.edu PacketPtr pkt; 3232678Sktlim@umich.edu 3242678Sktlim@umich.edu /** The pointer to the LSQ unit that issued the store. */ 3252678Sktlim@umich.edu LSQUnit<Impl> *lsqPtr; 3262678Sktlim@umich.edu }; 3272678Sktlim@umich.edu 3282292SN/A public: 3292292SN/A struct SQEntry { 3302292SN/A /** Constructs an empty store queue entry. */ 3312292SN/A SQEntry() 3324326Sgblack@eecs.umich.edu : inst(NULL), req(NULL), size(0), 3332292SN/A canWB(0), committed(0), completed(0) 3344326Sgblack@eecs.umich.edu { 3354395Ssaidi@eecs.umich.edu std::memset(data, 0, sizeof(data)); 3364326Sgblack@eecs.umich.edu } 3372292SN/A 3382292SN/A /** Constructs a store queue entry for a given instruction. */ 3392292SN/A SQEntry(DynInstPtr &_inst) 3406974Stjones1@inf.ed.ac.uk : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0), 3416974Stjones1@inf.ed.ac.uk isSplit(0), canWB(0), committed(0), completed(0) 3424326Sgblack@eecs.umich.edu { 3434395Ssaidi@eecs.umich.edu std::memset(data, 0, sizeof(data)); 3444326Sgblack@eecs.umich.edu } 3452292SN/A 3462292SN/A /** The store instruction. */ 3472292SN/A DynInstPtr inst; 3482669Sktlim@umich.edu /** The request for the store. */ 3492669Sktlim@umich.edu RequestPtr req; 3506974Stjones1@inf.ed.ac.uk /** The split requests for the store. */ 3516974Stjones1@inf.ed.ac.uk RequestPtr sreqLow; 3526974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh; 3532292SN/A /** The size of the store. */ 3542292SN/A int size; 3552292SN/A /** The store data. */ 3567786SAli.Saidi@ARM.com char data[16]; 3576974Stjones1@inf.ed.ac.uk /** Whether or not the store is split into two requests. */ 3586974Stjones1@inf.ed.ac.uk bool isSplit; 3592292SN/A /** Whether or not the store can writeback. */ 3602292SN/A bool canWB; 3612292SN/A /** Whether or not the store is committed. */ 3622292SN/A bool committed; 3632292SN/A /** Whether or not the store is completed. */ 3642292SN/A bool completed; 3652292SN/A }; 3662329SN/A 3672292SN/A private: 3682292SN/A /** The LSQUnit thread id. */ 3696221Snate@binkert.org ThreadID lsqID; 3702292SN/A 3712292SN/A /** The store queue. */ 3722292SN/A std::vector<SQEntry> storeQueue; 3732292SN/A 3742292SN/A /** The load queue. */ 3752292SN/A std::vector<DynInstPtr> loadQueue; 3762292SN/A 3772329SN/A /** The number of LQ entries, plus a sentinel entry (circular queue). 3782329SN/A * @todo: Consider having var that records the true number of LQ entries. 3792329SN/A */ 3802292SN/A unsigned LQEntries; 3812329SN/A /** The number of SQ entries, plus a sentinel entry (circular queue). 3822329SN/A * @todo: Consider having var that records the true number of SQ entries. 3832329SN/A */ 3842292SN/A unsigned SQEntries; 3852292SN/A 3868199SAli.Saidi@ARM.com /** The number of places to shift addresses in the LSQ before checking 3878199SAli.Saidi@ARM.com * for dependency violations 3888199SAli.Saidi@ARM.com */ 3898199SAli.Saidi@ARM.com unsigned depCheckShift; 3908199SAli.Saidi@ARM.com 3918199SAli.Saidi@ARM.com /** Should loads be checked for dependency issues */ 3928199SAli.Saidi@ARM.com bool checkLoads; 3938199SAli.Saidi@ARM.com 3942292SN/A /** The number of load instructions in the LQ. */ 3952292SN/A int loads; 3962329SN/A /** The number of store instructions in the SQ. */ 3972292SN/A int stores; 3982292SN/A /** The number of store instructions in the SQ waiting to writeback. */ 3992292SN/A int storesToWB; 4002292SN/A 4012292SN/A /** The index of the head instruction in the LQ. */ 4022292SN/A int loadHead; 4032292SN/A /** The index of the tail instruction in the LQ. */ 4042292SN/A int loadTail; 4052292SN/A 4062292SN/A /** The index of the head instruction in the SQ. */ 4072292SN/A int storeHead; 4082329SN/A /** The index of the first instruction that may be ready to be 4092329SN/A * written back, and has not yet been written back. 4102292SN/A */ 4112292SN/A int storeWBIdx; 4122292SN/A /** The index of the tail instruction in the SQ. */ 4132292SN/A int storeTail; 4142292SN/A 4152292SN/A /// @todo Consider moving to a more advanced model with write vs read ports 4162292SN/A /** The number of cache ports available each cycle. */ 4172292SN/A int cachePorts; 4182292SN/A 4192292SN/A /** The number of used cache ports in this cycle. */ 4202292SN/A int usedPorts; 4212292SN/A 4222348SN/A /** Is the LSQ switched out. */ 4232307SN/A bool switchedOut; 4242307SN/A 4252292SN/A //list<InstSeqNum> mshrSeqNums; 4262292SN/A 4278545Ssaidi@eecs.umich.edu /** Address Mask for a cache block (e.g. ~(cache_block_size-1)) */ 4288545Ssaidi@eecs.umich.edu Addr cacheBlockMask; 4298545Ssaidi@eecs.umich.edu 4302292SN/A /** Wire to read information from the issue stage time queue. */ 4312292SN/A typename TimeBuffer<IssueStruct>::wire fromIssue; 4322292SN/A 4332292SN/A /** Whether or not the LSQ is stalled. */ 4342292SN/A bool stalled; 4352292SN/A /** The store that causes the stall due to partial store to load 4362292SN/A * forwarding. 4372292SN/A */ 4382292SN/A InstSeqNum stallingStoreIsn; 4392292SN/A /** The index of the above store. */ 4402292SN/A int stallingLoadIdx; 4412292SN/A 4422698Sktlim@umich.edu /** The packet that needs to be retried. */ 4432698Sktlim@umich.edu PacketPtr retryPkt; 4442693Sktlim@umich.edu 4452698Sktlim@umich.edu /** Whehter or not a store is blocked due to the memory system. */ 4462678Sktlim@umich.edu bool isStoreBlocked; 4472678Sktlim@umich.edu 4482329SN/A /** Whether or not a load is blocked due to the memory system. */ 4492292SN/A bool isLoadBlocked; 4502292SN/A 4512348SN/A /** Has the blocked load been handled. */ 4522292SN/A bool loadBlockedHandled; 4532292SN/A 4548727Snilay@cs.wisc.edu /** Whether or not a store is in flight. */ 4558727Snilay@cs.wisc.edu bool storeInFlight; 4568727Snilay@cs.wisc.edu 4572348SN/A /** The sequence number of the blocked load. */ 4582292SN/A InstSeqNum blockedLoadSeqNum; 4592292SN/A 4602292SN/A /** The oldest load that caused a memory ordering violation. */ 4612292SN/A DynInstPtr memDepViolator; 4622292SN/A 4636974Stjones1@inf.ed.ac.uk /** Whether or not there is a packet that couldn't be sent because of 4646974Stjones1@inf.ed.ac.uk * a lack of cache ports. */ 4656974Stjones1@inf.ed.ac.uk bool hasPendingPkt; 4666974Stjones1@inf.ed.ac.uk 4676974Stjones1@inf.ed.ac.uk /** The packet that is pending free cache ports. */ 4686974Stjones1@inf.ed.ac.uk PacketPtr pendingPkt; 4696974Stjones1@inf.ed.ac.uk 4708727Snilay@cs.wisc.edu /** Flag for memory model. */ 4718727Snilay@cs.wisc.edu bool needsTSO; 4728727Snilay@cs.wisc.edu 4732292SN/A // Will also need how many read/write ports the Dcache has. Or keep track 4742292SN/A // of that in stage that is one level up, and only call executeLoad/Store 4752292SN/A // the appropriate number of times. 4762727Sktlim@umich.edu /** Total number of loads forwaded from LSQ stores. */ 4775999Snate@binkert.org Stats::Scalar lsqForwLoads; 4782307SN/A 4793126Sktlim@umich.edu /** Total number of loads ignored due to invalid addresses. */ 4805999Snate@binkert.org Stats::Scalar invAddrLoads; 4813126Sktlim@umich.edu 4823126Sktlim@umich.edu /** Total number of squashed loads. */ 4835999Snate@binkert.org Stats::Scalar lsqSquashedLoads; 4843126Sktlim@umich.edu 4853126Sktlim@umich.edu /** Total number of responses from the memory system that are 4863126Sktlim@umich.edu * ignored due to the instruction already being squashed. */ 4875999Snate@binkert.org Stats::Scalar lsqIgnoredResponses; 4883126Sktlim@umich.edu 4893126Sktlim@umich.edu /** Tota number of memory ordering violations. */ 4905999Snate@binkert.org Stats::Scalar lsqMemOrderViolation; 4913126Sktlim@umich.edu 4922727Sktlim@umich.edu /** Total number of squashed stores. */ 4935999Snate@binkert.org Stats::Scalar lsqSquashedStores; 4942727Sktlim@umich.edu 4952727Sktlim@umich.edu /** Total number of software prefetches ignored due to invalid addresses. */ 4965999Snate@binkert.org Stats::Scalar invAddrSwpfs; 4972727Sktlim@umich.edu 4982727Sktlim@umich.edu /** Ready loads blocked due to partial store-forwarding. */ 4995999Snate@binkert.org Stats::Scalar lsqBlockedLoads; 5002727Sktlim@umich.edu 5012727Sktlim@umich.edu /** Number of loads that were rescheduled. */ 5025999Snate@binkert.org Stats::Scalar lsqRescheduledLoads; 5032727Sktlim@umich.edu 5042727Sktlim@umich.edu /** Number of times the LSQ is blocked due to the cache. */ 5055999Snate@binkert.org Stats::Scalar lsqCacheBlocked; 5062727Sktlim@umich.edu 5072292SN/A public: 5082292SN/A /** Executes the load at the given index. */ 5097520Sgblack@eecs.umich.edu Fault read(Request *req, Request *sreqLow, Request *sreqHigh, 5107520Sgblack@eecs.umich.edu uint8_t *data, int load_idx); 5112292SN/A 5122292SN/A /** Executes the store at the given index. */ 5137520Sgblack@eecs.umich.edu Fault write(Request *req, Request *sreqLow, Request *sreqHigh, 5147520Sgblack@eecs.umich.edu uint8_t *data, int store_idx); 5152292SN/A 5162292SN/A /** Returns the index of the head load instruction. */ 5172292SN/A int getLoadHead() { return loadHead; } 5182292SN/A /** Returns the sequence number of the head load instruction. */ 5192292SN/A InstSeqNum getLoadHeadSeqNum() 5202292SN/A { 5212292SN/A if (loadQueue[loadHead]) { 5222292SN/A return loadQueue[loadHead]->seqNum; 5232292SN/A } else { 5242292SN/A return 0; 5252292SN/A } 5262292SN/A 5272292SN/A } 5282292SN/A 5292292SN/A /** Returns the index of the head store instruction. */ 5302292SN/A int getStoreHead() { return storeHead; } 5312292SN/A /** Returns the sequence number of the head store instruction. */ 5322292SN/A InstSeqNum getStoreHeadSeqNum() 5332292SN/A { 5342292SN/A if (storeQueue[storeHead].inst) { 5352292SN/A return storeQueue[storeHead].inst->seqNum; 5362292SN/A } else { 5372292SN/A return 0; 5382292SN/A } 5392292SN/A 5402292SN/A } 5412292SN/A 5422292SN/A /** Returns whether or not the LSQ unit is stalled. */ 5432292SN/A bool isStalled() { return stalled; } 5442292SN/A}; 5452292SN/A 5462292SN/Atemplate <class Impl> 5472292SN/AFault 5486974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, 5497520Sgblack@eecs.umich.edu uint8_t *data, int load_idx) 5502292SN/A{ 5512669Sktlim@umich.edu DynInstPtr load_inst = loadQueue[load_idx]; 5522292SN/A 5532669Sktlim@umich.edu assert(load_inst); 5542669Sktlim@umich.edu 5552669Sktlim@umich.edu assert(!load_inst->isExecuted()); 5562292SN/A 5572292SN/A // Make sure this isn't an uncacheable access 5582292SN/A // A bit of a hackish way to get uncached accesses to work only if they're 5592292SN/A // at the head of the LSQ and are ready to commit (at the head of the ROB 5602292SN/A // too). 5613172Sstever@eecs.umich.edu if (req->isUncacheable() && 5622731Sktlim@umich.edu (load_idx != loadHead || !load_inst->isAtCommit())) { 5632669Sktlim@umich.edu iewStage->rescheduleMemInst(load_inst); 5642727Sktlim@umich.edu ++lsqRescheduledLoads; 5657720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %s\n", 5667720Sgblack@eecs.umich.edu load_inst->seqNum, load_inst->pcState()); 5674032Sktlim@umich.edu 5684032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 5694032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 5704032Sktlim@umich.edu // place to really handle request deletes. 5714032Sktlim@umich.edu delete req; 5726974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 5736974Stjones1@inf.ed.ac.uk delete sreqLow; 5746974Stjones1@inf.ed.ac.uk delete sreqHigh; 5756974Stjones1@inf.ed.ac.uk } 5768591Sgblack@eecs.umich.edu return new GenericISA::M5PanicFault( 5778591Sgblack@eecs.umich.edu "Uncachable load [sn:%llx] PC %s\n", 5788591Sgblack@eecs.umich.edu load_inst->seqNum, load_inst->pcState()); 5792292SN/A } 5802292SN/A 5812292SN/A // Check the SQ for any previous stores that might lead to forwarding 5822669Sktlim@umich.edu int store_idx = load_inst->sqIdx; 5832292SN/A 5842292SN/A int store_size = 0; 5852292SN/A 5862292SN/A DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 5876974Stjones1@inf.ed.ac.uk "storeHead: %i addr: %#x%s\n", 5886974Stjones1@inf.ed.ac.uk load_idx, store_idx, storeHead, req->getPaddr(), 5896974Stjones1@inf.ed.ac.uk sreqLow ? " split" : ""); 5902292SN/A 5916102Sgblack@eecs.umich.edu if (req->isLLSC()) { 5926974Stjones1@inf.ed.ac.uk assert(!sreqLow); 5933326Sktlim@umich.edu // Disable recording the result temporarily. Writing to misc 5943326Sktlim@umich.edu // regs normally updates the result, but this is not the 5953326Sktlim@umich.edu // desired behavior when handling store conditionals. 5963326Sktlim@umich.edu load_inst->recordResult = false; 5973326Sktlim@umich.edu TheISA::handleLockedRead(load_inst.get(), req); 5983326Sktlim@umich.edu load_inst->recordResult = true; 5992292SN/A } 6002292SN/A 6018481Sgblack@eecs.umich.edu if (req->isMmappedIpr()) { 6028481Sgblack@eecs.umich.edu assert(!load_inst->memData); 6038481Sgblack@eecs.umich.edu load_inst->memData = new uint8_t[64]; 6048481Sgblack@eecs.umich.edu 6058481Sgblack@eecs.umich.edu ThreadContext *thread = cpu->tcBase(lsqID); 6068481Sgblack@eecs.umich.edu Tick delay; 6078949Sandreas.hansson@arm.com PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq); 6088481Sgblack@eecs.umich.edu 6098481Sgblack@eecs.umich.edu if (!TheISA::HasUnalignedMemAcc || !sreqLow) { 6108481Sgblack@eecs.umich.edu data_pkt->dataStatic(load_inst->memData); 6118481Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread, data_pkt); 6128481Sgblack@eecs.umich.edu } else { 6138481Sgblack@eecs.umich.edu assert(sreqLow->isMmappedIpr() && sreqHigh->isMmappedIpr()); 6148949Sandreas.hansson@arm.com PacketPtr fst_data_pkt = new Packet(sreqLow, MemCmd::ReadReq); 6158949Sandreas.hansson@arm.com PacketPtr snd_data_pkt = new Packet(sreqHigh, MemCmd::ReadReq); 6168481Sgblack@eecs.umich.edu 6178481Sgblack@eecs.umich.edu fst_data_pkt->dataStatic(load_inst->memData); 6188481Sgblack@eecs.umich.edu snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize()); 6198481Sgblack@eecs.umich.edu 6208481Sgblack@eecs.umich.edu delay = TheISA::handleIprRead(thread, fst_data_pkt); 6218481Sgblack@eecs.umich.edu unsigned delay2 = TheISA::handleIprRead(thread, snd_data_pkt); 6228481Sgblack@eecs.umich.edu if (delay2 > delay) 6238481Sgblack@eecs.umich.edu delay = delay2; 6248481Sgblack@eecs.umich.edu 6258481Sgblack@eecs.umich.edu delete sreqLow; 6268481Sgblack@eecs.umich.edu delete sreqHigh; 6278481Sgblack@eecs.umich.edu delete fst_data_pkt; 6288481Sgblack@eecs.umich.edu delete snd_data_pkt; 6298481Sgblack@eecs.umich.edu } 6308481Sgblack@eecs.umich.edu WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 6318481Sgblack@eecs.umich.edu cpu->schedule(wb, curTick() + delay); 6328481Sgblack@eecs.umich.edu return NoFault; 6338481Sgblack@eecs.umich.edu } 6348481Sgblack@eecs.umich.edu 6352292SN/A while (store_idx != -1) { 6362292SN/A // End once we've reached the top of the LSQ 6372292SN/A if (store_idx == storeWBIdx) { 6382292SN/A break; 6392292SN/A } 6402292SN/A 6412292SN/A // Move the index to one younger 6422292SN/A if (--store_idx < 0) 6432292SN/A store_idx += SQEntries; 6442292SN/A 6452292SN/A assert(storeQueue[store_idx].inst); 6462292SN/A 6472292SN/A store_size = storeQueue[store_idx].size; 6482292SN/A 6492292SN/A if (store_size == 0) 6502292SN/A continue; 6514032Sktlim@umich.edu else if (storeQueue[store_idx].inst->uncacheable()) 6524032Sktlim@umich.edu continue; 6534032Sktlim@umich.edu 6544032Sktlim@umich.edu assert(storeQueue[store_idx].inst->effAddrValid); 6552292SN/A 6562292SN/A // Check if the store data is within the lower and upper bounds of 6572292SN/A // addresses that the request needs. 6582292SN/A bool store_has_lower_limit = 6592669Sktlim@umich.edu req->getVaddr() >= storeQueue[store_idx].inst->effAddr; 6602292SN/A bool store_has_upper_limit = 6612669Sktlim@umich.edu (req->getVaddr() + req->getSize()) <= 6622669Sktlim@umich.edu (storeQueue[store_idx].inst->effAddr + store_size); 6632292SN/A bool lower_load_has_store_part = 6642669Sktlim@umich.edu req->getVaddr() < (storeQueue[store_idx].inst->effAddr + 6652292SN/A store_size); 6662292SN/A bool upper_load_has_store_part = 6672669Sktlim@umich.edu (req->getVaddr() + req->getSize()) > 6682669Sktlim@umich.edu storeQueue[store_idx].inst->effAddr; 6692292SN/A 6702292SN/A // If the store's data has all of the data needed, we can forward. 6714032Sktlim@umich.edu if ((store_has_lower_limit && store_has_upper_limit)) { 6722329SN/A // Get shift amount for offset into the store's data. 6738316Sgeoffrey.blake@arm.com int shift_amt = req->getVaddr() - storeQueue[store_idx].inst->effAddr; 6742292SN/A 6757520Sgblack@eecs.umich.edu memcpy(data, storeQueue[store_idx].data + shift_amt, 6767520Sgblack@eecs.umich.edu req->getSize()); 6773803Sgblack@eecs.umich.edu 6782669Sktlim@umich.edu assert(!load_inst->memData); 6792669Sktlim@umich.edu load_inst->memData = new uint8_t[64]; 6802292SN/A 6814326Sgblack@eecs.umich.edu memcpy(load_inst->memData, 6824326Sgblack@eecs.umich.edu storeQueue[store_idx].data + shift_amt, req->getSize()); 6832292SN/A 6842292SN/A DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 6852292SN/A "addr %#x, data %#x\n", 6862693Sktlim@umich.edu store_idx, req->getVaddr(), data); 6872678Sktlim@umich.edu 6888949Sandreas.hansson@arm.com PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq); 6892678Sktlim@umich.edu data_pkt->dataStatic(load_inst->memData); 6902678Sktlim@umich.edu 6912678Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 6922292SN/A 6932292SN/A // We'll say this has a 1 cycle load-store forwarding latency 6942292SN/A // for now. 6952292SN/A // @todo: Need to make this a parameter. 6967823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick()); 6972678Sktlim@umich.edu 6986974Stjones1@inf.ed.ac.uk // Don't need to do anything special for split loads. 6996974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 7006974Stjones1@inf.ed.ac.uk delete sreqLow; 7016974Stjones1@inf.ed.ac.uk delete sreqHigh; 7026974Stjones1@inf.ed.ac.uk } 7036974Stjones1@inf.ed.ac.uk 7042727Sktlim@umich.edu ++lsqForwLoads; 7052292SN/A return NoFault; 7062292SN/A } else if ((store_has_lower_limit && lower_load_has_store_part) || 7072292SN/A (store_has_upper_limit && upper_load_has_store_part) || 7082292SN/A (lower_load_has_store_part && upper_load_has_store_part)) { 7092292SN/A // This is the partial store-load forwarding case where a store 7102292SN/A // has only part of the load's data. 7112292SN/A 7122292SN/A // If it's already been written back, then don't worry about 7132292SN/A // stalling on it. 7142292SN/A if (storeQueue[store_idx].completed) { 7154032Sktlim@umich.edu panic("Should not check one of these"); 7162292SN/A continue; 7172292SN/A } 7182292SN/A 7192292SN/A // Must stall load and force it to retry, so long as it's the oldest 7202292SN/A // load that needs to do so. 7212292SN/A if (!stalled || 7222292SN/A (stalled && 7232669Sktlim@umich.edu load_inst->seqNum < 7242292SN/A loadQueue[stallingLoadIdx]->seqNum)) { 7252292SN/A stalled = true; 7262292SN/A stallingStoreIsn = storeQueue[store_idx].inst->seqNum; 7272292SN/A stallingLoadIdx = load_idx; 7282292SN/A } 7292292SN/A 7302292SN/A // Tell IQ/mem dep unit that this instruction will need to be 7312292SN/A // rescheduled eventually 7322669Sktlim@umich.edu iewStage->rescheduleMemInst(load_inst); 7332927Sktlim@umich.edu iewStage->decrWb(load_inst->seqNum); 7344032Sktlim@umich.edu load_inst->clearIssued(); 7352727Sktlim@umich.edu ++lsqRescheduledLoads; 7362292SN/A 7372292SN/A // Do not generate a writeback event as this instruction is not 7382292SN/A // complete. 7392292SN/A DPRINTF(LSQUnit, "Load-store forwarding mis-match. " 7402292SN/A "Store idx %i to load addr %#x\n", 7412669Sktlim@umich.edu store_idx, req->getVaddr()); 7422292SN/A 7434032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 7444032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the 7454032Sktlim@umich.edu // proper place to really handle request deletes. 7464032Sktlim@umich.edu delete req; 7476974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 7486974Stjones1@inf.ed.ac.uk delete sreqLow; 7496974Stjones1@inf.ed.ac.uk delete sreqHigh; 7506974Stjones1@inf.ed.ac.uk } 7514032Sktlim@umich.edu 7522292SN/A return NoFault; 7532292SN/A } 7542292SN/A } 7552292SN/A 7562292SN/A // If there's no forwarding case, then go access memory 7577720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n", 7587720Sgblack@eecs.umich.edu load_inst->seqNum, load_inst->pcState()); 7592292SN/A 7602669Sktlim@umich.edu assert(!load_inst->memData); 7612669Sktlim@umich.edu load_inst->memData = new uint8_t[64]; 7622292SN/A 7632292SN/A ++usedPorts; 7642292SN/A 7652907Sktlim@umich.edu // if we the cache is not blocked, do cache access 7666974Stjones1@inf.ed.ac.uk bool completedFirst = false; 7672907Sktlim@umich.edu if (!lsq->cacheBlocked()) { 7686974Stjones1@inf.ed.ac.uk MemCmd command = 7696974Stjones1@inf.ed.ac.uk req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq; 7708949Sandreas.hansson@arm.com PacketPtr data_pkt = new Packet(req, command); 7716974Stjones1@inf.ed.ac.uk PacketPtr fst_data_pkt = NULL; 7726974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 7736974Stjones1@inf.ed.ac.uk 7743228Sktlim@umich.edu data_pkt->dataStatic(load_inst->memData); 7753228Sktlim@umich.edu 7763228Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 7773228Sktlim@umich.edu state->isLoad = true; 7783228Sktlim@umich.edu state->idx = load_idx; 7793228Sktlim@umich.edu state->inst = load_inst; 7803228Sktlim@umich.edu data_pkt->senderState = state; 7813228Sktlim@umich.edu 7826974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !sreqLow) { 7836974Stjones1@inf.ed.ac.uk 7846974Stjones1@inf.ed.ac.uk // Point the first packet at the main data packet. 7856974Stjones1@inf.ed.ac.uk fst_data_pkt = data_pkt; 7866974Stjones1@inf.ed.ac.uk } else { 7876974Stjones1@inf.ed.ac.uk 7886974Stjones1@inf.ed.ac.uk // Create the split packets. 7898949Sandreas.hansson@arm.com fst_data_pkt = new Packet(sreqLow, command); 7908949Sandreas.hansson@arm.com snd_data_pkt = new Packet(sreqHigh, command); 7916974Stjones1@inf.ed.ac.uk 7926974Stjones1@inf.ed.ac.uk fst_data_pkt->dataStatic(load_inst->memData); 7936974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize()); 7946974Stjones1@inf.ed.ac.uk 7956974Stjones1@inf.ed.ac.uk fst_data_pkt->senderState = state; 7966974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 7976974Stjones1@inf.ed.ac.uk 7986974Stjones1@inf.ed.ac.uk state->isSplit = true; 7996974Stjones1@inf.ed.ac.uk state->outstanding = 2; 8006974Stjones1@inf.ed.ac.uk state->mainPkt = data_pkt; 8016974Stjones1@inf.ed.ac.uk } 8026974Stjones1@inf.ed.ac.uk 8038975Sandreas.hansson@arm.com if (!dcachePort->sendTimingReq(fst_data_pkt)) { 8043228Sktlim@umich.edu // Delete state and data packet because a load retry 8053228Sktlim@umich.edu // initiates a pipeline restart; it does not retry. 8063228Sktlim@umich.edu delete state; 8074032Sktlim@umich.edu delete data_pkt->req; 8083228Sktlim@umich.edu delete data_pkt; 8096974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 8106974Stjones1@inf.ed.ac.uk delete fst_data_pkt->req; 8116974Stjones1@inf.ed.ac.uk delete fst_data_pkt; 8126974Stjones1@inf.ed.ac.uk delete snd_data_pkt->req; 8136974Stjones1@inf.ed.ac.uk delete snd_data_pkt; 8147511Stjones1@inf.ed.ac.uk sreqLow = NULL; 8157511Stjones1@inf.ed.ac.uk sreqHigh = NULL; 8166974Stjones1@inf.ed.ac.uk } 8173228Sktlim@umich.edu 8184032Sktlim@umich.edu req = NULL; 8194032Sktlim@umich.edu 8202907Sktlim@umich.edu // If the access didn't succeed, tell the LSQ by setting 8212907Sktlim@umich.edu // the retry thread id. 8222907Sktlim@umich.edu lsq->setRetryTid(lsqID); 8236974Stjones1@inf.ed.ac.uk } else if (TheISA::HasUnalignedMemAcc && sreqLow) { 8246974Stjones1@inf.ed.ac.uk completedFirst = true; 8256974Stjones1@inf.ed.ac.uk 8266974Stjones1@inf.ed.ac.uk // The first packet was sent without problems, so send this one 8276974Stjones1@inf.ed.ac.uk // too. If there is a problem with this packet then the whole 8286974Stjones1@inf.ed.ac.uk // load will be squashed, so indicate this to the state object. 8296974Stjones1@inf.ed.ac.uk // The first packet will return in completeDataAccess and be 8306974Stjones1@inf.ed.ac.uk // handled there. 8316974Stjones1@inf.ed.ac.uk ++usedPorts; 8328975Sandreas.hansson@arm.com if (!dcachePort->sendTimingReq(snd_data_pkt)) { 8336974Stjones1@inf.ed.ac.uk 8346974Stjones1@inf.ed.ac.uk // The main packet will be deleted in completeDataAccess. 8356974Stjones1@inf.ed.ac.uk delete snd_data_pkt->req; 8366974Stjones1@inf.ed.ac.uk delete snd_data_pkt; 8376974Stjones1@inf.ed.ac.uk 8386974Stjones1@inf.ed.ac.uk state->complete(); 8396974Stjones1@inf.ed.ac.uk 8406974Stjones1@inf.ed.ac.uk req = NULL; 8417511Stjones1@inf.ed.ac.uk sreqHigh = NULL; 8426974Stjones1@inf.ed.ac.uk 8436974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 8446974Stjones1@inf.ed.ac.uk } 8452907Sktlim@umich.edu } 8462907Sktlim@umich.edu } 8472907Sktlim@umich.edu 8482907Sktlim@umich.edu // If the cache was blocked, or has become blocked due to the access, 8492907Sktlim@umich.edu // handle it. 8502907Sktlim@umich.edu if (lsq->cacheBlocked()) { 8514032Sktlim@umich.edu if (req) 8524032Sktlim@umich.edu delete req; 8536974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow && !completedFirst) { 8546974Stjones1@inf.ed.ac.uk delete sreqLow; 8556974Stjones1@inf.ed.ac.uk delete sreqHigh; 8566974Stjones1@inf.ed.ac.uk } 8574032Sktlim@umich.edu 8582727Sktlim@umich.edu ++lsqCacheBlocked; 8593014Srdreslin@umich.edu 8608315Sgeoffrey.blake@arm.com // If the first part of a split access succeeds, then let the LSQ 8618315Sgeoffrey.blake@arm.com // handle the decrWb when completeDataAccess is called upon return 8628315Sgeoffrey.blake@arm.com // of the requested first part of data 8638315Sgeoffrey.blake@arm.com if (!completedFirst) 8648315Sgeoffrey.blake@arm.com iewStage->decrWb(load_inst->seqNum); 8658315Sgeoffrey.blake@arm.com 8662669Sktlim@umich.edu // There's an older load that's already going to squash. 8672669Sktlim@umich.edu if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) 8682669Sktlim@umich.edu return NoFault; 8692292SN/A 8702669Sktlim@umich.edu // Record that the load was blocked due to memory. This 8712669Sktlim@umich.edu // load will squash all instructions after it, be 8722669Sktlim@umich.edu // refetched, and re-executed. 8732669Sktlim@umich.edu isLoadBlocked = true; 8742669Sktlim@umich.edu loadBlockedHandled = false; 8752669Sktlim@umich.edu blockedLoadSeqNum = load_inst->seqNum; 8762669Sktlim@umich.edu // No fault occurred, even though the interface is blocked. 8772669Sktlim@umich.edu return NoFault; 8782292SN/A } 8792292SN/A 8802669Sktlim@umich.edu return NoFault; 8812292SN/A} 8822292SN/A 8832292SN/Atemplate <class Impl> 8842292SN/AFault 8856974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh, 8867520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 8872292SN/A{ 8882292SN/A assert(storeQueue[store_idx].inst); 8892292SN/A 8902292SN/A DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x" 8912292SN/A " | storeHead:%i [sn:%i]\n", 8922669Sktlim@umich.edu store_idx, req->getPaddr(), data, storeHead, 8932292SN/A storeQueue[store_idx].inst->seqNum); 8942329SN/A 8952292SN/A storeQueue[store_idx].req = req; 8966974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = sreqLow; 8976974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = sreqHigh; 8987520Sgblack@eecs.umich.edu unsigned size = req->getSize(); 8997520Sgblack@eecs.umich.edu storeQueue[store_idx].size = size; 9007520Sgblack@eecs.umich.edu assert(size <= sizeof(storeQueue[store_idx].data)); 9017509Stjones1@inf.ed.ac.uk 9027509Stjones1@inf.ed.ac.uk // Split stores can only occur in ISAs with unaligned memory accesses. If 9037509Stjones1@inf.ed.ac.uk // a store request has been split, sreqLow and sreqHigh will be non-null. 9047509Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 9057509Stjones1@inf.ed.ac.uk storeQueue[store_idx].isSplit = true; 9067509Stjones1@inf.ed.ac.uk } 9074326Sgblack@eecs.umich.edu 9087520Sgblack@eecs.umich.edu memcpy(storeQueue[store_idx].data, data, size); 9092329SN/A 9102292SN/A // This function only writes the data to the store queue, so no fault 9112292SN/A // can happen here. 9122292SN/A return NoFault; 9132292SN/A} 9142292SN/A 9152292SN/A#endif // __CPU_O3_LSQ_UNIT_HH__ 916