lsq_unit.hh revision 8230
12292SN/A/* 22329SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Kevin Lim 292689Sktlim@umich.edu * Korey Sewell 302292SN/A */ 312292SN/A 322292SN/A#ifndef __CPU_O3_LSQ_UNIT_HH__ 332292SN/A#define __CPU_O3_LSQ_UNIT_HH__ 342292SN/A 352329SN/A#include <algorithm> 364395Ssaidi@eecs.umich.edu#include <cstring> 372292SN/A#include <map> 382292SN/A#include <queue> 392292SN/A 402329SN/A#include "arch/faults.hh" 413326Sktlim@umich.edu#include "arch/locked_mem.hh" 428229Snate@binkert.org#include "base/fast_alloc.hh" 438229Snate@binkert.org#include "base/hashmap.hh" 442292SN/A#include "config/full_system.hh" 456658Snate@binkert.org#include "config/the_isa.hh" 462292SN/A#include "cpu/inst_seq.hh" 478230Snate@binkert.org#include "cpu/timebuf.hh" 483348Sbinkertn@umich.edu#include "mem/packet.hh" 492669Sktlim@umich.edu#include "mem/port.hh" 502292SN/A 515529Snate@binkert.orgclass DerivO3CPUParams; 525529Snate@binkert.org 532292SN/A/** 542329SN/A * Class that implements the actual LQ and SQ for each specific 552329SN/A * thread. Both are circular queues; load entries are freed upon 562329SN/A * committing, while store entries are freed once they writeback. The 572329SN/A * LSQUnit tracks if there are memory ordering violations, and also 582329SN/A * detects partial load to store forwarding cases (a store only has 592329SN/A * part of a load's data) that requires the load to wait until the 602329SN/A * store writes back. In the former case it holds onto the instruction 612329SN/A * until the dependence unit looks at it, and in the latter it stalls 622329SN/A * the LSQ until the store writes back. At that point the load is 632329SN/A * replayed. 642292SN/A */ 652292SN/Atemplate <class Impl> 662292SN/Aclass LSQUnit { 672292SN/A public: 682733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 692292SN/A typedef typename Impl::DynInstPtr DynInstPtr; 702292SN/A typedef typename Impl::CPUPol::IEW IEW; 712907Sktlim@umich.edu typedef typename Impl::CPUPol::LSQ LSQ; 722292SN/A typedef typename Impl::CPUPol::IssueStruct IssueStruct; 732292SN/A 742292SN/A public: 752292SN/A /** Constructs an LSQ unit. init() must be called prior to use. */ 762292SN/A LSQUnit(); 772292SN/A 782292SN/A /** Initializes the LSQ unit with the specified number of entries. */ 795529Snate@binkert.org void init(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params, 805529Snate@binkert.org LSQ *lsq_ptr, unsigned maxLQEntries, unsigned maxSQEntries, 815529Snate@binkert.org unsigned id); 822292SN/A 832292SN/A /** Returns the name of the LSQ unit. */ 842292SN/A std::string name() const; 852292SN/A 862727Sktlim@umich.edu /** Registers statistics. */ 872727Sktlim@umich.edu void regStats(); 882727Sktlim@umich.edu 892907Sktlim@umich.edu /** Sets the pointer to the dcache port. */ 904329Sktlim@umich.edu void setDcachePort(Port *dcache_port); 912907Sktlim@umich.edu 922348SN/A /** Switches out LSQ unit. */ 932307SN/A void switchOut(); 942307SN/A 952348SN/A /** Takes over from another CPU's thread. */ 962307SN/A void takeOverFrom(); 972307SN/A 982348SN/A /** Returns if the LSQ is switched out. */ 992307SN/A bool isSwitchedOut() { return switchedOut; } 1002307SN/A 1012292SN/A /** Ticks the LSQ unit, which in this case only resets the number of 1022292SN/A * used cache ports. 1032292SN/A * @todo: Move the number of used ports up to the LSQ level so it can 1042292SN/A * be shared by all LSQ units. 1052292SN/A */ 1062292SN/A void tick() { usedPorts = 0; } 1072292SN/A 1082292SN/A /** Inserts an instruction. */ 1092292SN/A void insert(DynInstPtr &inst); 1102292SN/A /** Inserts a load instruction. */ 1112292SN/A void insertLoad(DynInstPtr &load_inst); 1122292SN/A /** Inserts a store instruction. */ 1132292SN/A void insertStore(DynInstPtr &store_inst); 1142292SN/A 1158199SAli.Saidi@ARM.com /** Check for ordering violations in the LSQ 1168199SAli.Saidi@ARM.com * @param load_idx index to start checking at 1178199SAli.Saidi@ARM.com * @param inst the instruction to check 1188199SAli.Saidi@ARM.com */ 1198199SAli.Saidi@ARM.com Fault checkViolations(int load_idx, DynInstPtr &inst); 1208199SAli.Saidi@ARM.com 1212292SN/A /** Executes a load instruction. */ 1222292SN/A Fault executeLoad(DynInstPtr &inst); 1232292SN/A 1242329SN/A Fault executeLoad(int lq_idx) { panic("Not implemented"); return NoFault; } 1252292SN/A /** Executes a store instruction. */ 1262292SN/A Fault executeStore(DynInstPtr &inst); 1272292SN/A 1282292SN/A /** Commits the head load. */ 1292292SN/A void commitLoad(); 1302292SN/A /** Commits loads older than a specific sequence number. */ 1312292SN/A void commitLoads(InstSeqNum &youngest_inst); 1322292SN/A 1332292SN/A /** Commits stores older than a specific sequence number. */ 1342292SN/A void commitStores(InstSeqNum &youngest_inst); 1352292SN/A 1362292SN/A /** Writes back stores. */ 1372292SN/A void writebackStores(); 1382292SN/A 1392790Sktlim@umich.edu /** Completes the data access that has been returned from the 1402790Sktlim@umich.edu * memory system. */ 1412669Sktlim@umich.edu void completeDataAccess(PacketPtr pkt); 1422669Sktlim@umich.edu 1432292SN/A /** Clears all the entries in the LQ. */ 1442292SN/A void clearLQ(); 1452292SN/A 1462292SN/A /** Clears all the entries in the SQ. */ 1472292SN/A void clearSQ(); 1482292SN/A 1492292SN/A /** Resizes the LQ to a given size. */ 1502292SN/A void resizeLQ(unsigned size); 1512292SN/A 1522292SN/A /** Resizes the SQ to a given size. */ 1532292SN/A void resizeSQ(unsigned size); 1542292SN/A 1552292SN/A /** Squashes all instructions younger than a specific sequence number. */ 1562292SN/A void squash(const InstSeqNum &squashed_num); 1572292SN/A 1582292SN/A /** Returns if there is a memory ordering violation. Value is reset upon 1592292SN/A * call to getMemDepViolator(). 1602292SN/A */ 1612292SN/A bool violation() { return memDepViolator; } 1622292SN/A 1632292SN/A /** Returns the memory ordering violator. */ 1642292SN/A DynInstPtr getMemDepViolator(); 1652292SN/A 1662329SN/A /** Returns if a load became blocked due to the memory system. */ 1672292SN/A bool loadBlocked() 1682292SN/A { return isLoadBlocked; } 1692292SN/A 1702348SN/A /** Clears the signal that a load became blocked. */ 1712292SN/A void clearLoadBlocked() 1722292SN/A { isLoadBlocked = false; } 1732292SN/A 1742348SN/A /** Returns if the blocked load was handled. */ 1752292SN/A bool isLoadBlockedHandled() 1762292SN/A { return loadBlockedHandled; } 1772292SN/A 1782348SN/A /** Records the blocked load as being handled. */ 1792292SN/A void setLoadBlockedHandled() 1802292SN/A { loadBlockedHandled = true; } 1812292SN/A 1822292SN/A /** Returns the number of free entries (min of free LQ and SQ entries). */ 1832292SN/A unsigned numFreeEntries(); 1842292SN/A 1852292SN/A /** Returns the number of loads ready to execute. */ 1862292SN/A int numLoadsReady(); 1872292SN/A 1882292SN/A /** Returns the number of loads in the LQ. */ 1892292SN/A int numLoads() { return loads; } 1902292SN/A 1912292SN/A /** Returns the number of stores in the SQ. */ 1922292SN/A int numStores() { return stores; } 1932292SN/A 1942292SN/A /** Returns if either the LQ or SQ is full. */ 1952292SN/A bool isFull() { return lqFull() || sqFull(); } 1962292SN/A 1972292SN/A /** Returns if the LQ is full. */ 1982292SN/A bool lqFull() { return loads >= (LQEntries - 1); } 1992292SN/A 2002292SN/A /** Returns if the SQ is full. */ 2012292SN/A bool sqFull() { return stores >= (SQEntries - 1); } 2022292SN/A 2032292SN/A /** Returns the number of instructions in the LSQ. */ 2042292SN/A unsigned getCount() { return loads + stores; } 2052292SN/A 2062292SN/A /** Returns if there are any stores to writeback. */ 2072292SN/A bool hasStoresToWB() { return storesToWB; } 2082292SN/A 2092292SN/A /** Returns the number of stores to writeback. */ 2102292SN/A int numStoresToWB() { return storesToWB; } 2112292SN/A 2122292SN/A /** Returns if the LSQ unit will writeback on this cycle. */ 2132292SN/A bool willWB() { return storeQueue[storeWBIdx].canWB && 2142678Sktlim@umich.edu !storeQueue[storeWBIdx].completed && 2152678Sktlim@umich.edu !isStoreBlocked; } 2162292SN/A 2172907Sktlim@umich.edu /** Handles doing the retry. */ 2182907Sktlim@umich.edu void recvRetry(); 2192907Sktlim@umich.edu 2202292SN/A private: 2212698Sktlim@umich.edu /** Writes back the instruction, sending it to IEW. */ 2222678Sktlim@umich.edu void writeback(DynInstPtr &inst, PacketPtr pkt); 2232678Sktlim@umich.edu 2246974Stjones1@inf.ed.ac.uk /** Writes back a store that couldn't be completed the previous cycle. */ 2256974Stjones1@inf.ed.ac.uk void writebackPendingStore(); 2266974Stjones1@inf.ed.ac.uk 2272698Sktlim@umich.edu /** Handles completing the send of a store to memory. */ 2283349Sbinkertn@umich.edu void storePostSend(PacketPtr pkt); 2292693Sktlim@umich.edu 2302292SN/A /** Completes the store at the specified index. */ 2312292SN/A void completeStore(int store_idx); 2322292SN/A 2336974Stjones1@inf.ed.ac.uk /** Attempts to send a store to the cache. */ 2346974Stjones1@inf.ed.ac.uk bool sendStore(PacketPtr data_pkt); 2356974Stjones1@inf.ed.ac.uk 2362292SN/A /** Increments the given store index (circular queue). */ 2372292SN/A inline void incrStIdx(int &store_idx); 2382292SN/A /** Decrements the given store index (circular queue). */ 2392292SN/A inline void decrStIdx(int &store_idx); 2402292SN/A /** Increments the given load index (circular queue). */ 2412292SN/A inline void incrLdIdx(int &load_idx); 2422292SN/A /** Decrements the given load index (circular queue). */ 2432292SN/A inline void decrLdIdx(int &load_idx); 2442292SN/A 2452329SN/A public: 2462329SN/A /** Debugging function to dump instructions in the LSQ. */ 2472329SN/A void dumpInsts(); 2482329SN/A 2492292SN/A private: 2502292SN/A /** Pointer to the CPU. */ 2512733Sktlim@umich.edu O3CPU *cpu; 2522292SN/A 2532292SN/A /** Pointer to the IEW stage. */ 2542292SN/A IEW *iewStage; 2552292SN/A 2562907Sktlim@umich.edu /** Pointer to the LSQ. */ 2572907Sktlim@umich.edu LSQ *lsq; 2582669Sktlim@umich.edu 2592907Sktlim@umich.edu /** Pointer to the dcache port. Used only for sending. */ 2602907Sktlim@umich.edu Port *dcachePort; 2612292SN/A 2622698Sktlim@umich.edu /** Derived class to hold any sender state the LSQ needs. */ 2635386Sstever@gmail.com class LSQSenderState : public Packet::SenderState, public FastAlloc 2642678Sktlim@umich.edu { 2652678Sktlim@umich.edu public: 2662698Sktlim@umich.edu /** Default constructor. */ 2672678Sktlim@umich.edu LSQSenderState() 2686974Stjones1@inf.ed.ac.uk : noWB(false), isSplit(false), pktToSend(false), outstanding(1), 2696974Stjones1@inf.ed.ac.uk mainPkt(NULL), pendingPacket(NULL) 2702678Sktlim@umich.edu { } 2712678Sktlim@umich.edu 2722698Sktlim@umich.edu /** Instruction who initiated the access to memory. */ 2732678Sktlim@umich.edu DynInstPtr inst; 2742698Sktlim@umich.edu /** Whether or not it is a load. */ 2752678Sktlim@umich.edu bool isLoad; 2762698Sktlim@umich.edu /** The LQ/SQ index of the instruction. */ 2772678Sktlim@umich.edu int idx; 2782698Sktlim@umich.edu /** Whether or not the instruction will need to writeback. */ 2792678Sktlim@umich.edu bool noWB; 2806974Stjones1@inf.ed.ac.uk /** Whether or not this access is split in two. */ 2816974Stjones1@inf.ed.ac.uk bool isSplit; 2826974Stjones1@inf.ed.ac.uk /** Whether or not there is a packet that needs sending. */ 2836974Stjones1@inf.ed.ac.uk bool pktToSend; 2846974Stjones1@inf.ed.ac.uk /** Number of outstanding packets to complete. */ 2856974Stjones1@inf.ed.ac.uk int outstanding; 2866974Stjones1@inf.ed.ac.uk /** The main packet from a split load, used during writeback. */ 2876974Stjones1@inf.ed.ac.uk PacketPtr mainPkt; 2886974Stjones1@inf.ed.ac.uk /** A second packet from a split store that needs sending. */ 2896974Stjones1@inf.ed.ac.uk PacketPtr pendingPacket; 2906974Stjones1@inf.ed.ac.uk 2916974Stjones1@inf.ed.ac.uk /** Completes a packet and returns whether the access is finished. */ 2926974Stjones1@inf.ed.ac.uk inline bool complete() { return --outstanding == 0; } 2932678Sktlim@umich.edu }; 2942678Sktlim@umich.edu 2952698Sktlim@umich.edu /** Writeback event, specifically for when stores forward data to loads. */ 2962678Sktlim@umich.edu class WritebackEvent : public Event { 2972678Sktlim@umich.edu public: 2982678Sktlim@umich.edu /** Constructs a writeback event. */ 2992678Sktlim@umich.edu WritebackEvent(DynInstPtr &_inst, PacketPtr pkt, LSQUnit *lsq_ptr); 3002678Sktlim@umich.edu 3012678Sktlim@umich.edu /** Processes the writeback event. */ 3022678Sktlim@umich.edu void process(); 3032678Sktlim@umich.edu 3042678Sktlim@umich.edu /** Returns the description of this event. */ 3055336Shines@cs.fsu.edu const char *description() const; 3062678Sktlim@umich.edu 3072678Sktlim@umich.edu private: 3082698Sktlim@umich.edu /** Instruction whose results are being written back. */ 3092678Sktlim@umich.edu DynInstPtr inst; 3102678Sktlim@umich.edu 3112698Sktlim@umich.edu /** The packet that would have been sent to memory. */ 3122678Sktlim@umich.edu PacketPtr pkt; 3132678Sktlim@umich.edu 3142678Sktlim@umich.edu /** The pointer to the LSQ unit that issued the store. */ 3152678Sktlim@umich.edu LSQUnit<Impl> *lsqPtr; 3162678Sktlim@umich.edu }; 3172678Sktlim@umich.edu 3182292SN/A public: 3192292SN/A struct SQEntry { 3202292SN/A /** Constructs an empty store queue entry. */ 3212292SN/A SQEntry() 3224326Sgblack@eecs.umich.edu : inst(NULL), req(NULL), size(0), 3232292SN/A canWB(0), committed(0), completed(0) 3244326Sgblack@eecs.umich.edu { 3254395Ssaidi@eecs.umich.edu std::memset(data, 0, sizeof(data)); 3264326Sgblack@eecs.umich.edu } 3272292SN/A 3282292SN/A /** Constructs a store queue entry for a given instruction. */ 3292292SN/A SQEntry(DynInstPtr &_inst) 3306974Stjones1@inf.ed.ac.uk : inst(_inst), req(NULL), sreqLow(NULL), sreqHigh(NULL), size(0), 3316974Stjones1@inf.ed.ac.uk isSplit(0), canWB(0), committed(0), completed(0) 3324326Sgblack@eecs.umich.edu { 3334395Ssaidi@eecs.umich.edu std::memset(data, 0, sizeof(data)); 3344326Sgblack@eecs.umich.edu } 3352292SN/A 3362292SN/A /** The store instruction. */ 3372292SN/A DynInstPtr inst; 3382669Sktlim@umich.edu /** The request for the store. */ 3392669Sktlim@umich.edu RequestPtr req; 3406974Stjones1@inf.ed.ac.uk /** The split requests for the store. */ 3416974Stjones1@inf.ed.ac.uk RequestPtr sreqLow; 3426974Stjones1@inf.ed.ac.uk RequestPtr sreqHigh; 3432292SN/A /** The size of the store. */ 3442292SN/A int size; 3452292SN/A /** The store data. */ 3467786SAli.Saidi@ARM.com char data[16]; 3476974Stjones1@inf.ed.ac.uk /** Whether or not the store is split into two requests. */ 3486974Stjones1@inf.ed.ac.uk bool isSplit; 3492292SN/A /** Whether or not the store can writeback. */ 3502292SN/A bool canWB; 3512292SN/A /** Whether or not the store is committed. */ 3522292SN/A bool committed; 3532292SN/A /** Whether or not the store is completed. */ 3542292SN/A bool completed; 3552292SN/A }; 3562329SN/A 3572292SN/A private: 3582292SN/A /** The LSQUnit thread id. */ 3596221Snate@binkert.org ThreadID lsqID; 3602292SN/A 3612292SN/A /** The store queue. */ 3622292SN/A std::vector<SQEntry> storeQueue; 3632292SN/A 3642292SN/A /** The load queue. */ 3652292SN/A std::vector<DynInstPtr> loadQueue; 3662292SN/A 3672329SN/A /** The number of LQ entries, plus a sentinel entry (circular queue). 3682329SN/A * @todo: Consider having var that records the true number of LQ entries. 3692329SN/A */ 3702292SN/A unsigned LQEntries; 3712329SN/A /** The number of SQ entries, plus a sentinel entry (circular queue). 3722329SN/A * @todo: Consider having var that records the true number of SQ entries. 3732329SN/A */ 3742292SN/A unsigned SQEntries; 3752292SN/A 3768199SAli.Saidi@ARM.com /** The number of places to shift addresses in the LSQ before checking 3778199SAli.Saidi@ARM.com * for dependency violations 3788199SAli.Saidi@ARM.com */ 3798199SAli.Saidi@ARM.com unsigned depCheckShift; 3808199SAli.Saidi@ARM.com 3818199SAli.Saidi@ARM.com /** Should loads be checked for dependency issues */ 3828199SAli.Saidi@ARM.com bool checkLoads; 3838199SAli.Saidi@ARM.com 3842292SN/A /** The number of load instructions in the LQ. */ 3852292SN/A int loads; 3862329SN/A /** The number of store instructions in the SQ. */ 3872292SN/A int stores; 3882292SN/A /** The number of store instructions in the SQ waiting to writeback. */ 3892292SN/A int storesToWB; 3902292SN/A 3912292SN/A /** The index of the head instruction in the LQ. */ 3922292SN/A int loadHead; 3932292SN/A /** The index of the tail instruction in the LQ. */ 3942292SN/A int loadTail; 3952292SN/A 3962292SN/A /** The index of the head instruction in the SQ. */ 3972292SN/A int storeHead; 3982329SN/A /** The index of the first instruction that may be ready to be 3992329SN/A * written back, and has not yet been written back. 4002292SN/A */ 4012292SN/A int storeWBIdx; 4022292SN/A /** The index of the tail instruction in the SQ. */ 4032292SN/A int storeTail; 4042292SN/A 4052292SN/A /// @todo Consider moving to a more advanced model with write vs read ports 4062292SN/A /** The number of cache ports available each cycle. */ 4072292SN/A int cachePorts; 4082292SN/A 4092292SN/A /** The number of used cache ports in this cycle. */ 4102292SN/A int usedPorts; 4112292SN/A 4122348SN/A /** Is the LSQ switched out. */ 4132307SN/A bool switchedOut; 4142307SN/A 4152292SN/A //list<InstSeqNum> mshrSeqNums; 4162292SN/A 4172292SN/A /** Wire to read information from the issue stage time queue. */ 4182292SN/A typename TimeBuffer<IssueStruct>::wire fromIssue; 4192292SN/A 4202292SN/A /** Whether or not the LSQ is stalled. */ 4212292SN/A bool stalled; 4222292SN/A /** The store that causes the stall due to partial store to load 4232292SN/A * forwarding. 4242292SN/A */ 4252292SN/A InstSeqNum stallingStoreIsn; 4262292SN/A /** The index of the above store. */ 4272292SN/A int stallingLoadIdx; 4282292SN/A 4292698Sktlim@umich.edu /** The packet that needs to be retried. */ 4302698Sktlim@umich.edu PacketPtr retryPkt; 4312693Sktlim@umich.edu 4322698Sktlim@umich.edu /** Whehter or not a store is blocked due to the memory system. */ 4332678Sktlim@umich.edu bool isStoreBlocked; 4342678Sktlim@umich.edu 4352329SN/A /** Whether or not a load is blocked due to the memory system. */ 4362292SN/A bool isLoadBlocked; 4372292SN/A 4382348SN/A /** Has the blocked load been handled. */ 4392292SN/A bool loadBlockedHandled; 4402292SN/A 4412348SN/A /** The sequence number of the blocked load. */ 4422292SN/A InstSeqNum blockedLoadSeqNum; 4432292SN/A 4442292SN/A /** The oldest load that caused a memory ordering violation. */ 4452292SN/A DynInstPtr memDepViolator; 4462292SN/A 4476974Stjones1@inf.ed.ac.uk /** Whether or not there is a packet that couldn't be sent because of 4486974Stjones1@inf.ed.ac.uk * a lack of cache ports. */ 4496974Stjones1@inf.ed.ac.uk bool hasPendingPkt; 4506974Stjones1@inf.ed.ac.uk 4516974Stjones1@inf.ed.ac.uk /** The packet that is pending free cache ports. */ 4526974Stjones1@inf.ed.ac.uk PacketPtr pendingPkt; 4536974Stjones1@inf.ed.ac.uk 4542292SN/A // Will also need how many read/write ports the Dcache has. Or keep track 4552292SN/A // of that in stage that is one level up, and only call executeLoad/Store 4562292SN/A // the appropriate number of times. 4572727Sktlim@umich.edu /** Total number of loads forwaded from LSQ stores. */ 4585999Snate@binkert.org Stats::Scalar lsqForwLoads; 4592307SN/A 4603126Sktlim@umich.edu /** Total number of loads ignored due to invalid addresses. */ 4615999Snate@binkert.org Stats::Scalar invAddrLoads; 4623126Sktlim@umich.edu 4633126Sktlim@umich.edu /** Total number of squashed loads. */ 4645999Snate@binkert.org Stats::Scalar lsqSquashedLoads; 4653126Sktlim@umich.edu 4663126Sktlim@umich.edu /** Total number of responses from the memory system that are 4673126Sktlim@umich.edu * ignored due to the instruction already being squashed. */ 4685999Snate@binkert.org Stats::Scalar lsqIgnoredResponses; 4693126Sktlim@umich.edu 4703126Sktlim@umich.edu /** Tota number of memory ordering violations. */ 4715999Snate@binkert.org Stats::Scalar lsqMemOrderViolation; 4723126Sktlim@umich.edu 4732727Sktlim@umich.edu /** Total number of squashed stores. */ 4745999Snate@binkert.org Stats::Scalar lsqSquashedStores; 4752727Sktlim@umich.edu 4762727Sktlim@umich.edu /** Total number of software prefetches ignored due to invalid addresses. */ 4775999Snate@binkert.org Stats::Scalar invAddrSwpfs; 4782727Sktlim@umich.edu 4792727Sktlim@umich.edu /** Ready loads blocked due to partial store-forwarding. */ 4805999Snate@binkert.org Stats::Scalar lsqBlockedLoads; 4812727Sktlim@umich.edu 4822727Sktlim@umich.edu /** Number of loads that were rescheduled. */ 4835999Snate@binkert.org Stats::Scalar lsqRescheduledLoads; 4842727Sktlim@umich.edu 4852727Sktlim@umich.edu /** Number of times the LSQ is blocked due to the cache. */ 4865999Snate@binkert.org Stats::Scalar lsqCacheBlocked; 4872727Sktlim@umich.edu 4882292SN/A public: 4892292SN/A /** Executes the load at the given index. */ 4907520Sgblack@eecs.umich.edu Fault read(Request *req, Request *sreqLow, Request *sreqHigh, 4917520Sgblack@eecs.umich.edu uint8_t *data, int load_idx); 4922292SN/A 4932292SN/A /** Executes the store at the given index. */ 4947520Sgblack@eecs.umich.edu Fault write(Request *req, Request *sreqLow, Request *sreqHigh, 4957520Sgblack@eecs.umich.edu uint8_t *data, int store_idx); 4962292SN/A 4972292SN/A /** Returns the index of the head load instruction. */ 4982292SN/A int getLoadHead() { return loadHead; } 4992292SN/A /** Returns the sequence number of the head load instruction. */ 5002292SN/A InstSeqNum getLoadHeadSeqNum() 5012292SN/A { 5022292SN/A if (loadQueue[loadHead]) { 5032292SN/A return loadQueue[loadHead]->seqNum; 5042292SN/A } else { 5052292SN/A return 0; 5062292SN/A } 5072292SN/A 5082292SN/A } 5092292SN/A 5102292SN/A /** Returns the index of the head store instruction. */ 5112292SN/A int getStoreHead() { return storeHead; } 5122292SN/A /** Returns the sequence number of the head store instruction. */ 5132292SN/A InstSeqNum getStoreHeadSeqNum() 5142292SN/A { 5152292SN/A if (storeQueue[storeHead].inst) { 5162292SN/A return storeQueue[storeHead].inst->seqNum; 5172292SN/A } else { 5182292SN/A return 0; 5192292SN/A } 5202292SN/A 5212292SN/A } 5222292SN/A 5232292SN/A /** Returns whether or not the LSQ unit is stalled. */ 5242292SN/A bool isStalled() { return stalled; } 5252292SN/A}; 5262292SN/A 5272292SN/Atemplate <class Impl> 5282292SN/AFault 5296974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::read(Request *req, Request *sreqLow, Request *sreqHigh, 5307520Sgblack@eecs.umich.edu uint8_t *data, int load_idx) 5312292SN/A{ 5322669Sktlim@umich.edu DynInstPtr load_inst = loadQueue[load_idx]; 5332292SN/A 5342669Sktlim@umich.edu assert(load_inst); 5352669Sktlim@umich.edu 5362669Sktlim@umich.edu assert(!load_inst->isExecuted()); 5372292SN/A 5382292SN/A // Make sure this isn't an uncacheable access 5392292SN/A // A bit of a hackish way to get uncached accesses to work only if they're 5402292SN/A // at the head of the LSQ and are ready to commit (at the head of the ROB 5412292SN/A // too). 5423172Sstever@eecs.umich.edu if (req->isUncacheable() && 5432731Sktlim@umich.edu (load_idx != loadHead || !load_inst->isAtCommit())) { 5442669Sktlim@umich.edu iewStage->rescheduleMemInst(load_inst); 5452727Sktlim@umich.edu ++lsqRescheduledLoads; 5467720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Uncachable load [sn:%lli] PC %s\n", 5477720Sgblack@eecs.umich.edu load_inst->seqNum, load_inst->pcState()); 5484032Sktlim@umich.edu 5494032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 5504032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the proper 5514032Sktlim@umich.edu // place to really handle request deletes. 5524032Sktlim@umich.edu delete req; 5536974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 5546974Stjones1@inf.ed.ac.uk delete sreqLow; 5556974Stjones1@inf.ed.ac.uk delete sreqHigh; 5566974Stjones1@inf.ed.ac.uk } 5572292SN/A return TheISA::genMachineCheckFault(); 5582292SN/A } 5592292SN/A 5602292SN/A // Check the SQ for any previous stores that might lead to forwarding 5612669Sktlim@umich.edu int store_idx = load_inst->sqIdx; 5622292SN/A 5632292SN/A int store_size = 0; 5642292SN/A 5652292SN/A DPRINTF(LSQUnit, "Read called, load idx: %i, store idx: %i, " 5666974Stjones1@inf.ed.ac.uk "storeHead: %i addr: %#x%s\n", 5676974Stjones1@inf.ed.ac.uk load_idx, store_idx, storeHead, req->getPaddr(), 5686974Stjones1@inf.ed.ac.uk sreqLow ? " split" : ""); 5692292SN/A 5706102Sgblack@eecs.umich.edu if (req->isLLSC()) { 5716974Stjones1@inf.ed.ac.uk assert(!sreqLow); 5723326Sktlim@umich.edu // Disable recording the result temporarily. Writing to misc 5733326Sktlim@umich.edu // regs normally updates the result, but this is not the 5743326Sktlim@umich.edu // desired behavior when handling store conditionals. 5753326Sktlim@umich.edu load_inst->recordResult = false; 5763326Sktlim@umich.edu TheISA::handleLockedRead(load_inst.get(), req); 5773326Sktlim@umich.edu load_inst->recordResult = true; 5782292SN/A } 5792292SN/A 5802292SN/A while (store_idx != -1) { 5812292SN/A // End once we've reached the top of the LSQ 5822292SN/A if (store_idx == storeWBIdx) { 5832292SN/A break; 5842292SN/A } 5852292SN/A 5862292SN/A // Move the index to one younger 5872292SN/A if (--store_idx < 0) 5882292SN/A store_idx += SQEntries; 5892292SN/A 5902292SN/A assert(storeQueue[store_idx].inst); 5912292SN/A 5922292SN/A store_size = storeQueue[store_idx].size; 5932292SN/A 5942292SN/A if (store_size == 0) 5952292SN/A continue; 5964032Sktlim@umich.edu else if (storeQueue[store_idx].inst->uncacheable()) 5974032Sktlim@umich.edu continue; 5984032Sktlim@umich.edu 5994032Sktlim@umich.edu assert(storeQueue[store_idx].inst->effAddrValid); 6002292SN/A 6012292SN/A // Check if the store data is within the lower and upper bounds of 6022292SN/A // addresses that the request needs. 6032292SN/A bool store_has_lower_limit = 6042669Sktlim@umich.edu req->getVaddr() >= storeQueue[store_idx].inst->effAddr; 6052292SN/A bool store_has_upper_limit = 6062669Sktlim@umich.edu (req->getVaddr() + req->getSize()) <= 6072669Sktlim@umich.edu (storeQueue[store_idx].inst->effAddr + store_size); 6082292SN/A bool lower_load_has_store_part = 6092669Sktlim@umich.edu req->getVaddr() < (storeQueue[store_idx].inst->effAddr + 6102292SN/A store_size); 6112292SN/A bool upper_load_has_store_part = 6122669Sktlim@umich.edu (req->getVaddr() + req->getSize()) > 6132669Sktlim@umich.edu storeQueue[store_idx].inst->effAddr; 6142292SN/A 6152292SN/A // If the store's data has all of the data needed, we can forward. 6164032Sktlim@umich.edu if ((store_has_lower_limit && store_has_upper_limit)) { 6172329SN/A // Get shift amount for offset into the store's data. 6182669Sktlim@umich.edu int shift_amt = req->getVaddr() & (store_size - 1); 6192292SN/A 6207520Sgblack@eecs.umich.edu memcpy(data, storeQueue[store_idx].data + shift_amt, 6217520Sgblack@eecs.umich.edu req->getSize()); 6223803Sgblack@eecs.umich.edu 6232669Sktlim@umich.edu assert(!load_inst->memData); 6242669Sktlim@umich.edu load_inst->memData = new uint8_t[64]; 6252292SN/A 6264326Sgblack@eecs.umich.edu memcpy(load_inst->memData, 6274326Sgblack@eecs.umich.edu storeQueue[store_idx].data + shift_amt, req->getSize()); 6282292SN/A 6292292SN/A DPRINTF(LSQUnit, "Forwarding from store idx %i to load to " 6302292SN/A "addr %#x, data %#x\n", 6312693Sktlim@umich.edu store_idx, req->getVaddr(), data); 6322678Sktlim@umich.edu 6334022Sstever@eecs.umich.edu PacketPtr data_pkt = new Packet(req, MemCmd::ReadReq, 6344022Sstever@eecs.umich.edu Packet::Broadcast); 6352678Sktlim@umich.edu data_pkt->dataStatic(load_inst->memData); 6362678Sktlim@umich.edu 6372678Sktlim@umich.edu WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this); 6382292SN/A 6392292SN/A // We'll say this has a 1 cycle load-store forwarding latency 6402292SN/A // for now. 6412292SN/A // @todo: Need to make this a parameter. 6427823Ssteve.reinhardt@amd.com cpu->schedule(wb, curTick()); 6432678Sktlim@umich.edu 6446974Stjones1@inf.ed.ac.uk // Don't need to do anything special for split loads. 6456974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 6466974Stjones1@inf.ed.ac.uk delete sreqLow; 6476974Stjones1@inf.ed.ac.uk delete sreqHigh; 6486974Stjones1@inf.ed.ac.uk } 6496974Stjones1@inf.ed.ac.uk 6502727Sktlim@umich.edu ++lsqForwLoads; 6512292SN/A return NoFault; 6522292SN/A } else if ((store_has_lower_limit && lower_load_has_store_part) || 6532292SN/A (store_has_upper_limit && upper_load_has_store_part) || 6542292SN/A (lower_load_has_store_part && upper_load_has_store_part)) { 6552292SN/A // This is the partial store-load forwarding case where a store 6562292SN/A // has only part of the load's data. 6572292SN/A 6582292SN/A // If it's already been written back, then don't worry about 6592292SN/A // stalling on it. 6602292SN/A if (storeQueue[store_idx].completed) { 6614032Sktlim@umich.edu panic("Should not check one of these"); 6622292SN/A continue; 6632292SN/A } 6642292SN/A 6652292SN/A // Must stall load and force it to retry, so long as it's the oldest 6662292SN/A // load that needs to do so. 6672292SN/A if (!stalled || 6682292SN/A (stalled && 6692669Sktlim@umich.edu load_inst->seqNum < 6702292SN/A loadQueue[stallingLoadIdx]->seqNum)) { 6712292SN/A stalled = true; 6722292SN/A stallingStoreIsn = storeQueue[store_idx].inst->seqNum; 6732292SN/A stallingLoadIdx = load_idx; 6742292SN/A } 6752292SN/A 6762292SN/A // Tell IQ/mem dep unit that this instruction will need to be 6772292SN/A // rescheduled eventually 6782669Sktlim@umich.edu iewStage->rescheduleMemInst(load_inst); 6792927Sktlim@umich.edu iewStage->decrWb(load_inst->seqNum); 6804032Sktlim@umich.edu load_inst->clearIssued(); 6812727Sktlim@umich.edu ++lsqRescheduledLoads; 6822292SN/A 6832292SN/A // Do not generate a writeback event as this instruction is not 6842292SN/A // complete. 6852292SN/A DPRINTF(LSQUnit, "Load-store forwarding mis-match. " 6862292SN/A "Store idx %i to load addr %#x\n", 6872669Sktlim@umich.edu store_idx, req->getVaddr()); 6882292SN/A 6894032Sktlim@umich.edu // Must delete request now that it wasn't handed off to 6904032Sktlim@umich.edu // memory. This is quite ugly. @todo: Figure out the 6914032Sktlim@umich.edu // proper place to really handle request deletes. 6924032Sktlim@umich.edu delete req; 6936974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 6946974Stjones1@inf.ed.ac.uk delete sreqLow; 6956974Stjones1@inf.ed.ac.uk delete sreqHigh; 6966974Stjones1@inf.ed.ac.uk } 6974032Sktlim@umich.edu 6982292SN/A return NoFault; 6992292SN/A } 7002292SN/A } 7012292SN/A 7022292SN/A // If there's no forwarding case, then go access memory 7037720Sgblack@eecs.umich.edu DPRINTF(LSQUnit, "Doing memory access for inst [sn:%lli] PC %s\n", 7047720Sgblack@eecs.umich.edu load_inst->seqNum, load_inst->pcState()); 7052292SN/A 7062669Sktlim@umich.edu assert(!load_inst->memData); 7072669Sktlim@umich.edu load_inst->memData = new uint8_t[64]; 7082292SN/A 7092292SN/A ++usedPorts; 7102292SN/A 7112907Sktlim@umich.edu // if we the cache is not blocked, do cache access 7126974Stjones1@inf.ed.ac.uk bool completedFirst = false; 7132907Sktlim@umich.edu if (!lsq->cacheBlocked()) { 7146974Stjones1@inf.ed.ac.uk MemCmd command = 7156974Stjones1@inf.ed.ac.uk req->isLLSC() ? MemCmd::LoadLockedReq : MemCmd::ReadReq; 7166974Stjones1@inf.ed.ac.uk PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast); 7176974Stjones1@inf.ed.ac.uk PacketPtr fst_data_pkt = NULL; 7186974Stjones1@inf.ed.ac.uk PacketPtr snd_data_pkt = NULL; 7196974Stjones1@inf.ed.ac.uk 7203228Sktlim@umich.edu data_pkt->dataStatic(load_inst->memData); 7213228Sktlim@umich.edu 7223228Sktlim@umich.edu LSQSenderState *state = new LSQSenderState; 7233228Sktlim@umich.edu state->isLoad = true; 7243228Sktlim@umich.edu state->idx = load_idx; 7253228Sktlim@umich.edu state->inst = load_inst; 7263228Sktlim@umich.edu data_pkt->senderState = state; 7273228Sktlim@umich.edu 7286974Stjones1@inf.ed.ac.uk if (!TheISA::HasUnalignedMemAcc || !sreqLow) { 7296974Stjones1@inf.ed.ac.uk 7306974Stjones1@inf.ed.ac.uk // Point the first packet at the main data packet. 7316974Stjones1@inf.ed.ac.uk fst_data_pkt = data_pkt; 7326974Stjones1@inf.ed.ac.uk } else { 7336974Stjones1@inf.ed.ac.uk 7346974Stjones1@inf.ed.ac.uk // Create the split packets. 7356974Stjones1@inf.ed.ac.uk fst_data_pkt = new Packet(sreqLow, command, Packet::Broadcast); 7366974Stjones1@inf.ed.ac.uk snd_data_pkt = new Packet(sreqHigh, command, Packet::Broadcast); 7376974Stjones1@inf.ed.ac.uk 7386974Stjones1@inf.ed.ac.uk fst_data_pkt->dataStatic(load_inst->memData); 7396974Stjones1@inf.ed.ac.uk snd_data_pkt->dataStatic(load_inst->memData + sreqLow->getSize()); 7406974Stjones1@inf.ed.ac.uk 7416974Stjones1@inf.ed.ac.uk fst_data_pkt->senderState = state; 7426974Stjones1@inf.ed.ac.uk snd_data_pkt->senderState = state; 7436974Stjones1@inf.ed.ac.uk 7446974Stjones1@inf.ed.ac.uk state->isSplit = true; 7456974Stjones1@inf.ed.ac.uk state->outstanding = 2; 7466974Stjones1@inf.ed.ac.uk state->mainPkt = data_pkt; 7476974Stjones1@inf.ed.ac.uk } 7486974Stjones1@inf.ed.ac.uk 7496974Stjones1@inf.ed.ac.uk if (!dcachePort->sendTiming(fst_data_pkt)) { 7503228Sktlim@umich.edu // Delete state and data packet because a load retry 7513228Sktlim@umich.edu // initiates a pipeline restart; it does not retry. 7523228Sktlim@umich.edu delete state; 7534032Sktlim@umich.edu delete data_pkt->req; 7543228Sktlim@umich.edu delete data_pkt; 7556974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 7566974Stjones1@inf.ed.ac.uk delete fst_data_pkt->req; 7576974Stjones1@inf.ed.ac.uk delete fst_data_pkt; 7586974Stjones1@inf.ed.ac.uk delete snd_data_pkt->req; 7596974Stjones1@inf.ed.ac.uk delete snd_data_pkt; 7607511Stjones1@inf.ed.ac.uk sreqLow = NULL; 7617511Stjones1@inf.ed.ac.uk sreqHigh = NULL; 7626974Stjones1@inf.ed.ac.uk } 7633228Sktlim@umich.edu 7644032Sktlim@umich.edu req = NULL; 7654032Sktlim@umich.edu 7662907Sktlim@umich.edu // If the access didn't succeed, tell the LSQ by setting 7672907Sktlim@umich.edu // the retry thread id. 7682907Sktlim@umich.edu lsq->setRetryTid(lsqID); 7696974Stjones1@inf.ed.ac.uk } else if (TheISA::HasUnalignedMemAcc && sreqLow) { 7706974Stjones1@inf.ed.ac.uk completedFirst = true; 7716974Stjones1@inf.ed.ac.uk 7726974Stjones1@inf.ed.ac.uk // The first packet was sent without problems, so send this one 7736974Stjones1@inf.ed.ac.uk // too. If there is a problem with this packet then the whole 7746974Stjones1@inf.ed.ac.uk // load will be squashed, so indicate this to the state object. 7756974Stjones1@inf.ed.ac.uk // The first packet will return in completeDataAccess and be 7766974Stjones1@inf.ed.ac.uk // handled there. 7776974Stjones1@inf.ed.ac.uk ++usedPorts; 7786974Stjones1@inf.ed.ac.uk if (!dcachePort->sendTiming(snd_data_pkt)) { 7796974Stjones1@inf.ed.ac.uk 7806974Stjones1@inf.ed.ac.uk // The main packet will be deleted in completeDataAccess. 7816974Stjones1@inf.ed.ac.uk delete snd_data_pkt->req; 7826974Stjones1@inf.ed.ac.uk delete snd_data_pkt; 7836974Stjones1@inf.ed.ac.uk 7846974Stjones1@inf.ed.ac.uk state->complete(); 7856974Stjones1@inf.ed.ac.uk 7866974Stjones1@inf.ed.ac.uk req = NULL; 7877511Stjones1@inf.ed.ac.uk sreqHigh = NULL; 7886974Stjones1@inf.ed.ac.uk 7896974Stjones1@inf.ed.ac.uk lsq->setRetryTid(lsqID); 7906974Stjones1@inf.ed.ac.uk } 7912907Sktlim@umich.edu } 7922907Sktlim@umich.edu } 7932907Sktlim@umich.edu 7942907Sktlim@umich.edu // If the cache was blocked, or has become blocked due to the access, 7952907Sktlim@umich.edu // handle it. 7962907Sktlim@umich.edu if (lsq->cacheBlocked()) { 7974032Sktlim@umich.edu if (req) 7984032Sktlim@umich.edu delete req; 7996974Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow && !completedFirst) { 8006974Stjones1@inf.ed.ac.uk delete sreqLow; 8016974Stjones1@inf.ed.ac.uk delete sreqHigh; 8026974Stjones1@inf.ed.ac.uk } 8034032Sktlim@umich.edu 8042727Sktlim@umich.edu ++lsqCacheBlocked; 8053014Srdreslin@umich.edu 8063014Srdreslin@umich.edu iewStage->decrWb(load_inst->seqNum); 8072669Sktlim@umich.edu // There's an older load that's already going to squash. 8082669Sktlim@umich.edu if (isLoadBlocked && blockedLoadSeqNum < load_inst->seqNum) 8092669Sktlim@umich.edu return NoFault; 8102292SN/A 8112669Sktlim@umich.edu // Record that the load was blocked due to memory. This 8122669Sktlim@umich.edu // load will squash all instructions after it, be 8132669Sktlim@umich.edu // refetched, and re-executed. 8142669Sktlim@umich.edu isLoadBlocked = true; 8152669Sktlim@umich.edu loadBlockedHandled = false; 8162669Sktlim@umich.edu blockedLoadSeqNum = load_inst->seqNum; 8172669Sktlim@umich.edu // No fault occurred, even though the interface is blocked. 8182669Sktlim@umich.edu return NoFault; 8192292SN/A } 8202292SN/A 8212669Sktlim@umich.edu return NoFault; 8222292SN/A} 8232292SN/A 8242292SN/Atemplate <class Impl> 8252292SN/AFault 8266974Stjones1@inf.ed.ac.ukLSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh, 8277520Sgblack@eecs.umich.edu uint8_t *data, int store_idx) 8282292SN/A{ 8292292SN/A assert(storeQueue[store_idx].inst); 8302292SN/A 8312292SN/A DPRINTF(LSQUnit, "Doing write to store idx %i, addr %#x data %#x" 8322292SN/A " | storeHead:%i [sn:%i]\n", 8332669Sktlim@umich.edu store_idx, req->getPaddr(), data, storeHead, 8342292SN/A storeQueue[store_idx].inst->seqNum); 8352329SN/A 8362292SN/A storeQueue[store_idx].req = req; 8376974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqLow = sreqLow; 8386974Stjones1@inf.ed.ac.uk storeQueue[store_idx].sreqHigh = sreqHigh; 8397520Sgblack@eecs.umich.edu unsigned size = req->getSize(); 8407520Sgblack@eecs.umich.edu storeQueue[store_idx].size = size; 8417520Sgblack@eecs.umich.edu assert(size <= sizeof(storeQueue[store_idx].data)); 8427509Stjones1@inf.ed.ac.uk 8437509Stjones1@inf.ed.ac.uk // Split stores can only occur in ISAs with unaligned memory accesses. If 8447509Stjones1@inf.ed.ac.uk // a store request has been split, sreqLow and sreqHigh will be non-null. 8457509Stjones1@inf.ed.ac.uk if (TheISA::HasUnalignedMemAcc && sreqLow) { 8467509Stjones1@inf.ed.ac.uk storeQueue[store_idx].isSplit = true; 8477509Stjones1@inf.ed.ac.uk } 8484326Sgblack@eecs.umich.edu 8497520Sgblack@eecs.umich.edu memcpy(storeQueue[store_idx].data, data, size); 8502329SN/A 8512292SN/A // This function only writes the data to the store queue, so no fault 8522292SN/A // can happen here. 8532292SN/A return NoFault; 8542292SN/A} 8552292SN/A 8562292SN/A#endif // __CPU_O3_LSQ_UNIT_HH__ 857