lsq_impl.hh revision 2307
12810SN/A/*
210028SGiacomo.Gabrielli@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan
38856Sandreas.hansson@arm.com * All rights reserved.
48856Sandreas.hansson@arm.com *
58856Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without
68856Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are
78856Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright
88856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer;
98856Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright
108856Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the
118856Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution;
128856Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its
138856Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from
142810SN/A * this software without specific prior written permission.
152810SN/A *
162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272810SN/A */
282810SN/A
292810SN/A#include "cpu/o3/lsq.hh"
302810SN/A
312810SN/Ausing namespace std;
322810SN/A
332810SN/Atemplate <class Impl>
342810SN/ALSQ<Impl>::LSQ(Params *params)
352810SN/A    : LQEntries(params->LQEntries), SQEntries(params->SQEntries),
362810SN/A      numThreads(params->numberOfThreads)
372810SN/A{
382810SN/A    DPRINTF(LSQ, "Creating LSQ object.\n");
392810SN/A
402810SN/A    //**********************************************/
414458SN/A    //************ Handle SMT Parameters ***********/
424458SN/A    //**********************************************/
432810SN/A    string policy = params->smtLSQPolicy;
442810SN/A
452810SN/A    //Convert string to lowercase
462810SN/A    std::transform(policy.begin(), policy.end(), policy.begin(),
472810SN/A                   (int(*)(int)) tolower);
482810SN/A
492810SN/A    //Figure out fetch policy
502810SN/A    if (policy == "dynamic") {
512810SN/A        lsqPolicy = Dynamic;
522810SN/A
537676Snate@binkert.org        maxLQEntries = LQEntries;
547676Snate@binkert.org        maxSQEntries = SQEntries;
557676Snate@binkert.org
562810SN/A        DPRINTF(LSQ, "LSQ sharing policy set to Dynamic\n");
572810SN/A
582825SN/A    } else if (policy == "partitioned") {
592810SN/A        lsqPolicy = Partitioned;
602810SN/A
616215Snate@binkert.org        //@todo:make work if part_amt doesnt divide evenly.
628232Snate@binkert.org        maxLQEntries = LQEntries / numThreads;
638232Snate@binkert.org        maxSQEntries = SQEntries / numThreads;
645338Sstever@gmail.com
652810SN/A        DPRINTF(Fetch, "LSQ sharing policy set to Partitioned: "
662810SN/A                "%i entries per LQ | %i entries per SQ",
678914Sandreas.hansson@arm.com                maxLQEntries,maxSQEntries);
688229Snate@binkert.org
695034SN/A    } else if (policy == "threshold") {
702811SN/A        lsqPolicy = Threshold;
718786Sgblack@eecs.umich.edu
724626SN/A        assert(params->smtLSQThreshold > LQEntries);
738833Sdam.sunwoo@arm.com        assert(params->smtLSQThreshold > SQEntries);
742810SN/A
753194SN/A        //Divide up by threshold amount
762810SN/A        //@todo: Should threads check the max and the total
772810SN/A        //amount of the LSQ
782810SN/A        maxLQEntries  = params->smtLSQThreshold;
792810SN/A        maxSQEntries  = params->smtLSQThreshold;
802810SN/A
814628SN/A        DPRINTF(LSQ, "LSQ sharing policy set to Threshold: "
824628SN/A                "%i entries per LQ | %i entries per SQ",
834628SN/A                maxLQEntries,maxSQEntries);
844628SN/A
854628SN/A    } else {
864628SN/A        assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic,"
874628SN/A                    "Partitioned, Threshold}");
884628SN/A    }
898737Skoansin.tan@gmail.com
904628SN/A    //Initialize LSQs
914628SN/A    for (int tid=0; tid < numThreads; tid++) {
924628SN/A        thread[tid].init(params, maxLQEntries+1, maxSQEntries+1, tid);
934628SN/A    }
944628SN/A}
954628SN/A
964628SN/A
974628SN/Atemplate<class Impl>
984628SN/Astd::string
994628SN/ALSQ<Impl>::name() const
1004628SN/A{
1014628SN/A    return iewStage->name() + ".lsq";
1024628SN/A}
1034628SN/A
1044628SN/Atemplate<class Impl>
1054628SN/Avoid
1064628SN/ALSQ<Impl>::setActiveThreads(list<unsigned> *at_ptr)
1074628SN/A{
1084628SN/A    activeThreads = at_ptr;
1094628SN/A    assert(activeThreads != 0);
1108737Skoansin.tan@gmail.com}
1114628SN/A
1128856Sandreas.hansson@arm.comtemplate<class Impl>
1138856Sandreas.hansson@arm.comvoid
1148856Sandreas.hansson@arm.comLSQ<Impl>::setCPU(FullCPU *cpu_ptr)
1158856Sandreas.hansson@arm.com{
1168856Sandreas.hansson@arm.com    cpu = cpu_ptr;
1178856Sandreas.hansson@arm.com
1188856Sandreas.hansson@arm.com    for (int tid=0; tid < numThreads; tid++) {
1198856Sandreas.hansson@arm.com        thread[tid].setCPU(cpu_ptr);
1208856Sandreas.hansson@arm.com    }
1218922Swilliam.wang@arm.com}
1222810SN/A
1238856Sandreas.hansson@arm.comtemplate<class Impl>
1242844SN/Avoid
1258856Sandreas.hansson@arm.comLSQ<Impl>::setIEW(IEW *iew_ptr)
1268856Sandreas.hansson@arm.com{
1278856Sandreas.hansson@arm.com    iewStage = iew_ptr;
1288856Sandreas.hansson@arm.com
1298856Sandreas.hansson@arm.com    for (int tid=0; tid < numThreads; tid++) {
1308856Sandreas.hansson@arm.com        thread[tid].setIEW(iew_ptr);
1318856Sandreas.hansson@arm.com    }
1328856Sandreas.hansson@arm.com}
1338856Sandreas.hansson@arm.com
1348914Sandreas.hansson@arm.com#if 0
1358856Sandreas.hansson@arm.comtemplate<class Impl>
1368856Sandreas.hansson@arm.comvoid
1373738SN/ALSQ<Impl>::setPageTable(PageTable *pt_ptr)
1384458SN/A{
1398856Sandreas.hansson@arm.com    for (int tid=0; tid < numThreads; tid++) {
1408975Sandreas.hansson@arm.com        thread[tid].setPageTable(pt_ptr);
1418922Swilliam.wang@arm.com    }
1428914Sandreas.hansson@arm.com}
1432810SN/A#endif
1448856Sandreas.hansson@arm.com
1458856Sandreas.hansson@arm.comtemplate <class Impl>
1468856Sandreas.hansson@arm.comvoid
1478914Sandreas.hansson@arm.comLSQ<Impl>::switchOut()
1488856Sandreas.hansson@arm.com{
1498922Swilliam.wang@arm.com    for (int tid = 0; tid < numThreads; tid++) {
1508856Sandreas.hansson@arm.com        thread[tid].switchOut();
1513013SN/A    }
1528856Sandreas.hansson@arm.com}
1538856Sandreas.hansson@arm.com
1548856Sandreas.hansson@arm.comtemplate <class Impl>
1558856Sandreas.hansson@arm.comvoid
1568856Sandreas.hansson@arm.comLSQ<Impl>::takeOverFrom()
1578856Sandreas.hansson@arm.com{
1588856Sandreas.hansson@arm.com    for (int tid = 0; tid < numThreads; tid++) {
1598856Sandreas.hansson@arm.com        thread[tid].takeOverFrom();
1608922Swilliam.wang@arm.com    }
1618856Sandreas.hansson@arm.com}
1625314SN/A
1632811SN/Atemplate <class Impl>
1648856Sandreas.hansson@arm.comint
1658856Sandreas.hansson@arm.comLSQ<Impl>::entryAmount(int num_threads)
1662810SN/A{
1672810SN/A    if (lsqPolicy == Partitioned) {
1688856Sandreas.hansson@arm.com        return LQEntries / num_threads;
1692810SN/A    } else {
1702810SN/A        return 0;
1718856Sandreas.hansson@arm.com    }
1728856Sandreas.hansson@arm.com}
1738856Sandreas.hansson@arm.com
1748856Sandreas.hansson@arm.comtemplate <class Impl>
1753606SN/Avoid
1768914Sandreas.hansson@arm.comLSQ<Impl>::resetEntries()
1778975Sandreas.hansson@arm.com{
1788914Sandreas.hansson@arm.com    if (lsqPolicy != Dynamic || numThreads > 1) {
1792810SN/A        int active_threads = (*activeThreads).size();
1802810SN/A
1812897SN/A        list<unsigned>::iterator threads  = (*activeThreads).begin();
1822897SN/A        list<unsigned>::iterator list_end = (*activeThreads).end();
1838856Sandreas.hansson@arm.com
1844458SN/A        int maxEntries;
1859087Sandreas.hansson@arm.com
1868856Sandreas.hansson@arm.com        if (lsqPolicy == Partitioned) {
1872811SN/A            maxEntries = LQEntries / active_threads;
1882810SN/A        } else if (lsqPolicy == Threshold && active_threads == 1) {
1898856Sandreas.hansson@arm.com            maxEntries = LQEntries;
1908856Sandreas.hansson@arm.com        } else {
1913338SN/A            maxEntries = LQEntries;
1924626SN/A        }
1934626SN/A
1944626SN/A        while (threads != list_end) {
1954626SN/A            resizeEntries(maxEntries,*threads++);
1964626SN/A        }
1974626SN/A    }
1984626SN/A}
1994626SN/A
2004628SN/Atemplate<class Impl>
2014628SN/Avoid
2024628SN/ALSQ<Impl>::removeEntries(unsigned tid)
2034666SN/A{
2044628SN/A    thread[tid].clearLQ();
2054628SN/A    thread[tid].clearSQ();
2064628SN/A}
2074628SN/A
2084628SN/Atemplate<class Impl>
2094628SN/Avoid
2104628SN/ALSQ<Impl>::resizeEntries(unsigned size,unsigned tid)
2114628SN/A{
2124628SN/A    thread[tid].resizeLQ(size);
2134628SN/A    thread[tid].resizeSQ(size);
2144628SN/A}
2154628SN/A
2167667Ssteve.reinhardt@amd.comtemplate<class Impl>
2174628SN/Avoid
2184628SN/ALSQ<Impl>::tick()
2194628SN/A{
2207667Ssteve.reinhardt@amd.com    list<unsigned>::iterator active_threads = (*activeThreads).begin();
2214628SN/A
2224628SN/A    while (active_threads != (*activeThreads).end()) {
2234628SN/A        unsigned tid = *active_threads++;
2244628SN/A
2254628SN/A        thread[tid].tick();
2269347SAndreas.Sandberg@arm.com    }
2279347SAndreas.Sandberg@arm.com}
2289347SAndreas.Sandberg@arm.com
2299347SAndreas.Sandberg@arm.comtemplate<class Impl>
2309347SAndreas.Sandberg@arm.comvoid
2319347SAndreas.Sandberg@arm.comLSQ<Impl>::tick(unsigned tid)
2329347SAndreas.Sandberg@arm.com{
2339347SAndreas.Sandberg@arm.com    thread[tid].tick();
2349347SAndreas.Sandberg@arm.com}
2359347SAndreas.Sandberg@arm.com
2369347SAndreas.Sandberg@arm.comtemplate<class Impl>
2379347SAndreas.Sandberg@arm.comvoid
2389347SAndreas.Sandberg@arm.comLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
2399347SAndreas.Sandberg@arm.com{
2409347SAndreas.Sandberg@arm.com    unsigned tid = load_inst->threadNumber;
2419347SAndreas.Sandberg@arm.com
2429347SAndreas.Sandberg@arm.com    thread[tid].insertLoad(load_inst);
2439347SAndreas.Sandberg@arm.com}
2449347SAndreas.Sandberg@arm.com
2454626SN/Atemplate<class Impl>
2466227Snate@binkert.orgvoid
2474626SN/ALSQ<Impl>::insertStore(DynInstPtr &store_inst)
2484630SN/A{
2494630SN/A    unsigned tid = store_inst->threadNumber;
2504630SN/A
2519288Sandreas.hansson@arm.com    thread[tid].insertStore(store_inst);
2529263Smrinmoy.ghosh@arm.com}
2539263Smrinmoy.ghosh@arm.com
2549263Smrinmoy.ghosh@arm.comtemplate<class Impl>
2559263Smrinmoy.ghosh@arm.comFault
2569263Smrinmoy.ghosh@arm.comLSQ<Impl>::executeLoad(DynInstPtr &inst)
2579263Smrinmoy.ghosh@arm.com{
2589263Smrinmoy.ghosh@arm.com    unsigned tid = inst->threadNumber;
2599288Sandreas.hansson@arm.com
2604630SN/A    return thread[tid].executeLoad(inst);
2614626SN/A}
2624626SN/A
2634626SN/Atemplate<class Impl>
2646122SSteve.Reinhardt@amd.comFault
2659529Sandreas.hansson@arm.comLSQ<Impl>::executeLoad(int lq_idx, unsigned tid)
2664626SN/A{
2678134SAli.Saidi@ARM.com    return thread[tid].executeLoad(lq_idx);
2688134SAli.Saidi@ARM.com}
2698134SAli.Saidi@ARM.com
2709529Sandreas.hansson@arm.comtemplate<class Impl>
2718134SAli.Saidi@ARM.comFault
2722810SN/ALSQ<Impl>::executeStore(DynInstPtr &inst)
2732810SN/A{
2742810SN/A    unsigned tid = inst->threadNumber;
2752810SN/A
2762810SN/A    return thread[tid].executeStore(inst);
2772810SN/A}
2786122SSteve.Reinhardt@amd.com
2796122SSteve.Reinhardt@amd.comtemplate<class Impl>
2806122SSteve.Reinhardt@amd.comvoid
2812810SN/ALSQ<Impl>::commitLoads(InstSeqNum &youngest_inst,unsigned tid)
2829288Sandreas.hansson@arm.com{
2832810SN/A    thread[tid].commitLoads(youngest_inst);
2844626SN/A}
2854626SN/A
2862810SN/Atemplate<class Impl>
2872810SN/Avoid
2882810SN/ALSQ<Impl>::commitStores(InstSeqNum &youngest_inst,unsigned tid)
2892810SN/A{
2906122SSteve.Reinhardt@amd.com    thread[tid].commitStores(youngest_inst);
2916122SSteve.Reinhardt@amd.com}
2926122SSteve.Reinhardt@amd.com
2939529Sandreas.hansson@arm.comtemplate<class Impl>
2946122SSteve.Reinhardt@amd.comvoid
2958833Sdam.sunwoo@arm.comLSQ<Impl>::writebackStores()
2968833Sdam.sunwoo@arm.com{
2978833Sdam.sunwoo@arm.com    list<unsigned>::iterator active_threads = (*activeThreads).begin();
2986978SLisa.Hsu@amd.com
2992810SN/A    while (active_threads != (*activeThreads).end()) {
3002810SN/A        unsigned tid = *active_threads++;
3012810SN/A
3022810SN/A        if (numStoresToWB(tid) > 0) {
3032810SN/A            DPRINTF(Writeback,"[tid:%i] Writing back stores. %i stores available"
3042810SN/A                " for Writeback.\n", tid, numStoresToWB(tid));
3052810SN/A        }
3065999Snate@binkert.org
3072810SN/A        thread[tid].writebackStores();
3082810SN/A    }
3092810SN/A}
3102810SN/A
3112810SN/Atemplate<class Impl>
3122810SN/Aint
3135999Snate@binkert.orgLSQ<Impl>::numStoresToWB(unsigned tid)
3142810SN/A{
3152810SN/A    return thread[tid].numStoresToWB();
3162810SN/A}
3172810SN/A
3182810SN/Atemplate<class Impl>
3192810SN/Avoid
3202810SN/ALSQ<Impl>::squash(const InstSeqNum &squashed_num, unsigned tid)
3212810SN/A{
3222810SN/A        thread[tid].squash(squashed_num);
3235999Snate@binkert.org}
3242810SN/A
3252810SN/Atemplate<class Impl>
3262810SN/Abool
3272810SN/ALSQ<Impl>::violation()
3282810SN/A{
3292810SN/A    /* Answers: Does Anybody Have a Violation?*/
3304022SN/A    list<unsigned>::iterator active_threads = (*activeThreads).begin();
3312810SN/A
3322810SN/A    while (active_threads != (*activeThreads).end()) {
3332810SN/A        unsigned tid = *active_threads++;
3342810SN/A        if (thread[tid].violation())
3352810SN/A            return true;
3362810SN/A    }
3374022SN/A
3382810SN/A    return false;
3392810SN/A}
3402810SN/A
3412810SN/Atemplate<class Impl>
3422810SN/Abool
3432810SN/ALSQ<Impl>::violation(unsigned tid)
3444022SN/A{
3452810SN/A    return thread[tid].violation();
3462810SN/A}
3472810SN/A
3482810SN/Atemplate<class Impl>
3492810SN/Abool
3502810SN/ALSQ<Impl>::loadBlocked(unsigned tid)
3515999Snate@binkert.org{
3522810SN/A    return thread[tid].loadBlocked();
3535999Snate@binkert.org}
3542810SN/A
3552810SN/Atemplate<class Impl>
3562810SN/Atypename Impl::DynInstPtr
3572810SN/ALSQ<Impl>::getMemDepViolator(unsigned tid)
3582810SN/A{
3595999Snate@binkert.org    return thread[tid].getMemDepViolator();
3602810SN/A}
3612810SN/A
3625999Snate@binkert.orgtemplate<class Impl>
3632810SN/Aint
3644626SN/ALSQ<Impl>::getLoadHead(unsigned tid)
3655999Snate@binkert.org{
3664626SN/A    return thread[tid].getLoadHead();
3674626SN/A}
3685999Snate@binkert.org
3694626SN/Atemplate<class Impl>
3704626SN/Aint
3714626SN/ALSQ<Impl>::getStoreHead(unsigned tid)
3724626SN/A{
3734626SN/A    return thread[tid].getStoreHead();
3744626SN/A}
3755999Snate@binkert.org
3764626SN/Atemplate<class Impl>
3774626SN/Aint
3784626SN/ALSQ<Impl>::getCount()
3794626SN/A{
3804626SN/A    unsigned total = 0;
3814626SN/A
3825999Snate@binkert.org    list<unsigned>::iterator active_threads = (*activeThreads).begin();
3834626SN/A
3844626SN/A    while (active_threads != (*activeThreads).end()) {
3854626SN/A        unsigned tid = *active_threads++;
3864626SN/A        total += getCount(tid);
3875999Snate@binkert.org    }
3884626SN/A
3894626SN/A    return total;
3904626SN/A}
3914626SN/A
3924626SN/Atemplate<class Impl>
3934626SN/Aint
3945999Snate@binkert.orgLSQ<Impl>::getCount(unsigned tid)
3954626SN/A{
3964626SN/A    return thread[tid].getCount();
3974626SN/A}
3987461Snate@binkert.org
3994626SN/Atemplate<class Impl>
4004626SN/Aint
4014626SN/ALSQ<Impl>::numLoads()
4024626SN/A{
4034626SN/A    unsigned total = 0;
4044626SN/A
4057461Snate@binkert.org    list<unsigned>::iterator active_threads = (*activeThreads).begin();
4064626SN/A
4074626SN/A    while (active_threads != (*activeThreads).end()) {
4084626SN/A        unsigned tid = *active_threads++;
4094626SN/A        total += numLoads(tid);
4104626SN/A    }
4114626SN/A
4124626SN/A    return total;
4134626SN/A}
4144626SN/A
4154626SN/Atemplate<class Impl>
4164626SN/Aint
4174626SN/ALSQ<Impl>::numLoads(unsigned tid)
4184626SN/A{
4194626SN/A    return thread[tid].numLoads();
4204626SN/A}
4214626SN/A
4224626SN/Atemplate<class Impl>
4234626SN/Aint
4244626SN/ALSQ<Impl>::numStores()
4254626SN/A{
4264626SN/A    unsigned total = 0;
4275999Snate@binkert.org
4284626SN/A    list<unsigned>::iterator active_threads = (*activeThreads).begin();
4295999Snate@binkert.org
4304626SN/A    while (active_threads != (*activeThreads).end()) {
4315999Snate@binkert.org        unsigned tid = *active_threads++;
4324626SN/A        total += thread[tid].numStores();
4332810SN/A    }
4342810SN/A
4352810SN/A    return total;
4362810SN/A}
4372810SN/A
4382810SN/Atemplate<class Impl>
4392810SN/Aint
4402810SN/ALSQ<Impl>::numStores(unsigned tid)
4412810SN/A{
4422810SN/A    return thread[tid].numStores();
4435034SN/A}
4445034SN/A
4455034SN/Atemplate<class Impl>
4463606SN/Aint
4472858SN/ALSQ<Impl>::numLoadsReady()
4482858SN/A{
4499294Sandreas.hansson@arm.com    unsigned total = 0;
4509294Sandreas.hansson@arm.com
4519294Sandreas.hansson@arm.com    list<unsigned>::iterator active_threads = (*activeThreads).begin();
4529294Sandreas.hansson@arm.com
4538922Swilliam.wang@arm.com    while (active_threads != (*activeThreads).end()) {
4542810SN/A        unsigned tid = *active_threads++;
4552810SN/A        total += thread[tid].numLoadsReady();
4562810SN/A    }
4572810SN/A
4586227Snate@binkert.org    return total;
4596227Snate@binkert.org}
4602810SN/A
4612810SN/Atemplate<class Impl>
4622810SN/Aint
4632810SN/ALSQ<Impl>::numLoadsReady(unsigned tid)
4644626SN/A{
4656666Ssteve.reinhardt@amd.com    return thread[tid].numLoadsReady();
4664626SN/A}
4674626SN/A
4688883SAli.Saidi@ARM.comtemplate<class Impl>
4696122SSteve.Reinhardt@amd.comunsigned
4704628SN/ALSQ<Impl>::numFreeEntries()
4714628SN/A{
4724902SN/A    unsigned total = 0;
4734628SN/A
4744628SN/A    list<unsigned>::iterator active_threads = (*activeThreads).begin();
4754628SN/A
4764628SN/A    while (active_threads != (*activeThreads).end()) {
4774628SN/A        unsigned tid = *active_threads++;
4784902SN/A        total += thread[tid].numFreeEntries();
4794628SN/A    }
4804902SN/A
4814902SN/A    return total;
4824902SN/A}
4834628SN/A
4844628SN/Atemplate<class Impl>
4854628SN/Aunsigned
4864902SN/ALSQ<Impl>::numFreeEntries(unsigned tid)
4874902SN/A{
4884902SN/A    //if( lsqPolicy == Dynamic )
4894902SN/A    //return numFreeEntries();
4904902SN/A    //else
4914902SN/A        return thread[tid].numFreeEntries();
4924902SN/A}
4934902SN/A
4944628SN/Atemplate<class Impl>
4952810SN/Abool
4962810SN/ALSQ<Impl>::isFull()
4972810SN/A{
4989529Sandreas.hansson@arm.com    list<unsigned>::iterator active_threads = (*activeThreads).begin();
4992810SN/A
5002810SN/A    while (active_threads != (*activeThreads).end()) {
5012810SN/A        unsigned tid = *active_threads++;
5022810SN/A        if (! (thread[tid].lqFull() || thread[tid].sqFull()) )
5032810SN/A            return false;
5042810SN/A    }
5052810SN/A
5062810SN/A    return true;
5072810SN/A}
5082810SN/A
5092810SN/Atemplate<class Impl>
5102810SN/Abool
5112810SN/ALSQ<Impl>::isFull(unsigned tid)
5122810SN/A{
5139288Sandreas.hansson@arm.com    //@todo: Change to Calculate All Entries for
5144630SN/A    //Dynamic Policy
5152810SN/A    if( lsqPolicy == Dynamic )
5164630SN/A        return isFull();
5174630SN/A    else
5182810SN/A        return thread[tid].lqFull() || thread[tid].sqFull();
5192810SN/A}
5202810SN/A
5212810SN/Atemplate<class Impl>
5222810SN/Abool
5232810SN/ALSQ<Impl>::lqFull()
5242810SN/A{
5252810SN/A    list<unsigned>::iterator active_threads = (*activeThreads).begin();
5262810SN/A
5272810SN/A    while (active_threads != (*activeThreads).end()) {
5282810SN/A        unsigned tid = *active_threads++;
5292810SN/A        if (!thread[tid].lqFull())
5304630SN/A            return false;
5314630SN/A    }
5324630SN/A
5339288Sandreas.hansson@arm.com    return true;
5344630SN/A}
5352810SN/A
5362810SN/Atemplate<class Impl>
5372810SN/Abool
5382810SN/ALSQ<Impl>::lqFull(unsigned tid)
5392810SN/A{
5402810SN/A    //@todo: Change to Calculate All Entries for
5412810SN/A    //Dynamic Policy
5422810SN/A    if( lsqPolicy == Dynamic )
5434458SN/A        return lqFull();
5442810SN/A    else
5454458SN/A        return thread[tid].lqFull();
5462810SN/A}
5472810SN/A
5482810SN/Atemplate<class Impl>
5492810SN/Abool
5502810SN/ALSQ<Impl>::sqFull()
5512810SN/A{
5524458SN/A    list<unsigned>::iterator active_threads = (*activeThreads).begin();
5532810SN/A
5545875Ssteve.reinhardt@amd.com    while (active_threads != (*activeThreads).end()) {
5555875Ssteve.reinhardt@amd.com        unsigned tid = *active_threads++;
5565875Ssteve.reinhardt@amd.com        if (!sqFull(tid))
5575875Ssteve.reinhardt@amd.com            return false;
5585875Ssteve.reinhardt@amd.com    }
5592811SN/A
5603503SN/A    return true;
5619342SAndreas.Sandberg@arm.com}
5623503SN/A
56310028SGiacomo.Gabrielli@arm.comtemplate<class Impl>
5644626SN/Abool
56510028SGiacomo.Gabrielli@arm.comLSQ<Impl>::sqFull(unsigned tid)
5664626SN/A{
5678833Sdam.sunwoo@arm.com     //@todo: Change to Calculate All Entries for
5683503SN/A    //Dynamic Policy
5698833Sdam.sunwoo@arm.com    if( lsqPolicy == Dynamic )
5708833Sdam.sunwoo@arm.com        return sqFull();
57110020Smatt.horsnell@ARM.com    else
5724626SN/A        return thread[tid].sqFull();
5734626SN/A}
5744626SN/A
5754626SN/Atemplate<class Impl>
5763503SN/Abool
5773503SN/ALSQ<Impl>::isStalled()
5788833Sdam.sunwoo@arm.com{
5796978SLisa.Hsu@amd.com    list<unsigned>::iterator active_threads = (*activeThreads).begin();
5808833Sdam.sunwoo@arm.com
5818833Sdam.sunwoo@arm.com    while (active_threads != (*activeThreads).end()) {
5826978SLisa.Hsu@amd.com        unsigned tid = *active_threads++;
5836978SLisa.Hsu@amd.com        if (!thread[tid].isStalled())
5843503SN/A            return false;
5852810SN/A    }
5862810SN/A
5872810SN/A    return true;
588}
589
590template<class Impl>
591bool
592LSQ<Impl>::isStalled(unsigned tid)
593{
594    if( lsqPolicy == Dynamic )
595        return isStalled();
596    else
597        return thread[tid].isStalled();
598}
599
600template<class Impl>
601bool
602LSQ<Impl>::hasStoresToWB()
603{
604    list<unsigned>::iterator active_threads = (*activeThreads).begin();
605
606    while (active_threads != (*activeThreads).end()) {
607        unsigned tid = *active_threads++;
608        if (!hasStoresToWB(tid))
609            return false;
610    }
611
612    return true;
613}
614
615
616template<class Impl>
617bool
618LSQ<Impl>::hasStoresToWB(unsigned tid)
619{
620    return thread[tid].hasStoresToWB();
621}
622
623template<class Impl>
624bool
625LSQ<Impl>::willWB()
626{
627    list<unsigned>::iterator active_threads = (*activeThreads).begin();
628
629    while (active_threads != (*activeThreads).end()) {
630        unsigned tid = *active_threads++;
631        if (!willWB(tid))
632            return false;
633    }
634
635    return true;
636}
637
638template<class Impl>
639bool
640LSQ<Impl>::willWB(unsigned tid)
641{
642    return thread[tid].willWB();
643}
644
645template<class Impl>
646void
647LSQ<Impl>::dumpInsts()
648{
649    list<unsigned>::iterator active_threads = (*activeThreads).begin();
650
651    while (active_threads != (*activeThreads).end()) {
652        unsigned tid = *active_threads++;
653        thread[tid].dumpInsts();
654    }
655}
656
657template<class Impl>
658void
659LSQ<Impl>::dumpInsts(unsigned tid)
660{
661    thread[tid].dumpInsts();
662}
663