lsq_impl.hh revision 2907
12292SN/A/* 22727Sktlim@umich.edu * Copyright (c) 2005-2006 The Regents of The University of Michigan 32292SN/A * All rights reserved. 42292SN/A * 52292SN/A * Redistribution and use in source and binary forms, with or without 62292SN/A * modification, are permitted provided that the following conditions are 72292SN/A * met: redistributions of source code must retain the above copyright 82292SN/A * notice, this list of conditions and the following disclaimer; 92292SN/A * redistributions in binary form must reproduce the above copyright 102292SN/A * notice, this list of conditions and the following disclaimer in the 112292SN/A * documentation and/or other materials provided with the distribution; 122292SN/A * neither the name of the copyright holders nor the names of its 132292SN/A * contributors may be used to endorse or promote products derived from 142292SN/A * this software without specific prior written permission. 152292SN/A * 162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272689Sktlim@umich.edu * 282689Sktlim@umich.edu * Authors: Korey Sewell 292292SN/A */ 302292SN/A 312329SN/A#include <algorithm> 322329SN/A#include <string> 332329SN/A 342292SN/A#include "cpu/o3/lsq.hh" 352292SN/A 362292SN/Ausing namespace std; 372292SN/A 382292SN/Atemplate <class Impl> 392907Sktlim@umich.eduTick 402907Sktlim@umich.eduLSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt) 412907Sktlim@umich.edu{ 422907Sktlim@umich.edu panic("O3CPU model does not work with atomic mode!"); 432907Sktlim@umich.edu return curTick; 442907Sktlim@umich.edu} 452907Sktlim@umich.edu 462907Sktlim@umich.edutemplate <class Impl> 472907Sktlim@umich.eduvoid 482907Sktlim@umich.eduLSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt) 492907Sktlim@umich.edu{ 502907Sktlim@umich.edu panic("O3CPU doesn't expect recvFunctional callback!"); 512907Sktlim@umich.edu} 522907Sktlim@umich.edu 532907Sktlim@umich.edutemplate <class Impl> 542907Sktlim@umich.eduvoid 552907Sktlim@umich.eduLSQ<Impl>::DcachePort::recvStatusChange(Status status) 562907Sktlim@umich.edu{ 572907Sktlim@umich.edu if (status == RangeChange) 582907Sktlim@umich.edu return; 592907Sktlim@umich.edu 602907Sktlim@umich.edu panic("O3CPU doesn't expect recvStatusChange callback!"); 612907Sktlim@umich.edu} 622907Sktlim@umich.edu 632907Sktlim@umich.edutemplate <class Impl> 642907Sktlim@umich.edubool 652907Sktlim@umich.eduLSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt) 662907Sktlim@umich.edu{ 672907Sktlim@umich.edu lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt); 682907Sktlim@umich.edu return true; 692907Sktlim@umich.edu} 702907Sktlim@umich.edu 712907Sktlim@umich.edutemplate <class Impl> 722907Sktlim@umich.eduvoid 732907Sktlim@umich.eduLSQ<Impl>::DcachePort::recvRetry() 742907Sktlim@umich.edu{ 752907Sktlim@umich.edu lsq->thread[lsq->retryTid].recvRetry(); 762907Sktlim@umich.edu // Speculatively clear the retry Tid. This will get set again if 772907Sktlim@umich.edu // the LSQUnit was unable to complete its access. 782907Sktlim@umich.edu lsq->retryTid = -1; 792907Sktlim@umich.edu} 802907Sktlim@umich.edu 812907Sktlim@umich.edutemplate <class Impl> 822292SN/ALSQ<Impl>::LSQ(Params *params) 832907Sktlim@umich.edu : dcachePort(this), LQEntries(params->LQEntries), 842907Sktlim@umich.edu SQEntries(params->SQEntries), numThreads(params->numberOfThreads), 852907Sktlim@umich.edu retryTid(-1) 862292SN/A{ 872292SN/A DPRINTF(LSQ, "Creating LSQ object.\n"); 882292SN/A 892292SN/A //**********************************************/ 902292SN/A //************ Handle SMT Parameters ***********/ 912292SN/A //**********************************************/ 922292SN/A string policy = params->smtLSQPolicy; 932292SN/A 942292SN/A //Convert string to lowercase 952292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 962292SN/A (int(*)(int)) tolower); 972292SN/A 982292SN/A //Figure out fetch policy 992292SN/A if (policy == "dynamic") { 1002292SN/A lsqPolicy = Dynamic; 1012292SN/A 1022292SN/A maxLQEntries = LQEntries; 1032292SN/A maxSQEntries = SQEntries; 1042292SN/A 1052292SN/A DPRINTF(LSQ, "LSQ sharing policy set to Dynamic\n"); 1062292SN/A 1072292SN/A } else if (policy == "partitioned") { 1082292SN/A lsqPolicy = Partitioned; 1092292SN/A 1102292SN/A //@todo:make work if part_amt doesnt divide evenly. 1112292SN/A maxLQEntries = LQEntries / numThreads; 1122292SN/A maxSQEntries = SQEntries / numThreads; 1132292SN/A 1142292SN/A DPRINTF(Fetch, "LSQ sharing policy set to Partitioned: " 1152292SN/A "%i entries per LQ | %i entries per SQ", 1162292SN/A maxLQEntries,maxSQEntries); 1172292SN/A 1182292SN/A } else if (policy == "threshold") { 1192292SN/A lsqPolicy = Threshold; 1202292SN/A 1212292SN/A assert(params->smtLSQThreshold > LQEntries); 1222292SN/A assert(params->smtLSQThreshold > SQEntries); 1232292SN/A 1242292SN/A //Divide up by threshold amount 1252292SN/A //@todo: Should threads check the max and the total 1262292SN/A //amount of the LSQ 1272292SN/A maxLQEntries = params->smtLSQThreshold; 1282292SN/A maxSQEntries = params->smtLSQThreshold; 1292292SN/A 1302292SN/A DPRINTF(LSQ, "LSQ sharing policy set to Threshold: " 1312292SN/A "%i entries per LQ | %i entries per SQ", 1322292SN/A maxLQEntries,maxSQEntries); 1332292SN/A 1342292SN/A } else { 1352292SN/A assert(0 && "Invalid LSQ Sharing Policy.Options Are:{Dynamic," 1362292SN/A "Partitioned, Threshold}"); 1372292SN/A } 1382292SN/A 1392292SN/A //Initialize LSQs 1402292SN/A for (int tid=0; tid < numThreads; tid++) { 1412907Sktlim@umich.edu thread[tid].init(params, this, maxLQEntries, maxSQEntries, tid); 1422907Sktlim@umich.edu thread[tid].setDcachePort(&dcachePort); 1432292SN/A } 1442292SN/A} 1452292SN/A 1462292SN/A 1472292SN/Atemplate<class Impl> 1482292SN/Astd::string 1492292SN/ALSQ<Impl>::name() const 1502292SN/A{ 1512292SN/A return iewStage->name() + ".lsq"; 1522292SN/A} 1532292SN/A 1542292SN/Atemplate<class Impl> 1552292SN/Avoid 1562727Sktlim@umich.eduLSQ<Impl>::regStats() 1572727Sktlim@umich.edu{ 1582727Sktlim@umich.edu //Initialize LSQs 1592727Sktlim@umich.edu for (int tid=0; tid < numThreads; tid++) { 1602727Sktlim@umich.edu thread[tid].regStats(); 1612727Sktlim@umich.edu } 1622727Sktlim@umich.edu} 1632727Sktlim@umich.edu 1642727Sktlim@umich.edutemplate<class Impl> 1652727Sktlim@umich.eduvoid 1662292SN/ALSQ<Impl>::setActiveThreads(list<unsigned> *at_ptr) 1672292SN/A{ 1682292SN/A activeThreads = at_ptr; 1692292SN/A assert(activeThreads != 0); 1702292SN/A} 1712292SN/A 1722292SN/Atemplate<class Impl> 1732292SN/Avoid 1742733Sktlim@umich.eduLSQ<Impl>::setCPU(O3CPU *cpu_ptr) 1752292SN/A{ 1762292SN/A cpu = cpu_ptr; 1772292SN/A 1782907Sktlim@umich.edu dcachePort.setName(name()); 1792907Sktlim@umich.edu 1802292SN/A for (int tid=0; tid < numThreads; tid++) { 1812292SN/A thread[tid].setCPU(cpu_ptr); 1822292SN/A } 1832292SN/A} 1842292SN/A 1852292SN/Atemplate<class Impl> 1862292SN/Avoid 1872292SN/ALSQ<Impl>::setIEW(IEW *iew_ptr) 1882292SN/A{ 1892292SN/A iewStage = iew_ptr; 1902292SN/A 1912292SN/A for (int tid=0; tid < numThreads; tid++) { 1922292SN/A thread[tid].setIEW(iew_ptr); 1932292SN/A } 1942292SN/A} 1952292SN/A 1962292SN/Atemplate <class Impl> 1972307SN/Avoid 1982307SN/ALSQ<Impl>::switchOut() 1992307SN/A{ 2002307SN/A for (int tid = 0; tid < numThreads; tid++) { 2012307SN/A thread[tid].switchOut(); 2022307SN/A } 2032307SN/A} 2042307SN/A 2052307SN/Atemplate <class Impl> 2062307SN/Avoid 2072307SN/ALSQ<Impl>::takeOverFrom() 2082307SN/A{ 2092307SN/A for (int tid = 0; tid < numThreads; tid++) { 2102307SN/A thread[tid].takeOverFrom(); 2112307SN/A } 2122307SN/A} 2132307SN/A 2142307SN/Atemplate <class Impl> 2152292SN/Aint 2162292SN/ALSQ<Impl>::entryAmount(int num_threads) 2172292SN/A{ 2182292SN/A if (lsqPolicy == Partitioned) { 2192292SN/A return LQEntries / num_threads; 2202292SN/A } else { 2212292SN/A return 0; 2222292SN/A } 2232292SN/A} 2242292SN/A 2252292SN/Atemplate <class Impl> 2262292SN/Avoid 2272292SN/ALSQ<Impl>::resetEntries() 2282292SN/A{ 2292292SN/A if (lsqPolicy != Dynamic || numThreads > 1) { 2302292SN/A int active_threads = (*activeThreads).size(); 2312292SN/A 2322292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 2332292SN/A list<unsigned>::iterator list_end = (*activeThreads).end(); 2342292SN/A 2352292SN/A int maxEntries; 2362292SN/A 2372292SN/A if (lsqPolicy == Partitioned) { 2382292SN/A maxEntries = LQEntries / active_threads; 2392292SN/A } else if (lsqPolicy == Threshold && active_threads == 1) { 2402292SN/A maxEntries = LQEntries; 2412292SN/A } else { 2422292SN/A maxEntries = LQEntries; 2432292SN/A } 2442292SN/A 2452292SN/A while (threads != list_end) { 2462292SN/A resizeEntries(maxEntries,*threads++); 2472292SN/A } 2482292SN/A } 2492292SN/A} 2502292SN/A 2512292SN/Atemplate<class Impl> 2522292SN/Avoid 2532292SN/ALSQ<Impl>::removeEntries(unsigned tid) 2542292SN/A{ 2552292SN/A thread[tid].clearLQ(); 2562292SN/A thread[tid].clearSQ(); 2572292SN/A} 2582292SN/A 2592292SN/Atemplate<class Impl> 2602292SN/Avoid 2612292SN/ALSQ<Impl>::resizeEntries(unsigned size,unsigned tid) 2622292SN/A{ 2632292SN/A thread[tid].resizeLQ(size); 2642292SN/A thread[tid].resizeSQ(size); 2652292SN/A} 2662292SN/A 2672292SN/Atemplate<class Impl> 2682292SN/Avoid 2692292SN/ALSQ<Impl>::tick() 2702292SN/A{ 2712292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 2722292SN/A 2732292SN/A while (active_threads != (*activeThreads).end()) { 2742292SN/A unsigned tid = *active_threads++; 2752292SN/A 2762292SN/A thread[tid].tick(); 2772292SN/A } 2782292SN/A} 2792292SN/A 2802292SN/Atemplate<class Impl> 2812292SN/Avoid 2822292SN/ALSQ<Impl>::insertLoad(DynInstPtr &load_inst) 2832292SN/A{ 2842292SN/A unsigned tid = load_inst->threadNumber; 2852292SN/A 2862292SN/A thread[tid].insertLoad(load_inst); 2872292SN/A} 2882292SN/A 2892292SN/Atemplate<class Impl> 2902292SN/Avoid 2912292SN/ALSQ<Impl>::insertStore(DynInstPtr &store_inst) 2922292SN/A{ 2932292SN/A unsigned tid = store_inst->threadNumber; 2942292SN/A 2952292SN/A thread[tid].insertStore(store_inst); 2962292SN/A} 2972292SN/A 2982292SN/Atemplate<class Impl> 2992292SN/AFault 3002292SN/ALSQ<Impl>::executeLoad(DynInstPtr &inst) 3012292SN/A{ 3022292SN/A unsigned tid = inst->threadNumber; 3032292SN/A 3042292SN/A return thread[tid].executeLoad(inst); 3052292SN/A} 3062292SN/A 3072292SN/Atemplate<class Impl> 3082292SN/AFault 3092292SN/ALSQ<Impl>::executeStore(DynInstPtr &inst) 3102292SN/A{ 3112292SN/A unsigned tid = inst->threadNumber; 3122292SN/A 3132292SN/A return thread[tid].executeStore(inst); 3142292SN/A} 3152292SN/A 3162292SN/Atemplate<class Impl> 3172292SN/Avoid 3182292SN/ALSQ<Impl>::writebackStores() 3192292SN/A{ 3202292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 3212292SN/A 3222292SN/A while (active_threads != (*activeThreads).end()) { 3232292SN/A unsigned tid = *active_threads++; 3242292SN/A 3252292SN/A if (numStoresToWB(tid) > 0) { 3262329SN/A DPRINTF(Writeback,"[tid:%i] Writing back stores. %i stores " 3272329SN/A "available for Writeback.\n", tid, numStoresToWB(tid)); 3282292SN/A } 3292292SN/A 3302292SN/A thread[tid].writebackStores(); 3312292SN/A } 3322292SN/A} 3332292SN/A 3342292SN/Atemplate<class Impl> 3352292SN/Abool 3362292SN/ALSQ<Impl>::violation() 3372292SN/A{ 3382292SN/A /* Answers: Does Anybody Have a Violation?*/ 3392292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 3402292SN/A 3412292SN/A while (active_threads != (*activeThreads).end()) { 3422292SN/A unsigned tid = *active_threads++; 3432292SN/A if (thread[tid].violation()) 3442292SN/A return true; 3452292SN/A } 3462292SN/A 3472292SN/A return false; 3482292SN/A} 3492292SN/A 3502292SN/Atemplate<class Impl> 3512292SN/Aint 3522292SN/ALSQ<Impl>::getCount() 3532292SN/A{ 3542292SN/A unsigned total = 0; 3552292SN/A 3562292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 3572292SN/A 3582292SN/A while (active_threads != (*activeThreads).end()) { 3592292SN/A unsigned tid = *active_threads++; 3602292SN/A total += getCount(tid); 3612292SN/A } 3622292SN/A 3632292SN/A return total; 3642292SN/A} 3652292SN/A 3662292SN/Atemplate<class Impl> 3672292SN/Aint 3682292SN/ALSQ<Impl>::numLoads() 3692292SN/A{ 3702292SN/A unsigned total = 0; 3712292SN/A 3722292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 3732292SN/A 3742292SN/A while (active_threads != (*activeThreads).end()) { 3752292SN/A unsigned tid = *active_threads++; 3762292SN/A total += numLoads(tid); 3772292SN/A } 3782292SN/A 3792292SN/A return total; 3802292SN/A} 3812292SN/A 3822292SN/Atemplate<class Impl> 3832292SN/Aint 3842292SN/ALSQ<Impl>::numStores() 3852292SN/A{ 3862292SN/A unsigned total = 0; 3872292SN/A 3882292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 3892292SN/A 3902292SN/A while (active_threads != (*activeThreads).end()) { 3912292SN/A unsigned tid = *active_threads++; 3922292SN/A total += thread[tid].numStores(); 3932292SN/A } 3942292SN/A 3952292SN/A return total; 3962292SN/A} 3972292SN/A 3982292SN/Atemplate<class Impl> 3992292SN/Aint 4002292SN/ALSQ<Impl>::numLoadsReady() 4012292SN/A{ 4022292SN/A unsigned total = 0; 4032292SN/A 4042292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 4052292SN/A 4062292SN/A while (active_threads != (*activeThreads).end()) { 4072292SN/A unsigned tid = *active_threads++; 4082292SN/A total += thread[tid].numLoadsReady(); 4092292SN/A } 4102292SN/A 4112292SN/A return total; 4122292SN/A} 4132292SN/A 4142292SN/Atemplate<class Impl> 4152292SN/Aunsigned 4162292SN/ALSQ<Impl>::numFreeEntries() 4172292SN/A{ 4182292SN/A unsigned total = 0; 4192292SN/A 4202292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 4212292SN/A 4222292SN/A while (active_threads != (*activeThreads).end()) { 4232292SN/A unsigned tid = *active_threads++; 4242292SN/A total += thread[tid].numFreeEntries(); 4252292SN/A } 4262292SN/A 4272292SN/A return total; 4282292SN/A} 4292292SN/A 4302292SN/Atemplate<class Impl> 4312292SN/Aunsigned 4322292SN/ALSQ<Impl>::numFreeEntries(unsigned tid) 4332292SN/A{ 4342292SN/A //if( lsqPolicy == Dynamic ) 4352292SN/A //return numFreeEntries(); 4362292SN/A //else 4372292SN/A return thread[tid].numFreeEntries(); 4382292SN/A} 4392292SN/A 4402292SN/Atemplate<class Impl> 4412292SN/Abool 4422292SN/ALSQ<Impl>::isFull() 4432292SN/A{ 4442292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 4452292SN/A 4462292SN/A while (active_threads != (*activeThreads).end()) { 4472292SN/A unsigned tid = *active_threads++; 4482292SN/A if (! (thread[tid].lqFull() || thread[tid].sqFull()) ) 4492292SN/A return false; 4502292SN/A } 4512292SN/A 4522292SN/A return true; 4532292SN/A} 4542292SN/A 4552292SN/Atemplate<class Impl> 4562292SN/Abool 4572292SN/ALSQ<Impl>::isFull(unsigned tid) 4582292SN/A{ 4592292SN/A //@todo: Change to Calculate All Entries for 4602292SN/A //Dynamic Policy 4612292SN/A if( lsqPolicy == Dynamic ) 4622292SN/A return isFull(); 4632292SN/A else 4642292SN/A return thread[tid].lqFull() || thread[tid].sqFull(); 4652292SN/A} 4662292SN/A 4672292SN/Atemplate<class Impl> 4682292SN/Abool 4692292SN/ALSQ<Impl>::lqFull() 4702292SN/A{ 4712292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 4722292SN/A 4732292SN/A while (active_threads != (*activeThreads).end()) { 4742292SN/A unsigned tid = *active_threads++; 4752292SN/A if (!thread[tid].lqFull()) 4762292SN/A return false; 4772292SN/A } 4782292SN/A 4792292SN/A return true; 4802292SN/A} 4812292SN/A 4822292SN/Atemplate<class Impl> 4832292SN/Abool 4842292SN/ALSQ<Impl>::lqFull(unsigned tid) 4852292SN/A{ 4862292SN/A //@todo: Change to Calculate All Entries for 4872292SN/A //Dynamic Policy 4882292SN/A if( lsqPolicy == Dynamic ) 4892292SN/A return lqFull(); 4902292SN/A else 4912292SN/A return thread[tid].lqFull(); 4922292SN/A} 4932292SN/A 4942292SN/Atemplate<class Impl> 4952292SN/Abool 4962292SN/ALSQ<Impl>::sqFull() 4972292SN/A{ 4982292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 4992292SN/A 5002292SN/A while (active_threads != (*activeThreads).end()) { 5012292SN/A unsigned tid = *active_threads++; 5022292SN/A if (!sqFull(tid)) 5032292SN/A return false; 5042292SN/A } 5052292SN/A 5062292SN/A return true; 5072292SN/A} 5082292SN/A 5092292SN/Atemplate<class Impl> 5102292SN/Abool 5112292SN/ALSQ<Impl>::sqFull(unsigned tid) 5122292SN/A{ 5132292SN/A //@todo: Change to Calculate All Entries for 5142292SN/A //Dynamic Policy 5152292SN/A if( lsqPolicy == Dynamic ) 5162292SN/A return sqFull(); 5172292SN/A else 5182292SN/A return thread[tid].sqFull(); 5192292SN/A} 5202292SN/A 5212292SN/Atemplate<class Impl> 5222292SN/Abool 5232292SN/ALSQ<Impl>::isStalled() 5242292SN/A{ 5252292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 5262292SN/A 5272292SN/A while (active_threads != (*activeThreads).end()) { 5282292SN/A unsigned tid = *active_threads++; 5292292SN/A if (!thread[tid].isStalled()) 5302292SN/A return false; 5312292SN/A } 5322292SN/A 5332292SN/A return true; 5342292SN/A} 5352292SN/A 5362292SN/Atemplate<class Impl> 5372292SN/Abool 5382292SN/ALSQ<Impl>::isStalled(unsigned tid) 5392292SN/A{ 5402292SN/A if( lsqPolicy == Dynamic ) 5412292SN/A return isStalled(); 5422292SN/A else 5432292SN/A return thread[tid].isStalled(); 5442292SN/A} 5452292SN/A 5462292SN/Atemplate<class Impl> 5472292SN/Abool 5482292SN/ALSQ<Impl>::hasStoresToWB() 5492292SN/A{ 5502292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 5512292SN/A 5522864Sktlim@umich.edu if ((*activeThreads).empty()) 5532864Sktlim@umich.edu return false; 5542864Sktlim@umich.edu 5552292SN/A while (active_threads != (*activeThreads).end()) { 5562292SN/A unsigned tid = *active_threads++; 5572292SN/A if (!hasStoresToWB(tid)) 5582292SN/A return false; 5592292SN/A } 5602292SN/A 5612292SN/A return true; 5622292SN/A} 5632292SN/A 5642292SN/Atemplate<class Impl> 5652292SN/Abool 5662292SN/ALSQ<Impl>::willWB() 5672292SN/A{ 5682292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 5692292SN/A 5702292SN/A while (active_threads != (*activeThreads).end()) { 5712292SN/A unsigned tid = *active_threads++; 5722292SN/A if (!willWB(tid)) 5732292SN/A return false; 5742292SN/A } 5752292SN/A 5762292SN/A return true; 5772292SN/A} 5782292SN/A 5792292SN/Atemplate<class Impl> 5802292SN/Avoid 5812292SN/ALSQ<Impl>::dumpInsts() 5822292SN/A{ 5832292SN/A list<unsigned>::iterator active_threads = (*activeThreads).begin(); 5842292SN/A 5852292SN/A while (active_threads != (*activeThreads).end()) { 5862292SN/A unsigned tid = *active_threads++; 5872292SN/A thread[tid].dumpInsts(); 5882292SN/A } 5892292SN/A} 590