inst_queue_impl.hh revision 8071
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#include <limits>
45#include <vector>
46
47#include "cpu/o3/fu_pool.hh"
48#include "cpu/o3/inst_queue.hh"
49#include "enums/OpClass.hh"
50#include "params/DerivO3CPU.hh"
51#include "sim/core.hh"
52
53using namespace std;
54
55template <class Impl>
56InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
57    int fu_idx, InstructionQueue<Impl> *iq_ptr)
58    : Event(Stat_Event_Pri), inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr),
59      freeFU(false)
60{
61    this->setFlags(Event::AutoDelete);
62}
63
64template <class Impl>
65void
66InstructionQueue<Impl>::FUCompletion::process()
67{
68    iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
69    inst = NULL;
70}
71
72
73template <class Impl>
74const char *
75InstructionQueue<Impl>::FUCompletion::description() const
76{
77    return "Functional unit completion";
78}
79
80template <class Impl>
81InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
82                                         DerivO3CPUParams *params)
83    : cpu(cpu_ptr),
84      iewStage(iew_ptr),
85      fuPool(params->fuPool),
86      numEntries(params->numIQEntries),
87      totalWidth(params->issueWidth),
88      numPhysIntRegs(params->numPhysIntRegs),
89      numPhysFloatRegs(params->numPhysFloatRegs),
90      commitToIEWDelay(params->commitToIEWDelay)
91{
92    assert(fuPool);
93
94    switchedOut = false;
95
96    numThreads = params->numThreads;
97
98    // Set the number of physical registers as the number of int + float
99    numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
100
101    //Create an entry for each physical register within the
102    //dependency graph.
103    dependGraph.resize(numPhysRegs);
104
105    // Resize the register scoreboard.
106    regScoreboard.resize(numPhysRegs);
107
108    //Initialize Mem Dependence Units
109    for (ThreadID tid = 0; tid < numThreads; tid++) {
110        memDepUnit[tid].init(params, tid);
111        memDepUnit[tid].setIQ(this);
112    }
113
114    resetState();
115
116    std::string policy = params->smtIQPolicy;
117
118    //Convert string to lowercase
119    std::transform(policy.begin(), policy.end(), policy.begin(),
120                   (int(*)(int)) tolower);
121
122    //Figure out resource sharing policy
123    if (policy == "dynamic") {
124        iqPolicy = Dynamic;
125
126        //Set Max Entries to Total ROB Capacity
127        for (ThreadID tid = 0; tid < numThreads; tid++) {
128            maxEntries[tid] = numEntries;
129        }
130
131    } else if (policy == "partitioned") {
132        iqPolicy = Partitioned;
133
134        //@todo:make work if part_amt doesnt divide evenly.
135        int part_amt = numEntries / numThreads;
136
137        //Divide ROB up evenly
138        for (ThreadID tid = 0; tid < numThreads; tid++) {
139            maxEntries[tid] = part_amt;
140        }
141
142        DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
143                "%i entries per thread.\n",part_amt);
144    } else if (policy == "threshold") {
145        iqPolicy = Threshold;
146
147        double threshold =  (double)params->smtIQThreshold / 100;
148
149        int thresholdIQ = (int)((double)threshold * numEntries);
150
151        //Divide up by threshold amount
152        for (ThreadID tid = 0; tid < numThreads; tid++) {
153            maxEntries[tid] = thresholdIQ;
154        }
155
156        DPRINTF(IQ, "IQ sharing policy set to Threshold:"
157                "%i entries per thread.\n",thresholdIQ);
158   } else {
159       assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
160              "Partitioned, Threshold}");
161   }
162}
163
164template <class Impl>
165InstructionQueue<Impl>::~InstructionQueue()
166{
167    dependGraph.reset();
168#ifdef DEBUG
169    cprintf("Nodes traversed: %i, removed: %i\n",
170            dependGraph.nodesTraversed, dependGraph.nodesRemoved);
171#endif
172}
173
174template <class Impl>
175std::string
176InstructionQueue<Impl>::name() const
177{
178    return cpu->name() + ".iq";
179}
180
181template <class Impl>
182void
183InstructionQueue<Impl>::regStats()
184{
185    using namespace Stats;
186    iqInstsAdded
187        .name(name() + ".iqInstsAdded")
188        .desc("Number of instructions added to the IQ (excludes non-spec)")
189        .prereq(iqInstsAdded);
190
191    iqNonSpecInstsAdded
192        .name(name() + ".iqNonSpecInstsAdded")
193        .desc("Number of non-speculative instructions added to the IQ")
194        .prereq(iqNonSpecInstsAdded);
195
196    iqInstsIssued
197        .name(name() + ".iqInstsIssued")
198        .desc("Number of instructions issued")
199        .prereq(iqInstsIssued);
200
201    iqIntInstsIssued
202        .name(name() + ".iqIntInstsIssued")
203        .desc("Number of integer instructions issued")
204        .prereq(iqIntInstsIssued);
205
206    iqFloatInstsIssued
207        .name(name() + ".iqFloatInstsIssued")
208        .desc("Number of float instructions issued")
209        .prereq(iqFloatInstsIssued);
210
211    iqBranchInstsIssued
212        .name(name() + ".iqBranchInstsIssued")
213        .desc("Number of branch instructions issued")
214        .prereq(iqBranchInstsIssued);
215
216    iqMemInstsIssued
217        .name(name() + ".iqMemInstsIssued")
218        .desc("Number of memory instructions issued")
219        .prereq(iqMemInstsIssued);
220
221    iqMiscInstsIssued
222        .name(name() + ".iqMiscInstsIssued")
223        .desc("Number of miscellaneous instructions issued")
224        .prereq(iqMiscInstsIssued);
225
226    iqSquashedInstsIssued
227        .name(name() + ".iqSquashedInstsIssued")
228        .desc("Number of squashed instructions issued")
229        .prereq(iqSquashedInstsIssued);
230
231    iqSquashedInstsExamined
232        .name(name() + ".iqSquashedInstsExamined")
233        .desc("Number of squashed instructions iterated over during squash;"
234              " mainly for profiling")
235        .prereq(iqSquashedInstsExamined);
236
237    iqSquashedOperandsExamined
238        .name(name() + ".iqSquashedOperandsExamined")
239        .desc("Number of squashed operands that are examined and possibly "
240              "removed from graph")
241        .prereq(iqSquashedOperandsExamined);
242
243    iqSquashedNonSpecRemoved
244        .name(name() + ".iqSquashedNonSpecRemoved")
245        .desc("Number of squashed non-spec instructions that were removed")
246        .prereq(iqSquashedNonSpecRemoved);
247/*
248    queueResDist
249        .init(Num_OpClasses, 0, 99, 2)
250        .name(name() + ".IQ:residence:")
251        .desc("cycles from dispatch to issue")
252        .flags(total | pdf | cdf )
253        ;
254    for (int i = 0; i < Num_OpClasses; ++i) {
255        queueResDist.subname(i, opClassStrings[i]);
256    }
257*/
258    numIssuedDist
259        .init(0,totalWidth,1)
260        .name(name() + ".ISSUE:issued_per_cycle")
261        .desc("Number of insts issued each cycle")
262        .flags(pdf)
263        ;
264/*
265    dist_unissued
266        .init(Num_OpClasses+2)
267        .name(name() + ".ISSUE:unissued_cause")
268        .desc("Reason ready instruction not issued")
269        .flags(pdf | dist)
270        ;
271    for (int i=0; i < (Num_OpClasses + 2); ++i) {
272        dist_unissued.subname(i, unissued_names[i]);
273    }
274*/
275    statIssuedInstType
276        .init(numThreads,Enums::Num_OpClass)
277        .name(name() + ".ISSUE:FU_type")
278        .desc("Type of FU issued")
279        .flags(total | pdf | dist)
280        ;
281    statIssuedInstType.ysubnames(Enums::OpClassStrings);
282
283    //
284    //  How long did instructions for a particular FU type wait prior to issue
285    //
286/*
287    issueDelayDist
288        .init(Num_OpClasses,0,99,2)
289        .name(name() + ".ISSUE:")
290        .desc("cycles from operands ready to issue")
291        .flags(pdf | cdf)
292        ;
293
294    for (int i=0; i<Num_OpClasses; ++i) {
295        std::stringstream subname;
296        subname << opClassStrings[i] << "_delay";
297        issueDelayDist.subname(i, subname.str());
298    }
299*/
300    issueRate
301        .name(name() + ".ISSUE:rate")
302        .desc("Inst issue rate")
303        .flags(total)
304        ;
305    issueRate = iqInstsIssued / cpu->numCycles;
306
307    statFuBusy
308        .init(Num_OpClasses)
309        .name(name() + ".ISSUE:fu_full")
310        .desc("attempts to use FU when none available")
311        .flags(pdf | dist)
312        ;
313    for (int i=0; i < Num_OpClasses; ++i) {
314        statFuBusy.subname(i, Enums::OpClassStrings[i]);
315    }
316
317    fuBusy
318        .init(numThreads)
319        .name(name() + ".ISSUE:fu_busy_cnt")
320        .desc("FU busy when requested")
321        .flags(total)
322        ;
323
324    fuBusyRate
325        .name(name() + ".ISSUE:fu_busy_rate")
326        .desc("FU busy rate (busy events/executed inst)")
327        .flags(total)
328        ;
329    fuBusyRate = fuBusy / iqInstsIssued;
330
331    for (ThreadID tid = 0; tid < numThreads; tid++) {
332        // Tell mem dependence unit to reg stats as well.
333        memDepUnit[tid].regStats();
334    }
335
336    intInstQueueReads
337        .name(name() + ".int_inst_queue_reads")
338        .desc("Number of integer instruction queue reads")
339        .flags(total);
340
341    intInstQueueWrites
342        .name(name() + ".int_inst_queue_writes")
343        .desc("Number of integer instruction queue writes")
344        .flags(total);
345
346    intInstQueueWakeupAccesses
347        .name(name() + ".int_inst_queue_wakeup_accesses")
348        .desc("Number of integer instruction queue wakeup accesses")
349        .flags(total);
350
351    fpInstQueueReads
352        .name(name() + ".fp_inst_queue_reads")
353        .desc("Number of floating instruction queue reads")
354        .flags(total);
355
356    fpInstQueueWrites
357        .name(name() + ".fp_inst_queue_writes")
358        .desc("Number of floating instruction queue writes")
359        .flags(total);
360
361    fpInstQueueWakeupQccesses
362        .name(name() + ".fp_inst_queue_wakeup_accesses")
363        .desc("Number of floating instruction queue wakeup accesses")
364        .flags(total);
365
366    intAluAccesses
367        .name(name() + ".int_alu_accesses")
368        .desc("Number of integer alu accesses")
369        .flags(total);
370
371    fpAluAccesses
372        .name(name() + ".fp_alu_accesses")
373        .desc("Number of floating point alu accesses")
374        .flags(total);
375
376}
377
378template <class Impl>
379void
380InstructionQueue<Impl>::resetState()
381{
382    //Initialize thread IQ counts
383    for (ThreadID tid = 0; tid <numThreads; tid++) {
384        count[tid] = 0;
385        instList[tid].clear();
386    }
387
388    // Initialize the number of free IQ entries.
389    freeEntries = numEntries;
390
391    // Note that in actuality, the registers corresponding to the logical
392    // registers start off as ready.  However this doesn't matter for the
393    // IQ as the instruction should have been correctly told if those
394    // registers are ready in rename.  Thus it can all be initialized as
395    // unready.
396    for (int i = 0; i < numPhysRegs; ++i) {
397        regScoreboard[i] = false;
398    }
399
400    for (ThreadID tid = 0; tid < numThreads; ++tid) {
401        squashedSeqNum[tid] = 0;
402    }
403
404    for (int i = 0; i < Num_OpClasses; ++i) {
405        while (!readyInsts[i].empty())
406            readyInsts[i].pop();
407        queueOnList[i] = false;
408        readyIt[i] = listOrder.end();
409    }
410    nonSpecInsts.clear();
411    listOrder.clear();
412    deferredMemInsts.clear();
413}
414
415template <class Impl>
416void
417InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
418{
419    activeThreads = at_ptr;
420}
421
422template <class Impl>
423void
424InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
425{
426      issueToExecuteQueue = i2e_ptr;
427}
428
429template <class Impl>
430void
431InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
432{
433    timeBuffer = tb_ptr;
434
435    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
436}
437
438template <class Impl>
439void
440InstructionQueue<Impl>::switchOut()
441{
442/*
443    if (!instList[0].empty() || (numEntries != freeEntries) ||
444        !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
445        dumpInsts();
446//        assert(0);
447    }
448*/
449    resetState();
450    dependGraph.reset();
451    instsToExecute.clear();
452    switchedOut = true;
453    for (ThreadID tid = 0; tid < numThreads; ++tid) {
454        memDepUnit[tid].switchOut();
455    }
456}
457
458template <class Impl>
459void
460InstructionQueue<Impl>::takeOverFrom()
461{
462    switchedOut = false;
463}
464
465template <class Impl>
466int
467InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
468{
469    if (iqPolicy == Partitioned) {
470        return numEntries / num_threads;
471    } else {
472        return 0;
473    }
474}
475
476
477template <class Impl>
478void
479InstructionQueue<Impl>::resetEntries()
480{
481    if (iqPolicy != Dynamic || numThreads > 1) {
482        int active_threads = activeThreads->size();
483
484        list<ThreadID>::iterator threads = activeThreads->begin();
485        list<ThreadID>::iterator end = activeThreads->end();
486
487        while (threads != end) {
488            ThreadID tid = *threads++;
489
490            if (iqPolicy == Partitioned) {
491                maxEntries[tid] = numEntries / active_threads;
492            } else if(iqPolicy == Threshold && active_threads == 1) {
493                maxEntries[tid] = numEntries;
494            }
495        }
496    }
497}
498
499template <class Impl>
500unsigned
501InstructionQueue<Impl>::numFreeEntries()
502{
503    return freeEntries;
504}
505
506template <class Impl>
507unsigned
508InstructionQueue<Impl>::numFreeEntries(ThreadID tid)
509{
510    return maxEntries[tid] - count[tid];
511}
512
513// Might want to do something more complex if it knows how many instructions
514// will be issued this cycle.
515template <class Impl>
516bool
517InstructionQueue<Impl>::isFull()
518{
519    if (freeEntries == 0) {
520        return(true);
521    } else {
522        return(false);
523    }
524}
525
526template <class Impl>
527bool
528InstructionQueue<Impl>::isFull(ThreadID tid)
529{
530    if (numFreeEntries(tid) == 0) {
531        return(true);
532    } else {
533        return(false);
534    }
535}
536
537template <class Impl>
538bool
539InstructionQueue<Impl>::hasReadyInsts()
540{
541    if (!listOrder.empty()) {
542        return true;
543    }
544
545    for (int i = 0; i < Num_OpClasses; ++i) {
546        if (!readyInsts[i].empty()) {
547            return true;
548        }
549    }
550
551    return false;
552}
553
554template <class Impl>
555void
556InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
557{
558    new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
559    // Make sure the instruction is valid
560    assert(new_inst);
561
562    DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n",
563            new_inst->seqNum, new_inst->pcState());
564
565    assert(freeEntries != 0);
566
567    instList[new_inst->threadNumber].push_back(new_inst);
568
569    --freeEntries;
570
571    new_inst->setInIQ();
572
573    // Look through its source registers (physical regs), and mark any
574    // dependencies.
575    addToDependents(new_inst);
576
577    // Have this instruction set itself as the producer of its destination
578    // register(s).
579    addToProducers(new_inst);
580
581    if (new_inst->isMemRef()) {
582        memDepUnit[new_inst->threadNumber].insert(new_inst);
583    } else {
584        addIfReady(new_inst);
585    }
586
587    ++iqInstsAdded;
588
589    count[new_inst->threadNumber]++;
590
591    assert(freeEntries == (numEntries - countInsts()));
592}
593
594template <class Impl>
595void
596InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
597{
598    // @todo: Clean up this code; can do it by setting inst as unable
599    // to issue, then calling normal insert on the inst.
600    new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
601
602    assert(new_inst);
603
604    nonSpecInsts[new_inst->seqNum] = new_inst;
605
606    DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s "
607            "to the IQ.\n",
608            new_inst->seqNum, new_inst->pcState());
609
610    assert(freeEntries != 0);
611
612    instList[new_inst->threadNumber].push_back(new_inst);
613
614    --freeEntries;
615
616    new_inst->setInIQ();
617
618    // Have this instruction set itself as the producer of its destination
619    // register(s).
620    addToProducers(new_inst);
621
622    // If it's a memory instruction, add it to the memory dependency
623    // unit.
624    if (new_inst->isMemRef()) {
625        memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
626    }
627
628    ++iqNonSpecInstsAdded;
629
630    count[new_inst->threadNumber]++;
631
632    assert(freeEntries == (numEntries - countInsts()));
633}
634
635template <class Impl>
636void
637InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
638{
639    memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
640
641    insertNonSpec(barr_inst);
642}
643
644template <class Impl>
645typename Impl::DynInstPtr
646InstructionQueue<Impl>::getInstToExecute()
647{
648    assert(!instsToExecute.empty());
649    DynInstPtr inst = instsToExecute.front();
650    instsToExecute.pop_front();
651    if (inst->isFloating()){
652        fpInstQueueReads++;
653    } else {
654        intInstQueueReads++;
655    }
656    return inst;
657}
658
659template <class Impl>
660void
661InstructionQueue<Impl>::addToOrderList(OpClass op_class)
662{
663    assert(!readyInsts[op_class].empty());
664
665    ListOrderEntry queue_entry;
666
667    queue_entry.queueType = op_class;
668
669    queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
670
671    ListOrderIt list_it = listOrder.begin();
672    ListOrderIt list_end_it = listOrder.end();
673
674    while (list_it != list_end_it) {
675        if ((*list_it).oldestInst > queue_entry.oldestInst) {
676            break;
677        }
678
679        list_it++;
680    }
681
682    readyIt[op_class] = listOrder.insert(list_it, queue_entry);
683    queueOnList[op_class] = true;
684}
685
686template <class Impl>
687void
688InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
689{
690    // Get iterator of next item on the list
691    // Delete the original iterator
692    // Determine if the next item is either the end of the list or younger
693    // than the new instruction.  If so, then add in a new iterator right here.
694    // If not, then move along.
695    ListOrderEntry queue_entry;
696    OpClass op_class = (*list_order_it).queueType;
697    ListOrderIt next_it = list_order_it;
698
699    ++next_it;
700
701    queue_entry.queueType = op_class;
702    queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
703
704    while (next_it != listOrder.end() &&
705           (*next_it).oldestInst < queue_entry.oldestInst) {
706        ++next_it;
707    }
708
709    readyIt[op_class] = listOrder.insert(next_it, queue_entry);
710}
711
712template <class Impl>
713void
714InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
715{
716    DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
717    // The CPU could have been sleeping until this op completed (*extremely*
718    // long latency op).  Wake it if it was.  This may be overkill.
719    if (isSwitchedOut()) {
720        DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n",
721                inst->seqNum);
722        return;
723    }
724
725    iewStage->wakeCPU();
726
727    if (fu_idx > -1)
728        fuPool->freeUnitNextCycle(fu_idx);
729
730    // @todo: Ensure that these FU Completions happen at the beginning
731    // of a cycle, otherwise they could add too many instructions to
732    // the queue.
733    issueToExecuteQueue->access(-1)->size++;
734    instsToExecute.push_back(inst);
735}
736
737// @todo: Figure out a better way to remove the squashed items from the
738// lists.  Checking the top item of each list to see if it's squashed
739// wastes time and forces jumps.
740template <class Impl>
741void
742InstructionQueue<Impl>::scheduleReadyInsts()
743{
744    DPRINTF(IQ, "Attempting to schedule ready instructions from "
745            "the IQ.\n");
746
747    IssueStruct *i2e_info = issueToExecuteQueue->access(0);
748
749    DynInstPtr deferred_mem_inst;
750    int total_deferred_mem_issued = 0;
751    while (total_deferred_mem_issued < totalWidth &&
752           (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) {
753        issueToExecuteQueue->access(0)->size++;
754        instsToExecute.push_back(deferred_mem_inst);
755        total_deferred_mem_issued++;
756    }
757
758    // Have iterator to head of the list
759    // While I haven't exceeded bandwidth or reached the end of the list,
760    // Try to get a FU that can do what this op needs.
761    // If successful, change the oldestInst to the new top of the list, put
762    // the queue in the proper place in the list.
763    // Increment the iterator.
764    // This will avoid trying to schedule a certain op class if there are no
765    // FUs that handle it.
766    ListOrderIt order_it = listOrder.begin();
767    ListOrderIt order_end_it = listOrder.end();
768    int total_issued = 0;
769
770    while (total_issued < (totalWidth - total_deferred_mem_issued) &&
771           iewStage->canIssue() &&
772           order_it != order_end_it) {
773        OpClass op_class = (*order_it).queueType;
774
775        assert(!readyInsts[op_class].empty());
776
777        DynInstPtr issuing_inst = readyInsts[op_class].top();
778
779        issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++;
780
781        assert(issuing_inst->seqNum == (*order_it).oldestInst);
782
783        if (issuing_inst->isSquashed()) {
784            readyInsts[op_class].pop();
785
786            if (!readyInsts[op_class].empty()) {
787                moveToYoungerInst(order_it);
788            } else {
789                readyIt[op_class] = listOrder.end();
790                queueOnList[op_class] = false;
791            }
792
793            listOrder.erase(order_it++);
794
795            ++iqSquashedInstsIssued;
796
797            continue;
798        }
799
800        int idx = -2;
801        int op_latency = 1;
802        ThreadID tid = issuing_inst->threadNumber;
803
804        if (op_class != No_OpClass) {
805            idx = fuPool->getUnit(op_class);
806            issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++;
807            if (idx > -1) {
808                op_latency = fuPool->getOpLatency(op_class);
809            }
810        }
811
812        // If we have an instruction that doesn't require a FU, or a
813        // valid FU, then schedule for execution.
814        if (idx == -2 || idx != -1) {
815            if (op_latency == 1) {
816                i2e_info->size++;
817                instsToExecute.push_back(issuing_inst);
818
819                // Add the FU onto the list of FU's to be freed next
820                // cycle if we used one.
821                if (idx >= 0)
822                    fuPool->freeUnitNextCycle(idx);
823            } else {
824                int issue_latency = fuPool->getIssueLatency(op_class);
825                // Generate completion event for the FU
826                FUCompletion *execution = new FUCompletion(issuing_inst,
827                                                           idx, this);
828
829                cpu->schedule(execution, curTick() + cpu->ticks(op_latency - 1));
830
831                // @todo: Enforce that issue_latency == 1 or op_latency
832                if (issue_latency > 1) {
833                    // If FU isn't pipelined, then it must be freed
834                    // upon the execution completing.
835                    execution->setFreeFU();
836                } else {
837                    // Add the FU onto the list of FU's to be freed next cycle.
838                    fuPool->freeUnitNextCycle(idx);
839                }
840            }
841
842            DPRINTF(IQ, "Thread %i: Issuing instruction PC %s "
843                    "[sn:%lli]\n",
844                    tid, issuing_inst->pcState(),
845                    issuing_inst->seqNum);
846
847            readyInsts[op_class].pop();
848
849            if (!readyInsts[op_class].empty()) {
850                moveToYoungerInst(order_it);
851            } else {
852                readyIt[op_class] = listOrder.end();
853                queueOnList[op_class] = false;
854            }
855
856            issuing_inst->setIssued();
857            ++total_issued;
858
859            if (!issuing_inst->isMemRef()) {
860                // Memory instructions can not be freed from the IQ until they
861                // complete.
862                ++freeEntries;
863                count[tid]--;
864                issuing_inst->clearInIQ();
865            } else {
866                memDepUnit[tid].issue(issuing_inst);
867            }
868
869            listOrder.erase(order_it++);
870            statIssuedInstType[tid][op_class]++;
871            iewStage->incrWb(issuing_inst->seqNum);
872        } else {
873            statFuBusy[op_class]++;
874            fuBusy[tid]++;
875            ++order_it;
876        }
877    }
878
879    numIssuedDist.sample(total_issued);
880    iqInstsIssued+= total_issued;
881
882    // If we issued any instructions, tell the CPU we had activity.
883    // @todo If the way deferred memory instructions are handeled due to
884    // translation changes then the deferredMemInsts condition should be removed
885    // from the code below.
886    if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) {
887        cpu->activityThisCycle();
888    } else {
889        DPRINTF(IQ, "Not able to schedule any instructions.\n");
890    }
891}
892
893template <class Impl>
894void
895InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
896{
897    DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
898            "to execute.\n", inst);
899
900    NonSpecMapIt inst_it = nonSpecInsts.find(inst);
901
902    assert(inst_it != nonSpecInsts.end());
903
904    ThreadID tid = (*inst_it).second->threadNumber;
905
906    (*inst_it).second->setAtCommit();
907
908    (*inst_it).second->setCanIssue();
909
910    if (!(*inst_it).second->isMemRef()) {
911        addIfReady((*inst_it).second);
912    } else {
913        memDepUnit[tid].nonSpecInstReady((*inst_it).second);
914    }
915
916    (*inst_it).second = NULL;
917
918    nonSpecInsts.erase(inst_it);
919}
920
921template <class Impl>
922void
923InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
924{
925    DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
926            tid,inst);
927
928    ListIt iq_it = instList[tid].begin();
929
930    while (iq_it != instList[tid].end() &&
931           (*iq_it)->seqNum <= inst) {
932        ++iq_it;
933        instList[tid].pop_front();
934    }
935
936    assert(freeEntries == (numEntries - countInsts()));
937}
938
939template <class Impl>
940int
941InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
942{
943    int dependents = 0;
944
945    // The instruction queue here takes care of both floating and int ops
946    if (completed_inst->isFloating()) {
947        fpInstQueueWakeupQccesses++;
948    } else {
949        intInstQueueWakeupAccesses++;
950    }
951
952    DPRINTF(IQ, "Waking dependents of completed instruction.\n");
953
954    assert(!completed_inst->isSquashed());
955
956    // Tell the memory dependence unit to wake any dependents on this
957    // instruction if it is a memory instruction.  Also complete the memory
958    // instruction at this point since we know it executed without issues.
959    // @todo: Might want to rename "completeMemInst" to something that
960    // indicates that it won't need to be replayed, and call this
961    // earlier.  Might not be a big deal.
962    if (completed_inst->isMemRef()) {
963        memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
964        completeMemInst(completed_inst);
965    } else if (completed_inst->isMemBarrier() ||
966               completed_inst->isWriteBarrier()) {
967        memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
968    }
969
970    for (int dest_reg_idx = 0;
971         dest_reg_idx < completed_inst->numDestRegs();
972         dest_reg_idx++)
973    {
974        PhysRegIndex dest_reg =
975            completed_inst->renamedDestRegIdx(dest_reg_idx);
976
977        // Special case of uniq or control registers.  They are not
978        // handled by the IQ and thus have no dependency graph entry.
979        // @todo Figure out a cleaner way to handle this.
980        if (dest_reg >= numPhysRegs) {
981            DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg,
982                    numPhysRegs);
983            continue;
984        }
985
986        DPRINTF(IQ, "Waking any dependents on register %i.\n",
987                (int) dest_reg);
988
989        //Go through the dependency chain, marking the registers as
990        //ready within the waiting instructions.
991        DynInstPtr dep_inst = dependGraph.pop(dest_reg);
992
993        while (dep_inst) {
994            DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
995                    "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
996
997            // Might want to give more information to the instruction
998            // so that it knows which of its source registers is
999            // ready.  However that would mean that the dependency
1000            // graph entries would need to hold the src_reg_idx.
1001            dep_inst->markSrcRegReady();
1002
1003            addIfReady(dep_inst);
1004
1005            dep_inst = dependGraph.pop(dest_reg);
1006
1007            ++dependents;
1008        }
1009
1010        // Reset the head node now that all of its dependents have
1011        // been woken up.
1012        assert(dependGraph.empty(dest_reg));
1013        dependGraph.clearInst(dest_reg);
1014
1015        // Mark the scoreboard as having that register ready.
1016        regScoreboard[dest_reg] = true;
1017    }
1018    return dependents;
1019}
1020
1021template <class Impl>
1022void
1023InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
1024{
1025    OpClass op_class = ready_inst->opClass();
1026
1027    readyInsts[op_class].push(ready_inst);
1028
1029    // Will need to reorder the list if either a queue is not on the list,
1030    // or it has an older instruction than last time.
1031    if (!queueOnList[op_class]) {
1032        addToOrderList(op_class);
1033    } else if (readyInsts[op_class].top()->seqNum  <
1034               (*readyIt[op_class]).oldestInst) {
1035        listOrder.erase(readyIt[op_class]);
1036        addToOrderList(op_class);
1037    }
1038
1039    DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1040            "the ready list, PC %s opclass:%i [sn:%lli].\n",
1041            ready_inst->pcState(), op_class, ready_inst->seqNum);
1042}
1043
1044template <class Impl>
1045void
1046InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
1047{
1048    DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
1049
1050    // Reset DTB translation state
1051    resched_inst->translationStarted = false;
1052    resched_inst->translationCompleted = false;
1053
1054    resched_inst->clearCanIssue();
1055    memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
1056}
1057
1058template <class Impl>
1059void
1060InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
1061{
1062    memDepUnit[replay_inst->threadNumber].replay(replay_inst);
1063}
1064
1065template <class Impl>
1066void
1067InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
1068{
1069    ThreadID tid = completed_inst->threadNumber;
1070
1071    DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n",
1072            completed_inst->pcState(), completed_inst->seqNum);
1073
1074    ++freeEntries;
1075
1076    completed_inst->memOpDone = true;
1077
1078    memDepUnit[tid].completed(completed_inst);
1079    count[tid]--;
1080}
1081
1082template <class Impl>
1083void
1084InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst)
1085{
1086    deferredMemInsts.push_back(deferred_inst);
1087}
1088
1089template <class Impl>
1090typename Impl::DynInstPtr
1091InstructionQueue<Impl>::getDeferredMemInstToExecute()
1092{
1093    for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end();
1094         ++it) {
1095        if ((*it)->translationCompleted) {
1096            DynInstPtr ret = *it;
1097            deferredMemInsts.erase(it);
1098            return ret;
1099        }
1100    }
1101    return NULL;
1102}
1103
1104template <class Impl>
1105void
1106InstructionQueue<Impl>::violation(DynInstPtr &store,
1107                                  DynInstPtr &faulting_load)
1108{
1109    intInstQueueWrites++;
1110    memDepUnit[store->threadNumber].violation(store, faulting_load);
1111}
1112
1113template <class Impl>
1114void
1115InstructionQueue<Impl>::squash(ThreadID tid)
1116{
1117    DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1118            "the IQ.\n", tid);
1119
1120    // Read instruction sequence number of last instruction out of the
1121    // time buffer.
1122    squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1123
1124    // Call doSquash if there are insts in the IQ
1125    if (count[tid] > 0) {
1126        doSquash(tid);
1127    }
1128
1129    // Also tell the memory dependence unit to squash.
1130    memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1131}
1132
1133template <class Impl>
1134void
1135InstructionQueue<Impl>::doSquash(ThreadID tid)
1136{
1137    // Start at the tail.
1138    ListIt squash_it = instList[tid].end();
1139    --squash_it;
1140
1141    DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1142            tid, squashedSeqNum[tid]);
1143
1144    // Squash any instructions younger than the squashed sequence number
1145    // given.
1146    while (squash_it != instList[tid].end() &&
1147           (*squash_it)->seqNum > squashedSeqNum[tid]) {
1148
1149        DynInstPtr squashed_inst = (*squash_it);
1150        squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
1151
1152        // Only handle the instruction if it actually is in the IQ and
1153        // hasn't already been squashed in the IQ.
1154        if (squashed_inst->threadNumber != tid ||
1155            squashed_inst->isSquashedInIQ()) {
1156            --squash_it;
1157            continue;
1158        }
1159
1160        if (!squashed_inst->isIssued() ||
1161            (squashed_inst->isMemRef() &&
1162             !squashed_inst->memOpDone)) {
1163
1164            DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
1165                    tid, squashed_inst->seqNum, squashed_inst->pcState());
1166
1167            // Remove the instruction from the dependency list.
1168            if (!squashed_inst->isNonSpeculative() &&
1169                !squashed_inst->isStoreConditional() &&
1170                !squashed_inst->isMemBarrier() &&
1171                !squashed_inst->isWriteBarrier()) {
1172
1173                for (int src_reg_idx = 0;
1174                     src_reg_idx < squashed_inst->numSrcRegs();
1175                     src_reg_idx++)
1176                {
1177                    PhysRegIndex src_reg =
1178                        squashed_inst->renamedSrcRegIdx(src_reg_idx);
1179
1180                    // Only remove it from the dependency graph if it
1181                    // was placed there in the first place.
1182
1183                    // Instead of doing a linked list traversal, we
1184                    // can just remove these squashed instructions
1185                    // either at issue time, or when the register is
1186                    // overwritten.  The only downside to this is it
1187                    // leaves more room for error.
1188
1189                    if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1190                        src_reg < numPhysRegs) {
1191                        dependGraph.remove(src_reg, squashed_inst);
1192                    }
1193
1194
1195                    ++iqSquashedOperandsExamined;
1196                }
1197            } else if (!squashed_inst->isStoreConditional() ||
1198                       !squashed_inst->isCompleted()) {
1199                NonSpecMapIt ns_inst_it =
1200                    nonSpecInsts.find(squashed_inst->seqNum);
1201                assert(ns_inst_it != nonSpecInsts.end());
1202                if (ns_inst_it == nonSpecInsts.end()) {
1203                    assert(squashed_inst->getFault() != NoFault);
1204                } else {
1205
1206                    (*ns_inst_it).second = NULL;
1207
1208                    nonSpecInsts.erase(ns_inst_it);
1209
1210                    ++iqSquashedNonSpecRemoved;
1211                }
1212            }
1213
1214            // Might want to also clear out the head of the dependency graph.
1215
1216            // Mark it as squashed within the IQ.
1217            squashed_inst->setSquashedInIQ();
1218
1219            // @todo: Remove this hack where several statuses are set so the
1220            // inst will flow through the rest of the pipeline.
1221            squashed_inst->setIssued();
1222            squashed_inst->setCanCommit();
1223            squashed_inst->clearInIQ();
1224
1225            //Update Thread IQ Count
1226            count[squashed_inst->threadNumber]--;
1227
1228            ++freeEntries;
1229        }
1230
1231        instList[tid].erase(squash_it--);
1232        ++iqSquashedInstsExamined;
1233    }
1234}
1235
1236template <class Impl>
1237bool
1238InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1239{
1240    // Loop through the instruction's source registers, adding
1241    // them to the dependency list if they are not ready.
1242    int8_t total_src_regs = new_inst->numSrcRegs();
1243    bool return_val = false;
1244
1245    for (int src_reg_idx = 0;
1246         src_reg_idx < total_src_regs;
1247         src_reg_idx++)
1248    {
1249        // Only add it to the dependency graph if it's not ready.
1250        if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1251            PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1252
1253            // Check the IQ's scoreboard to make sure the register
1254            // hasn't become ready while the instruction was in flight
1255            // between stages.  Only if it really isn't ready should
1256            // it be added to the dependency graph.
1257            if (src_reg >= numPhysRegs) {
1258                continue;
1259            } else if (regScoreboard[src_reg] == false) {
1260                DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1261                        "is being added to the dependency chain.\n",
1262                        new_inst->pcState(), src_reg);
1263
1264                dependGraph.insert(src_reg, new_inst);
1265
1266                // Change the return value to indicate that something
1267                // was added to the dependency graph.
1268                return_val = true;
1269            } else {
1270                DPRINTF(IQ, "Instruction PC %s has src reg %i that "
1271                        "became ready before it reached the IQ.\n",
1272                        new_inst->pcState(), src_reg);
1273                // Mark a register ready within the instruction.
1274                new_inst->markSrcRegReady(src_reg_idx);
1275            }
1276        }
1277    }
1278
1279    return return_val;
1280}
1281
1282template <class Impl>
1283void
1284InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1285{
1286    // Nothing really needs to be marked when an instruction becomes
1287    // the producer of a register's value, but for convenience a ptr
1288    // to the producing instruction will be placed in the head node of
1289    // the dependency links.
1290    int8_t total_dest_regs = new_inst->numDestRegs();
1291
1292    for (int dest_reg_idx = 0;
1293         dest_reg_idx < total_dest_regs;
1294         dest_reg_idx++)
1295    {
1296        PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1297
1298        // Instructions that use the misc regs will have a reg number
1299        // higher than the normal physical registers.  In this case these
1300        // registers are not renamed, and there is no need to track
1301        // dependencies as these instructions must be executed at commit.
1302        if (dest_reg >= numPhysRegs) {
1303            continue;
1304        }
1305
1306        if (!dependGraph.empty(dest_reg)) {
1307            dependGraph.dump();
1308            panic("Dependency graph %i not empty!", dest_reg);
1309        }
1310
1311        dependGraph.setInst(dest_reg, new_inst);
1312
1313        // Mark the scoreboard to say it's not yet ready.
1314        regScoreboard[dest_reg] = false;
1315    }
1316}
1317
1318template <class Impl>
1319void
1320InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1321{
1322    // If the instruction now has all of its source registers
1323    // available, then add it to the list of ready instructions.
1324    if (inst->readyToIssue()) {
1325
1326        //Add the instruction to the proper ready list.
1327        if (inst->isMemRef()) {
1328
1329            DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1330
1331            // Message to the mem dependence unit that this instruction has
1332            // its registers ready.
1333            memDepUnit[inst->threadNumber].regsReady(inst);
1334
1335            return;
1336        }
1337
1338        OpClass op_class = inst->opClass();
1339
1340        DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1341                "the ready list, PC %s opclass:%i [sn:%lli].\n",
1342                inst->pcState(), op_class, inst->seqNum);
1343
1344        readyInsts[op_class].push(inst);
1345
1346        // Will need to reorder the list if either a queue is not on the list,
1347        // or it has an older instruction than last time.
1348        if (!queueOnList[op_class]) {
1349            addToOrderList(op_class);
1350        } else if (readyInsts[op_class].top()->seqNum  <
1351                   (*readyIt[op_class]).oldestInst) {
1352            listOrder.erase(readyIt[op_class]);
1353            addToOrderList(op_class);
1354        }
1355    }
1356}
1357
1358template <class Impl>
1359int
1360InstructionQueue<Impl>::countInsts()
1361{
1362#if 0
1363    //ksewell:This works but definitely could use a cleaner write
1364    //with a more intuitive way of counting. Right now it's
1365    //just brute force ....
1366    // Change the #if if you want to use this method.
1367    int total_insts = 0;
1368
1369    for (ThreadID tid = 0; tid < numThreads; ++tid) {
1370        ListIt count_it = instList[tid].begin();
1371
1372        while (count_it != instList[tid].end()) {
1373            if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1374                if (!(*count_it)->isIssued()) {
1375                    ++total_insts;
1376                } else if ((*count_it)->isMemRef() &&
1377                           !(*count_it)->memOpDone) {
1378                    // Loads that have not been marked as executed still count
1379                    // towards the total instructions.
1380                    ++total_insts;
1381                }
1382            }
1383
1384            ++count_it;
1385        }
1386    }
1387
1388    return total_insts;
1389#else
1390    return numEntries - freeEntries;
1391#endif
1392}
1393
1394template <class Impl>
1395void
1396InstructionQueue<Impl>::dumpLists()
1397{
1398    for (int i = 0; i < Num_OpClasses; ++i) {
1399        cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1400
1401        cprintf("\n");
1402    }
1403
1404    cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1405
1406    NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1407    NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1408
1409    cprintf("Non speculative list: ");
1410
1411    while (non_spec_it != non_spec_end_it) {
1412        cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(),
1413                (*non_spec_it).second->seqNum);
1414        ++non_spec_it;
1415    }
1416
1417    cprintf("\n");
1418
1419    ListOrderIt list_order_it = listOrder.begin();
1420    ListOrderIt list_order_end_it = listOrder.end();
1421    int i = 1;
1422
1423    cprintf("List order: ");
1424
1425    while (list_order_it != list_order_end_it) {
1426        cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1427                (*list_order_it).oldestInst);
1428
1429        ++list_order_it;
1430        ++i;
1431    }
1432
1433    cprintf("\n");
1434}
1435
1436
1437template <class Impl>
1438void
1439InstructionQueue<Impl>::dumpInsts()
1440{
1441    for (ThreadID tid = 0; tid < numThreads; ++tid) {
1442        int num = 0;
1443        int valid_num = 0;
1444        ListIt inst_list_it = instList[tid].begin();
1445
1446        while (inst_list_it != instList[tid].end()) {
1447            cprintf("Instruction:%i\n", num);
1448            if (!(*inst_list_it)->isSquashed()) {
1449                if (!(*inst_list_it)->isIssued()) {
1450                    ++valid_num;
1451                    cprintf("Count:%i\n", valid_num);
1452                } else if ((*inst_list_it)->isMemRef() &&
1453                           !(*inst_list_it)->memOpDone) {
1454                    // Loads that have not been marked as executed
1455                    // still count towards the total instructions.
1456                    ++valid_num;
1457                    cprintf("Count:%i\n", valid_num);
1458                }
1459            }
1460
1461            cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1462                    "Issued:%i\nSquashed:%i\n",
1463                    (*inst_list_it)->pcState(),
1464                    (*inst_list_it)->seqNum,
1465                    (*inst_list_it)->threadNumber,
1466                    (*inst_list_it)->isIssued(),
1467                    (*inst_list_it)->isSquashed());
1468
1469            if ((*inst_list_it)->isMemRef()) {
1470                cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1471            }
1472
1473            cprintf("\n");
1474
1475            inst_list_it++;
1476            ++num;
1477        }
1478    }
1479
1480    cprintf("Insts to Execute list:\n");
1481
1482    int num = 0;
1483    int valid_num = 0;
1484    ListIt inst_list_it = instsToExecute.begin();
1485
1486    while (inst_list_it != instsToExecute.end())
1487    {
1488        cprintf("Instruction:%i\n",
1489                num);
1490        if (!(*inst_list_it)->isSquashed()) {
1491            if (!(*inst_list_it)->isIssued()) {
1492                ++valid_num;
1493                cprintf("Count:%i\n", valid_num);
1494            } else if ((*inst_list_it)->isMemRef() &&
1495                       !(*inst_list_it)->memOpDone) {
1496                // Loads that have not been marked as executed
1497                // still count towards the total instructions.
1498                ++valid_num;
1499                cprintf("Count:%i\n", valid_num);
1500            }
1501        }
1502
1503        cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1504                "Issued:%i\nSquashed:%i\n",
1505                (*inst_list_it)->pcState(),
1506                (*inst_list_it)->seqNum,
1507                (*inst_list_it)->threadNumber,
1508                (*inst_list_it)->isIssued(),
1509                (*inst_list_it)->isSquashed());
1510
1511        if ((*inst_list_it)->isMemRef()) {
1512            cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1513        }
1514
1515        cprintf("\n");
1516
1517        inst_list_it++;
1518        ++num;
1519    }
1520}
1521