inst_queue_impl.hh revision 7897
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 * Korey Sewell 30 */ 31 32#include <limits> 33#include <vector> 34 35#include "cpu/o3/fu_pool.hh" 36#include "cpu/o3/inst_queue.hh" 37#include "enums/OpClass.hh" 38#include "params/DerivO3CPU.hh" 39#include "sim/core.hh" 40 41using namespace std; 42 43template <class Impl> 44InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 45 int fu_idx, InstructionQueue<Impl> *iq_ptr) 46 : Event(Stat_Event_Pri), inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), 47 freeFU(false) 48{ 49 this->setFlags(Event::AutoDelete); 50} 51 52template <class Impl> 53void 54InstructionQueue<Impl>::FUCompletion::process() 55{ 56 iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 57 inst = NULL; 58} 59 60 61template <class Impl> 62const char * 63InstructionQueue<Impl>::FUCompletion::description() const 64{ 65 return "Functional unit completion"; 66} 67 68template <class Impl> 69InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 70 DerivO3CPUParams *params) 71 : cpu(cpu_ptr), 72 iewStage(iew_ptr), 73 fuPool(params->fuPool), 74 numEntries(params->numIQEntries), 75 totalWidth(params->issueWidth), 76 numPhysIntRegs(params->numPhysIntRegs), 77 numPhysFloatRegs(params->numPhysFloatRegs), 78 commitToIEWDelay(params->commitToIEWDelay) 79{ 80 assert(fuPool); 81 82 switchedOut = false; 83 84 numThreads = params->numThreads; 85 86 // Set the number of physical registers as the number of int + float 87 numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 88 89 //Create an entry for each physical register within the 90 //dependency graph. 91 dependGraph.resize(numPhysRegs); 92 93 // Resize the register scoreboard. 94 regScoreboard.resize(numPhysRegs); 95 96 //Initialize Mem Dependence Units 97 for (ThreadID tid = 0; tid < numThreads; tid++) { 98 memDepUnit[tid].init(params, tid); 99 memDepUnit[tid].setIQ(this); 100 } 101 102 resetState(); 103 104 std::string policy = params->smtIQPolicy; 105 106 //Convert string to lowercase 107 std::transform(policy.begin(), policy.end(), policy.begin(), 108 (int(*)(int)) tolower); 109 110 //Figure out resource sharing policy 111 if (policy == "dynamic") { 112 iqPolicy = Dynamic; 113 114 //Set Max Entries to Total ROB Capacity 115 for (ThreadID tid = 0; tid < numThreads; tid++) { 116 maxEntries[tid] = numEntries; 117 } 118 119 } else if (policy == "partitioned") { 120 iqPolicy = Partitioned; 121 122 //@todo:make work if part_amt doesnt divide evenly. 123 int part_amt = numEntries / numThreads; 124 125 //Divide ROB up evenly 126 for (ThreadID tid = 0; tid < numThreads; tid++) { 127 maxEntries[tid] = part_amt; 128 } 129 130 DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 131 "%i entries per thread.\n",part_amt); 132 } else if (policy == "threshold") { 133 iqPolicy = Threshold; 134 135 double threshold = (double)params->smtIQThreshold / 100; 136 137 int thresholdIQ = (int)((double)threshold * numEntries); 138 139 //Divide up by threshold amount 140 for (ThreadID tid = 0; tid < numThreads; tid++) { 141 maxEntries[tid] = thresholdIQ; 142 } 143 144 DPRINTF(IQ, "IQ sharing policy set to Threshold:" 145 "%i entries per thread.\n",thresholdIQ); 146 } else { 147 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 148 "Partitioned, Threshold}"); 149 } 150} 151 152template <class Impl> 153InstructionQueue<Impl>::~InstructionQueue() 154{ 155 dependGraph.reset(); 156#ifdef DEBUG 157 cprintf("Nodes traversed: %i, removed: %i\n", 158 dependGraph.nodesTraversed, dependGraph.nodesRemoved); 159#endif 160} 161 162template <class Impl> 163std::string 164InstructionQueue<Impl>::name() const 165{ 166 return cpu->name() + ".iq"; 167} 168 169template <class Impl> 170void 171InstructionQueue<Impl>::regStats() 172{ 173 using namespace Stats; 174 iqInstsAdded 175 .name(name() + ".iqInstsAdded") 176 .desc("Number of instructions added to the IQ (excludes non-spec)") 177 .prereq(iqInstsAdded); 178 179 iqNonSpecInstsAdded 180 .name(name() + ".iqNonSpecInstsAdded") 181 .desc("Number of non-speculative instructions added to the IQ") 182 .prereq(iqNonSpecInstsAdded); 183 184 iqInstsIssued 185 .name(name() + ".iqInstsIssued") 186 .desc("Number of instructions issued") 187 .prereq(iqInstsIssued); 188 189 iqIntInstsIssued 190 .name(name() + ".iqIntInstsIssued") 191 .desc("Number of integer instructions issued") 192 .prereq(iqIntInstsIssued); 193 194 iqFloatInstsIssued 195 .name(name() + ".iqFloatInstsIssued") 196 .desc("Number of float instructions issued") 197 .prereq(iqFloatInstsIssued); 198 199 iqBranchInstsIssued 200 .name(name() + ".iqBranchInstsIssued") 201 .desc("Number of branch instructions issued") 202 .prereq(iqBranchInstsIssued); 203 204 iqMemInstsIssued 205 .name(name() + ".iqMemInstsIssued") 206 .desc("Number of memory instructions issued") 207 .prereq(iqMemInstsIssued); 208 209 iqMiscInstsIssued 210 .name(name() + ".iqMiscInstsIssued") 211 .desc("Number of miscellaneous instructions issued") 212 .prereq(iqMiscInstsIssued); 213 214 iqSquashedInstsIssued 215 .name(name() + ".iqSquashedInstsIssued") 216 .desc("Number of squashed instructions issued") 217 .prereq(iqSquashedInstsIssued); 218 219 iqSquashedInstsExamined 220 .name(name() + ".iqSquashedInstsExamined") 221 .desc("Number of squashed instructions iterated over during squash;" 222 " mainly for profiling") 223 .prereq(iqSquashedInstsExamined); 224 225 iqSquashedOperandsExamined 226 .name(name() + ".iqSquashedOperandsExamined") 227 .desc("Number of squashed operands that are examined and possibly " 228 "removed from graph") 229 .prereq(iqSquashedOperandsExamined); 230 231 iqSquashedNonSpecRemoved 232 .name(name() + ".iqSquashedNonSpecRemoved") 233 .desc("Number of squashed non-spec instructions that were removed") 234 .prereq(iqSquashedNonSpecRemoved); 235/* 236 queueResDist 237 .init(Num_OpClasses, 0, 99, 2) 238 .name(name() + ".IQ:residence:") 239 .desc("cycles from dispatch to issue") 240 .flags(total | pdf | cdf ) 241 ; 242 for (int i = 0; i < Num_OpClasses; ++i) { 243 queueResDist.subname(i, opClassStrings[i]); 244 } 245*/ 246 numIssuedDist 247 .init(0,totalWidth,1) 248 .name(name() + ".ISSUE:issued_per_cycle") 249 .desc("Number of insts issued each cycle") 250 .flags(pdf) 251 ; 252/* 253 dist_unissued 254 .init(Num_OpClasses+2) 255 .name(name() + ".ISSUE:unissued_cause") 256 .desc("Reason ready instruction not issued") 257 .flags(pdf | dist) 258 ; 259 for (int i=0; i < (Num_OpClasses + 2); ++i) { 260 dist_unissued.subname(i, unissued_names[i]); 261 } 262*/ 263 statIssuedInstType 264 .init(numThreads,Enums::Num_OpClass) 265 .name(name() + ".ISSUE:FU_type") 266 .desc("Type of FU issued") 267 .flags(total | pdf | dist) 268 ; 269 statIssuedInstType.ysubnames(Enums::OpClassStrings); 270 271 // 272 // How long did instructions for a particular FU type wait prior to issue 273 // 274/* 275 issueDelayDist 276 .init(Num_OpClasses,0,99,2) 277 .name(name() + ".ISSUE:") 278 .desc("cycles from operands ready to issue") 279 .flags(pdf | cdf) 280 ; 281 282 for (int i=0; i<Num_OpClasses; ++i) { 283 std::stringstream subname; 284 subname << opClassStrings[i] << "_delay"; 285 issueDelayDist.subname(i, subname.str()); 286 } 287*/ 288 issueRate 289 .name(name() + ".ISSUE:rate") 290 .desc("Inst issue rate") 291 .flags(total) 292 ; 293 issueRate = iqInstsIssued / cpu->numCycles; 294 295 statFuBusy 296 .init(Num_OpClasses) 297 .name(name() + ".ISSUE:fu_full") 298 .desc("attempts to use FU when none available") 299 .flags(pdf | dist) 300 ; 301 for (int i=0; i < Num_OpClasses; ++i) { 302 statFuBusy.subname(i, Enums::OpClassStrings[i]); 303 } 304 305 fuBusy 306 .init(numThreads) 307 .name(name() + ".ISSUE:fu_busy_cnt") 308 .desc("FU busy when requested") 309 .flags(total) 310 ; 311 312 fuBusyRate 313 .name(name() + ".ISSUE:fu_busy_rate") 314 .desc("FU busy rate (busy events/executed inst)") 315 .flags(total) 316 ; 317 fuBusyRate = fuBusy / iqInstsIssued; 318 319 for (ThreadID tid = 0; tid < numThreads; tid++) { 320 // Tell mem dependence unit to reg stats as well. 321 memDepUnit[tid].regStats(); 322 } 323 324 intInstQueueReads 325 .name(name() + ".int_inst_queue_reads") 326 .desc("Number of integer instruction queue reads") 327 .flags(total); 328 329 intInstQueueWrites 330 .name(name() + ".int_inst_queue_writes") 331 .desc("Number of integer instruction queue writes") 332 .flags(total); 333 334 intInstQueueWakeupAccesses 335 .name(name() + ".int_inst_queue_wakeup_accesses") 336 .desc("Number of integer instruction queue wakeup accesses") 337 .flags(total); 338 339 fpInstQueueReads 340 .name(name() + ".fp_inst_queue_reads") 341 .desc("Number of floating instruction queue reads") 342 .flags(total); 343 344 fpInstQueueWrites 345 .name(name() + ".fp_inst_queue_writes") 346 .desc("Number of floating instruction queue writes") 347 .flags(total); 348 349 fpInstQueueWakeupQccesses 350 .name(name() + ".fp_inst_queue_wakeup_accesses") 351 .desc("Number of floating instruction queue wakeup accesses") 352 .flags(total); 353 354 intAluAccesses 355 .name(name() + ".int_alu_accesses") 356 .desc("Number of integer alu accesses") 357 .flags(total); 358 359 fpAluAccesses 360 .name(name() + ".fp_alu_accesses") 361 .desc("Number of floating point alu accesses") 362 .flags(total); 363 364} 365 366template <class Impl> 367void 368InstructionQueue<Impl>::resetState() 369{ 370 //Initialize thread IQ counts 371 for (ThreadID tid = 0; tid <numThreads; tid++) { 372 count[tid] = 0; 373 instList[tid].clear(); 374 } 375 376 // Initialize the number of free IQ entries. 377 freeEntries = numEntries; 378 379 // Note that in actuality, the registers corresponding to the logical 380 // registers start off as ready. However this doesn't matter for the 381 // IQ as the instruction should have been correctly told if those 382 // registers are ready in rename. Thus it can all be initialized as 383 // unready. 384 for (int i = 0; i < numPhysRegs; ++i) { 385 regScoreboard[i] = false; 386 } 387 388 for (ThreadID tid = 0; tid < numThreads; ++tid) { 389 squashedSeqNum[tid] = 0; 390 } 391 392 for (int i = 0; i < Num_OpClasses; ++i) { 393 while (!readyInsts[i].empty()) 394 readyInsts[i].pop(); 395 queueOnList[i] = false; 396 readyIt[i] = listOrder.end(); 397 } 398 nonSpecInsts.clear(); 399 listOrder.clear(); 400} 401 402template <class Impl> 403void 404InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 405{ 406 activeThreads = at_ptr; 407} 408 409template <class Impl> 410void 411InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 412{ 413 issueToExecuteQueue = i2e_ptr; 414} 415 416template <class Impl> 417void 418InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 419{ 420 timeBuffer = tb_ptr; 421 422 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 423} 424 425template <class Impl> 426void 427InstructionQueue<Impl>::switchOut() 428{ 429/* 430 if (!instList[0].empty() || (numEntries != freeEntries) || 431 !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) { 432 dumpInsts(); 433// assert(0); 434 } 435*/ 436 resetState(); 437 dependGraph.reset(); 438 instsToExecute.clear(); 439 switchedOut = true; 440 for (ThreadID tid = 0; tid < numThreads; ++tid) { 441 memDepUnit[tid].switchOut(); 442 } 443} 444 445template <class Impl> 446void 447InstructionQueue<Impl>::takeOverFrom() 448{ 449 switchedOut = false; 450} 451 452template <class Impl> 453int 454InstructionQueue<Impl>::entryAmount(ThreadID num_threads) 455{ 456 if (iqPolicy == Partitioned) { 457 return numEntries / num_threads; 458 } else { 459 return 0; 460 } 461} 462 463 464template <class Impl> 465void 466InstructionQueue<Impl>::resetEntries() 467{ 468 if (iqPolicy != Dynamic || numThreads > 1) { 469 int active_threads = activeThreads->size(); 470 471 list<ThreadID>::iterator threads = activeThreads->begin(); 472 list<ThreadID>::iterator end = activeThreads->end(); 473 474 while (threads != end) { 475 ThreadID tid = *threads++; 476 477 if (iqPolicy == Partitioned) { 478 maxEntries[tid] = numEntries / active_threads; 479 } else if(iqPolicy == Threshold && active_threads == 1) { 480 maxEntries[tid] = numEntries; 481 } 482 } 483 } 484} 485 486template <class Impl> 487unsigned 488InstructionQueue<Impl>::numFreeEntries() 489{ 490 return freeEntries; 491} 492 493template <class Impl> 494unsigned 495InstructionQueue<Impl>::numFreeEntries(ThreadID tid) 496{ 497 return maxEntries[tid] - count[tid]; 498} 499 500// Might want to do something more complex if it knows how many instructions 501// will be issued this cycle. 502template <class Impl> 503bool 504InstructionQueue<Impl>::isFull() 505{ 506 if (freeEntries == 0) { 507 return(true); 508 } else { 509 return(false); 510 } 511} 512 513template <class Impl> 514bool 515InstructionQueue<Impl>::isFull(ThreadID tid) 516{ 517 if (numFreeEntries(tid) == 0) { 518 return(true); 519 } else { 520 return(false); 521 } 522} 523 524template <class Impl> 525bool 526InstructionQueue<Impl>::hasReadyInsts() 527{ 528 if (!listOrder.empty()) { 529 return true; 530 } 531 532 for (int i = 0; i < Num_OpClasses; ++i) { 533 if (!readyInsts[i].empty()) { 534 return true; 535 } 536 } 537 538 return false; 539} 540 541template <class Impl> 542void 543InstructionQueue<Impl>::insert(DynInstPtr &new_inst) 544{ 545 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 546 // Make sure the instruction is valid 547 assert(new_inst); 548 549 DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 550 new_inst->seqNum, new_inst->pcState()); 551 552 assert(freeEntries != 0); 553 554 instList[new_inst->threadNumber].push_back(new_inst); 555 556 --freeEntries; 557 558 new_inst->setInIQ(); 559 560 // Look through its source registers (physical regs), and mark any 561 // dependencies. 562 addToDependents(new_inst); 563 564 // Have this instruction set itself as the producer of its destination 565 // register(s). 566 addToProducers(new_inst); 567 568 if (new_inst->isMemRef()) { 569 memDepUnit[new_inst->threadNumber].insert(new_inst); 570 } else { 571 addIfReady(new_inst); 572 } 573 574 ++iqInstsAdded; 575 576 count[new_inst->threadNumber]++; 577 578 assert(freeEntries == (numEntries - countInsts())); 579} 580 581template <class Impl> 582void 583InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 584{ 585 // @todo: Clean up this code; can do it by setting inst as unable 586 // to issue, then calling normal insert on the inst. 587 new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 588 589 assert(new_inst); 590 591 nonSpecInsts[new_inst->seqNum] = new_inst; 592 593 DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 594 "to the IQ.\n", 595 new_inst->seqNum, new_inst->pcState()); 596 597 assert(freeEntries != 0); 598 599 instList[new_inst->threadNumber].push_back(new_inst); 600 601 --freeEntries; 602 603 new_inst->setInIQ(); 604 605 // Have this instruction set itself as the producer of its destination 606 // register(s). 607 addToProducers(new_inst); 608 609 // If it's a memory instruction, add it to the memory dependency 610 // unit. 611 if (new_inst->isMemRef()) { 612 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 613 } 614 615 ++iqNonSpecInstsAdded; 616 617 count[new_inst->threadNumber]++; 618 619 assert(freeEntries == (numEntries - countInsts())); 620} 621 622template <class Impl> 623void 624InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 625{ 626 memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 627 628 insertNonSpec(barr_inst); 629} 630 631template <class Impl> 632typename Impl::DynInstPtr 633InstructionQueue<Impl>::getInstToExecute() 634{ 635 assert(!instsToExecute.empty()); 636 DynInstPtr inst = instsToExecute.front(); 637 instsToExecute.pop_front(); 638 if (inst->isFloating()){ 639 fpInstQueueReads++; 640 } else { 641 intInstQueueReads++; 642 } 643 return inst; 644} 645 646template <class Impl> 647void 648InstructionQueue<Impl>::addToOrderList(OpClass op_class) 649{ 650 assert(!readyInsts[op_class].empty()); 651 652 ListOrderEntry queue_entry; 653 654 queue_entry.queueType = op_class; 655 656 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 657 658 ListOrderIt list_it = listOrder.begin(); 659 ListOrderIt list_end_it = listOrder.end(); 660 661 while (list_it != list_end_it) { 662 if ((*list_it).oldestInst > queue_entry.oldestInst) { 663 break; 664 } 665 666 list_it++; 667 } 668 669 readyIt[op_class] = listOrder.insert(list_it, queue_entry); 670 queueOnList[op_class] = true; 671} 672 673template <class Impl> 674void 675InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 676{ 677 // Get iterator of next item on the list 678 // Delete the original iterator 679 // Determine if the next item is either the end of the list or younger 680 // than the new instruction. If so, then add in a new iterator right here. 681 // If not, then move along. 682 ListOrderEntry queue_entry; 683 OpClass op_class = (*list_order_it).queueType; 684 ListOrderIt next_it = list_order_it; 685 686 ++next_it; 687 688 queue_entry.queueType = op_class; 689 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 690 691 while (next_it != listOrder.end() && 692 (*next_it).oldestInst < queue_entry.oldestInst) { 693 ++next_it; 694 } 695 696 readyIt[op_class] = listOrder.insert(next_it, queue_entry); 697} 698 699template <class Impl> 700void 701InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 702{ 703 DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 704 // The CPU could have been sleeping until this op completed (*extremely* 705 // long latency op). Wake it if it was. This may be overkill. 706 if (isSwitchedOut()) { 707 DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n", 708 inst->seqNum); 709 return; 710 } 711 712 iewStage->wakeCPU(); 713 714 if (fu_idx > -1) 715 fuPool->freeUnitNextCycle(fu_idx); 716 717 // @todo: Ensure that these FU Completions happen at the beginning 718 // of a cycle, otherwise they could add too many instructions to 719 // the queue. 720 issueToExecuteQueue->access(-1)->size++; 721 instsToExecute.push_back(inst); 722} 723 724// @todo: Figure out a better way to remove the squashed items from the 725// lists. Checking the top item of each list to see if it's squashed 726// wastes time and forces jumps. 727template <class Impl> 728void 729InstructionQueue<Impl>::scheduleReadyInsts() 730{ 731 DPRINTF(IQ, "Attempting to schedule ready instructions from " 732 "the IQ.\n"); 733 734 IssueStruct *i2e_info = issueToExecuteQueue->access(0); 735 736 // Have iterator to head of the list 737 // While I haven't exceeded bandwidth or reached the end of the list, 738 // Try to get a FU that can do what this op needs. 739 // If successful, change the oldestInst to the new top of the list, put 740 // the queue in the proper place in the list. 741 // Increment the iterator. 742 // This will avoid trying to schedule a certain op class if there are no 743 // FUs that handle it. 744 ListOrderIt order_it = listOrder.begin(); 745 ListOrderIt order_end_it = listOrder.end(); 746 int total_issued = 0; 747 748 while (total_issued < totalWidth && 749 iewStage->canIssue() && 750 order_it != order_end_it) { 751 OpClass op_class = (*order_it).queueType; 752 753 assert(!readyInsts[op_class].empty()); 754 755 DynInstPtr issuing_inst = readyInsts[op_class].top(); 756 757 issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 758 759 assert(issuing_inst->seqNum == (*order_it).oldestInst); 760 761 if (issuing_inst->isSquashed()) { 762 readyInsts[op_class].pop(); 763 764 if (!readyInsts[op_class].empty()) { 765 moveToYoungerInst(order_it); 766 } else { 767 readyIt[op_class] = listOrder.end(); 768 queueOnList[op_class] = false; 769 } 770 771 listOrder.erase(order_it++); 772 773 ++iqSquashedInstsIssued; 774 775 continue; 776 } 777 778 int idx = -2; 779 int op_latency = 1; 780 ThreadID tid = issuing_inst->threadNumber; 781 782 if (op_class != No_OpClass) { 783 idx = fuPool->getUnit(op_class); 784 issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 785 if (idx > -1) { 786 op_latency = fuPool->getOpLatency(op_class); 787 } 788 } 789 790 // If we have an instruction that doesn't require a FU, or a 791 // valid FU, then schedule for execution. 792 if (idx == -2 || idx != -1) { 793 if (op_latency == 1) { 794 i2e_info->size++; 795 instsToExecute.push_back(issuing_inst); 796 797 // Add the FU onto the list of FU's to be freed next 798 // cycle if we used one. 799 if (idx >= 0) 800 fuPool->freeUnitNextCycle(idx); 801 } else { 802 int issue_latency = fuPool->getIssueLatency(op_class); 803 // Generate completion event for the FU 804 FUCompletion *execution = new FUCompletion(issuing_inst, 805 idx, this); 806 807 cpu->schedule(execution, curTick() + cpu->ticks(op_latency - 1)); 808 809 // @todo: Enforce that issue_latency == 1 or op_latency 810 if (issue_latency > 1) { 811 // If FU isn't pipelined, then it must be freed 812 // upon the execution completing. 813 execution->setFreeFU(); 814 } else { 815 // Add the FU onto the list of FU's to be freed next cycle. 816 fuPool->freeUnitNextCycle(idx); 817 } 818 } 819 820 DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 821 "[sn:%lli]\n", 822 tid, issuing_inst->pcState(), 823 issuing_inst->seqNum); 824 825 readyInsts[op_class].pop(); 826 827 if (!readyInsts[op_class].empty()) { 828 moveToYoungerInst(order_it); 829 } else { 830 readyIt[op_class] = listOrder.end(); 831 queueOnList[op_class] = false; 832 } 833 834 issuing_inst->setIssued(); 835 ++total_issued; 836 837 if (!issuing_inst->isMemRef()) { 838 // Memory instructions can not be freed from the IQ until they 839 // complete. 840 ++freeEntries; 841 count[tid]--; 842 issuing_inst->clearInIQ(); 843 } else { 844 memDepUnit[tid].issue(issuing_inst); 845 } 846 847 listOrder.erase(order_it++); 848 statIssuedInstType[tid][op_class]++; 849 iewStage->incrWb(issuing_inst->seqNum); 850 } else { 851 statFuBusy[op_class]++; 852 fuBusy[tid]++; 853 ++order_it; 854 } 855 } 856 857 numIssuedDist.sample(total_issued); 858 iqInstsIssued+= total_issued; 859 860 // If we issued any instructions, tell the CPU we had activity. 861 if (total_issued) { 862 cpu->activityThisCycle(); 863 } else { 864 DPRINTF(IQ, "Not able to schedule any instructions.\n"); 865 } 866} 867 868template <class Impl> 869void 870InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 871{ 872 DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 873 "to execute.\n", inst); 874 875 NonSpecMapIt inst_it = nonSpecInsts.find(inst); 876 877 assert(inst_it != nonSpecInsts.end()); 878 879 ThreadID tid = (*inst_it).second->threadNumber; 880 881 (*inst_it).second->setAtCommit(); 882 883 (*inst_it).second->setCanIssue(); 884 885 if (!(*inst_it).second->isMemRef()) { 886 addIfReady((*inst_it).second); 887 } else { 888 memDepUnit[tid].nonSpecInstReady((*inst_it).second); 889 } 890 891 (*inst_it).second = NULL; 892 893 nonSpecInsts.erase(inst_it); 894} 895 896template <class Impl> 897void 898InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 899{ 900 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 901 tid,inst); 902 903 ListIt iq_it = instList[tid].begin(); 904 905 while (iq_it != instList[tid].end() && 906 (*iq_it)->seqNum <= inst) { 907 ++iq_it; 908 instList[tid].pop_front(); 909 } 910 911 assert(freeEntries == (numEntries - countInsts())); 912} 913 914template <class Impl> 915int 916InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 917{ 918 int dependents = 0; 919 920 // The instruction queue here takes care of both floating and int ops 921 if (completed_inst->isFloating()) { 922 fpInstQueueWakeupQccesses++; 923 } else { 924 intInstQueueWakeupAccesses++; 925 } 926 927 DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 928 929 assert(!completed_inst->isSquashed()); 930 931 // Tell the memory dependence unit to wake any dependents on this 932 // instruction if it is a memory instruction. Also complete the memory 933 // instruction at this point since we know it executed without issues. 934 // @todo: Might want to rename "completeMemInst" to something that 935 // indicates that it won't need to be replayed, and call this 936 // earlier. Might not be a big deal. 937 if (completed_inst->isMemRef()) { 938 memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 939 completeMemInst(completed_inst); 940 } else if (completed_inst->isMemBarrier() || 941 completed_inst->isWriteBarrier()) { 942 memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 943 } 944 945 for (int dest_reg_idx = 0; 946 dest_reg_idx < completed_inst->numDestRegs(); 947 dest_reg_idx++) 948 { 949 PhysRegIndex dest_reg = 950 completed_inst->renamedDestRegIdx(dest_reg_idx); 951 952 // Special case of uniq or control registers. They are not 953 // handled by the IQ and thus have no dependency graph entry. 954 // @todo Figure out a cleaner way to handle this. 955 if (dest_reg >= numPhysRegs) { 956 DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 957 numPhysRegs); 958 continue; 959 } 960 961 DPRINTF(IQ, "Waking any dependents on register %i.\n", 962 (int) dest_reg); 963 964 //Go through the dependency chain, marking the registers as 965 //ready within the waiting instructions. 966 DynInstPtr dep_inst = dependGraph.pop(dest_reg); 967 968 while (dep_inst) { 969 DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 970 "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 971 972 // Might want to give more information to the instruction 973 // so that it knows which of its source registers is 974 // ready. However that would mean that the dependency 975 // graph entries would need to hold the src_reg_idx. 976 dep_inst->markSrcRegReady(); 977 978 addIfReady(dep_inst); 979 980 dep_inst = dependGraph.pop(dest_reg); 981 982 ++dependents; 983 } 984 985 // Reset the head node now that all of its dependents have 986 // been woken up. 987 assert(dependGraph.empty(dest_reg)); 988 dependGraph.clearInst(dest_reg); 989 990 // Mark the scoreboard as having that register ready. 991 regScoreboard[dest_reg] = true; 992 } 993 return dependents; 994} 995 996template <class Impl> 997void 998InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 999{ 1000 OpClass op_class = ready_inst->opClass(); 1001 1002 readyInsts[op_class].push(ready_inst); 1003 1004 // Will need to reorder the list if either a queue is not on the list, 1005 // or it has an older instruction than last time. 1006 if (!queueOnList[op_class]) { 1007 addToOrderList(op_class); 1008 } else if (readyInsts[op_class].top()->seqNum < 1009 (*readyIt[op_class]).oldestInst) { 1010 listOrder.erase(readyIt[op_class]); 1011 addToOrderList(op_class); 1012 } 1013 1014 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1015 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1016 ready_inst->pcState(), op_class, ready_inst->seqNum); 1017} 1018 1019template <class Impl> 1020void 1021InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 1022{ 1023 DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 1024 resched_inst->clearCanIssue(); 1025 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 1026} 1027 1028template <class Impl> 1029void 1030InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 1031{ 1032 memDepUnit[replay_inst->threadNumber].replay(replay_inst); 1033} 1034 1035template <class Impl> 1036void 1037InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 1038{ 1039 ThreadID tid = completed_inst->threadNumber; 1040 1041 DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 1042 completed_inst->pcState(), completed_inst->seqNum); 1043 1044 ++freeEntries; 1045 1046 completed_inst->memOpDone = true; 1047 1048 memDepUnit[tid].completed(completed_inst); 1049 count[tid]--; 1050} 1051 1052template <class Impl> 1053void 1054InstructionQueue<Impl>::violation(DynInstPtr &store, 1055 DynInstPtr &faulting_load) 1056{ 1057 intInstQueueWrites++; 1058 memDepUnit[store->threadNumber].violation(store, faulting_load); 1059} 1060 1061template <class Impl> 1062void 1063InstructionQueue<Impl>::squash(ThreadID tid) 1064{ 1065 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 1066 "the IQ.\n", tid); 1067 1068 // Read instruction sequence number of last instruction out of the 1069 // time buffer. 1070 squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 1071 1072 // Call doSquash if there are insts in the IQ 1073 if (count[tid] > 0) { 1074 doSquash(tid); 1075 } 1076 1077 // Also tell the memory dependence unit to squash. 1078 memDepUnit[tid].squash(squashedSeqNum[tid], tid); 1079} 1080 1081template <class Impl> 1082void 1083InstructionQueue<Impl>::doSquash(ThreadID tid) 1084{ 1085 // Start at the tail. 1086 ListIt squash_it = instList[tid].end(); 1087 --squash_it; 1088 1089 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 1090 tid, squashedSeqNum[tid]); 1091 1092 // Squash any instructions younger than the squashed sequence number 1093 // given. 1094 while (squash_it != instList[tid].end() && 1095 (*squash_it)->seqNum > squashedSeqNum[tid]) { 1096 1097 DynInstPtr squashed_inst = (*squash_it); 1098 squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 1099 1100 // Only handle the instruction if it actually is in the IQ and 1101 // hasn't already been squashed in the IQ. 1102 if (squashed_inst->threadNumber != tid || 1103 squashed_inst->isSquashedInIQ()) { 1104 --squash_it; 1105 continue; 1106 } 1107 1108 if (!squashed_inst->isIssued() || 1109 (squashed_inst->isMemRef() && 1110 !squashed_inst->memOpDone)) { 1111 1112 DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 1113 tid, squashed_inst->seqNum, squashed_inst->pcState()); 1114 1115 // Remove the instruction from the dependency list. 1116 if (!squashed_inst->isNonSpeculative() && 1117 !squashed_inst->isStoreConditional() && 1118 !squashed_inst->isMemBarrier() && 1119 !squashed_inst->isWriteBarrier()) { 1120 1121 for (int src_reg_idx = 0; 1122 src_reg_idx < squashed_inst->numSrcRegs(); 1123 src_reg_idx++) 1124 { 1125 PhysRegIndex src_reg = 1126 squashed_inst->renamedSrcRegIdx(src_reg_idx); 1127 1128 // Only remove it from the dependency graph if it 1129 // was placed there in the first place. 1130 1131 // Instead of doing a linked list traversal, we 1132 // can just remove these squashed instructions 1133 // either at issue time, or when the register is 1134 // overwritten. The only downside to this is it 1135 // leaves more room for error. 1136 1137 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 1138 src_reg < numPhysRegs) { 1139 dependGraph.remove(src_reg, squashed_inst); 1140 } 1141 1142 1143 ++iqSquashedOperandsExamined; 1144 } 1145 } else if (!squashed_inst->isStoreConditional() || 1146 !squashed_inst->isCompleted()) { 1147 NonSpecMapIt ns_inst_it = 1148 nonSpecInsts.find(squashed_inst->seqNum); 1149 assert(ns_inst_it != nonSpecInsts.end()); 1150 if (ns_inst_it == nonSpecInsts.end()) { 1151 assert(squashed_inst->getFault() != NoFault); 1152 } else { 1153 1154 (*ns_inst_it).second = NULL; 1155 1156 nonSpecInsts.erase(ns_inst_it); 1157 1158 ++iqSquashedNonSpecRemoved; 1159 } 1160 } 1161 1162 // Might want to also clear out the head of the dependency graph. 1163 1164 // Mark it as squashed within the IQ. 1165 squashed_inst->setSquashedInIQ(); 1166 1167 // @todo: Remove this hack where several statuses are set so the 1168 // inst will flow through the rest of the pipeline. 1169 squashed_inst->setIssued(); 1170 squashed_inst->setCanCommit(); 1171 squashed_inst->clearInIQ(); 1172 1173 //Update Thread IQ Count 1174 count[squashed_inst->threadNumber]--; 1175 1176 ++freeEntries; 1177 } 1178 1179 instList[tid].erase(squash_it--); 1180 ++iqSquashedInstsExamined; 1181 } 1182} 1183 1184template <class Impl> 1185bool 1186InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 1187{ 1188 // Loop through the instruction's source registers, adding 1189 // them to the dependency list if they are not ready. 1190 int8_t total_src_regs = new_inst->numSrcRegs(); 1191 bool return_val = false; 1192 1193 for (int src_reg_idx = 0; 1194 src_reg_idx < total_src_regs; 1195 src_reg_idx++) 1196 { 1197 // Only add it to the dependency graph if it's not ready. 1198 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 1199 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 1200 1201 // Check the IQ's scoreboard to make sure the register 1202 // hasn't become ready while the instruction was in flight 1203 // between stages. Only if it really isn't ready should 1204 // it be added to the dependency graph. 1205 if (src_reg >= numPhysRegs) { 1206 continue; 1207 } else if (regScoreboard[src_reg] == false) { 1208 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1209 "is being added to the dependency chain.\n", 1210 new_inst->pcState(), src_reg); 1211 1212 dependGraph.insert(src_reg, new_inst); 1213 1214 // Change the return value to indicate that something 1215 // was added to the dependency graph. 1216 return_val = true; 1217 } else { 1218 DPRINTF(IQ, "Instruction PC %s has src reg %i that " 1219 "became ready before it reached the IQ.\n", 1220 new_inst->pcState(), src_reg); 1221 // Mark a register ready within the instruction. 1222 new_inst->markSrcRegReady(src_reg_idx); 1223 } 1224 } 1225 } 1226 1227 return return_val; 1228} 1229 1230template <class Impl> 1231void 1232InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 1233{ 1234 // Nothing really needs to be marked when an instruction becomes 1235 // the producer of a register's value, but for convenience a ptr 1236 // to the producing instruction will be placed in the head node of 1237 // the dependency links. 1238 int8_t total_dest_regs = new_inst->numDestRegs(); 1239 1240 for (int dest_reg_idx = 0; 1241 dest_reg_idx < total_dest_regs; 1242 dest_reg_idx++) 1243 { 1244 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 1245 1246 // Instructions that use the misc regs will have a reg number 1247 // higher than the normal physical registers. In this case these 1248 // registers are not renamed, and there is no need to track 1249 // dependencies as these instructions must be executed at commit. 1250 if (dest_reg >= numPhysRegs) { 1251 continue; 1252 } 1253 1254 if (!dependGraph.empty(dest_reg)) { 1255 dependGraph.dump(); 1256 panic("Dependency graph %i not empty!", dest_reg); 1257 } 1258 1259 dependGraph.setInst(dest_reg, new_inst); 1260 1261 // Mark the scoreboard to say it's not yet ready. 1262 regScoreboard[dest_reg] = false; 1263 } 1264} 1265 1266template <class Impl> 1267void 1268InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 1269{ 1270 // If the instruction now has all of its source registers 1271 // available, then add it to the list of ready instructions. 1272 if (inst->readyToIssue()) { 1273 1274 //Add the instruction to the proper ready list. 1275 if (inst->isMemRef()) { 1276 1277 DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 1278 1279 // Message to the mem dependence unit that this instruction has 1280 // its registers ready. 1281 memDepUnit[inst->threadNumber].regsReady(inst); 1282 1283 return; 1284 } 1285 1286 OpClass op_class = inst->opClass(); 1287 1288 DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 1289 "the ready list, PC %s opclass:%i [sn:%lli].\n", 1290 inst->pcState(), op_class, inst->seqNum); 1291 1292 readyInsts[op_class].push(inst); 1293 1294 // Will need to reorder the list if either a queue is not on the list, 1295 // or it has an older instruction than last time. 1296 if (!queueOnList[op_class]) { 1297 addToOrderList(op_class); 1298 } else if (readyInsts[op_class].top()->seqNum < 1299 (*readyIt[op_class]).oldestInst) { 1300 listOrder.erase(readyIt[op_class]); 1301 addToOrderList(op_class); 1302 } 1303 } 1304} 1305 1306template <class Impl> 1307int 1308InstructionQueue<Impl>::countInsts() 1309{ 1310#if 0 1311 //ksewell:This works but definitely could use a cleaner write 1312 //with a more intuitive way of counting. Right now it's 1313 //just brute force .... 1314 // Change the #if if you want to use this method. 1315 int total_insts = 0; 1316 1317 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1318 ListIt count_it = instList[tid].begin(); 1319 1320 while (count_it != instList[tid].end()) { 1321 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 1322 if (!(*count_it)->isIssued()) { 1323 ++total_insts; 1324 } else if ((*count_it)->isMemRef() && 1325 !(*count_it)->memOpDone) { 1326 // Loads that have not been marked as executed still count 1327 // towards the total instructions. 1328 ++total_insts; 1329 } 1330 } 1331 1332 ++count_it; 1333 } 1334 } 1335 1336 return total_insts; 1337#else 1338 return numEntries - freeEntries; 1339#endif 1340} 1341 1342template <class Impl> 1343void 1344InstructionQueue<Impl>::dumpLists() 1345{ 1346 for (int i = 0; i < Num_OpClasses; ++i) { 1347 cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 1348 1349 cprintf("\n"); 1350 } 1351 1352 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1353 1354 NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 1355 NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 1356 1357 cprintf("Non speculative list: "); 1358 1359 while (non_spec_it != non_spec_end_it) { 1360 cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 1361 (*non_spec_it).second->seqNum); 1362 ++non_spec_it; 1363 } 1364 1365 cprintf("\n"); 1366 1367 ListOrderIt list_order_it = listOrder.begin(); 1368 ListOrderIt list_order_end_it = listOrder.end(); 1369 int i = 1; 1370 1371 cprintf("List order: "); 1372 1373 while (list_order_it != list_order_end_it) { 1374 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 1375 (*list_order_it).oldestInst); 1376 1377 ++list_order_it; 1378 ++i; 1379 } 1380 1381 cprintf("\n"); 1382} 1383 1384 1385template <class Impl> 1386void 1387InstructionQueue<Impl>::dumpInsts() 1388{ 1389 for (ThreadID tid = 0; tid < numThreads; ++tid) { 1390 int num = 0; 1391 int valid_num = 0; 1392 ListIt inst_list_it = instList[tid].begin(); 1393 1394 while (inst_list_it != instList[tid].end()) { 1395 cprintf("Instruction:%i\n", num); 1396 if (!(*inst_list_it)->isSquashed()) { 1397 if (!(*inst_list_it)->isIssued()) { 1398 ++valid_num; 1399 cprintf("Count:%i\n", valid_num); 1400 } else if ((*inst_list_it)->isMemRef() && 1401 !(*inst_list_it)->memOpDone) { 1402 // Loads that have not been marked as executed 1403 // still count towards the total instructions. 1404 ++valid_num; 1405 cprintf("Count:%i\n", valid_num); 1406 } 1407 } 1408 1409 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1410 "Issued:%i\nSquashed:%i\n", 1411 (*inst_list_it)->pcState(), 1412 (*inst_list_it)->seqNum, 1413 (*inst_list_it)->threadNumber, 1414 (*inst_list_it)->isIssued(), 1415 (*inst_list_it)->isSquashed()); 1416 1417 if ((*inst_list_it)->isMemRef()) { 1418 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1419 } 1420 1421 cprintf("\n"); 1422 1423 inst_list_it++; 1424 ++num; 1425 } 1426 } 1427 1428 cprintf("Insts to Execute list:\n"); 1429 1430 int num = 0; 1431 int valid_num = 0; 1432 ListIt inst_list_it = instsToExecute.begin(); 1433 1434 while (inst_list_it != instsToExecute.end()) 1435 { 1436 cprintf("Instruction:%i\n", 1437 num); 1438 if (!(*inst_list_it)->isSquashed()) { 1439 if (!(*inst_list_it)->isIssued()) { 1440 ++valid_num; 1441 cprintf("Count:%i\n", valid_num); 1442 } else if ((*inst_list_it)->isMemRef() && 1443 !(*inst_list_it)->memOpDone) { 1444 // Loads that have not been marked as executed 1445 // still count towards the total instructions. 1446 ++valid_num; 1447 cprintf("Count:%i\n", valid_num); 1448 } 1449 } 1450 1451 cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 1452 "Issued:%i\nSquashed:%i\n", 1453 (*inst_list_it)->pcState(), 1454 (*inst_list_it)->seqNum, 1455 (*inst_list_it)->threadNumber, 1456 (*inst_list_it)->isIssued(), 1457 (*inst_list_it)->isSquashed()); 1458 1459 if ((*inst_list_it)->isMemRef()) { 1460 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 1461 } 1462 1463 cprintf("\n"); 1464 1465 inst_list_it++; 1466 ++num; 1467 } 1468} 1469