inst_queue_impl.hh revision 2980:eab855f06b79
110037SARM gem5 Developers/*
210844Sandreas.sandberg@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan
310037SARM gem5 Developers * All rights reserved.
410037SARM gem5 Developers *
510037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without
610037SARM gem5 Developers * modification, are permitted provided that the following conditions are
710037SARM gem5 Developers * met: redistributions of source code must retain the above copyright
810037SARM gem5 Developers * notice, this list of conditions and the following disclaimer;
910037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright
1010037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the
1110037SARM gem5 Developers * documentation and/or other materials provided with the distribution;
1210037SARM gem5 Developers * neither the name of the copyright holders nor the names of its
1310037SARM gem5 Developers * contributors may be used to endorse or promote products derived from
1410037SARM gem5 Developers * this software without specific prior written permission.
1510037SARM gem5 Developers *
1610037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
1710037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
1810037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
1910037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
2010037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
2110037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
2210037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
2310037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
2410037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2510037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
2610037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2710037SARM gem5 Developers *
2810037SARM gem5 Developers * Authors: Kevin Lim
2910037SARM gem5 Developers *          Korey Sewell
3010037SARM gem5 Developers */
3110037SARM gem5 Developers
3210037SARM gem5 Developers#include <limits>
3310037SARM gem5 Developers#include <vector>
3410037SARM gem5 Developers
3510037SARM gem5 Developers#include "sim/root.hh"
3610037SARM gem5 Developers
3710037SARM gem5 Developers#include "cpu/o3/fu_pool.hh"
3810844Sandreas.sandberg@arm.com#include "cpu/o3/inst_queue.hh"
3910037SARM gem5 Developers
4010037SARM gem5 Developerstemplate <class Impl>
4110037SARM gem5 DevelopersInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
4210037SARM gem5 Developers                                                   int fu_idx,
4310037SARM gem5 Developers                                                   InstructionQueue<Impl> *iq_ptr)
4410844Sandreas.sandberg@arm.com    : Event(&mainEventQueue, Stat_Event_Pri),
4510037SARM gem5 Developers      inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
4610844Sandreas.sandberg@arm.com{
4710037SARM gem5 Developers    this->setFlags(Event::AutoDelete);
4810037SARM gem5 Developers}
4910037SARM gem5 Developers
5010037SARM gem5 Developerstemplate <class Impl>
5110037SARM gem5 Developersvoid
5210037SARM gem5 DevelopersInstructionQueue<Impl>::FUCompletion::process()
5310037SARM gem5 Developers{
5410037SARM gem5 Developers    iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
5510037SARM gem5 Developers    inst = NULL;
5610844Sandreas.sandberg@arm.com}
5710847Sandreas.sandberg@arm.com
5810037SARM gem5 Developers
5910844Sandreas.sandberg@arm.comtemplate <class Impl>
6010844Sandreas.sandberg@arm.comconst char *
6110905Sandreas.sandberg@arm.comInstructionQueue<Impl>::FUCompletion::description()
6210844Sandreas.sandberg@arm.com{
6310844Sandreas.sandberg@arm.com    return "Functional unit completion event";
6410844Sandreas.sandberg@arm.com}
6510844Sandreas.sandberg@arm.com
6610844Sandreas.sandberg@arm.comtemplate <class Impl>
6710844Sandreas.sandberg@arm.comInstructionQueue<Impl>::InstructionQueue(Params *params)
6810844Sandreas.sandberg@arm.com    : fuPool(params->fuPool),
6910844Sandreas.sandberg@arm.com      numEntries(params->numIQEntries),
7010844Sandreas.sandberg@arm.com      totalWidth(params->issueWidth),
7110844Sandreas.sandberg@arm.com      numPhysIntRegs(params->numPhysIntRegs),
7210844Sandreas.sandberg@arm.com      numPhysFloatRegs(params->numPhysFloatRegs),
7310844Sandreas.sandberg@arm.com      commitToIEWDelay(params->commitToIEWDelay)
7410844Sandreas.sandberg@arm.com{
7510844Sandreas.sandberg@arm.com    assert(fuPool);
7610844Sandreas.sandberg@arm.com
7710844Sandreas.sandberg@arm.com    switchedOut = false;
7810844Sandreas.sandberg@arm.com
7910844Sandreas.sandberg@arm.com    numThreads = params->numberOfThreads;
8010844Sandreas.sandberg@arm.com
8110844Sandreas.sandberg@arm.com    // Set the number of physical registers as the number of int + float
8210844Sandreas.sandberg@arm.com    numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
8310844Sandreas.sandberg@arm.com
8410844Sandreas.sandberg@arm.com    DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs);
8510844Sandreas.sandberg@arm.com
8610844Sandreas.sandberg@arm.com    //Create an entry for each physical register within the
8710844Sandreas.sandberg@arm.com    //dependency graph.
8810844Sandreas.sandberg@arm.com    dependGraph.resize(numPhysRegs);
8910844Sandreas.sandberg@arm.com
9010844Sandreas.sandberg@arm.com    // Resize the register scoreboard.
9110844Sandreas.sandberg@arm.com    regScoreboard.resize(numPhysRegs);
9210844Sandreas.sandberg@arm.com
9310844Sandreas.sandberg@arm.com    //Initialize Mem Dependence Units
9410844Sandreas.sandberg@arm.com    for (int i = 0; i < numThreads; i++) {
9510844Sandreas.sandberg@arm.com        memDepUnit[i].init(params,i);
9610905Sandreas.sandberg@arm.com        memDepUnit[i].setIQ(this);
9710905Sandreas.sandberg@arm.com    }
9810844Sandreas.sandberg@arm.com
9910844Sandreas.sandberg@arm.com    resetState();
10010844Sandreas.sandberg@arm.com
10110844Sandreas.sandberg@arm.com    std::string policy = params->smtIQPolicy;
10210844Sandreas.sandberg@arm.com
10310844Sandreas.sandberg@arm.com    //Convert string to lowercase
10410844Sandreas.sandberg@arm.com    std::transform(policy.begin(), policy.end(), policy.begin(),
10510905Sandreas.sandberg@arm.com                   (int(*)(int)) tolower);
10610844Sandreas.sandberg@arm.com
10710844Sandreas.sandberg@arm.com    //Figure out resource sharing policy
10810844Sandreas.sandberg@arm.com    if (policy == "dynamic") {
10910844Sandreas.sandberg@arm.com        iqPolicy = Dynamic;
11010844Sandreas.sandberg@arm.com
11110844Sandreas.sandberg@arm.com        //Set Max Entries to Total ROB Capacity
11210844Sandreas.sandberg@arm.com        for (int i = 0; i < numThreads; i++) {
11310844Sandreas.sandberg@arm.com            maxEntries[i] = numEntries;
11410844Sandreas.sandberg@arm.com        }
11510844Sandreas.sandberg@arm.com
11610844Sandreas.sandberg@arm.com    } else if (policy == "partitioned") {
11710844Sandreas.sandberg@arm.com        iqPolicy = Partitioned;
11810844Sandreas.sandberg@arm.com
11910844Sandreas.sandberg@arm.com        //@todo:make work if part_amt doesnt divide evenly.
12010844Sandreas.sandberg@arm.com        int part_amt = numEntries / numThreads;
12110844Sandreas.sandberg@arm.com
12210844Sandreas.sandberg@arm.com        //Divide ROB up evenly
12310844Sandreas.sandberg@arm.com        for (int i = 0; i < numThreads; i++) {
12410844Sandreas.sandberg@arm.com            maxEntries[i] = part_amt;
12510844Sandreas.sandberg@arm.com        }
12610844Sandreas.sandberg@arm.com
12710844Sandreas.sandberg@arm.com        DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
12810844Sandreas.sandberg@arm.com                "%i entries per thread.\n",part_amt);
12910844Sandreas.sandberg@arm.com
13010844Sandreas.sandberg@arm.com    } else if (policy == "threshold") {
13110844Sandreas.sandberg@arm.com        iqPolicy = Threshold;
13210844Sandreas.sandberg@arm.com
13310844Sandreas.sandberg@arm.com        double threshold =  (double)params->smtIQThreshold / 100;
13410844Sandreas.sandberg@arm.com
13510844Sandreas.sandberg@arm.com        int thresholdIQ = (int)((double)threshold * numEntries);
13610844Sandreas.sandberg@arm.com
13710844Sandreas.sandberg@arm.com        //Divide up by threshold amount
13810844Sandreas.sandberg@arm.com        for (int i = 0; i < numThreads; i++) {
13910844Sandreas.sandberg@arm.com            maxEntries[i] = thresholdIQ;
14010844Sandreas.sandberg@arm.com        }
14110844Sandreas.sandberg@arm.com
14210844Sandreas.sandberg@arm.com        DPRINTF(IQ, "IQ sharing policy set to Threshold:"
14310844Sandreas.sandberg@arm.com                "%i entries per thread.\n",thresholdIQ);
14410844Sandreas.sandberg@arm.com   } else {
14510844Sandreas.sandberg@arm.com       assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
14610844Sandreas.sandberg@arm.com              "Partitioned, Threshold}");
14710844Sandreas.sandberg@arm.com   }
14810844Sandreas.sandberg@arm.com}
14910845Sandreas.sandberg@arm.com
15010845Sandreas.sandberg@arm.comtemplate <class Impl>
15110844Sandreas.sandberg@arm.comInstructionQueue<Impl>::~InstructionQueue()
15210844Sandreas.sandberg@arm.com{
15310844Sandreas.sandberg@arm.com    dependGraph.reset();
15410844Sandreas.sandberg@arm.com#ifdef DEBUG
15510844Sandreas.sandberg@arm.com    cprintf("Nodes traversed: %i, removed: %i\n",
15610844Sandreas.sandberg@arm.com            dependGraph.nodesTraversed, dependGraph.nodesRemoved);
15710844Sandreas.sandberg@arm.com#endif
15810844Sandreas.sandberg@arm.com}
15910844Sandreas.sandberg@arm.com
16010844Sandreas.sandberg@arm.comtemplate <class Impl>
16110844Sandreas.sandberg@arm.comstd::string
16210844Sandreas.sandberg@arm.comInstructionQueue<Impl>::name() const
16310844Sandreas.sandberg@arm.com{
16410844Sandreas.sandberg@arm.com    return cpu->name() + ".iq";
16510844Sandreas.sandberg@arm.com}
16610844Sandreas.sandberg@arm.com
16710844Sandreas.sandberg@arm.comtemplate <class Impl>
16810844Sandreas.sandberg@arm.comvoid
16910844Sandreas.sandberg@arm.comInstructionQueue<Impl>::regStats()
17010844Sandreas.sandberg@arm.com{
17110844Sandreas.sandberg@arm.com    using namespace Stats;
17210844Sandreas.sandberg@arm.com    iqInstsAdded
17310844Sandreas.sandberg@arm.com        .name(name() + ".iqInstsAdded")
17410844Sandreas.sandberg@arm.com        .desc("Number of instructions added to the IQ (excludes non-spec)")
17510844Sandreas.sandberg@arm.com        .prereq(iqInstsAdded);
17610844Sandreas.sandberg@arm.com
17710844Sandreas.sandberg@arm.com    iqNonSpecInstsAdded
17810844Sandreas.sandberg@arm.com        .name(name() + ".iqNonSpecInstsAdded")
17910844Sandreas.sandberg@arm.com        .desc("Number of non-speculative instructions added to the IQ")
18010844Sandreas.sandberg@arm.com        .prereq(iqNonSpecInstsAdded);
18110844Sandreas.sandberg@arm.com
18210844Sandreas.sandberg@arm.com    iqInstsIssued
18310844Sandreas.sandberg@arm.com        .name(name() + ".iqInstsIssued")
18410844Sandreas.sandberg@arm.com        .desc("Number of instructions issued")
18510844Sandreas.sandberg@arm.com        .prereq(iqInstsIssued);
18610845Sandreas.sandberg@arm.com
18710845Sandreas.sandberg@arm.com    iqIntInstsIssued
18810845Sandreas.sandberg@arm.com        .name(name() + ".iqIntInstsIssued")
18910844Sandreas.sandberg@arm.com        .desc("Number of integer instructions issued")
19010844Sandreas.sandberg@arm.com        .prereq(iqIntInstsIssued);
19110844Sandreas.sandberg@arm.com
19210905Sandreas.sandberg@arm.com    iqFloatInstsIssued
19310905Sandreas.sandberg@arm.com        .name(name() + ".iqFloatInstsIssued")
19410844Sandreas.sandberg@arm.com        .desc("Number of float instructions issued")
19510844Sandreas.sandberg@arm.com        .prereq(iqFloatInstsIssued);
19610844Sandreas.sandberg@arm.com
19710844Sandreas.sandberg@arm.com    iqBranchInstsIssued
19810844Sandreas.sandberg@arm.com        .name(name() + ".iqBranchInstsIssued")
19910844Sandreas.sandberg@arm.com        .desc("Number of branch instructions issued")
20010037SARM gem5 Developers        .prereq(iqBranchInstsIssued);
20110037SARM gem5 Developers
20210037SARM gem5 Developers    iqMemInstsIssued
20310844Sandreas.sandberg@arm.com        .name(name() + ".iqMemInstsIssued")
20410037SARM gem5 Developers        .desc("Number of memory instructions issued")
20510905Sandreas.sandberg@arm.com        .prereq(iqMemInstsIssued);
20610905Sandreas.sandberg@arm.com
20710037SARM gem5 Developers    iqMiscInstsIssued
20810844Sandreas.sandberg@arm.com        .name(name() + ".iqMiscInstsIssued")
20910844Sandreas.sandberg@arm.com        .desc("Number of miscellaneous instructions issued")
21010844Sandreas.sandberg@arm.com        .prereq(iqMiscInstsIssued);
21110037SARM gem5 Developers
21210844Sandreas.sandberg@arm.com    iqSquashedInstsIssued
21310844Sandreas.sandberg@arm.com        .name(name() + ".iqSquashedInstsIssued")
21410844Sandreas.sandberg@arm.com        .desc("Number of squashed instructions issued")
21510845Sandreas.sandberg@arm.com        .prereq(iqSquashedInstsIssued);
21610844Sandreas.sandberg@arm.com
21710845Sandreas.sandberg@arm.com    iqSquashedInstsExamined
21810844Sandreas.sandberg@arm.com        .name(name() + ".iqSquashedInstsExamined")
21910844Sandreas.sandberg@arm.com        .desc("Number of squashed instructions iterated over during squash;"
22010844Sandreas.sandberg@arm.com              " mainly for profiling")
22110844Sandreas.sandberg@arm.com        .prereq(iqSquashedInstsExamined);
22210845Sandreas.sandberg@arm.com
22310845Sandreas.sandberg@arm.com    iqSquashedOperandsExamined
22410845Sandreas.sandberg@arm.com        .name(name() + ".iqSquashedOperandsExamined")
22510845Sandreas.sandberg@arm.com        .desc("Number of squashed operands that are examined and possibly "
22610844Sandreas.sandberg@arm.com              "removed from graph")
22710037SARM gem5 Developers        .prereq(iqSquashedOperandsExamined);
22810844Sandreas.sandberg@arm.com
22910845Sandreas.sandberg@arm.com    iqSquashedNonSpecRemoved
23010845Sandreas.sandberg@arm.com        .name(name() + ".iqSquashedNonSpecRemoved")
23110844Sandreas.sandberg@arm.com        .desc("Number of squashed non-spec instructions that were removed")
23210845Sandreas.sandberg@arm.com        .prereq(iqSquashedNonSpecRemoved);
23310037SARM gem5 Developers
23410844Sandreas.sandberg@arm.com    queueResDist
23510844Sandreas.sandberg@arm.com        .init(Num_OpClasses, 0, 99, 2)
23610844Sandreas.sandberg@arm.com        .name(name() + ".IQ:residence:")
23710037SARM gem5 Developers        .desc("cycles from dispatch to issue")
23810037SARM gem5 Developers        .flags(total | pdf | cdf )
23910844Sandreas.sandberg@arm.com        ;
24010844Sandreas.sandberg@arm.com    for (int i = 0; i < Num_OpClasses; ++i) {
24110037SARM gem5 Developers        queueResDist.subname(i, opClassStrings[i]);
24210844Sandreas.sandberg@arm.com    }
24310844Sandreas.sandberg@arm.com    numIssuedDist
24410037SARM gem5 Developers        .init(0,totalWidth,1)
24510844Sandreas.sandberg@arm.com        .name(name() + ".ISSUE:issued_per_cycle")
24610844Sandreas.sandberg@arm.com        .desc("Number of insts issued each cycle")
24710037SARM gem5 Developers        .flags(pdf)
24810844Sandreas.sandberg@arm.com        ;
24910844Sandreas.sandberg@arm.com/*
25010844Sandreas.sandberg@arm.com    dist_unissued
25110037SARM gem5 Developers        .init(Num_OpClasses+2)
25210844Sandreas.sandberg@arm.com        .name(name() + ".ISSUE:unissued_cause")
25310844Sandreas.sandberg@arm.com        .desc("Reason ready instruction not issued")
25410845Sandreas.sandberg@arm.com        .flags(pdf | dist)
25510845Sandreas.sandberg@arm.com        ;
25610845Sandreas.sandberg@arm.com    for (int i=0; i < (Num_OpClasses + 2); ++i) {
25710844Sandreas.sandberg@arm.com        dist_unissued.subname(i, unissued_names[i]);
25810037SARM gem5 Developers    }
25910844Sandreas.sandberg@arm.com*/
26010844Sandreas.sandberg@arm.com    statIssuedInstType
26110844Sandreas.sandberg@arm.com        .init(numThreads,Num_OpClasses)
26210844Sandreas.sandberg@arm.com        .name(name() + ".ISSUE:FU_type")
26310844Sandreas.sandberg@arm.com        .desc("Type of FU issued")
26410037SARM gem5 Developers        .flags(total | pdf | dist)
26510844Sandreas.sandberg@arm.com        ;
26610844Sandreas.sandberg@arm.com    statIssuedInstType.ysubnames(opClassStrings);
26710844Sandreas.sandberg@arm.com
26810844Sandreas.sandberg@arm.com    //
26910844Sandreas.sandberg@arm.com    //  How long did instructions for a particular FU type wait prior to issue
27010844Sandreas.sandberg@arm.com    //
27110037SARM gem5 Developers
27210037SARM gem5 Developers    issueDelayDist
27310844Sandreas.sandberg@arm.com        .init(Num_OpClasses,0,99,2)
27410844Sandreas.sandberg@arm.com        .name(name() + ".ISSUE:")
27510037SARM gem5 Developers        .desc("cycles from operands ready to issue")
27610037SARM gem5 Developers        .flags(pdf | cdf)
27710847Sandreas.sandberg@arm.com        ;
27810847Sandreas.sandberg@arm.com
27910847Sandreas.sandberg@arm.com    for (int i=0; i<Num_OpClasses; ++i) {
28010847Sandreas.sandberg@arm.com        std::stringstream subname;
28110847Sandreas.sandberg@arm.com        subname << opClassStrings[i] << "_delay";
28210905Sandreas.sandberg@arm.com        issueDelayDist.subname(i, subname.str());
28310905Sandreas.sandberg@arm.com    }
28410847Sandreas.sandberg@arm.com
28510847Sandreas.sandberg@arm.com    issueRate
28610847Sandreas.sandberg@arm.com        .name(name() + ".ISSUE:rate")
28710847Sandreas.sandberg@arm.com        .desc("Inst issue rate")
28810847Sandreas.sandberg@arm.com        .flags(total)
28910847Sandreas.sandberg@arm.com        ;
29010847Sandreas.sandberg@arm.com    issueRate = iqInstsIssued / cpu->numCycles;
29110847Sandreas.sandberg@arm.com
29210847Sandreas.sandberg@arm.com    statFuBusy
29310847Sandreas.sandberg@arm.com        .init(Num_OpClasses)
29410847Sandreas.sandberg@arm.com        .name(name() + ".ISSUE:fu_full")
29510847Sandreas.sandberg@arm.com        .desc("attempts to use FU when none available")
29610847Sandreas.sandberg@arm.com        .flags(pdf | dist)
29710847Sandreas.sandberg@arm.com        ;
29810847Sandreas.sandberg@arm.com    for (int i=0; i < Num_OpClasses; ++i) {
29910847Sandreas.sandberg@arm.com        statFuBusy.subname(i, opClassStrings[i]);
30010847Sandreas.sandberg@arm.com    }
30110847Sandreas.sandberg@arm.com
30210847Sandreas.sandberg@arm.com    fuBusy
30310847Sandreas.sandberg@arm.com        .init(numThreads)
30410847Sandreas.sandberg@arm.com        .name(name() + ".ISSUE:fu_busy_cnt")
30510847Sandreas.sandberg@arm.com        .desc("FU busy when requested")
30610847Sandreas.sandberg@arm.com        .flags(total)
30710847Sandreas.sandberg@arm.com        ;
30810847Sandreas.sandberg@arm.com
30910847Sandreas.sandberg@arm.com    fuBusyRate
31010847Sandreas.sandberg@arm.com        .name(name() + ".ISSUE:fu_busy_rate")
31110847Sandreas.sandberg@arm.com        .desc("FU busy rate (busy events/executed inst)")
31210847Sandreas.sandberg@arm.com        .flags(total)
31310847Sandreas.sandberg@arm.com        ;
31410847Sandreas.sandberg@arm.com    fuBusyRate = fuBusy / iqInstsIssued;
31510847Sandreas.sandberg@arm.com
31610847Sandreas.sandberg@arm.com    for ( int i=0; i < numThreads; i++) {
31710847Sandreas.sandberg@arm.com        // Tell mem dependence unit to reg stats as well.
31810847Sandreas.sandberg@arm.com        memDepUnit[i].regStats();
31910847Sandreas.sandberg@arm.com    }
32010847Sandreas.sandberg@arm.com}
32110847Sandreas.sandberg@arm.com
32210847Sandreas.sandberg@arm.comtemplate <class Impl>
32310847Sandreas.sandberg@arm.comvoid
32410847Sandreas.sandberg@arm.comInstructionQueue<Impl>::resetState()
32510847Sandreas.sandberg@arm.com{
32610847Sandreas.sandberg@arm.com    //Initialize thread IQ counts
32710847Sandreas.sandberg@arm.com    for (int i = 0; i <numThreads; i++) {
32810847Sandreas.sandberg@arm.com        count[i] = 0;
32910847Sandreas.sandberg@arm.com        instList[i].clear();
33010847Sandreas.sandberg@arm.com    }
33110847Sandreas.sandberg@arm.com
33210847Sandreas.sandberg@arm.com    // Initialize the number of free IQ entries.
33310847Sandreas.sandberg@arm.com    freeEntries = numEntries;
33410037SARM gem5 Developers
335    // Note that in actuality, the registers corresponding to the logical
336    // registers start off as ready.  However this doesn't matter for the
337    // IQ as the instruction should have been correctly told if those
338    // registers are ready in rename.  Thus it can all be initialized as
339    // unready.
340    for (int i = 0; i < numPhysRegs; ++i) {
341        regScoreboard[i] = false;
342    }
343
344    for (int i = 0; i < numThreads; ++i) {
345        squashedSeqNum[i] = 0;
346    }
347
348    for (int i = 0; i < Num_OpClasses; ++i) {
349        while (!readyInsts[i].empty())
350            readyInsts[i].pop();
351        queueOnList[i] = false;
352        readyIt[i] = listOrder.end();
353    }
354    nonSpecInsts.clear();
355    listOrder.clear();
356}
357
358template <class Impl>
359void
360InstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr)
361{
362    DPRINTF(IQ, "Setting active threads list pointer.\n");
363    activeThreads = at_ptr;
364}
365
366template <class Impl>
367void
368InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
369{
370    DPRINTF(IQ, "Set the issue to execute queue.\n");
371    issueToExecuteQueue = i2e_ptr;
372}
373
374template <class Impl>
375void
376InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
377{
378    DPRINTF(IQ, "Set the time buffer.\n");
379    timeBuffer = tb_ptr;
380
381    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
382}
383
384template <class Impl>
385void
386InstructionQueue<Impl>::switchOut()
387{
388    resetState();
389    dependGraph.reset();
390    switchedOut = true;
391    for (int i = 0; i < numThreads; ++i) {
392        memDepUnit[i].switchOut();
393    }
394}
395
396template <class Impl>
397void
398InstructionQueue<Impl>::takeOverFrom()
399{
400    switchedOut = false;
401}
402
403template <class Impl>
404int
405InstructionQueue<Impl>::entryAmount(int num_threads)
406{
407    if (iqPolicy == Partitioned) {
408        return numEntries / num_threads;
409    } else {
410        return 0;
411    }
412}
413
414
415template <class Impl>
416void
417InstructionQueue<Impl>::resetEntries()
418{
419    if (iqPolicy != Dynamic || numThreads > 1) {
420        int active_threads = (*activeThreads).size();
421
422        std::list<unsigned>::iterator threads  = (*activeThreads).begin();
423        std::list<unsigned>::iterator list_end = (*activeThreads).end();
424
425        while (threads != list_end) {
426            if (iqPolicy == Partitioned) {
427                maxEntries[*threads++] = numEntries / active_threads;
428            } else if(iqPolicy == Threshold && active_threads == 1) {
429                maxEntries[*threads++] = numEntries;
430            }
431        }
432    }
433}
434
435template <class Impl>
436unsigned
437InstructionQueue<Impl>::numFreeEntries()
438{
439    return freeEntries;
440}
441
442template <class Impl>
443unsigned
444InstructionQueue<Impl>::numFreeEntries(unsigned tid)
445{
446    return maxEntries[tid] - count[tid];
447}
448
449// Might want to do something more complex if it knows how many instructions
450// will be issued this cycle.
451template <class Impl>
452bool
453InstructionQueue<Impl>::isFull()
454{
455    if (freeEntries == 0) {
456        return(true);
457    } else {
458        return(false);
459    }
460}
461
462template <class Impl>
463bool
464InstructionQueue<Impl>::isFull(unsigned tid)
465{
466    if (numFreeEntries(tid) == 0) {
467        return(true);
468    } else {
469        return(false);
470    }
471}
472
473template <class Impl>
474bool
475InstructionQueue<Impl>::hasReadyInsts()
476{
477    if (!listOrder.empty()) {
478        return true;
479    }
480
481    for (int i = 0; i < Num_OpClasses; ++i) {
482        if (!readyInsts[i].empty()) {
483            return true;
484        }
485    }
486
487    return false;
488}
489
490template <class Impl>
491void
492InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
493{
494    // Make sure the instruction is valid
495    assert(new_inst);
496
497    DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n",
498            new_inst->seqNum, new_inst->readPC());
499
500    assert(freeEntries != 0);
501
502    instList[new_inst->threadNumber].push_back(new_inst);
503
504    --freeEntries;
505
506    new_inst->setInIQ();
507
508    // Look through its source registers (physical regs), and mark any
509    // dependencies.
510    addToDependents(new_inst);
511
512    // Have this instruction set itself as the producer of its destination
513    // register(s).
514    addToProducers(new_inst);
515
516    if (new_inst->isMemRef()) {
517        memDepUnit[new_inst->threadNumber].insert(new_inst);
518    } else {
519        addIfReady(new_inst);
520    }
521
522    ++iqInstsAdded;
523
524    count[new_inst->threadNumber]++;
525
526    assert(freeEntries == (numEntries - countInsts()));
527}
528
529template <class Impl>
530void
531InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
532{
533    // @todo: Clean up this code; can do it by setting inst as unable
534    // to issue, then calling normal insert on the inst.
535
536    assert(new_inst);
537
538    nonSpecInsts[new_inst->seqNum] = new_inst;
539
540    DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x "
541            "to the IQ.\n",
542            new_inst->seqNum, new_inst->readPC());
543
544    assert(freeEntries != 0);
545
546    instList[new_inst->threadNumber].push_back(new_inst);
547
548    --freeEntries;
549
550    new_inst->setInIQ();
551
552    // Have this instruction set itself as the producer of its destination
553    // register(s).
554    addToProducers(new_inst);
555
556    // If it's a memory instruction, add it to the memory dependency
557    // unit.
558    if (new_inst->isMemRef()) {
559        memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
560    }
561
562    ++iqNonSpecInstsAdded;
563
564    count[new_inst->threadNumber]++;
565
566    assert(freeEntries == (numEntries - countInsts()));
567}
568
569template <class Impl>
570void
571InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
572{
573    memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
574
575    insertNonSpec(barr_inst);
576}
577
578template <class Impl>
579typename Impl::DynInstPtr
580InstructionQueue<Impl>::getInstToExecute()
581{
582    assert(!instsToExecute.empty());
583    DynInstPtr inst = instsToExecute.front();
584    instsToExecute.pop_front();
585    return inst;
586}
587
588template <class Impl>
589void
590InstructionQueue<Impl>::addToOrderList(OpClass op_class)
591{
592    assert(!readyInsts[op_class].empty());
593
594    ListOrderEntry queue_entry;
595
596    queue_entry.queueType = op_class;
597
598    queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
599
600    ListOrderIt list_it = listOrder.begin();
601    ListOrderIt list_end_it = listOrder.end();
602
603    while (list_it != list_end_it) {
604        if ((*list_it).oldestInst > queue_entry.oldestInst) {
605            break;
606        }
607
608        list_it++;
609    }
610
611    readyIt[op_class] = listOrder.insert(list_it, queue_entry);
612    queueOnList[op_class] = true;
613}
614
615template <class Impl>
616void
617InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
618{
619    // Get iterator of next item on the list
620    // Delete the original iterator
621    // Determine if the next item is either the end of the list or younger
622    // than the new instruction.  If so, then add in a new iterator right here.
623    // If not, then move along.
624    ListOrderEntry queue_entry;
625    OpClass op_class = (*list_order_it).queueType;
626    ListOrderIt next_it = list_order_it;
627
628    ++next_it;
629
630    queue_entry.queueType = op_class;
631    queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
632
633    while (next_it != listOrder.end() &&
634           (*next_it).oldestInst < queue_entry.oldestInst) {
635        ++next_it;
636    }
637
638    readyIt[op_class] = listOrder.insert(next_it, queue_entry);
639}
640
641template <class Impl>
642void
643InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
644{
645    // The CPU could have been sleeping until this op completed (*extremely*
646    // long latency op).  Wake it if it was.  This may be overkill.
647    if (isSwitchedOut()) {
648        return;
649    }
650
651    iewStage->wakeCPU();
652
653    if (fu_idx > -1)
654        fuPool->freeUnitNextCycle(fu_idx);
655
656    // @todo: Ensure that these FU Completions happen at the beginning
657    // of a cycle, otherwise they could add too many instructions to
658    // the queue.
659    issueToExecuteQueue->access(0)->size++;
660    instsToExecute.push_back(inst);
661}
662
663// @todo: Figure out a better way to remove the squashed items from the
664// lists.  Checking the top item of each list to see if it's squashed
665// wastes time and forces jumps.
666template <class Impl>
667void
668InstructionQueue<Impl>::scheduleReadyInsts()
669{
670    DPRINTF(IQ, "Attempting to schedule ready instructions from "
671            "the IQ.\n");
672
673    IssueStruct *i2e_info = issueToExecuteQueue->access(0);
674
675    // Have iterator to head of the list
676    // While I haven't exceeded bandwidth or reached the end of the list,
677    // Try to get a FU that can do what this op needs.
678    // If successful, change the oldestInst to the new top of the list, put
679    // the queue in the proper place in the list.
680    // Increment the iterator.
681    // This will avoid trying to schedule a certain op class if there are no
682    // FUs that handle it.
683    ListOrderIt order_it = listOrder.begin();
684    ListOrderIt order_end_it = listOrder.end();
685    int total_issued = 0;
686
687    while (total_issued < totalWidth &&
688           iewStage->canIssue() &&
689           order_it != order_end_it) {
690        OpClass op_class = (*order_it).queueType;
691
692        assert(!readyInsts[op_class].empty());
693
694        DynInstPtr issuing_inst = readyInsts[op_class].top();
695
696        assert(issuing_inst->seqNum == (*order_it).oldestInst);
697
698        if (issuing_inst->isSquashed()) {
699            readyInsts[op_class].pop();
700
701            if (!readyInsts[op_class].empty()) {
702                moveToYoungerInst(order_it);
703            } else {
704                readyIt[op_class] = listOrder.end();
705                queueOnList[op_class] = false;
706            }
707
708            listOrder.erase(order_it++);
709
710            ++iqSquashedInstsIssued;
711
712            continue;
713        }
714
715        int idx = -2;
716        int op_latency = 1;
717        int tid = issuing_inst->threadNumber;
718
719        if (op_class != No_OpClass) {
720            idx = fuPool->getUnit(op_class);
721
722            if (idx > -1) {
723                op_latency = fuPool->getOpLatency(op_class);
724            }
725        }
726
727        // If we have an instruction that doesn't require a FU, or a
728        // valid FU, then schedule for execution.
729        if (idx == -2 || idx != -1) {
730            if (op_latency == 1) {
731                i2e_info->size++;
732                instsToExecute.push_back(issuing_inst);
733
734                // Add the FU onto the list of FU's to be freed next
735                // cycle if we used one.
736                if (idx >= 0)
737                    fuPool->freeUnitNextCycle(idx);
738            } else {
739                int issue_latency = fuPool->getIssueLatency(op_class);
740                // Generate completion event for the FU
741                FUCompletion *execution = new FUCompletion(issuing_inst,
742                                                           idx, this);
743
744                execution->schedule(curTick + cpu->cycles(issue_latency - 1));
745
746                // @todo: Enforce that issue_latency == 1 or op_latency
747                if (issue_latency > 1) {
748                    // If FU isn't pipelined, then it must be freed
749                    // upon the execution completing.
750                    execution->setFreeFU();
751                } else {
752                    // Add the FU onto the list of FU's to be freed next cycle.
753                    fuPool->freeUnitNextCycle(idx);
754                }
755            }
756
757            DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
758                    "[sn:%lli]\n",
759                    tid, issuing_inst->readPC(),
760                    issuing_inst->seqNum);
761
762            readyInsts[op_class].pop();
763
764            if (!readyInsts[op_class].empty()) {
765                moveToYoungerInst(order_it);
766            } else {
767                readyIt[op_class] = listOrder.end();
768                queueOnList[op_class] = false;
769            }
770
771            issuing_inst->setIssued();
772            ++total_issued;
773
774            if (!issuing_inst->isMemRef()) {
775                // Memory instructions can not be freed from the IQ until they
776                // complete.
777                ++freeEntries;
778                count[tid]--;
779                issuing_inst->clearInIQ();
780            } else {
781                memDepUnit[tid].issue(issuing_inst);
782            }
783
784            listOrder.erase(order_it++);
785            statIssuedInstType[tid][op_class]++;
786            iewStage->incrWb(issuing_inst->seqNum);
787        } else {
788            statFuBusy[op_class]++;
789            fuBusy[tid]++;
790            ++order_it;
791        }
792    }
793
794    numIssuedDist.sample(total_issued);
795    iqInstsIssued+= total_issued;
796
797    // If we issued any instructions, tell the CPU we had activity.
798    if (total_issued) {
799        cpu->activityThisCycle();
800    } else {
801        DPRINTF(IQ, "Not able to schedule any instructions.\n");
802    }
803}
804
805template <class Impl>
806void
807InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
808{
809    DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
810            "to execute.\n", inst);
811
812    NonSpecMapIt inst_it = nonSpecInsts.find(inst);
813
814    assert(inst_it != nonSpecInsts.end());
815
816    unsigned tid = (*inst_it).second->threadNumber;
817
818    (*inst_it).second->setCanIssue();
819
820    if (!(*inst_it).second->isMemRef()) {
821        addIfReady((*inst_it).second);
822    } else {
823        memDepUnit[tid].nonSpecInstReady((*inst_it).second);
824    }
825
826    (*inst_it).second = NULL;
827
828    nonSpecInsts.erase(inst_it);
829}
830
831template <class Impl>
832void
833InstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid)
834{
835    DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
836            tid,inst);
837
838    ListIt iq_it = instList[tid].begin();
839
840    while (iq_it != instList[tid].end() &&
841           (*iq_it)->seqNum <= inst) {
842        ++iq_it;
843        instList[tid].pop_front();
844    }
845
846    assert(freeEntries == (numEntries - countInsts()));
847}
848
849template <class Impl>
850int
851InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
852{
853    int dependents = 0;
854
855    DPRINTF(IQ, "Waking dependents of completed instruction.\n");
856
857    assert(!completed_inst->isSquashed());
858
859    // Tell the memory dependence unit to wake any dependents on this
860    // instruction if it is a memory instruction.  Also complete the memory
861    // instruction at this point since we know it executed without issues.
862    // @todo: Might want to rename "completeMemInst" to something that
863    // indicates that it won't need to be replayed, and call this
864    // earlier.  Might not be a big deal.
865    if (completed_inst->isMemRef()) {
866        memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
867        completeMemInst(completed_inst);
868    } else if (completed_inst->isMemBarrier() ||
869               completed_inst->isWriteBarrier()) {
870        memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
871    }
872
873    for (int dest_reg_idx = 0;
874         dest_reg_idx < completed_inst->numDestRegs();
875         dest_reg_idx++)
876    {
877        PhysRegIndex dest_reg =
878            completed_inst->renamedDestRegIdx(dest_reg_idx);
879
880        // Special case of uniq or control registers.  They are not
881        // handled by the IQ and thus have no dependency graph entry.
882        // @todo Figure out a cleaner way to handle this.
883        if (dest_reg >= numPhysRegs) {
884            continue;
885        }
886
887        DPRINTF(IQ, "Waking any dependents on register %i.\n",
888                (int) dest_reg);
889
890        //Go through the dependency chain, marking the registers as
891        //ready within the waiting instructions.
892        DynInstPtr dep_inst = dependGraph.pop(dest_reg);
893
894        while (dep_inst) {
895            DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
896                    dep_inst->readPC());
897
898            // Might want to give more information to the instruction
899            // so that it knows which of its source registers is
900            // ready.  However that would mean that the dependency
901            // graph entries would need to hold the src_reg_idx.
902            dep_inst->markSrcRegReady();
903
904            addIfReady(dep_inst);
905
906            dep_inst = dependGraph.pop(dest_reg);
907
908            ++dependents;
909        }
910
911        // Reset the head node now that all of its dependents have
912        // been woken up.
913        assert(dependGraph.empty(dest_reg));
914        dependGraph.clearInst(dest_reg);
915
916        // Mark the scoreboard as having that register ready.
917        regScoreboard[dest_reg] = true;
918    }
919    return dependents;
920}
921
922template <class Impl>
923void
924InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
925{
926    OpClass op_class = ready_inst->opClass();
927
928    readyInsts[op_class].push(ready_inst);
929
930    // Will need to reorder the list if either a queue is not on the list,
931    // or it has an older instruction than last time.
932    if (!queueOnList[op_class]) {
933        addToOrderList(op_class);
934    } else if (readyInsts[op_class].top()->seqNum  <
935               (*readyIt[op_class]).oldestInst) {
936        listOrder.erase(readyIt[op_class]);
937        addToOrderList(op_class);
938    }
939
940    DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
941            "the ready list, PC %#x opclass:%i [sn:%lli].\n",
942            ready_inst->readPC(), op_class, ready_inst->seqNum);
943}
944
945template <class Impl>
946void
947InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
948{
949    memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
950}
951
952template <class Impl>
953void
954InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
955{
956    memDepUnit[replay_inst->threadNumber].replay(replay_inst);
957}
958
959template <class Impl>
960void
961InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
962{
963    int tid = completed_inst->threadNumber;
964
965    DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
966            completed_inst->readPC(), completed_inst->seqNum);
967
968    ++freeEntries;
969
970    completed_inst->memOpDone = true;
971
972    memDepUnit[tid].completed(completed_inst);
973
974    count[tid]--;
975}
976
977template <class Impl>
978void
979InstructionQueue<Impl>::violation(DynInstPtr &store,
980                                  DynInstPtr &faulting_load)
981{
982    memDepUnit[store->threadNumber].violation(store, faulting_load);
983}
984
985template <class Impl>
986void
987InstructionQueue<Impl>::squash(unsigned tid)
988{
989    DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
990            "the IQ.\n", tid);
991
992    // Read instruction sequence number of last instruction out of the
993    // time buffer.
994#if THE_ISA == ALPHA_ISA
995    squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
996#else
997    squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum;
998#endif
999
1000    // Call doSquash if there are insts in the IQ
1001    if (count[tid] > 0) {
1002        doSquash(tid);
1003    }
1004
1005    // Also tell the memory dependence unit to squash.
1006    memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1007}
1008
1009template <class Impl>
1010void
1011InstructionQueue<Impl>::doSquash(unsigned tid)
1012{
1013    // Start at the tail.
1014    ListIt squash_it = instList[tid].end();
1015    --squash_it;
1016
1017    DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1018            tid, squashedSeqNum[tid]);
1019
1020    // Squash any instructions younger than the squashed sequence number
1021    // given.
1022    while (squash_it != instList[tid].end() &&
1023           (*squash_it)->seqNum > squashedSeqNum[tid]) {
1024
1025        DynInstPtr squashed_inst = (*squash_it);
1026
1027        // Only handle the instruction if it actually is in the IQ and
1028        // hasn't already been squashed in the IQ.
1029        if (squashed_inst->threadNumber != tid ||
1030            squashed_inst->isSquashedInIQ()) {
1031            --squash_it;
1032            continue;
1033        }
1034
1035        if (!squashed_inst->isIssued() ||
1036            (squashed_inst->isMemRef() &&
1037             !squashed_inst->memOpDone)) {
1038
1039            // Remove the instruction from the dependency list.
1040            if (!squashed_inst->isNonSpeculative() &&
1041                !squashed_inst->isStoreConditional() &&
1042                !squashed_inst->isMemBarrier() &&
1043                !squashed_inst->isWriteBarrier()) {
1044
1045                for (int src_reg_idx = 0;
1046                     src_reg_idx < squashed_inst->numSrcRegs();
1047                     src_reg_idx++)
1048                {
1049                    PhysRegIndex src_reg =
1050                        squashed_inst->renamedSrcRegIdx(src_reg_idx);
1051
1052                    // Only remove it from the dependency graph if it
1053                    // was placed there in the first place.
1054
1055                    // Instead of doing a linked list traversal, we
1056                    // can just remove these squashed instructions
1057                    // either at issue time, or when the register is
1058                    // overwritten.  The only downside to this is it
1059                    // leaves more room for error.
1060
1061                    if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1062                        src_reg < numPhysRegs) {
1063                        dependGraph.remove(src_reg, squashed_inst);
1064                    }
1065
1066
1067                    ++iqSquashedOperandsExamined;
1068                }
1069            } else {
1070                NonSpecMapIt ns_inst_it =
1071                    nonSpecInsts.find(squashed_inst->seqNum);
1072                assert(ns_inst_it != nonSpecInsts.end());
1073
1074                (*ns_inst_it).second = NULL;
1075
1076                nonSpecInsts.erase(ns_inst_it);
1077
1078                ++iqSquashedNonSpecRemoved;
1079            }
1080
1081            // Might want to also clear out the head of the dependency graph.
1082
1083            // Mark it as squashed within the IQ.
1084            squashed_inst->setSquashedInIQ();
1085
1086            // @todo: Remove this hack where several statuses are set so the
1087            // inst will flow through the rest of the pipeline.
1088            squashed_inst->setIssued();
1089            squashed_inst->setCanCommit();
1090            squashed_inst->clearInIQ();
1091
1092            //Update Thread IQ Count
1093            count[squashed_inst->threadNumber]--;
1094
1095            ++freeEntries;
1096
1097            DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
1098                    "squashed.\n",
1099                    tid, squashed_inst->seqNum, squashed_inst->readPC());
1100        }
1101
1102        instList[tid].erase(squash_it--);
1103        ++iqSquashedInstsExamined;
1104    }
1105}
1106
1107template <class Impl>
1108bool
1109InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1110{
1111    // Loop through the instruction's source registers, adding
1112    // them to the dependency list if they are not ready.
1113    int8_t total_src_regs = new_inst->numSrcRegs();
1114    bool return_val = false;
1115
1116    for (int src_reg_idx = 0;
1117         src_reg_idx < total_src_regs;
1118         src_reg_idx++)
1119    {
1120        // Only add it to the dependency graph if it's not ready.
1121        if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1122            PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1123
1124            // Check the IQ's scoreboard to make sure the register
1125            // hasn't become ready while the instruction was in flight
1126            // between stages.  Only if it really isn't ready should
1127            // it be added to the dependency graph.
1128            if (src_reg >= numPhysRegs) {
1129                continue;
1130            } else if (regScoreboard[src_reg] == false) {
1131                DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1132                        "is being added to the dependency chain.\n",
1133                        new_inst->readPC(), src_reg);
1134
1135                dependGraph.insert(src_reg, new_inst);
1136
1137                // Change the return value to indicate that something
1138                // was added to the dependency graph.
1139                return_val = true;
1140            } else {
1141                DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1142                        "became ready before it reached the IQ.\n",
1143                        new_inst->readPC(), src_reg);
1144                // Mark a register ready within the instruction.
1145                new_inst->markSrcRegReady(src_reg_idx);
1146            }
1147        }
1148    }
1149
1150    return return_val;
1151}
1152
1153template <class Impl>
1154void
1155InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1156{
1157    // Nothing really needs to be marked when an instruction becomes
1158    // the producer of a register's value, but for convenience a ptr
1159    // to the producing instruction will be placed in the head node of
1160    // the dependency links.
1161    int8_t total_dest_regs = new_inst->numDestRegs();
1162
1163    for (int dest_reg_idx = 0;
1164         dest_reg_idx < total_dest_regs;
1165         dest_reg_idx++)
1166    {
1167        PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1168
1169        // Instructions that use the misc regs will have a reg number
1170        // higher than the normal physical registers.  In this case these
1171        // registers are not renamed, and there is no need to track
1172        // dependencies as these instructions must be executed at commit.
1173        if (dest_reg >= numPhysRegs) {
1174            continue;
1175        }
1176
1177        if (!dependGraph.empty(dest_reg)) {
1178            dependGraph.dump();
1179            panic("Dependency graph %i not empty!", dest_reg);
1180        }
1181
1182        dependGraph.setInst(dest_reg, new_inst);
1183
1184        // Mark the scoreboard to say it's not yet ready.
1185        regScoreboard[dest_reg] = false;
1186    }
1187}
1188
1189template <class Impl>
1190void
1191InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1192{
1193    // If the instruction now has all of its source registers
1194    // available, then add it to the list of ready instructions.
1195    if (inst->readyToIssue()) {
1196
1197        //Add the instruction to the proper ready list.
1198        if (inst->isMemRef()) {
1199
1200            DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1201
1202            // Message to the mem dependence unit that this instruction has
1203            // its registers ready.
1204            memDepUnit[inst->threadNumber].regsReady(inst);
1205
1206            return;
1207        }
1208
1209        OpClass op_class = inst->opClass();
1210
1211        DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1212                "the ready list, PC %#x opclass:%i [sn:%lli].\n",
1213                inst->readPC(), op_class, inst->seqNum);
1214
1215        readyInsts[op_class].push(inst);
1216
1217        // Will need to reorder the list if either a queue is not on the list,
1218        // or it has an older instruction than last time.
1219        if (!queueOnList[op_class]) {
1220            addToOrderList(op_class);
1221        } else if (readyInsts[op_class].top()->seqNum  <
1222                   (*readyIt[op_class]).oldestInst) {
1223            listOrder.erase(readyIt[op_class]);
1224            addToOrderList(op_class);
1225        }
1226    }
1227}
1228
1229template <class Impl>
1230int
1231InstructionQueue<Impl>::countInsts()
1232{
1233#if 0
1234    //ksewell:This works but definitely could use a cleaner write
1235    //with a more intuitive way of counting. Right now it's
1236    //just brute force ....
1237    // Change the #if if you want to use this method.
1238    int total_insts = 0;
1239
1240    for (int i = 0; i < numThreads; ++i) {
1241        ListIt count_it = instList[i].begin();
1242
1243        while (count_it != instList[i].end()) {
1244            if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1245                if (!(*count_it)->isIssued()) {
1246                    ++total_insts;
1247                } else if ((*count_it)->isMemRef() &&
1248                           !(*count_it)->memOpDone) {
1249                    // Loads that have not been marked as executed still count
1250                    // towards the total instructions.
1251                    ++total_insts;
1252                }
1253            }
1254
1255            ++count_it;
1256        }
1257    }
1258
1259    return total_insts;
1260#else
1261    return numEntries - freeEntries;
1262#endif
1263}
1264
1265template <class Impl>
1266void
1267InstructionQueue<Impl>::dumpLists()
1268{
1269    for (int i = 0; i < Num_OpClasses; ++i) {
1270        cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1271
1272        cprintf("\n");
1273    }
1274
1275    cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1276
1277    NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1278    NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1279
1280    cprintf("Non speculative list: ");
1281
1282    while (non_spec_it != non_spec_end_it) {
1283        cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
1284                (*non_spec_it).second->seqNum);
1285        ++non_spec_it;
1286    }
1287
1288    cprintf("\n");
1289
1290    ListOrderIt list_order_it = listOrder.begin();
1291    ListOrderIt list_order_end_it = listOrder.end();
1292    int i = 1;
1293
1294    cprintf("List order: ");
1295
1296    while (list_order_it != list_order_end_it) {
1297        cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1298                (*list_order_it).oldestInst);
1299
1300        ++list_order_it;
1301        ++i;
1302    }
1303
1304    cprintf("\n");
1305}
1306
1307
1308template <class Impl>
1309void
1310InstructionQueue<Impl>::dumpInsts()
1311{
1312    for (int i = 0; i < numThreads; ++i) {
1313        int num = 0;
1314        int valid_num = 0;
1315        ListIt inst_list_it = instList[i].begin();
1316
1317        while (inst_list_it != instList[i].end())
1318        {
1319            cprintf("Instruction:%i\n",
1320                    num);
1321            if (!(*inst_list_it)->isSquashed()) {
1322                if (!(*inst_list_it)->isIssued()) {
1323                    ++valid_num;
1324                    cprintf("Count:%i\n", valid_num);
1325                } else if ((*inst_list_it)->isMemRef() &&
1326                           !(*inst_list_it)->memOpDone) {
1327                    // Loads that have not been marked as executed
1328                    // still count towards the total instructions.
1329                    ++valid_num;
1330                    cprintf("Count:%i\n", valid_num);
1331                }
1332            }
1333
1334            cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1335                    "Issued:%i\nSquashed:%i\n",
1336                    (*inst_list_it)->readPC(),
1337                    (*inst_list_it)->seqNum,
1338                    (*inst_list_it)->threadNumber,
1339                    (*inst_list_it)->isIssued(),
1340                    (*inst_list_it)->isSquashed());
1341
1342            if ((*inst_list_it)->isMemRef()) {
1343                cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1344            }
1345
1346            cprintf("\n");
1347
1348            inst_list_it++;
1349            ++num;
1350        }
1351    }
1352
1353    cprintf("Insts to Execute list:\n");
1354
1355    int num = 0;
1356    int valid_num = 0;
1357    ListIt inst_list_it = instsToExecute.begin();
1358
1359    while (inst_list_it != instsToExecute.end())
1360    {
1361        cprintf("Instruction:%i\n",
1362                num);
1363        if (!(*inst_list_it)->isSquashed()) {
1364            if (!(*inst_list_it)->isIssued()) {
1365                ++valid_num;
1366                cprintf("Count:%i\n", valid_num);
1367            } else if ((*inst_list_it)->isMemRef() &&
1368                       !(*inst_list_it)->memOpDone) {
1369                // Loads that have not been marked as executed
1370                // still count towards the total instructions.
1371                ++valid_num;
1372                cprintf("Count:%i\n", valid_num);
1373            }
1374        }
1375
1376        cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1377                "Issued:%i\nSquashed:%i\n",
1378                (*inst_list_it)->readPC(),
1379                (*inst_list_it)->seqNum,
1380                (*inst_list_it)->threadNumber,
1381                (*inst_list_it)->isIssued(),
1382                (*inst_list_it)->isSquashed());
1383
1384        if ((*inst_list_it)->isMemRef()) {
1385            cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1386        }
1387
1388        cprintf("\n");
1389
1390        inst_list_it++;
1391        ++num;
1392    }
1393}
1394