inst_queue_impl.hh revision 12110
1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 */
44
45#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__
46#define __CPU_O3_INST_QUEUE_IMPL_HH__
47
48#include <limits>
49#include <vector>
50
51#include "cpu/o3/fu_pool.hh"
52#include "cpu/o3/inst_queue.hh"
53#include "debug/IQ.hh"
54#include "enums/OpClass.hh"
55#include "params/DerivO3CPU.hh"
56#include "sim/core.hh"
57
58// clang complains about std::set being overloaded with Packet::set if
59// we open up the entire namespace std
60using std::list;
61
62template <class Impl>
63InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
64    int fu_idx, InstructionQueue<Impl> *iq_ptr)
65    : Event(Stat_Event_Pri, AutoDelete),
66      inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
67{
68}
69
70template <class Impl>
71void
72InstructionQueue<Impl>::FUCompletion::process()
73{
74    iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
75    inst = NULL;
76}
77
78
79template <class Impl>
80const char *
81InstructionQueue<Impl>::FUCompletion::description() const
82{
83    return "Functional unit completion";
84}
85
86template <class Impl>
87InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
88                                         DerivO3CPUParams *params)
89    : cpu(cpu_ptr),
90      iewStage(iew_ptr),
91      fuPool(params->fuPool),
92      numEntries(params->numIQEntries),
93      totalWidth(params->issueWidth),
94      commitToIEWDelay(params->commitToIEWDelay)
95{
96    assert(fuPool);
97
98    numThreads = params->numThreads;
99
100    // Set the number of total physical registers
101    // As the vector registers have two addressing modes, they are added twice
102    numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs +
103                    params->numPhysVecRegs +
104                    params->numPhysVecRegs * TheISA::NumVecElemPerVecReg +
105                    params->numPhysCCRegs;
106
107    //Create an entry for each physical register within the
108    //dependency graph.
109    dependGraph.resize(numPhysRegs);
110
111    // Resize the register scoreboard.
112    regScoreboard.resize(numPhysRegs);
113
114    //Initialize Mem Dependence Units
115    for (ThreadID tid = 0; tid < numThreads; tid++) {
116        memDepUnit[tid].init(params, tid);
117        memDepUnit[tid].setIQ(this);
118    }
119
120    resetState();
121
122    std::string policy = params->smtIQPolicy;
123
124    //Convert string to lowercase
125    std::transform(policy.begin(), policy.end(), policy.begin(),
126                   (int(*)(int)) tolower);
127
128    //Figure out resource sharing policy
129    if (policy == "dynamic") {
130        iqPolicy = Dynamic;
131
132        //Set Max Entries to Total ROB Capacity
133        for (ThreadID tid = 0; tid < numThreads; tid++) {
134            maxEntries[tid] = numEntries;
135        }
136
137    } else if (policy == "partitioned") {
138        iqPolicy = Partitioned;
139
140        //@todo:make work if part_amt doesnt divide evenly.
141        int part_amt = numEntries / numThreads;
142
143        //Divide ROB up evenly
144        for (ThreadID tid = 0; tid < numThreads; tid++) {
145            maxEntries[tid] = part_amt;
146        }
147
148        DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
149                "%i entries per thread.\n",part_amt);
150    } else if (policy == "threshold") {
151        iqPolicy = Threshold;
152
153        double threshold =  (double)params->smtIQThreshold / 100;
154
155        int thresholdIQ = (int)((double)threshold * numEntries);
156
157        //Divide up by threshold amount
158        for (ThreadID tid = 0; tid < numThreads; tid++) {
159            maxEntries[tid] = thresholdIQ;
160        }
161
162        DPRINTF(IQ, "IQ sharing policy set to Threshold:"
163                "%i entries per thread.\n",thresholdIQ);
164   } else {
165       assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
166              "Partitioned, Threshold}");
167   }
168}
169
170template <class Impl>
171InstructionQueue<Impl>::~InstructionQueue()
172{
173    dependGraph.reset();
174#ifdef DEBUG
175    cprintf("Nodes traversed: %i, removed: %i\n",
176            dependGraph.nodesTraversed, dependGraph.nodesRemoved);
177#endif
178}
179
180template <class Impl>
181std::string
182InstructionQueue<Impl>::name() const
183{
184    return cpu->name() + ".iq";
185}
186
187template <class Impl>
188void
189InstructionQueue<Impl>::regStats()
190{
191    using namespace Stats;
192    iqInstsAdded
193        .name(name() + ".iqInstsAdded")
194        .desc("Number of instructions added to the IQ (excludes non-spec)")
195        .prereq(iqInstsAdded);
196
197    iqNonSpecInstsAdded
198        .name(name() + ".iqNonSpecInstsAdded")
199        .desc("Number of non-speculative instructions added to the IQ")
200        .prereq(iqNonSpecInstsAdded);
201
202    iqInstsIssued
203        .name(name() + ".iqInstsIssued")
204        .desc("Number of instructions issued")
205        .prereq(iqInstsIssued);
206
207    iqIntInstsIssued
208        .name(name() + ".iqIntInstsIssued")
209        .desc("Number of integer instructions issued")
210        .prereq(iqIntInstsIssued);
211
212    iqFloatInstsIssued
213        .name(name() + ".iqFloatInstsIssued")
214        .desc("Number of float instructions issued")
215        .prereq(iqFloatInstsIssued);
216
217    iqBranchInstsIssued
218        .name(name() + ".iqBranchInstsIssued")
219        .desc("Number of branch instructions issued")
220        .prereq(iqBranchInstsIssued);
221
222    iqMemInstsIssued
223        .name(name() + ".iqMemInstsIssued")
224        .desc("Number of memory instructions issued")
225        .prereq(iqMemInstsIssued);
226
227    iqMiscInstsIssued
228        .name(name() + ".iqMiscInstsIssued")
229        .desc("Number of miscellaneous instructions issued")
230        .prereq(iqMiscInstsIssued);
231
232    iqSquashedInstsIssued
233        .name(name() + ".iqSquashedInstsIssued")
234        .desc("Number of squashed instructions issued")
235        .prereq(iqSquashedInstsIssued);
236
237    iqSquashedInstsExamined
238        .name(name() + ".iqSquashedInstsExamined")
239        .desc("Number of squashed instructions iterated over during squash;"
240              " mainly for profiling")
241        .prereq(iqSquashedInstsExamined);
242
243    iqSquashedOperandsExamined
244        .name(name() + ".iqSquashedOperandsExamined")
245        .desc("Number of squashed operands that are examined and possibly "
246              "removed from graph")
247        .prereq(iqSquashedOperandsExamined);
248
249    iqSquashedNonSpecRemoved
250        .name(name() + ".iqSquashedNonSpecRemoved")
251        .desc("Number of squashed non-spec instructions that were removed")
252        .prereq(iqSquashedNonSpecRemoved);
253/*
254    queueResDist
255        .init(Num_OpClasses, 0, 99, 2)
256        .name(name() + ".IQ:residence:")
257        .desc("cycles from dispatch to issue")
258        .flags(total | pdf | cdf )
259        ;
260    for (int i = 0; i < Num_OpClasses; ++i) {
261        queueResDist.subname(i, opClassStrings[i]);
262    }
263*/
264    numIssuedDist
265        .init(0,totalWidth,1)
266        .name(name() + ".issued_per_cycle")
267        .desc("Number of insts issued each cycle")
268        .flags(pdf)
269        ;
270/*
271    dist_unissued
272        .init(Num_OpClasses+2)
273        .name(name() + ".unissued_cause")
274        .desc("Reason ready instruction not issued")
275        .flags(pdf | dist)
276        ;
277    for (int i=0; i < (Num_OpClasses + 2); ++i) {
278        dist_unissued.subname(i, unissued_names[i]);
279    }
280*/
281    statIssuedInstType
282        .init(numThreads,Enums::Num_OpClass)
283        .name(name() + ".FU_type")
284        .desc("Type of FU issued")
285        .flags(total | pdf | dist)
286        ;
287    statIssuedInstType.ysubnames(Enums::OpClassStrings);
288
289    //
290    //  How long did instructions for a particular FU type wait prior to issue
291    //
292/*
293    issueDelayDist
294        .init(Num_OpClasses,0,99,2)
295        .name(name() + ".")
296        .desc("cycles from operands ready to issue")
297        .flags(pdf | cdf)
298        ;
299
300    for (int i=0; i<Num_OpClasses; ++i) {
301        std::stringstream subname;
302        subname << opClassStrings[i] << "_delay";
303        issueDelayDist.subname(i, subname.str());
304    }
305*/
306    issueRate
307        .name(name() + ".rate")
308        .desc("Inst issue rate")
309        .flags(total)
310        ;
311    issueRate = iqInstsIssued / cpu->numCycles;
312
313    statFuBusy
314        .init(Num_OpClasses)
315        .name(name() + ".fu_full")
316        .desc("attempts to use FU when none available")
317        .flags(pdf | dist)
318        ;
319    for (int i=0; i < Num_OpClasses; ++i) {
320        statFuBusy.subname(i, Enums::OpClassStrings[i]);
321    }
322
323    fuBusy
324        .init(numThreads)
325        .name(name() + ".fu_busy_cnt")
326        .desc("FU busy when requested")
327        .flags(total)
328        ;
329
330    fuBusyRate
331        .name(name() + ".fu_busy_rate")
332        .desc("FU busy rate (busy events/executed inst)")
333        .flags(total)
334        ;
335    fuBusyRate = fuBusy / iqInstsIssued;
336
337    for (ThreadID tid = 0; tid < numThreads; tid++) {
338        // Tell mem dependence unit to reg stats as well.
339        memDepUnit[tid].regStats();
340    }
341
342    intInstQueueReads
343        .name(name() + ".int_inst_queue_reads")
344        .desc("Number of integer instruction queue reads")
345        .flags(total);
346
347    intInstQueueWrites
348        .name(name() + ".int_inst_queue_writes")
349        .desc("Number of integer instruction queue writes")
350        .flags(total);
351
352    intInstQueueWakeupAccesses
353        .name(name() + ".int_inst_queue_wakeup_accesses")
354        .desc("Number of integer instruction queue wakeup accesses")
355        .flags(total);
356
357    fpInstQueueReads
358        .name(name() + ".fp_inst_queue_reads")
359        .desc("Number of floating instruction queue reads")
360        .flags(total);
361
362    fpInstQueueWrites
363        .name(name() + ".fp_inst_queue_writes")
364        .desc("Number of floating instruction queue writes")
365        .flags(total);
366
367    fpInstQueueWakeupAccesses
368        .name(name() + ".fp_inst_queue_wakeup_accesses")
369        .desc("Number of floating instruction queue wakeup accesses")
370        .flags(total);
371
372    intAluAccesses
373        .name(name() + ".int_alu_accesses")
374        .desc("Number of integer alu accesses")
375        .flags(total);
376
377    fpAluAccesses
378        .name(name() + ".fp_alu_accesses")
379        .desc("Number of floating point alu accesses")
380        .flags(total);
381
382}
383
384template <class Impl>
385void
386InstructionQueue<Impl>::resetState()
387{
388    //Initialize thread IQ counts
389    for (ThreadID tid = 0; tid <numThreads; tid++) {
390        count[tid] = 0;
391        instList[tid].clear();
392    }
393
394    // Initialize the number of free IQ entries.
395    freeEntries = numEntries;
396
397    // Note that in actuality, the registers corresponding to the logical
398    // registers start off as ready.  However this doesn't matter for the
399    // IQ as the instruction should have been correctly told if those
400    // registers are ready in rename.  Thus it can all be initialized as
401    // unready.
402    for (int i = 0; i < numPhysRegs; ++i) {
403        regScoreboard[i] = false;
404    }
405
406    for (ThreadID tid = 0; tid < numThreads; ++tid) {
407        squashedSeqNum[tid] = 0;
408    }
409
410    for (int i = 0; i < Num_OpClasses; ++i) {
411        while (!readyInsts[i].empty())
412            readyInsts[i].pop();
413        queueOnList[i] = false;
414        readyIt[i] = listOrder.end();
415    }
416    nonSpecInsts.clear();
417    listOrder.clear();
418    deferredMemInsts.clear();
419    blockedMemInsts.clear();
420    retryMemInsts.clear();
421    wbOutstanding = 0;
422}
423
424template <class Impl>
425void
426InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
427{
428    activeThreads = at_ptr;
429}
430
431template <class Impl>
432void
433InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
434{
435      issueToExecuteQueue = i2e_ptr;
436}
437
438template <class Impl>
439void
440InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
441{
442    timeBuffer = tb_ptr;
443
444    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
445}
446
447template <class Impl>
448bool
449InstructionQueue<Impl>::isDrained() const
450{
451    bool drained = dependGraph.empty() &&
452                   instsToExecute.empty() &&
453                   wbOutstanding == 0;
454    for (ThreadID tid = 0; tid < numThreads; ++tid)
455        drained = drained && memDepUnit[tid].isDrained();
456
457    return drained;
458}
459
460template <class Impl>
461void
462InstructionQueue<Impl>::drainSanityCheck() const
463{
464    assert(dependGraph.empty());
465    assert(instsToExecute.empty());
466    for (ThreadID tid = 0; tid < numThreads; ++tid)
467        memDepUnit[tid].drainSanityCheck();
468}
469
470template <class Impl>
471void
472InstructionQueue<Impl>::takeOverFrom()
473{
474    resetState();
475}
476
477template <class Impl>
478int
479InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
480{
481    if (iqPolicy == Partitioned) {
482        return numEntries / num_threads;
483    } else {
484        return 0;
485    }
486}
487
488
489template <class Impl>
490void
491InstructionQueue<Impl>::resetEntries()
492{
493    if (iqPolicy != Dynamic || numThreads > 1) {
494        int active_threads = activeThreads->size();
495
496        list<ThreadID>::iterator threads = activeThreads->begin();
497        list<ThreadID>::iterator end = activeThreads->end();
498
499        while (threads != end) {
500            ThreadID tid = *threads++;
501
502            if (iqPolicy == Partitioned) {
503                maxEntries[tid] = numEntries / active_threads;
504            } else if (iqPolicy == Threshold && active_threads == 1) {
505                maxEntries[tid] = numEntries;
506            }
507        }
508    }
509}
510
511template <class Impl>
512unsigned
513InstructionQueue<Impl>::numFreeEntries()
514{
515    return freeEntries;
516}
517
518template <class Impl>
519unsigned
520InstructionQueue<Impl>::numFreeEntries(ThreadID tid)
521{
522    return maxEntries[tid] - count[tid];
523}
524
525// Might want to do something more complex if it knows how many instructions
526// will be issued this cycle.
527template <class Impl>
528bool
529InstructionQueue<Impl>::isFull()
530{
531    if (freeEntries == 0) {
532        return(true);
533    } else {
534        return(false);
535    }
536}
537
538template <class Impl>
539bool
540InstructionQueue<Impl>::isFull(ThreadID tid)
541{
542    if (numFreeEntries(tid) == 0) {
543        return(true);
544    } else {
545        return(false);
546    }
547}
548
549template <class Impl>
550bool
551InstructionQueue<Impl>::hasReadyInsts()
552{
553    if (!listOrder.empty()) {
554        return true;
555    }
556
557    for (int i = 0; i < Num_OpClasses; ++i) {
558        if (!readyInsts[i].empty()) {
559            return true;
560        }
561    }
562
563    return false;
564}
565
566template <class Impl>
567void
568InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
569{
570    if (new_inst->isFloating()) {
571        fpInstQueueWrites++;
572    } else if (new_inst->isVector()) {
573        vecInstQueueWrites++;
574    } else {
575        intInstQueueWrites++;
576    }
577    // Make sure the instruction is valid
578    assert(new_inst);
579
580    DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n",
581            new_inst->seqNum, new_inst->pcState());
582
583    assert(freeEntries != 0);
584
585    instList[new_inst->threadNumber].push_back(new_inst);
586
587    --freeEntries;
588
589    new_inst->setInIQ();
590
591    // Look through its source registers (physical regs), and mark any
592    // dependencies.
593    addToDependents(new_inst);
594
595    // Have this instruction set itself as the producer of its destination
596    // register(s).
597    addToProducers(new_inst);
598
599    if (new_inst->isMemRef()) {
600        memDepUnit[new_inst->threadNumber].insert(new_inst);
601    } else {
602        addIfReady(new_inst);
603    }
604
605    ++iqInstsAdded;
606
607    count[new_inst->threadNumber]++;
608
609    assert(freeEntries == (numEntries - countInsts()));
610}
611
612template <class Impl>
613void
614InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
615{
616    // @todo: Clean up this code; can do it by setting inst as unable
617    // to issue, then calling normal insert on the inst.
618    if (new_inst->isFloating()) {
619        fpInstQueueWrites++;
620    } else if (new_inst->isVector()) {
621        vecInstQueueWrites++;
622    } else {
623        intInstQueueWrites++;
624    }
625
626    assert(new_inst);
627
628    nonSpecInsts[new_inst->seqNum] = new_inst;
629
630    DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s "
631            "to the IQ.\n",
632            new_inst->seqNum, new_inst->pcState());
633
634    assert(freeEntries != 0);
635
636    instList[new_inst->threadNumber].push_back(new_inst);
637
638    --freeEntries;
639
640    new_inst->setInIQ();
641
642    // Have this instruction set itself as the producer of its destination
643    // register(s).
644    addToProducers(new_inst);
645
646    // If it's a memory instruction, add it to the memory dependency
647    // unit.
648    if (new_inst->isMemRef()) {
649        memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
650    }
651
652    ++iqNonSpecInstsAdded;
653
654    count[new_inst->threadNumber]++;
655
656    assert(freeEntries == (numEntries - countInsts()));
657}
658
659template <class Impl>
660void
661InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
662{
663    memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
664
665    insertNonSpec(barr_inst);
666}
667
668template <class Impl>
669typename Impl::DynInstPtr
670InstructionQueue<Impl>::getInstToExecute()
671{
672    assert(!instsToExecute.empty());
673    DynInstPtr inst = instsToExecute.front();
674    instsToExecute.pop_front();
675    if (inst->isFloating()) {
676        fpInstQueueReads++;
677    } else if (inst->isVector()) {
678        vecInstQueueReads++;
679    } else {
680        intInstQueueReads++;
681    }
682    return inst;
683}
684
685template <class Impl>
686void
687InstructionQueue<Impl>::addToOrderList(OpClass op_class)
688{
689    assert(!readyInsts[op_class].empty());
690
691    ListOrderEntry queue_entry;
692
693    queue_entry.queueType = op_class;
694
695    queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
696
697    ListOrderIt list_it = listOrder.begin();
698    ListOrderIt list_end_it = listOrder.end();
699
700    while (list_it != list_end_it) {
701        if ((*list_it).oldestInst > queue_entry.oldestInst) {
702            break;
703        }
704
705        list_it++;
706    }
707
708    readyIt[op_class] = listOrder.insert(list_it, queue_entry);
709    queueOnList[op_class] = true;
710}
711
712template <class Impl>
713void
714InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
715{
716    // Get iterator of next item on the list
717    // Delete the original iterator
718    // Determine if the next item is either the end of the list or younger
719    // than the new instruction.  If so, then add in a new iterator right here.
720    // If not, then move along.
721    ListOrderEntry queue_entry;
722    OpClass op_class = (*list_order_it).queueType;
723    ListOrderIt next_it = list_order_it;
724
725    ++next_it;
726
727    queue_entry.queueType = op_class;
728    queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
729
730    while (next_it != listOrder.end() &&
731           (*next_it).oldestInst < queue_entry.oldestInst) {
732        ++next_it;
733    }
734
735    readyIt[op_class] = listOrder.insert(next_it, queue_entry);
736}
737
738template <class Impl>
739void
740InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
741{
742    DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
743    assert(!cpu->switchedOut());
744    // The CPU could have been sleeping until this op completed (*extremely*
745    // long latency op).  Wake it if it was.  This may be overkill.
746   --wbOutstanding;
747    iewStage->wakeCPU();
748
749    if (fu_idx > -1)
750        fuPool->freeUnitNextCycle(fu_idx);
751
752    // @todo: Ensure that these FU Completions happen at the beginning
753    // of a cycle, otherwise they could add too many instructions to
754    // the queue.
755    issueToExecuteQueue->access(-1)->size++;
756    instsToExecute.push_back(inst);
757}
758
759// @todo: Figure out a better way to remove the squashed items from the
760// lists.  Checking the top item of each list to see if it's squashed
761// wastes time and forces jumps.
762template <class Impl>
763void
764InstructionQueue<Impl>::scheduleReadyInsts()
765{
766    DPRINTF(IQ, "Attempting to schedule ready instructions from "
767            "the IQ.\n");
768
769    IssueStruct *i2e_info = issueToExecuteQueue->access(0);
770
771    DynInstPtr mem_inst;
772    while (mem_inst = getDeferredMemInstToExecute()) {
773        addReadyMemInst(mem_inst);
774    }
775
776    // See if any cache blocked instructions are able to be executed
777    while (mem_inst = getBlockedMemInstToExecute()) {
778        addReadyMemInst(mem_inst);
779    }
780
781    // Have iterator to head of the list
782    // While I haven't exceeded bandwidth or reached the end of the list,
783    // Try to get a FU that can do what this op needs.
784    // If successful, change the oldestInst to the new top of the list, put
785    // the queue in the proper place in the list.
786    // Increment the iterator.
787    // This will avoid trying to schedule a certain op class if there are no
788    // FUs that handle it.
789    int total_issued = 0;
790    ListOrderIt order_it = listOrder.begin();
791    ListOrderIt order_end_it = listOrder.end();
792
793    while (total_issued < totalWidth && order_it != order_end_it) {
794        OpClass op_class = (*order_it).queueType;
795
796        assert(!readyInsts[op_class].empty());
797
798        DynInstPtr issuing_inst = readyInsts[op_class].top();
799
800        if (issuing_inst->isFloating()) {
801            fpInstQueueReads++;
802        } else if (issuing_inst->isVector()) {
803            vecInstQueueReads++;
804        } else {
805            intInstQueueReads++;
806        }
807
808        assert(issuing_inst->seqNum == (*order_it).oldestInst);
809
810        if (issuing_inst->isSquashed()) {
811            readyInsts[op_class].pop();
812
813            if (!readyInsts[op_class].empty()) {
814                moveToYoungerInst(order_it);
815            } else {
816                readyIt[op_class] = listOrder.end();
817                queueOnList[op_class] = false;
818            }
819
820            listOrder.erase(order_it++);
821
822            ++iqSquashedInstsIssued;
823
824            continue;
825        }
826
827        int idx = FUPool::NoCapableFU;
828        Cycles op_latency = Cycles(1);
829        ThreadID tid = issuing_inst->threadNumber;
830
831        if (op_class != No_OpClass) {
832            idx = fuPool->getUnit(op_class);
833            if (issuing_inst->isFloating()) {
834                fpAluAccesses++;
835            } else if (issuing_inst->isVector()) {
836                vecAluAccesses++;
837            } else {
838                intAluAccesses++;
839            }
840            if (idx > FUPool::NoFreeFU) {
841                op_latency = fuPool->getOpLatency(op_class);
842            }
843        }
844
845        // If we have an instruction that doesn't require a FU, or a
846        // valid FU, then schedule for execution.
847        if (idx != FUPool::NoFreeFU) {
848            if (op_latency == Cycles(1)) {
849                i2e_info->size++;
850                instsToExecute.push_back(issuing_inst);
851
852                // Add the FU onto the list of FU's to be freed next
853                // cycle if we used one.
854                if (idx >= 0)
855                    fuPool->freeUnitNextCycle(idx);
856            } else {
857                bool pipelined = fuPool->isPipelined(op_class);
858                // Generate completion event for the FU
859                ++wbOutstanding;
860                FUCompletion *execution = new FUCompletion(issuing_inst,
861                                                           idx, this);
862
863                cpu->schedule(execution,
864                              cpu->clockEdge(Cycles(op_latency - 1)));
865
866                if (!pipelined) {
867                    // If FU isn't pipelined, then it must be freed
868                    // upon the execution completing.
869                    execution->setFreeFU();
870                } else {
871                    // Add the FU onto the list of FU's to be freed next cycle.
872                    fuPool->freeUnitNextCycle(idx);
873                }
874            }
875
876            DPRINTF(IQ, "Thread %i: Issuing instruction PC %s "
877                    "[sn:%lli]\n",
878                    tid, issuing_inst->pcState(),
879                    issuing_inst->seqNum);
880
881            readyInsts[op_class].pop();
882
883            if (!readyInsts[op_class].empty()) {
884                moveToYoungerInst(order_it);
885            } else {
886                readyIt[op_class] = listOrder.end();
887                queueOnList[op_class] = false;
888            }
889
890            issuing_inst->setIssued();
891            ++total_issued;
892
893#if TRACING_ON
894            issuing_inst->issueTick = curTick() - issuing_inst->fetchTick;
895#endif
896
897            if (!issuing_inst->isMemRef()) {
898                // Memory instructions can not be freed from the IQ until they
899                // complete.
900                ++freeEntries;
901                count[tid]--;
902                issuing_inst->clearInIQ();
903            } else {
904                memDepUnit[tid].issue(issuing_inst);
905            }
906
907            listOrder.erase(order_it++);
908            statIssuedInstType[tid][op_class]++;
909        } else {
910            statFuBusy[op_class]++;
911            fuBusy[tid]++;
912            ++order_it;
913        }
914    }
915
916    numIssuedDist.sample(total_issued);
917    iqInstsIssued+= total_issued;
918
919    // If we issued any instructions, tell the CPU we had activity.
920    // @todo If the way deferred memory instructions are handeled due to
921    // translation changes then the deferredMemInsts condition should be removed
922    // from the code below.
923    if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) {
924        cpu->activityThisCycle();
925    } else {
926        DPRINTF(IQ, "Not able to schedule any instructions.\n");
927    }
928}
929
930template <class Impl>
931void
932InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
933{
934    DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
935            "to execute.\n", inst);
936
937    NonSpecMapIt inst_it = nonSpecInsts.find(inst);
938
939    assert(inst_it != nonSpecInsts.end());
940
941    ThreadID tid = (*inst_it).second->threadNumber;
942
943    (*inst_it).second->setAtCommit();
944
945    (*inst_it).second->setCanIssue();
946
947    if (!(*inst_it).second->isMemRef()) {
948        addIfReady((*inst_it).second);
949    } else {
950        memDepUnit[tid].nonSpecInstReady((*inst_it).second);
951    }
952
953    (*inst_it).second = NULL;
954
955    nonSpecInsts.erase(inst_it);
956}
957
958template <class Impl>
959void
960InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
961{
962    DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
963            tid,inst);
964
965    ListIt iq_it = instList[tid].begin();
966
967    while (iq_it != instList[tid].end() &&
968           (*iq_it)->seqNum <= inst) {
969        ++iq_it;
970        instList[tid].pop_front();
971    }
972
973    assert(freeEntries == (numEntries - countInsts()));
974}
975
976template <class Impl>
977int
978InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
979{
980    int dependents = 0;
981
982    // The instruction queue here takes care of both floating and int ops
983    if (completed_inst->isFloating()) {
984        fpInstQueueWakeupAccesses++;
985    } else if (completed_inst->isVector()) {
986        vecInstQueueWakeupAccesses++;
987    } else {
988        intInstQueueWakeupAccesses++;
989    }
990
991    DPRINTF(IQ, "Waking dependents of completed instruction.\n");
992
993    assert(!completed_inst->isSquashed());
994
995    // Tell the memory dependence unit to wake any dependents on this
996    // instruction if it is a memory instruction.  Also complete the memory
997    // instruction at this point since we know it executed without issues.
998    // @todo: Might want to rename "completeMemInst" to something that
999    // indicates that it won't need to be replayed, and call this
1000    // earlier.  Might not be a big deal.
1001    if (completed_inst->isMemRef()) {
1002        memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
1003        completeMemInst(completed_inst);
1004    } else if (completed_inst->isMemBarrier() ||
1005               completed_inst->isWriteBarrier()) {
1006        memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
1007    }
1008
1009    for (int dest_reg_idx = 0;
1010         dest_reg_idx < completed_inst->numDestRegs();
1011         dest_reg_idx++)
1012    {
1013        PhysRegIdPtr dest_reg =
1014            completed_inst->renamedDestRegIdx(dest_reg_idx);
1015
1016        // Special case of uniq or control registers.  They are not
1017        // handled by the IQ and thus have no dependency graph entry.
1018        if (dest_reg->isFixedMapping()) {
1019            DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n",
1020                    dest_reg->index(), dest_reg->className());
1021            continue;
1022        }
1023
1024        DPRINTF(IQ, "Waking any dependents on register %i (%s).\n",
1025                dest_reg->index(),
1026                dest_reg->className());
1027
1028        //Go through the dependency chain, marking the registers as
1029        //ready within the waiting instructions.
1030        DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex());
1031
1032        while (dep_inst) {
1033            DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
1034                    "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
1035
1036            // Might want to give more information to the instruction
1037            // so that it knows which of its source registers is
1038            // ready.  However that would mean that the dependency
1039            // graph entries would need to hold the src_reg_idx.
1040            dep_inst->markSrcRegReady();
1041
1042            addIfReady(dep_inst);
1043
1044            dep_inst = dependGraph.pop(dest_reg->flatIndex());
1045
1046            ++dependents;
1047        }
1048
1049        // Reset the head node now that all of its dependents have
1050        // been woken up.
1051        assert(dependGraph.empty(dest_reg->flatIndex()));
1052        dependGraph.clearInst(dest_reg->flatIndex());
1053
1054        // Mark the scoreboard as having that register ready.
1055        regScoreboard[dest_reg->flatIndex()] = true;
1056    }
1057    return dependents;
1058}
1059
1060template <class Impl>
1061void
1062InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
1063{
1064    OpClass op_class = ready_inst->opClass();
1065
1066    readyInsts[op_class].push(ready_inst);
1067
1068    // Will need to reorder the list if either a queue is not on the list,
1069    // or it has an older instruction than last time.
1070    if (!queueOnList[op_class]) {
1071        addToOrderList(op_class);
1072    } else if (readyInsts[op_class].top()->seqNum  <
1073               (*readyIt[op_class]).oldestInst) {
1074        listOrder.erase(readyIt[op_class]);
1075        addToOrderList(op_class);
1076    }
1077
1078    DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1079            "the ready list, PC %s opclass:%i [sn:%lli].\n",
1080            ready_inst->pcState(), op_class, ready_inst->seqNum);
1081}
1082
1083template <class Impl>
1084void
1085InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
1086{
1087    DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
1088
1089    // Reset DTB translation state
1090    resched_inst->translationStarted(false);
1091    resched_inst->translationCompleted(false);
1092
1093    resched_inst->clearCanIssue();
1094    memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
1095}
1096
1097template <class Impl>
1098void
1099InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
1100{
1101    memDepUnit[replay_inst->threadNumber].replay();
1102}
1103
1104template <class Impl>
1105void
1106InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
1107{
1108    ThreadID tid = completed_inst->threadNumber;
1109
1110    DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n",
1111            completed_inst->pcState(), completed_inst->seqNum);
1112
1113    ++freeEntries;
1114
1115    completed_inst->memOpDone(true);
1116
1117    memDepUnit[tid].completed(completed_inst);
1118    count[tid]--;
1119}
1120
1121template <class Impl>
1122void
1123InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst)
1124{
1125    deferredMemInsts.push_back(deferred_inst);
1126}
1127
1128template <class Impl>
1129void
1130InstructionQueue<Impl>::blockMemInst(DynInstPtr &blocked_inst)
1131{
1132    blocked_inst->translationStarted(false);
1133    blocked_inst->translationCompleted(false);
1134
1135    blocked_inst->clearIssued();
1136    blocked_inst->clearCanIssue();
1137    blockedMemInsts.push_back(blocked_inst);
1138}
1139
1140template <class Impl>
1141void
1142InstructionQueue<Impl>::cacheUnblocked()
1143{
1144    retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts);
1145    // Get the CPU ticking again
1146    cpu->wakeCPU();
1147}
1148
1149template <class Impl>
1150typename Impl::DynInstPtr
1151InstructionQueue<Impl>::getDeferredMemInstToExecute()
1152{
1153    for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end();
1154         ++it) {
1155        if ((*it)->translationCompleted() || (*it)->isSquashed()) {
1156            DynInstPtr mem_inst = *it;
1157            deferredMemInsts.erase(it);
1158            return mem_inst;
1159        }
1160    }
1161    return nullptr;
1162}
1163
1164template <class Impl>
1165typename Impl::DynInstPtr
1166InstructionQueue<Impl>::getBlockedMemInstToExecute()
1167{
1168    if (retryMemInsts.empty()) {
1169        return nullptr;
1170    } else {
1171        DynInstPtr mem_inst = retryMemInsts.front();
1172        retryMemInsts.pop_front();
1173        return mem_inst;
1174    }
1175}
1176
1177template <class Impl>
1178void
1179InstructionQueue<Impl>::violation(DynInstPtr &store,
1180                                  DynInstPtr &faulting_load)
1181{
1182    intInstQueueWrites++;
1183    memDepUnit[store->threadNumber].violation(store, faulting_load);
1184}
1185
1186template <class Impl>
1187void
1188InstructionQueue<Impl>::squash(ThreadID tid)
1189{
1190    DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1191            "the IQ.\n", tid);
1192
1193    // Read instruction sequence number of last instruction out of the
1194    // time buffer.
1195    squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1196
1197    doSquash(tid);
1198
1199    // Also tell the memory dependence unit to squash.
1200    memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1201}
1202
1203template <class Impl>
1204void
1205InstructionQueue<Impl>::doSquash(ThreadID tid)
1206{
1207    // Start at the tail.
1208    ListIt squash_it = instList[tid].end();
1209    --squash_it;
1210
1211    DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1212            tid, squashedSeqNum[tid]);
1213
1214    // Squash any instructions younger than the squashed sequence number
1215    // given.
1216    while (squash_it != instList[tid].end() &&
1217           (*squash_it)->seqNum > squashedSeqNum[tid]) {
1218
1219        DynInstPtr squashed_inst = (*squash_it);
1220        if (squashed_inst->isFloating()) {
1221            fpInstQueueWrites++;
1222        } else if (squashed_inst->isVector()) {
1223            vecInstQueueWrites++;
1224        } else {
1225            intInstQueueWrites++;
1226        }
1227
1228        // Only handle the instruction if it actually is in the IQ and
1229        // hasn't already been squashed in the IQ.
1230        if (squashed_inst->threadNumber != tid ||
1231            squashed_inst->isSquashedInIQ()) {
1232            --squash_it;
1233            continue;
1234        }
1235
1236        if (!squashed_inst->isIssued() ||
1237            (squashed_inst->isMemRef() &&
1238             !squashed_inst->memOpDone())) {
1239
1240            DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
1241                    tid, squashed_inst->seqNum, squashed_inst->pcState());
1242
1243            bool is_acq_rel = squashed_inst->isMemBarrier() &&
1244                         (squashed_inst->isLoad() ||
1245                           (squashed_inst->isStore() &&
1246                             !squashed_inst->isStoreConditional()));
1247
1248            // Remove the instruction from the dependency list.
1249            if (is_acq_rel ||
1250                (!squashed_inst->isNonSpeculative() &&
1251                 !squashed_inst->isStoreConditional() &&
1252                 !squashed_inst->isMemBarrier() &&
1253                 !squashed_inst->isWriteBarrier())) {
1254
1255                for (int src_reg_idx = 0;
1256                     src_reg_idx < squashed_inst->numSrcRegs();
1257                     src_reg_idx++)
1258                {
1259                    PhysRegIdPtr src_reg =
1260                        squashed_inst->renamedSrcRegIdx(src_reg_idx);
1261
1262                    // Only remove it from the dependency graph if it
1263                    // was placed there in the first place.
1264
1265                    // Instead of doing a linked list traversal, we
1266                    // can just remove these squashed instructions
1267                    // either at issue time, or when the register is
1268                    // overwritten.  The only downside to this is it
1269                    // leaves more room for error.
1270
1271                    if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1272                        !src_reg->isFixedMapping()) {
1273                        dependGraph.remove(src_reg->flatIndex(),
1274                                           squashed_inst);
1275                    }
1276
1277
1278                    ++iqSquashedOperandsExamined;
1279                }
1280            } else if (!squashed_inst->isStoreConditional() ||
1281                       !squashed_inst->isCompleted()) {
1282                NonSpecMapIt ns_inst_it =
1283                    nonSpecInsts.find(squashed_inst->seqNum);
1284
1285                // we remove non-speculative instructions from
1286                // nonSpecInsts already when they are ready, and so we
1287                // cannot always expect to find them
1288                if (ns_inst_it == nonSpecInsts.end()) {
1289                    // loads that became ready but stalled on a
1290                    // blocked cache are alreayd removed from
1291                    // nonSpecInsts, and have not faulted
1292                    assert(squashed_inst->getFault() != NoFault ||
1293                           squashed_inst->isMemRef());
1294                } else {
1295
1296                    (*ns_inst_it).second = NULL;
1297
1298                    nonSpecInsts.erase(ns_inst_it);
1299
1300                    ++iqSquashedNonSpecRemoved;
1301                }
1302            }
1303
1304            // Might want to also clear out the head of the dependency graph.
1305
1306            // Mark it as squashed within the IQ.
1307            squashed_inst->setSquashedInIQ();
1308
1309            // @todo: Remove this hack where several statuses are set so the
1310            // inst will flow through the rest of the pipeline.
1311            squashed_inst->setIssued();
1312            squashed_inst->setCanCommit();
1313            squashed_inst->clearInIQ();
1314
1315            //Update Thread IQ Count
1316            count[squashed_inst->threadNumber]--;
1317
1318            ++freeEntries;
1319        }
1320
1321        instList[tid].erase(squash_it--);
1322        ++iqSquashedInstsExamined;
1323    }
1324}
1325
1326template <class Impl>
1327bool
1328InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1329{
1330    // Loop through the instruction's source registers, adding
1331    // them to the dependency list if they are not ready.
1332    int8_t total_src_regs = new_inst->numSrcRegs();
1333    bool return_val = false;
1334
1335    for (int src_reg_idx = 0;
1336         src_reg_idx < total_src_regs;
1337         src_reg_idx++)
1338    {
1339        // Only add it to the dependency graph if it's not ready.
1340        if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1341            PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1342
1343            // Check the IQ's scoreboard to make sure the register
1344            // hasn't become ready while the instruction was in flight
1345            // between stages.  Only if it really isn't ready should
1346            // it be added to the dependency graph.
1347            if (src_reg->isFixedMapping()) {
1348                continue;
1349            } else if (!regScoreboard[src_reg->flatIndex()]) {
1350                DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that "
1351                        "is being added to the dependency chain.\n",
1352                        new_inst->pcState(), src_reg->index(),
1353                        src_reg->className());
1354
1355                dependGraph.insert(src_reg->flatIndex(), new_inst);
1356
1357                // Change the return value to indicate that something
1358                // was added to the dependency graph.
1359                return_val = true;
1360            } else {
1361                DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that "
1362                        "became ready before it reached the IQ.\n",
1363                        new_inst->pcState(), src_reg->index(),
1364                        src_reg->className());
1365                // Mark a register ready within the instruction.
1366                new_inst->markSrcRegReady(src_reg_idx);
1367            }
1368        }
1369    }
1370
1371    return return_val;
1372}
1373
1374template <class Impl>
1375void
1376InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1377{
1378    // Nothing really needs to be marked when an instruction becomes
1379    // the producer of a register's value, but for convenience a ptr
1380    // to the producing instruction will be placed in the head node of
1381    // the dependency links.
1382    int8_t total_dest_regs = new_inst->numDestRegs();
1383
1384    for (int dest_reg_idx = 0;
1385         dest_reg_idx < total_dest_regs;
1386         dest_reg_idx++)
1387    {
1388        PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1389
1390        // Some registers have fixed mapping, and there is no need to track
1391        // dependencies as these instructions must be executed at commit.
1392        if (dest_reg->isFixedMapping()) {
1393            continue;
1394        }
1395
1396        if (!dependGraph.empty(dest_reg->flatIndex())) {
1397            dependGraph.dump();
1398            panic("Dependency graph %i (%s) (flat: %i) not empty!",
1399                  dest_reg->index(), dest_reg->className(),
1400                  dest_reg->flatIndex());
1401        }
1402
1403        dependGraph.setInst(dest_reg->flatIndex(), new_inst);
1404
1405        // Mark the scoreboard to say it's not yet ready.
1406        regScoreboard[dest_reg->flatIndex()] = false;
1407    }
1408}
1409
1410template <class Impl>
1411void
1412InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1413{
1414    // If the instruction now has all of its source registers
1415    // available, then add it to the list of ready instructions.
1416    if (inst->readyToIssue()) {
1417
1418        //Add the instruction to the proper ready list.
1419        if (inst->isMemRef()) {
1420
1421            DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1422
1423            // Message to the mem dependence unit that this instruction has
1424            // its registers ready.
1425            memDepUnit[inst->threadNumber].regsReady(inst);
1426
1427            return;
1428        }
1429
1430        OpClass op_class = inst->opClass();
1431
1432        DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1433                "the ready list, PC %s opclass:%i [sn:%lli].\n",
1434                inst->pcState(), op_class, inst->seqNum);
1435
1436        readyInsts[op_class].push(inst);
1437
1438        // Will need to reorder the list if either a queue is not on the list,
1439        // or it has an older instruction than last time.
1440        if (!queueOnList[op_class]) {
1441            addToOrderList(op_class);
1442        } else if (readyInsts[op_class].top()->seqNum  <
1443                   (*readyIt[op_class]).oldestInst) {
1444            listOrder.erase(readyIt[op_class]);
1445            addToOrderList(op_class);
1446        }
1447    }
1448}
1449
1450template <class Impl>
1451int
1452InstructionQueue<Impl>::countInsts()
1453{
1454#if 0
1455    //ksewell:This works but definitely could use a cleaner write
1456    //with a more intuitive way of counting. Right now it's
1457    //just brute force ....
1458    // Change the #if if you want to use this method.
1459    int total_insts = 0;
1460
1461    for (ThreadID tid = 0; tid < numThreads; ++tid) {
1462        ListIt count_it = instList[tid].begin();
1463
1464        while (count_it != instList[tid].end()) {
1465            if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1466                if (!(*count_it)->isIssued()) {
1467                    ++total_insts;
1468                } else if ((*count_it)->isMemRef() &&
1469                           !(*count_it)->memOpDone) {
1470                    // Loads that have not been marked as executed still count
1471                    // towards the total instructions.
1472                    ++total_insts;
1473                }
1474            }
1475
1476            ++count_it;
1477        }
1478    }
1479
1480    return total_insts;
1481#else
1482    return numEntries - freeEntries;
1483#endif
1484}
1485
1486template <class Impl>
1487void
1488InstructionQueue<Impl>::dumpLists()
1489{
1490    for (int i = 0; i < Num_OpClasses; ++i) {
1491        cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1492
1493        cprintf("\n");
1494    }
1495
1496    cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1497
1498    NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1499    NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1500
1501    cprintf("Non speculative list: ");
1502
1503    while (non_spec_it != non_spec_end_it) {
1504        cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(),
1505                (*non_spec_it).second->seqNum);
1506        ++non_spec_it;
1507    }
1508
1509    cprintf("\n");
1510
1511    ListOrderIt list_order_it = listOrder.begin();
1512    ListOrderIt list_order_end_it = listOrder.end();
1513    int i = 1;
1514
1515    cprintf("List order: ");
1516
1517    while (list_order_it != list_order_end_it) {
1518        cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1519                (*list_order_it).oldestInst);
1520
1521        ++list_order_it;
1522        ++i;
1523    }
1524
1525    cprintf("\n");
1526}
1527
1528
1529template <class Impl>
1530void
1531InstructionQueue<Impl>::dumpInsts()
1532{
1533    for (ThreadID tid = 0; tid < numThreads; ++tid) {
1534        int num = 0;
1535        int valid_num = 0;
1536        ListIt inst_list_it = instList[tid].begin();
1537
1538        while (inst_list_it != instList[tid].end()) {
1539            cprintf("Instruction:%i\n", num);
1540            if (!(*inst_list_it)->isSquashed()) {
1541                if (!(*inst_list_it)->isIssued()) {
1542                    ++valid_num;
1543                    cprintf("Count:%i\n", valid_num);
1544                } else if ((*inst_list_it)->isMemRef() &&
1545                           !(*inst_list_it)->memOpDone()) {
1546                    // Loads that have not been marked as executed
1547                    // still count towards the total instructions.
1548                    ++valid_num;
1549                    cprintf("Count:%i\n", valid_num);
1550                }
1551            }
1552
1553            cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1554                    "Issued:%i\nSquashed:%i\n",
1555                    (*inst_list_it)->pcState(),
1556                    (*inst_list_it)->seqNum,
1557                    (*inst_list_it)->threadNumber,
1558                    (*inst_list_it)->isIssued(),
1559                    (*inst_list_it)->isSquashed());
1560
1561            if ((*inst_list_it)->isMemRef()) {
1562                cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1563            }
1564
1565            cprintf("\n");
1566
1567            inst_list_it++;
1568            ++num;
1569        }
1570    }
1571
1572    cprintf("Insts to Execute list:\n");
1573
1574    int num = 0;
1575    int valid_num = 0;
1576    ListIt inst_list_it = instsToExecute.begin();
1577
1578    while (inst_list_it != instsToExecute.end())
1579    {
1580        cprintf("Instruction:%i\n",
1581                num);
1582        if (!(*inst_list_it)->isSquashed()) {
1583            if (!(*inst_list_it)->isIssued()) {
1584                ++valid_num;
1585                cprintf("Count:%i\n", valid_num);
1586            } else if ((*inst_list_it)->isMemRef() &&
1587                       !(*inst_list_it)->memOpDone()) {
1588                // Loads that have not been marked as executed
1589                // still count towards the total instructions.
1590                ++valid_num;
1591                cprintf("Count:%i\n", valid_num);
1592            }
1593        }
1594
1595        cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1596                "Issued:%i\nSquashed:%i\n",
1597                (*inst_list_it)->pcState(),
1598                (*inst_list_it)->seqNum,
1599                (*inst_list_it)->threadNumber,
1600                (*inst_list_it)->isIssued(),
1601                (*inst_list_it)->isSquashed());
1602
1603        if ((*inst_list_it)->isMemRef()) {
1604            cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1605        }
1606
1607        cprintf("\n");
1608
1609        inst_list_it++;
1610        ++num;
1611    }
1612}
1613
1614#endif//__CPU_O3_INST_QUEUE_IMPL_HH__
1615