inst_queue_impl.hh revision 12109
1/*
2 * Copyright (c) 2011-2014 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder.  You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
14 *
15 * Copyright (c) 2004-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Kevin Lim
42 *          Korey Sewell
43 */
44
45#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__
46#define __CPU_O3_INST_QUEUE_IMPL_HH__
47
48#include <limits>
49#include <vector>
50
51#include "cpu/o3/fu_pool.hh"
52#include "cpu/o3/inst_queue.hh"
53#include "debug/IQ.hh"
54#include "enums/OpClass.hh"
55#include "params/DerivO3CPU.hh"
56#include "sim/core.hh"
57
58// clang complains about std::set being overloaded with Packet::set if
59// we open up the entire namespace std
60using std::list;
61
62template <class Impl>
63InstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
64    int fu_idx, InstructionQueue<Impl> *iq_ptr)
65    : Event(Stat_Event_Pri, AutoDelete),
66      inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false)
67{
68}
69
70template <class Impl>
71void
72InstructionQueue<Impl>::FUCompletion::process()
73{
74    iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
75    inst = NULL;
76}
77
78
79template <class Impl>
80const char *
81InstructionQueue<Impl>::FUCompletion::description() const
82{
83    return "Functional unit completion";
84}
85
86template <class Impl>
87InstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
88                                         DerivO3CPUParams *params)
89    : cpu(cpu_ptr),
90      iewStage(iew_ptr),
91      fuPool(params->fuPool),
92      numEntries(params->numIQEntries),
93      totalWidth(params->issueWidth),
94      commitToIEWDelay(params->commitToIEWDelay)
95{
96    assert(fuPool);
97
98    numThreads = params->numThreads;
99
100    // Set the number of total physical registers
101    // As the vector registers have two addressing modes, they are added twice
102    numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs +
103                    params->numPhysVecRegs +
104                    params->numPhysVecRegs * TheISA::NumVecElemPerVecReg +
105                    params->numPhysCCRegs;
106
107    //Create an entry for each physical register within the
108    //dependency graph.
109    dependGraph.resize(numPhysRegs);
110
111    // Resize the register scoreboard.
112    regScoreboard.resize(numPhysRegs);
113
114    //Initialize Mem Dependence Units
115    for (ThreadID tid = 0; tid < numThreads; tid++) {
116        memDepUnit[tid].init(params, tid);
117        memDepUnit[tid].setIQ(this);
118    }
119
120    resetState();
121
122    std::string policy = params->smtIQPolicy;
123
124    //Convert string to lowercase
125    std::transform(policy.begin(), policy.end(), policy.begin(),
126                   (int(*)(int)) tolower);
127
128    //Figure out resource sharing policy
129    if (policy == "dynamic") {
130        iqPolicy = Dynamic;
131
132        //Set Max Entries to Total ROB Capacity
133        for (ThreadID tid = 0; tid < numThreads; tid++) {
134            maxEntries[tid] = numEntries;
135        }
136
137    } else if (policy == "partitioned") {
138        iqPolicy = Partitioned;
139
140        //@todo:make work if part_amt doesnt divide evenly.
141        int part_amt = numEntries / numThreads;
142
143        //Divide ROB up evenly
144        for (ThreadID tid = 0; tid < numThreads; tid++) {
145            maxEntries[tid] = part_amt;
146        }
147
148        DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
149                "%i entries per thread.\n",part_amt);
150    } else if (policy == "threshold") {
151        iqPolicy = Threshold;
152
153        double threshold =  (double)params->smtIQThreshold / 100;
154
155        int thresholdIQ = (int)((double)threshold * numEntries);
156
157        //Divide up by threshold amount
158        for (ThreadID tid = 0; tid < numThreads; tid++) {
159            maxEntries[tid] = thresholdIQ;
160        }
161
162        DPRINTF(IQ, "IQ sharing policy set to Threshold:"
163                "%i entries per thread.\n",thresholdIQ);
164   } else {
165       assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
166              "Partitioned, Threshold}");
167   }
168}
169
170template <class Impl>
171InstructionQueue<Impl>::~InstructionQueue()
172{
173    dependGraph.reset();
174#ifdef DEBUG
175    cprintf("Nodes traversed: %i, removed: %i\n",
176            dependGraph.nodesTraversed, dependGraph.nodesRemoved);
177#endif
178}
179
180template <class Impl>
181std::string
182InstructionQueue<Impl>::name() const
183{
184    return cpu->name() + ".iq";
185}
186
187template <class Impl>
188void
189InstructionQueue<Impl>::regStats()
190{
191    using namespace Stats;
192    iqInstsAdded
193        .name(name() + ".iqInstsAdded")
194        .desc("Number of instructions added to the IQ (excludes non-spec)")
195        .prereq(iqInstsAdded);
196
197    iqNonSpecInstsAdded
198        .name(name() + ".iqNonSpecInstsAdded")
199        .desc("Number of non-speculative instructions added to the IQ")
200        .prereq(iqNonSpecInstsAdded);
201
202    iqInstsIssued
203        .name(name() + ".iqInstsIssued")
204        .desc("Number of instructions issued")
205        .prereq(iqInstsIssued);
206
207    iqIntInstsIssued
208        .name(name() + ".iqIntInstsIssued")
209        .desc("Number of integer instructions issued")
210        .prereq(iqIntInstsIssued);
211
212    iqFloatInstsIssued
213        .name(name() + ".iqFloatInstsIssued")
214        .desc("Number of float instructions issued")
215        .prereq(iqFloatInstsIssued);
216
217    iqBranchInstsIssued
218        .name(name() + ".iqBranchInstsIssued")
219        .desc("Number of branch instructions issued")
220        .prereq(iqBranchInstsIssued);
221
222    iqMemInstsIssued
223        .name(name() + ".iqMemInstsIssued")
224        .desc("Number of memory instructions issued")
225        .prereq(iqMemInstsIssued);
226
227    iqMiscInstsIssued
228        .name(name() + ".iqMiscInstsIssued")
229        .desc("Number of miscellaneous instructions issued")
230        .prereq(iqMiscInstsIssued);
231
232    iqSquashedInstsIssued
233        .name(name() + ".iqSquashedInstsIssued")
234        .desc("Number of squashed instructions issued")
235        .prereq(iqSquashedInstsIssued);
236
237    iqSquashedInstsExamined
238        .name(name() + ".iqSquashedInstsExamined")
239        .desc("Number of squashed instructions iterated over during squash;"
240              " mainly for profiling")
241        .prereq(iqSquashedInstsExamined);
242
243    iqSquashedOperandsExamined
244        .name(name() + ".iqSquashedOperandsExamined")
245        .desc("Number of squashed operands that are examined and possibly "
246              "removed from graph")
247        .prereq(iqSquashedOperandsExamined);
248
249    iqSquashedNonSpecRemoved
250        .name(name() + ".iqSquashedNonSpecRemoved")
251        .desc("Number of squashed non-spec instructions that were removed")
252        .prereq(iqSquashedNonSpecRemoved);
253/*
254    queueResDist
255        .init(Num_OpClasses, 0, 99, 2)
256        .name(name() + ".IQ:residence:")
257        .desc("cycles from dispatch to issue")
258        .flags(total | pdf | cdf )
259        ;
260    for (int i = 0; i < Num_OpClasses; ++i) {
261        queueResDist.subname(i, opClassStrings[i]);
262    }
263*/
264    numIssuedDist
265        .init(0,totalWidth,1)
266        .name(name() + ".issued_per_cycle")
267        .desc("Number of insts issued each cycle")
268        .flags(pdf)
269        ;
270/*
271    dist_unissued
272        .init(Num_OpClasses+2)
273        .name(name() + ".unissued_cause")
274        .desc("Reason ready instruction not issued")
275        .flags(pdf | dist)
276        ;
277    for (int i=0; i < (Num_OpClasses + 2); ++i) {
278        dist_unissued.subname(i, unissued_names[i]);
279    }
280*/
281    statIssuedInstType
282        .init(numThreads,Enums::Num_OpClass)
283        .name(name() + ".FU_type")
284        .desc("Type of FU issued")
285        .flags(total | pdf | dist)
286        ;
287    statIssuedInstType.ysubnames(Enums::OpClassStrings);
288
289    //
290    //  How long did instructions for a particular FU type wait prior to issue
291    //
292/*
293    issueDelayDist
294        .init(Num_OpClasses,0,99,2)
295        .name(name() + ".")
296        .desc("cycles from operands ready to issue")
297        .flags(pdf | cdf)
298        ;
299
300    for (int i=0; i<Num_OpClasses; ++i) {
301        std::stringstream subname;
302        subname << opClassStrings[i] << "_delay";
303        issueDelayDist.subname(i, subname.str());
304    }
305*/
306    issueRate
307        .name(name() + ".rate")
308        .desc("Inst issue rate")
309        .flags(total)
310        ;
311    issueRate = iqInstsIssued / cpu->numCycles;
312
313    statFuBusy
314        .init(Num_OpClasses)
315        .name(name() + ".fu_full")
316        .desc("attempts to use FU when none available")
317        .flags(pdf | dist)
318        ;
319    for (int i=0; i < Num_OpClasses; ++i) {
320        statFuBusy.subname(i, Enums::OpClassStrings[i]);
321    }
322
323    fuBusy
324        .init(numThreads)
325        .name(name() + ".fu_busy_cnt")
326        .desc("FU busy when requested")
327        .flags(total)
328        ;
329
330    fuBusyRate
331        .name(name() + ".fu_busy_rate")
332        .desc("FU busy rate (busy events/executed inst)")
333        .flags(total)
334        ;
335    fuBusyRate = fuBusy / iqInstsIssued;
336
337    for (ThreadID tid = 0; tid < numThreads; tid++) {
338        // Tell mem dependence unit to reg stats as well.
339        memDepUnit[tid].regStats();
340    }
341
342    intInstQueueReads
343        .name(name() + ".int_inst_queue_reads")
344        .desc("Number of integer instruction queue reads")
345        .flags(total);
346
347    intInstQueueWrites
348        .name(name() + ".int_inst_queue_writes")
349        .desc("Number of integer instruction queue writes")
350        .flags(total);
351
352    intInstQueueWakeupAccesses
353        .name(name() + ".int_inst_queue_wakeup_accesses")
354        .desc("Number of integer instruction queue wakeup accesses")
355        .flags(total);
356
357    fpInstQueueReads
358        .name(name() + ".fp_inst_queue_reads")
359        .desc("Number of floating instruction queue reads")
360        .flags(total);
361
362    fpInstQueueWrites
363        .name(name() + ".fp_inst_queue_writes")
364        .desc("Number of floating instruction queue writes")
365        .flags(total);
366
367    fpInstQueueWakeupQccesses
368        .name(name() + ".fp_inst_queue_wakeup_accesses")
369        .desc("Number of floating instruction queue wakeup accesses")
370        .flags(total);
371
372    intAluAccesses
373        .name(name() + ".int_alu_accesses")
374        .desc("Number of integer alu accesses")
375        .flags(total);
376
377    fpAluAccesses
378        .name(name() + ".fp_alu_accesses")
379        .desc("Number of floating point alu accesses")
380        .flags(total);
381
382}
383
384template <class Impl>
385void
386InstructionQueue<Impl>::resetState()
387{
388    //Initialize thread IQ counts
389    for (ThreadID tid = 0; tid <numThreads; tid++) {
390        count[tid] = 0;
391        instList[tid].clear();
392    }
393
394    // Initialize the number of free IQ entries.
395    freeEntries = numEntries;
396
397    // Note that in actuality, the registers corresponding to the logical
398    // registers start off as ready.  However this doesn't matter for the
399    // IQ as the instruction should have been correctly told if those
400    // registers are ready in rename.  Thus it can all be initialized as
401    // unready.
402    for (int i = 0; i < numPhysRegs; ++i) {
403        regScoreboard[i] = false;
404    }
405
406    for (ThreadID tid = 0; tid < numThreads; ++tid) {
407        squashedSeqNum[tid] = 0;
408    }
409
410    for (int i = 0; i < Num_OpClasses; ++i) {
411        while (!readyInsts[i].empty())
412            readyInsts[i].pop();
413        queueOnList[i] = false;
414        readyIt[i] = listOrder.end();
415    }
416    nonSpecInsts.clear();
417    listOrder.clear();
418    deferredMemInsts.clear();
419    blockedMemInsts.clear();
420    retryMemInsts.clear();
421    wbOutstanding = 0;
422}
423
424template <class Impl>
425void
426InstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
427{
428    activeThreads = at_ptr;
429}
430
431template <class Impl>
432void
433InstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
434{
435      issueToExecuteQueue = i2e_ptr;
436}
437
438template <class Impl>
439void
440InstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
441{
442    timeBuffer = tb_ptr;
443
444    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
445}
446
447template <class Impl>
448bool
449InstructionQueue<Impl>::isDrained() const
450{
451    bool drained = dependGraph.empty() &&
452                   instsToExecute.empty() &&
453                   wbOutstanding == 0;
454    for (ThreadID tid = 0; tid < numThreads; ++tid)
455        drained = drained && memDepUnit[tid].isDrained();
456
457    return drained;
458}
459
460template <class Impl>
461void
462InstructionQueue<Impl>::drainSanityCheck() const
463{
464    assert(dependGraph.empty());
465    assert(instsToExecute.empty());
466    for (ThreadID tid = 0; tid < numThreads; ++tid)
467        memDepUnit[tid].drainSanityCheck();
468}
469
470template <class Impl>
471void
472InstructionQueue<Impl>::takeOverFrom()
473{
474    resetState();
475}
476
477template <class Impl>
478int
479InstructionQueue<Impl>::entryAmount(ThreadID num_threads)
480{
481    if (iqPolicy == Partitioned) {
482        return numEntries / num_threads;
483    } else {
484        return 0;
485    }
486}
487
488
489template <class Impl>
490void
491InstructionQueue<Impl>::resetEntries()
492{
493    if (iqPolicy != Dynamic || numThreads > 1) {
494        int active_threads = activeThreads->size();
495
496        list<ThreadID>::iterator threads = activeThreads->begin();
497        list<ThreadID>::iterator end = activeThreads->end();
498
499        while (threads != end) {
500            ThreadID tid = *threads++;
501
502            if (iqPolicy == Partitioned) {
503                maxEntries[tid] = numEntries / active_threads;
504            } else if (iqPolicy == Threshold && active_threads == 1) {
505                maxEntries[tid] = numEntries;
506            }
507        }
508    }
509}
510
511template <class Impl>
512unsigned
513InstructionQueue<Impl>::numFreeEntries()
514{
515    return freeEntries;
516}
517
518template <class Impl>
519unsigned
520InstructionQueue<Impl>::numFreeEntries(ThreadID tid)
521{
522    return maxEntries[tid] - count[tid];
523}
524
525// Might want to do something more complex if it knows how many instructions
526// will be issued this cycle.
527template <class Impl>
528bool
529InstructionQueue<Impl>::isFull()
530{
531    if (freeEntries == 0) {
532        return(true);
533    } else {
534        return(false);
535    }
536}
537
538template <class Impl>
539bool
540InstructionQueue<Impl>::isFull(ThreadID tid)
541{
542    if (numFreeEntries(tid) == 0) {
543        return(true);
544    } else {
545        return(false);
546    }
547}
548
549template <class Impl>
550bool
551InstructionQueue<Impl>::hasReadyInsts()
552{
553    if (!listOrder.empty()) {
554        return true;
555    }
556
557    for (int i = 0; i < Num_OpClasses; ++i) {
558        if (!readyInsts[i].empty()) {
559            return true;
560        }
561    }
562
563    return false;
564}
565
566template <class Impl>
567void
568InstructionQueue<Impl>::insert(DynInstPtr &new_inst)
569{
570    new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
571    // Make sure the instruction is valid
572    assert(new_inst);
573
574    DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n",
575            new_inst->seqNum, new_inst->pcState());
576
577    assert(freeEntries != 0);
578
579    instList[new_inst->threadNumber].push_back(new_inst);
580
581    --freeEntries;
582
583    new_inst->setInIQ();
584
585    // Look through its source registers (physical regs), and mark any
586    // dependencies.
587    addToDependents(new_inst);
588
589    // Have this instruction set itself as the producer of its destination
590    // register(s).
591    addToProducers(new_inst);
592
593    if (new_inst->isMemRef()) {
594        memDepUnit[new_inst->threadNumber].insert(new_inst);
595    } else {
596        addIfReady(new_inst);
597    }
598
599    ++iqInstsAdded;
600
601    count[new_inst->threadNumber]++;
602
603    assert(freeEntries == (numEntries - countInsts()));
604}
605
606template <class Impl>
607void
608InstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
609{
610    // @todo: Clean up this code; can do it by setting inst as unable
611    // to issue, then calling normal insert on the inst.
612    new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
613
614    assert(new_inst);
615
616    nonSpecInsts[new_inst->seqNum] = new_inst;
617
618    DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s "
619            "to the IQ.\n",
620            new_inst->seqNum, new_inst->pcState());
621
622    assert(freeEntries != 0);
623
624    instList[new_inst->threadNumber].push_back(new_inst);
625
626    --freeEntries;
627
628    new_inst->setInIQ();
629
630    // Have this instruction set itself as the producer of its destination
631    // register(s).
632    addToProducers(new_inst);
633
634    // If it's a memory instruction, add it to the memory dependency
635    // unit.
636    if (new_inst->isMemRef()) {
637        memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
638    }
639
640    ++iqNonSpecInstsAdded;
641
642    count[new_inst->threadNumber]++;
643
644    assert(freeEntries == (numEntries - countInsts()));
645}
646
647template <class Impl>
648void
649InstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
650{
651    memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
652
653    insertNonSpec(barr_inst);
654}
655
656template <class Impl>
657typename Impl::DynInstPtr
658InstructionQueue<Impl>::getInstToExecute()
659{
660    assert(!instsToExecute.empty());
661    DynInstPtr inst = instsToExecute.front();
662    instsToExecute.pop_front();
663    if (inst->isFloating()){
664        fpInstQueueReads++;
665    } else {
666        intInstQueueReads++;
667    }
668    return inst;
669}
670
671template <class Impl>
672void
673InstructionQueue<Impl>::addToOrderList(OpClass op_class)
674{
675    assert(!readyInsts[op_class].empty());
676
677    ListOrderEntry queue_entry;
678
679    queue_entry.queueType = op_class;
680
681    queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
682
683    ListOrderIt list_it = listOrder.begin();
684    ListOrderIt list_end_it = listOrder.end();
685
686    while (list_it != list_end_it) {
687        if ((*list_it).oldestInst > queue_entry.oldestInst) {
688            break;
689        }
690
691        list_it++;
692    }
693
694    readyIt[op_class] = listOrder.insert(list_it, queue_entry);
695    queueOnList[op_class] = true;
696}
697
698template <class Impl>
699void
700InstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
701{
702    // Get iterator of next item on the list
703    // Delete the original iterator
704    // Determine if the next item is either the end of the list or younger
705    // than the new instruction.  If so, then add in a new iterator right here.
706    // If not, then move along.
707    ListOrderEntry queue_entry;
708    OpClass op_class = (*list_order_it).queueType;
709    ListOrderIt next_it = list_order_it;
710
711    ++next_it;
712
713    queue_entry.queueType = op_class;
714    queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
715
716    while (next_it != listOrder.end() &&
717           (*next_it).oldestInst < queue_entry.oldestInst) {
718        ++next_it;
719    }
720
721    readyIt[op_class] = listOrder.insert(next_it, queue_entry);
722}
723
724template <class Impl>
725void
726InstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
727{
728    DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
729    assert(!cpu->switchedOut());
730    // The CPU could have been sleeping until this op completed (*extremely*
731    // long latency op).  Wake it if it was.  This may be overkill.
732   --wbOutstanding;
733    iewStage->wakeCPU();
734
735    if (fu_idx > -1)
736        fuPool->freeUnitNextCycle(fu_idx);
737
738    // @todo: Ensure that these FU Completions happen at the beginning
739    // of a cycle, otherwise they could add too many instructions to
740    // the queue.
741    issueToExecuteQueue->access(-1)->size++;
742    instsToExecute.push_back(inst);
743}
744
745// @todo: Figure out a better way to remove the squashed items from the
746// lists.  Checking the top item of each list to see if it's squashed
747// wastes time and forces jumps.
748template <class Impl>
749void
750InstructionQueue<Impl>::scheduleReadyInsts()
751{
752    DPRINTF(IQ, "Attempting to schedule ready instructions from "
753            "the IQ.\n");
754
755    IssueStruct *i2e_info = issueToExecuteQueue->access(0);
756
757    DynInstPtr mem_inst;
758    while (mem_inst = getDeferredMemInstToExecute()) {
759        addReadyMemInst(mem_inst);
760    }
761
762    // See if any cache blocked instructions are able to be executed
763    while (mem_inst = getBlockedMemInstToExecute()) {
764        addReadyMemInst(mem_inst);
765    }
766
767    // Have iterator to head of the list
768    // While I haven't exceeded bandwidth or reached the end of the list,
769    // Try to get a FU that can do what this op needs.
770    // If successful, change the oldestInst to the new top of the list, put
771    // the queue in the proper place in the list.
772    // Increment the iterator.
773    // This will avoid trying to schedule a certain op class if there are no
774    // FUs that handle it.
775    int total_issued = 0;
776    ListOrderIt order_it = listOrder.begin();
777    ListOrderIt order_end_it = listOrder.end();
778
779    while (total_issued < totalWidth && order_it != order_end_it) {
780        OpClass op_class = (*order_it).queueType;
781
782        assert(!readyInsts[op_class].empty());
783
784        DynInstPtr issuing_inst = readyInsts[op_class].top();
785
786        issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++;
787
788        assert(issuing_inst->seqNum == (*order_it).oldestInst);
789
790        if (issuing_inst->isSquashed()) {
791            readyInsts[op_class].pop();
792
793            if (!readyInsts[op_class].empty()) {
794                moveToYoungerInst(order_it);
795            } else {
796                readyIt[op_class] = listOrder.end();
797                queueOnList[op_class] = false;
798            }
799
800            listOrder.erase(order_it++);
801
802            ++iqSquashedInstsIssued;
803
804            continue;
805        }
806
807        int idx = FUPool::NoCapableFU;
808        Cycles op_latency = Cycles(1);
809        ThreadID tid = issuing_inst->threadNumber;
810
811        if (op_class != No_OpClass) {
812            idx = fuPool->getUnit(op_class);
813            issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++;
814            if (idx > FUPool::NoFreeFU) {
815                op_latency = fuPool->getOpLatency(op_class);
816            }
817        }
818
819        // If we have an instruction that doesn't require a FU, or a
820        // valid FU, then schedule for execution.
821        if (idx != FUPool::NoFreeFU) {
822            if (op_latency == Cycles(1)) {
823                i2e_info->size++;
824                instsToExecute.push_back(issuing_inst);
825
826                // Add the FU onto the list of FU's to be freed next
827                // cycle if we used one.
828                if (idx >= 0)
829                    fuPool->freeUnitNextCycle(idx);
830            } else {
831                bool pipelined = fuPool->isPipelined(op_class);
832                // Generate completion event for the FU
833                ++wbOutstanding;
834                FUCompletion *execution = new FUCompletion(issuing_inst,
835                                                           idx, this);
836
837                cpu->schedule(execution,
838                              cpu->clockEdge(Cycles(op_latency - 1)));
839
840                if (!pipelined) {
841                    // If FU isn't pipelined, then it must be freed
842                    // upon the execution completing.
843                    execution->setFreeFU();
844                } else {
845                    // Add the FU onto the list of FU's to be freed next cycle.
846                    fuPool->freeUnitNextCycle(idx);
847                }
848            }
849
850            DPRINTF(IQ, "Thread %i: Issuing instruction PC %s "
851                    "[sn:%lli]\n",
852                    tid, issuing_inst->pcState(),
853                    issuing_inst->seqNum);
854
855            readyInsts[op_class].pop();
856
857            if (!readyInsts[op_class].empty()) {
858                moveToYoungerInst(order_it);
859            } else {
860                readyIt[op_class] = listOrder.end();
861                queueOnList[op_class] = false;
862            }
863
864            issuing_inst->setIssued();
865            ++total_issued;
866
867#if TRACING_ON
868            issuing_inst->issueTick = curTick() - issuing_inst->fetchTick;
869#endif
870
871            if (!issuing_inst->isMemRef()) {
872                // Memory instructions can not be freed from the IQ until they
873                // complete.
874                ++freeEntries;
875                count[tid]--;
876                issuing_inst->clearInIQ();
877            } else {
878                memDepUnit[tid].issue(issuing_inst);
879            }
880
881            listOrder.erase(order_it++);
882            statIssuedInstType[tid][op_class]++;
883        } else {
884            statFuBusy[op_class]++;
885            fuBusy[tid]++;
886            ++order_it;
887        }
888    }
889
890    numIssuedDist.sample(total_issued);
891    iqInstsIssued+= total_issued;
892
893    // If we issued any instructions, tell the CPU we had activity.
894    // @todo If the way deferred memory instructions are handeled due to
895    // translation changes then the deferredMemInsts condition should be removed
896    // from the code below.
897    if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) {
898        cpu->activityThisCycle();
899    } else {
900        DPRINTF(IQ, "Not able to schedule any instructions.\n");
901    }
902}
903
904template <class Impl>
905void
906InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
907{
908    DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
909            "to execute.\n", inst);
910
911    NonSpecMapIt inst_it = nonSpecInsts.find(inst);
912
913    assert(inst_it != nonSpecInsts.end());
914
915    ThreadID tid = (*inst_it).second->threadNumber;
916
917    (*inst_it).second->setAtCommit();
918
919    (*inst_it).second->setCanIssue();
920
921    if (!(*inst_it).second->isMemRef()) {
922        addIfReady((*inst_it).second);
923    } else {
924        memDepUnit[tid].nonSpecInstReady((*inst_it).second);
925    }
926
927    (*inst_it).second = NULL;
928
929    nonSpecInsts.erase(inst_it);
930}
931
932template <class Impl>
933void
934InstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
935{
936    DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
937            tid,inst);
938
939    ListIt iq_it = instList[tid].begin();
940
941    while (iq_it != instList[tid].end() &&
942           (*iq_it)->seqNum <= inst) {
943        ++iq_it;
944        instList[tid].pop_front();
945    }
946
947    assert(freeEntries == (numEntries - countInsts()));
948}
949
950template <class Impl>
951int
952InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
953{
954    int dependents = 0;
955
956    // The instruction queue here takes care of both floating and int ops
957    if (completed_inst->isFloating()) {
958        fpInstQueueWakeupQccesses++;
959    } else {
960        intInstQueueWakeupAccesses++;
961    }
962
963    DPRINTF(IQ, "Waking dependents of completed instruction.\n");
964
965    assert(!completed_inst->isSquashed());
966
967    // Tell the memory dependence unit to wake any dependents on this
968    // instruction if it is a memory instruction.  Also complete the memory
969    // instruction at this point since we know it executed without issues.
970    // @todo: Might want to rename "completeMemInst" to something that
971    // indicates that it won't need to be replayed, and call this
972    // earlier.  Might not be a big deal.
973    if (completed_inst->isMemRef()) {
974        memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
975        completeMemInst(completed_inst);
976    } else if (completed_inst->isMemBarrier() ||
977               completed_inst->isWriteBarrier()) {
978        memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
979    }
980
981    for (int dest_reg_idx = 0;
982         dest_reg_idx < completed_inst->numDestRegs();
983         dest_reg_idx++)
984    {
985        PhysRegIdPtr dest_reg =
986            completed_inst->renamedDestRegIdx(dest_reg_idx);
987
988        // Special case of uniq or control registers.  They are not
989        // handled by the IQ and thus have no dependency graph entry.
990        if (dest_reg->isFixedMapping()) {
991            DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n",
992                    dest_reg->index(), dest_reg->className());
993            continue;
994        }
995
996        DPRINTF(IQ, "Waking any dependents on register %i (%s).\n",
997                dest_reg->index(),
998                dest_reg->className());
999
1000        //Go through the dependency chain, marking the registers as
1001        //ready within the waiting instructions.
1002        DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex());
1003
1004        while (dep_inst) {
1005            DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
1006                    "PC %s.\n", dep_inst->seqNum, dep_inst->pcState());
1007
1008            // Might want to give more information to the instruction
1009            // so that it knows which of its source registers is
1010            // ready.  However that would mean that the dependency
1011            // graph entries would need to hold the src_reg_idx.
1012            dep_inst->markSrcRegReady();
1013
1014            addIfReady(dep_inst);
1015
1016            dep_inst = dependGraph.pop(dest_reg->flatIndex());
1017
1018            ++dependents;
1019        }
1020
1021        // Reset the head node now that all of its dependents have
1022        // been woken up.
1023        assert(dependGraph.empty(dest_reg->flatIndex()));
1024        dependGraph.clearInst(dest_reg->flatIndex());
1025
1026        // Mark the scoreboard as having that register ready.
1027        regScoreboard[dest_reg->flatIndex()] = true;
1028    }
1029    return dependents;
1030}
1031
1032template <class Impl>
1033void
1034InstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
1035{
1036    OpClass op_class = ready_inst->opClass();
1037
1038    readyInsts[op_class].push(ready_inst);
1039
1040    // Will need to reorder the list if either a queue is not on the list,
1041    // or it has an older instruction than last time.
1042    if (!queueOnList[op_class]) {
1043        addToOrderList(op_class);
1044    } else if (readyInsts[op_class].top()->seqNum  <
1045               (*readyIt[op_class]).oldestInst) {
1046        listOrder.erase(readyIt[op_class]);
1047        addToOrderList(op_class);
1048    }
1049
1050    DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1051            "the ready list, PC %s opclass:%i [sn:%lli].\n",
1052            ready_inst->pcState(), op_class, ready_inst->seqNum);
1053}
1054
1055template <class Impl>
1056void
1057InstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
1058{
1059    DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
1060
1061    // Reset DTB translation state
1062    resched_inst->translationStarted(false);
1063    resched_inst->translationCompleted(false);
1064
1065    resched_inst->clearCanIssue();
1066    memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
1067}
1068
1069template <class Impl>
1070void
1071InstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
1072{
1073    memDepUnit[replay_inst->threadNumber].replay();
1074}
1075
1076template <class Impl>
1077void
1078InstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
1079{
1080    ThreadID tid = completed_inst->threadNumber;
1081
1082    DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n",
1083            completed_inst->pcState(), completed_inst->seqNum);
1084
1085    ++freeEntries;
1086
1087    completed_inst->memOpDone(true);
1088
1089    memDepUnit[tid].completed(completed_inst);
1090    count[tid]--;
1091}
1092
1093template <class Impl>
1094void
1095InstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst)
1096{
1097    deferredMemInsts.push_back(deferred_inst);
1098}
1099
1100template <class Impl>
1101void
1102InstructionQueue<Impl>::blockMemInst(DynInstPtr &blocked_inst)
1103{
1104    blocked_inst->translationStarted(false);
1105    blocked_inst->translationCompleted(false);
1106
1107    blocked_inst->clearIssued();
1108    blocked_inst->clearCanIssue();
1109    blockedMemInsts.push_back(blocked_inst);
1110}
1111
1112template <class Impl>
1113void
1114InstructionQueue<Impl>::cacheUnblocked()
1115{
1116    retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts);
1117    // Get the CPU ticking again
1118    cpu->wakeCPU();
1119}
1120
1121template <class Impl>
1122typename Impl::DynInstPtr
1123InstructionQueue<Impl>::getDeferredMemInstToExecute()
1124{
1125    for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end();
1126         ++it) {
1127        if ((*it)->translationCompleted() || (*it)->isSquashed()) {
1128            DynInstPtr mem_inst = *it;
1129            deferredMemInsts.erase(it);
1130            return mem_inst;
1131        }
1132    }
1133    return nullptr;
1134}
1135
1136template <class Impl>
1137typename Impl::DynInstPtr
1138InstructionQueue<Impl>::getBlockedMemInstToExecute()
1139{
1140    if (retryMemInsts.empty()) {
1141        return nullptr;
1142    } else {
1143        DynInstPtr mem_inst = retryMemInsts.front();
1144        retryMemInsts.pop_front();
1145        return mem_inst;
1146    }
1147}
1148
1149template <class Impl>
1150void
1151InstructionQueue<Impl>::violation(DynInstPtr &store,
1152                                  DynInstPtr &faulting_load)
1153{
1154    intInstQueueWrites++;
1155    memDepUnit[store->threadNumber].violation(store, faulting_load);
1156}
1157
1158template <class Impl>
1159void
1160InstructionQueue<Impl>::squash(ThreadID tid)
1161{
1162    DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
1163            "the IQ.\n", tid);
1164
1165    // Read instruction sequence number of last instruction out of the
1166    // time buffer.
1167    squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
1168
1169    doSquash(tid);
1170
1171    // Also tell the memory dependence unit to squash.
1172    memDepUnit[tid].squash(squashedSeqNum[tid], tid);
1173}
1174
1175template <class Impl>
1176void
1177InstructionQueue<Impl>::doSquash(ThreadID tid)
1178{
1179    // Start at the tail.
1180    ListIt squash_it = instList[tid].end();
1181    --squash_it;
1182
1183    DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
1184            tid, squashedSeqNum[tid]);
1185
1186    // Squash any instructions younger than the squashed sequence number
1187    // given.
1188    while (squash_it != instList[tid].end() &&
1189           (*squash_it)->seqNum > squashedSeqNum[tid]) {
1190
1191        DynInstPtr squashed_inst = (*squash_it);
1192        squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++;
1193
1194        // Only handle the instruction if it actually is in the IQ and
1195        // hasn't already been squashed in the IQ.
1196        if (squashed_inst->threadNumber != tid ||
1197            squashed_inst->isSquashedInIQ()) {
1198            --squash_it;
1199            continue;
1200        }
1201
1202        if (!squashed_inst->isIssued() ||
1203            (squashed_inst->isMemRef() &&
1204             !squashed_inst->memOpDone())) {
1205
1206            DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n",
1207                    tid, squashed_inst->seqNum, squashed_inst->pcState());
1208
1209            bool is_acq_rel = squashed_inst->isMemBarrier() &&
1210                         (squashed_inst->isLoad() ||
1211                           (squashed_inst->isStore() &&
1212                             !squashed_inst->isStoreConditional()));
1213
1214            // Remove the instruction from the dependency list.
1215            if (is_acq_rel ||
1216                (!squashed_inst->isNonSpeculative() &&
1217                 !squashed_inst->isStoreConditional() &&
1218                 !squashed_inst->isMemBarrier() &&
1219                 !squashed_inst->isWriteBarrier())) {
1220
1221                for (int src_reg_idx = 0;
1222                     src_reg_idx < squashed_inst->numSrcRegs();
1223                     src_reg_idx++)
1224                {
1225                    PhysRegIdPtr src_reg =
1226                        squashed_inst->renamedSrcRegIdx(src_reg_idx);
1227
1228                    // Only remove it from the dependency graph if it
1229                    // was placed there in the first place.
1230
1231                    // Instead of doing a linked list traversal, we
1232                    // can just remove these squashed instructions
1233                    // either at issue time, or when the register is
1234                    // overwritten.  The only downside to this is it
1235                    // leaves more room for error.
1236
1237                    if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
1238                        !src_reg->isFixedMapping()) {
1239                        dependGraph.remove(src_reg->flatIndex(),
1240                                           squashed_inst);
1241                    }
1242
1243
1244                    ++iqSquashedOperandsExamined;
1245                }
1246            } else if (!squashed_inst->isStoreConditional() ||
1247                       !squashed_inst->isCompleted()) {
1248                NonSpecMapIt ns_inst_it =
1249                    nonSpecInsts.find(squashed_inst->seqNum);
1250
1251                // we remove non-speculative instructions from
1252                // nonSpecInsts already when they are ready, and so we
1253                // cannot always expect to find them
1254                if (ns_inst_it == nonSpecInsts.end()) {
1255                    // loads that became ready but stalled on a
1256                    // blocked cache are alreayd removed from
1257                    // nonSpecInsts, and have not faulted
1258                    assert(squashed_inst->getFault() != NoFault ||
1259                           squashed_inst->isMemRef());
1260                } else {
1261
1262                    (*ns_inst_it).second = NULL;
1263
1264                    nonSpecInsts.erase(ns_inst_it);
1265
1266                    ++iqSquashedNonSpecRemoved;
1267                }
1268            }
1269
1270            // Might want to also clear out the head of the dependency graph.
1271
1272            // Mark it as squashed within the IQ.
1273            squashed_inst->setSquashedInIQ();
1274
1275            // @todo: Remove this hack where several statuses are set so the
1276            // inst will flow through the rest of the pipeline.
1277            squashed_inst->setIssued();
1278            squashed_inst->setCanCommit();
1279            squashed_inst->clearInIQ();
1280
1281            //Update Thread IQ Count
1282            count[squashed_inst->threadNumber]--;
1283
1284            ++freeEntries;
1285        }
1286
1287        instList[tid].erase(squash_it--);
1288        ++iqSquashedInstsExamined;
1289    }
1290}
1291
1292template <class Impl>
1293bool
1294InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1295{
1296    // Loop through the instruction's source registers, adding
1297    // them to the dependency list if they are not ready.
1298    int8_t total_src_regs = new_inst->numSrcRegs();
1299    bool return_val = false;
1300
1301    for (int src_reg_idx = 0;
1302         src_reg_idx < total_src_regs;
1303         src_reg_idx++)
1304    {
1305        // Only add it to the dependency graph if it's not ready.
1306        if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1307            PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1308
1309            // Check the IQ's scoreboard to make sure the register
1310            // hasn't become ready while the instruction was in flight
1311            // between stages.  Only if it really isn't ready should
1312            // it be added to the dependency graph.
1313            if (src_reg->isFixedMapping()) {
1314                continue;
1315            } else if (!regScoreboard[src_reg->flatIndex()]) {
1316                DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that "
1317                        "is being added to the dependency chain.\n",
1318                        new_inst->pcState(), src_reg->index(),
1319                        src_reg->className());
1320
1321                dependGraph.insert(src_reg->flatIndex(), new_inst);
1322
1323                // Change the return value to indicate that something
1324                // was added to the dependency graph.
1325                return_val = true;
1326            } else {
1327                DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that "
1328                        "became ready before it reached the IQ.\n",
1329                        new_inst->pcState(), src_reg->index(),
1330                        src_reg->className());
1331                // Mark a register ready within the instruction.
1332                new_inst->markSrcRegReady(src_reg_idx);
1333            }
1334        }
1335    }
1336
1337    return return_val;
1338}
1339
1340template <class Impl>
1341void
1342InstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
1343{
1344    // Nothing really needs to be marked when an instruction becomes
1345    // the producer of a register's value, but for convenience a ptr
1346    // to the producing instruction will be placed in the head node of
1347    // the dependency links.
1348    int8_t total_dest_regs = new_inst->numDestRegs();
1349
1350    for (int dest_reg_idx = 0;
1351         dest_reg_idx < total_dest_regs;
1352         dest_reg_idx++)
1353    {
1354        PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1355
1356        // Some registers have fixed mapping, and there is no need to track
1357        // dependencies as these instructions must be executed at commit.
1358        if (dest_reg->isFixedMapping()) {
1359            continue;
1360        }
1361
1362        if (!dependGraph.empty(dest_reg->flatIndex())) {
1363            dependGraph.dump();
1364            panic("Dependency graph %i (%s) (flat: %i) not empty!",
1365                  dest_reg->index(), dest_reg->className(),
1366                  dest_reg->flatIndex());
1367        }
1368
1369        dependGraph.setInst(dest_reg->flatIndex(), new_inst);
1370
1371        // Mark the scoreboard to say it's not yet ready.
1372        regScoreboard[dest_reg->flatIndex()] = false;
1373    }
1374}
1375
1376template <class Impl>
1377void
1378InstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
1379{
1380    // If the instruction now has all of its source registers
1381    // available, then add it to the list of ready instructions.
1382    if (inst->readyToIssue()) {
1383
1384        //Add the instruction to the proper ready list.
1385        if (inst->isMemRef()) {
1386
1387            DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1388
1389            // Message to the mem dependence unit that this instruction has
1390            // its registers ready.
1391            memDepUnit[inst->threadNumber].regsReady(inst);
1392
1393            return;
1394        }
1395
1396        OpClass op_class = inst->opClass();
1397
1398        DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1399                "the ready list, PC %s opclass:%i [sn:%lli].\n",
1400                inst->pcState(), op_class, inst->seqNum);
1401
1402        readyInsts[op_class].push(inst);
1403
1404        // Will need to reorder the list if either a queue is not on the list,
1405        // or it has an older instruction than last time.
1406        if (!queueOnList[op_class]) {
1407            addToOrderList(op_class);
1408        } else if (readyInsts[op_class].top()->seqNum  <
1409                   (*readyIt[op_class]).oldestInst) {
1410            listOrder.erase(readyIt[op_class]);
1411            addToOrderList(op_class);
1412        }
1413    }
1414}
1415
1416template <class Impl>
1417int
1418InstructionQueue<Impl>::countInsts()
1419{
1420#if 0
1421    //ksewell:This works but definitely could use a cleaner write
1422    //with a more intuitive way of counting. Right now it's
1423    //just brute force ....
1424    // Change the #if if you want to use this method.
1425    int total_insts = 0;
1426
1427    for (ThreadID tid = 0; tid < numThreads; ++tid) {
1428        ListIt count_it = instList[tid].begin();
1429
1430        while (count_it != instList[tid].end()) {
1431            if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1432                if (!(*count_it)->isIssued()) {
1433                    ++total_insts;
1434                } else if ((*count_it)->isMemRef() &&
1435                           !(*count_it)->memOpDone) {
1436                    // Loads that have not been marked as executed still count
1437                    // towards the total instructions.
1438                    ++total_insts;
1439                }
1440            }
1441
1442            ++count_it;
1443        }
1444    }
1445
1446    return total_insts;
1447#else
1448    return numEntries - freeEntries;
1449#endif
1450}
1451
1452template <class Impl>
1453void
1454InstructionQueue<Impl>::dumpLists()
1455{
1456    for (int i = 0; i < Num_OpClasses; ++i) {
1457        cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
1458
1459        cprintf("\n");
1460    }
1461
1462    cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1463
1464    NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1465    NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1466
1467    cprintf("Non speculative list: ");
1468
1469    while (non_spec_it != non_spec_end_it) {
1470        cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(),
1471                (*non_spec_it).second->seqNum);
1472        ++non_spec_it;
1473    }
1474
1475    cprintf("\n");
1476
1477    ListOrderIt list_order_it = listOrder.begin();
1478    ListOrderIt list_order_end_it = listOrder.end();
1479    int i = 1;
1480
1481    cprintf("List order: ");
1482
1483    while (list_order_it != list_order_end_it) {
1484        cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1485                (*list_order_it).oldestInst);
1486
1487        ++list_order_it;
1488        ++i;
1489    }
1490
1491    cprintf("\n");
1492}
1493
1494
1495template <class Impl>
1496void
1497InstructionQueue<Impl>::dumpInsts()
1498{
1499    for (ThreadID tid = 0; tid < numThreads; ++tid) {
1500        int num = 0;
1501        int valid_num = 0;
1502        ListIt inst_list_it = instList[tid].begin();
1503
1504        while (inst_list_it != instList[tid].end()) {
1505            cprintf("Instruction:%i\n", num);
1506            if (!(*inst_list_it)->isSquashed()) {
1507                if (!(*inst_list_it)->isIssued()) {
1508                    ++valid_num;
1509                    cprintf("Count:%i\n", valid_num);
1510                } else if ((*inst_list_it)->isMemRef() &&
1511                           !(*inst_list_it)->memOpDone()) {
1512                    // Loads that have not been marked as executed
1513                    // still count towards the total instructions.
1514                    ++valid_num;
1515                    cprintf("Count:%i\n", valid_num);
1516                }
1517            }
1518
1519            cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1520                    "Issued:%i\nSquashed:%i\n",
1521                    (*inst_list_it)->pcState(),
1522                    (*inst_list_it)->seqNum,
1523                    (*inst_list_it)->threadNumber,
1524                    (*inst_list_it)->isIssued(),
1525                    (*inst_list_it)->isSquashed());
1526
1527            if ((*inst_list_it)->isMemRef()) {
1528                cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1529            }
1530
1531            cprintf("\n");
1532
1533            inst_list_it++;
1534            ++num;
1535        }
1536    }
1537
1538    cprintf("Insts to Execute list:\n");
1539
1540    int num = 0;
1541    int valid_num = 0;
1542    ListIt inst_list_it = instsToExecute.begin();
1543
1544    while (inst_list_it != instsToExecute.end())
1545    {
1546        cprintf("Instruction:%i\n",
1547                num);
1548        if (!(*inst_list_it)->isSquashed()) {
1549            if (!(*inst_list_it)->isIssued()) {
1550                ++valid_num;
1551                cprintf("Count:%i\n", valid_num);
1552            } else if ((*inst_list_it)->isMemRef() &&
1553                       !(*inst_list_it)->memOpDone()) {
1554                // Loads that have not been marked as executed
1555                // still count towards the total instructions.
1556                ++valid_num;
1557                cprintf("Count:%i\n", valid_num);
1558            }
1559        }
1560
1561        cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n"
1562                "Issued:%i\nSquashed:%i\n",
1563                (*inst_list_it)->pcState(),
1564                (*inst_list_it)->seqNum,
1565                (*inst_list_it)->threadNumber,
1566                (*inst_list_it)->isIssued(),
1567                (*inst_list_it)->isSquashed());
1568
1569        if ((*inst_list_it)->isMemRef()) {
1570            cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone());
1571        }
1572
1573        cprintf("\n");
1574
1575        inst_list_it++;
1576        ++num;
1577    }
1578}
1579
1580#endif//__CPU_O3_INST_QUEUE_IMPL_HH__
1581