inst_queue_impl.hh revision 1062
18713Sandreas.hansson@arm.com#ifndef __INST_QUEUE_IMPL_HH__ 27586SAli.Saidi@arm.com#define __INST_QUEUE_IMPL_HH__ 37586SAli.Saidi@arm.com 47586SAli.Saidi@arm.com// Todo: 57586SAli.Saidi@arm.com// Current ordering allows for 0 cycle added-to-scheduled. Could maybe fake 67586SAli.Saidi@arm.com// it; either do in reverse order, or have added instructions put into a 77586SAli.Saidi@arm.com// different ready queue that, in scheduleRreadyInsts(), gets put onto the 87586SAli.Saidi@arm.com// normal ready queue. This would however give only a one cycle delay, 97586SAli.Saidi@arm.com// but probably is more flexible to actually add in a delay parameter than 107586SAli.Saidi@arm.com// just running it backwards. 117586SAli.Saidi@arm.com 127586SAli.Saidi@arm.com#include <vector> 133970Sgblack@eecs.umich.edu 143005Sstever@eecs.umich.edu#include "sim/universe.hh" 153005Sstever@eecs.umich.edu#include "cpu/beta_cpu/inst_queue.hh" 163005Sstever@eecs.umich.edu 173005Sstever@eecs.umich.edu// Either compile error or max int due to sign extension. 183005Sstever@eecs.umich.edu// Blatant hack to avoid compile warnings. 193005Sstever@eecs.umich.educonst InstSeqNum MaxInstSeqNum = 0 - 1; 203005Sstever@eecs.umich.edu 213005Sstever@eecs.umich.edutemplate <class Impl> 223005Sstever@eecs.umich.eduInstructionQueue<Impl>::InstructionQueue(Params ¶ms) 233005Sstever@eecs.umich.edu : memDepUnit(params), 243005Sstever@eecs.umich.edu numEntries(params.numIQEntries), 253005Sstever@eecs.umich.edu intWidth(params.executeIntWidth), 263005Sstever@eecs.umich.edu floatWidth(params.executeFloatWidth), 273005Sstever@eecs.umich.edu branchWidth(params.executeBranchWidth), 283005Sstever@eecs.umich.edu memoryWidth(params.executeMemoryWidth), 293005Sstever@eecs.umich.edu totalWidth(params.issueWidth), 303005Sstever@eecs.umich.edu numPhysIntRegs(params.numPhysIntRegs), 313005Sstever@eecs.umich.edu numPhysFloatRegs(params.numPhysFloatRegs), 323005Sstever@eecs.umich.edu commitToIEWDelay(params.commitToIEWDelay) 333005Sstever@eecs.umich.edu{ 343005Sstever@eecs.umich.edu DPRINTF(IQ, "IQ: Int width is %i.\n", params.executeIntWidth); 353005Sstever@eecs.umich.edu 363005Sstever@eecs.umich.edu // Initialize the number of free IQ entries. 373005Sstever@eecs.umich.edu freeEntries = numEntries; 383005Sstever@eecs.umich.edu 393005Sstever@eecs.umich.edu // Set the number of physical registers as the number of int + float 403005Sstever@eecs.umich.edu numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 416654Snate@binkert.org 426654Snate@binkert.org DPRINTF(IQ, "IQ: There are %i physical registers.\n", numPhysRegs); 436654Snate@binkert.org 442889SN/A //Create an entry for each physical register within the 452710SN/A //dependency graph. 466654Snate@binkert.org dependGraph = new DependencyEntry[numPhysRegs]; 476654Snate@binkert.org 486654Snate@binkert.org // Resize the register scoreboard. 495457Ssaidi@eecs.umich.edu regScoreboard.resize(numPhysRegs); 506654Snate@binkert.org 516654Snate@binkert.org // Initialize all the head pointers to point to NULL, and all the 522934SN/A // entries as unready. 532549SN/A // Note that in actuality, the registers corresponding to the logical 542995SN/A // registers start off as ready. However this doesn't matter for the 553395Shsul@eecs.umich.edu // IQ as the instruction should have been correctly told if those 566981SLisa.Hsu@amd.com // registers are ready in rename. Thus it can all be initialized as 573448Shsul@eecs.umich.edu // unready. 582549SN/A for (int i = 0; i < numPhysRegs; ++i) 593444Sktlim@umich.edu { 603444Sktlim@umich.edu dependGraph[i].next = NULL; 613444Sktlim@umich.edu dependGraph[i].inst = NULL; 623444Sktlim@umich.edu regScoreboard[i] = false; 632889SN/A } 642710SN/A 657861Sgblack@eecs.umich.edu} 667861Sgblack@eecs.umich.edu 677861Sgblack@eecs.umich.edutemplate <class Impl> 687861Sgblack@eecs.umich.eduvoid 693873Sbinkertn@umich.eduInstructionQueue<Impl>::regStats() 703873Sbinkertn@umich.edu{ 713873Sbinkertn@umich.edu iqInstsAdded 728635Schris.emmons@arm.com .name(name() + ".iqInstsAdded") 738635Schris.emmons@arm.com .desc("Number of instructions added to the IQ (excludes non-spec)") 748635Schris.emmons@arm.com .prereq(iqInstsAdded); 758635Schris.emmons@arm.com 767586SAli.Saidi@arm.com iqNonSpecInstsAdded 777586SAli.Saidi@arm.com .name(name() + ".iqNonSpecInstsAdded") 787586SAli.Saidi@arm.com .desc("Number of non-speculative instructions added to the IQ") 797586SAli.Saidi@arm.com .prereq(iqNonSpecInstsAdded); 807586SAli.Saidi@arm.com 813322Shsul@eecs.umich.edu// iqIntInstsAdded; 822995SN/A 832995SN/A iqIntInstsIssued 842995SN/A .name(name() + ".iqIntInstsIssued") 852995SN/A .desc("Number of integer instructions issued") 862995SN/A .prereq(iqIntInstsIssued); 873143Shsul@eecs.umich.edu 883322Shsul@eecs.umich.edu// iqFloatInstsAdded; 893322Shsul@eecs.umich.edu 903025Ssaidi@eecs.umich.edu iqFloatInstsIssued 913143Shsul@eecs.umich.edu .name(name() + ".iqFloatInstsIssued") 923143Shsul@eecs.umich.edu .desc("Number of float instructions issued") 933322Shsul@eecs.umich.edu .prereq(iqFloatInstsIssued); 943444Sktlim@umich.edu 953322Shsul@eecs.umich.edu// iqBranchInstsAdded; 962710SN/A 972710SN/A iqBranchInstsIssued 982710SN/A .name(name() + ".iqBranchInstsIssued") 992710SN/A .desc("Number of branch instructions issued") 1002710SN/A .prereq(iqBranchInstsIssued); 1012710SN/A 1023322Shsul@eecs.umich.edu// iqMemInstsAdded; 1033304Sstever@eecs.umich.edu 1043322Shsul@eecs.umich.edu iqMemInstsIssued 1053322Shsul@eecs.umich.edu .name(name() + ".iqMemInstsIssued") 1063304Sstever@eecs.umich.edu .desc("Number of memory instructions issued") 1073481Shsul@eecs.umich.edu .prereq(iqMemInstsIssued); 1083481Shsul@eecs.umich.edu 1092566SN/A// iqMiscInstsAdded; 1103322Shsul@eecs.umich.edu 1113322Shsul@eecs.umich.edu iqMiscInstsIssued 1122995SN/A .name(name() + ".iqMiscInstsIssued") 1132995SN/A .desc("Number of miscellaneous instructions issued") 1143304Sstever@eecs.umich.edu .prereq(iqMiscInstsIssued); 1153304Sstever@eecs.umich.edu 1163304Sstever@eecs.umich.edu iqSquashedInstsIssued 1172995SN/A .name(name() + ".iqSquashedInstsIssued") 1182995SN/A .desc("Number of squashed instructions issued") 1192995SN/A .prereq(iqSquashedInstsIssued); 1202917SN/A 1212995SN/A iqLoopSquashStalls 1223304Sstever@eecs.umich.edu .name(name() + ".iqLoopSquashStalls") 1232995SN/A .desc("Number of times issue loop had to restart due to squashed " 1243304Sstever@eecs.umich.edu "inst; mainly for profiling") 1253304Sstever@eecs.umich.edu .prereq(iqLoopSquashStalls); 1266135Sgblack@eecs.umich.edu 1276135Sgblack@eecs.umich.edu iqSquashedInstsExamined 1286654Snate@binkert.org .name(name() + ".iqSquashedInstsExamined") 1293819Shsul@eecs.umich.edu .desc("Number of squashed instructions iterated over during squash;" 1306654Snate@binkert.org " mainly for profiling") 1315222Sksewell@umich.edu .prereq(iqSquashedInstsExamined); 1326654Snate@binkert.org 1333819Shsul@eecs.umich.edu iqSquashedOperandsExamined 1346654Snate@binkert.org .name(name() + ".iqSquashedOperandsExamined") 1357925Sgblack@eecs.umich.edu .desc("Number of squashed operands that are examined and possibly " 1367925Sgblack@eecs.umich.edu "removed from graph") 1377586SAli.Saidi@arm.com .prereq(iqSquashedOperandsExamined); 1388061SAli.Saidi@ARM.com 1398061SAli.Saidi@ARM.com iqSquashedNonSpecRemoved 1408061SAli.Saidi@ARM.com .name(name() + ".iqSquashedNonSpecRemoved") 1418354Sgedare@gwmail.gwu.edu .desc("Number of squashed non-spec instructions that were removed") 1423819Shsul@eecs.umich.edu .prereq(iqSquashedNonSpecRemoved); 1436654Snate@binkert.org 1443819Shsul@eecs.umich.edu // Tell mem dependence unit to reg stats as well. 1453873Sbinkertn@umich.edu memDepUnit.regStats(); 1463873Sbinkertn@umich.edu} 1473873Sbinkertn@umich.edu 1483873Sbinkertn@umich.edutemplate <class Impl> 1493873Sbinkertn@umich.eduvoid 1503873Sbinkertn@umich.eduInstructionQueue<Impl>::setCPU(FullCPU *cpu_ptr) 1518659SAli.Saidi@ARM.com{ 1528659SAli.Saidi@ARM.com cpu = cpu_ptr; 1536995Sgblack@eecs.umich.edu 1543668Srdreslin@umich.edu tail = cpu->instList.begin(); 1556995Sgblack@eecs.umich.edu} 1565142Ssaidi@eecs.umich.edu 1578713Sandreas.hansson@arm.comtemplate <class Impl> 1588713Sandreas.hansson@arm.comvoid 1598713Sandreas.hansson@arm.comInstructionQueue<Impl>::setIssueToExecuteQueue( 1608713Sandreas.hansson@arm.com TimeBuffer<IssueStruct> *i2e_ptr) 1616636Ssteve.reinhardt@amd.com{ 1628870SAli.Saidi@ARM.com DPRINTF(IQ, "IQ: Set the issue to execute queue.\n"); 1638839Sandreas.hansson@arm.com issueToExecuteQueue = i2e_ptr; 1648839Sandreas.hansson@arm.com} 1658713Sandreas.hansson@arm.com 1668713Sandreas.hansson@arm.comtemplate <class Impl> 1678870SAli.Saidi@ARM.comvoid 1688839Sandreas.hansson@arm.comInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 1698839Sandreas.hansson@arm.com{ 1705142Ssaidi@eecs.umich.edu DPRINTF(IQ, "IQ: Set the time buffer.\n"); 1713312Sstever@eecs.umich.edu timeBuffer = tb_ptr; 1724968Sacolyte@umich.edu 1734968Sacolyte@umich.edu fromCommit = timeBuffer->getWire(-commitToIEWDelay); 1744968Sacolyte@umich.edu} 1756654Snate@binkert.org 1765254Sksewell@umich.edu// Might want to do something more complex if it knows how many instructions 1775222Sksewell@umich.edu// will be issued this cycle. 1783005Sstever@eecs.umich.edutemplate <class Impl> 1796654Snate@binkert.orgbool 1803819Shsul@eecs.umich.eduInstructionQueue<Impl>::isFull() 1816654Snate@binkert.org{ 1825222Sksewell@umich.edu if (freeEntries == 0) { 1836654Snate@binkert.org return(true); 1843819Shsul@eecs.umich.edu } else { 1856654Snate@binkert.org return(false); 1866135Sgblack@eecs.umich.edu } 1877586SAli.Saidi@arm.com} 1888661SAli.Saidi@ARM.com 1898661SAli.Saidi@ARM.comtemplate <class Impl> 1903322Shsul@eecs.umich.eduunsigned 1918863Snilay@cs.wisc.eduInstructionQueue<Impl>::numFreeEntries() 1927876Sgblack@eecs.umich.edu{ 1934968Sacolyte@umich.edu return freeEntries; 1944968Sacolyte@umich.edu} 1954837Ssaidi@eecs.umich.edu 1964837Ssaidi@eecs.umich.edutemplate <class Impl> 1978810SAli.Saidi@ARM.comvoid 1988870SAli.Saidi@ARM.comInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 1998845Sandreas.hansson@arm.com{ 2008845Sandreas.hansson@arm.com // Make sure the instruction is valid 2014837Ssaidi@eecs.umich.edu assert(new_inst); 2028659SAli.Saidi@ARM.com 2038801Sgblack@eecs.umich.edu DPRINTF(IQ, "IQ: Adding instruction PC %#x to the IQ.\n", 2043005Sstever@eecs.umich.edu new_inst->readPC()); 2058801Sgblack@eecs.umich.edu 2063005Sstever@eecs.umich.edu // Check if there are any free entries. Panic if there are none. 2073005Sstever@eecs.umich.edu // Might want to have this return a fault in the future instead of 2083005Sstever@eecs.umich.edu // panicing. 2092566SN/A assert(freeEntries != 0); 2107861Sgblack@eecs.umich.edu 2117861Sgblack@eecs.umich.edu // If the IQ currently has nothing in it, then there's a possibility 2127861Sgblack@eecs.umich.edu // that the tail iterator is invalid (might have been pointing at an 2138635Schris.emmons@arm.com // instruction that was retired). Reset the tail iterator. 2148635Schris.emmons@arm.com if (freeEntries == numEntries) { 2158635Schris.emmons@arm.com tail = cpu->instList.begin(); 2163481Shsul@eecs.umich.edu } 217 218 // Move the tail iterator. Instructions may not have been issued 219 // to the IQ, so we may have to increment the iterator more than once. 220 while ((*tail) != new_inst) { 221 tail++; 222 223 // Make sure the tail iterator points at something legal. 224 assert(tail != cpu->instList.end()); 225 } 226 227 228 // Decrease the number of free entries. 229 --freeEntries; 230 231 // Look through its source registers (physical regs), and mark any 232 // dependencies. 233 addToDependents(new_inst); 234 235 // Have this instruction set itself as the producer of its destination 236 // register(s). 237 createDependency(new_inst); 238 239 // If it's a memory instruction, add it to the memory dependency 240 // unit. 241 if (new_inst->isMemRef()) { 242 memDepUnit.insert(new_inst); 243 // Uh..forgot to look it up and put it on the proper dependency list 244 // if the instruction should not go yet. 245 } else { 246 // If the instruction is ready then add it to the ready list. 247 addIfReady(new_inst); 248 } 249 250 ++iqInstsAdded; 251 252 assert(freeEntries == (numEntries - countInsts())); 253} 254 255template <class Impl> 256void 257InstructionQueue<Impl>::insertNonSpec(DynInstPtr &inst) 258{ 259 nonSpecInsts[inst->seqNum] = inst; 260 261 // @todo: Clean up this code; can do it by setting inst as unable 262 // to issue, then calling normal insert on the inst. 263 264 // Make sure the instruction is valid 265 assert(inst); 266 267 DPRINTF(IQ, "IQ: Adding instruction PC %#x to the IQ.\n", 268 inst->readPC()); 269 270 // Check if there are any free entries. Panic if there are none. 271 // Might want to have this return a fault in the future instead of 272 // panicing. 273 assert(freeEntries != 0); 274 275 // If the IQ currently has nothing in it, then there's a possibility 276 // that the tail iterator is invalid (might have been pointing at an 277 // instruction that was retired). Reset the tail iterator. 278 if (freeEntries == numEntries) { 279 tail = cpu->instList.begin(); 280 } 281 282 // Move the tail iterator. Instructions may not have been issued 283 // to the IQ, so we may have to increment the iterator more than once. 284 while ((*tail) != inst) { 285 tail++; 286 287 // Make sure the tail iterator points at something legal. 288 assert(tail != cpu->instList.end()); 289 } 290 291 // Decrease the number of free entries. 292 --freeEntries; 293 294 // Look through its source registers (physical regs), and mark any 295 // dependencies. 296// addToDependents(inst); 297 298 // Have this instruction set itself as the producer of its destination 299 // register(s). 300 createDependency(inst); 301 302 // If it's a memory instruction, add it to the memory dependency 303 // unit. 304 if (inst->isMemRef()) { 305 memDepUnit.insertNonSpec(inst); 306 } 307 308 ++iqNonSpecInstsAdded; 309} 310 311// Slightly hack function to advance the tail iterator in the case that 312// the IEW stage issues an instruction that is not added to the IQ. This 313// is needed in case a long chain of such instructions occurs. 314// I don't think this is used anymore. 315template <class Impl> 316void 317InstructionQueue<Impl>::advanceTail(DynInstPtr &inst) 318{ 319 // Make sure the instruction is valid 320 assert(inst); 321 322 DPRINTF(IQ, "IQ: Adding instruction PC %#x to the IQ.\n", 323 inst->readPC()); 324 325 // Check if there are any free entries. Panic if there are none. 326 // Might want to have this return a fault in the future instead of 327 // panicing. 328 assert(freeEntries != 0); 329 330 // If the IQ currently has nothing in it, then there's a possibility 331 // that the tail iterator is invalid (might have been pointing at an 332 // instruction that was retired). Reset the tail iterator. 333 if (freeEntries == numEntries) { 334 tail = cpu->instList.begin(); 335 } 336 337 // Move the tail iterator. Instructions may not have been issued 338 // to the IQ, so we may have to increment the iterator more than once. 339 while ((*tail) != inst) { 340 tail++; 341 342 // Make sure the tail iterator points at something legal. 343 assert(tail != cpu->instList.end()); 344 } 345 346 assert(freeEntries <= numEntries); 347 348 // Have this instruction set itself as the producer of its destination 349 // register(s). 350 createDependency(inst); 351} 352 353// Need to make sure the number of float and integer instructions 354// issued does not exceed the total issue bandwidth. 355// @todo: Figure out a better way to remove the squashed items from the 356// lists. Checking the top item of each list to see if it's squashed 357// wastes time and forces jumps. 358template <class Impl> 359void 360InstructionQueue<Impl>::scheduleReadyInsts() 361{ 362 DPRINTF(IQ, "IQ: Attempting to schedule ready instructions from " 363 "the IQ.\n"); 364 365 int int_issued = 0; 366 int float_issued = 0; 367 int branch_issued = 0; 368 int memory_issued = 0; 369 int squashed_issued = 0; 370 int total_issued = 0; 371 372 IssueStruct *i2e_info = issueToExecuteQueue->access(0); 373 374 bool insts_available = !readyBranchInsts.empty() || 375 !readyIntInsts.empty() || 376 !readyFloatInsts.empty() || 377 !memDepUnit.empty() || 378 !readyMiscInsts.empty() || 379 !squashedInsts.empty(); 380 381 // Note: Requires a globally defined constant. 382 InstSeqNum oldest_inst = MaxInstSeqNum; 383 InstList list_with_oldest = None; 384 385 // Temporary values. 386 DynInstPtr int_head_inst; 387 DynInstPtr float_head_inst; 388 DynInstPtr branch_head_inst; 389 DynInstPtr mem_head_inst; 390 DynInstPtr misc_head_inst; 391 DynInstPtr squashed_head_inst; 392 393 // Somewhat nasty code to look at all of the lists where issuable 394 // instructions are located, and choose the oldest instruction among 395 // those lists. Consider a rewrite in the future. 396 while (insts_available && total_issued < totalWidth) 397 { 398 // Set this to false. Each if-block is required to set it to true 399 // if there were instructions available this check. This will cause 400 // this loop to run once more than necessary, but avoids extra calls. 401 insts_available = false; 402 403 oldest_inst = MaxInstSeqNum; 404 405 list_with_oldest = None; 406 407 if (!readyIntInsts.empty() && 408 int_issued < intWidth) { 409 410 insts_available = true; 411 412 int_head_inst = readyIntInsts.top(); 413 414 if (int_head_inst->isSquashed()) { 415 readyIntInsts.pop(); 416 417 ++iqLoopSquashStalls; 418 419 continue; 420 } 421 422 oldest_inst = int_head_inst->seqNum; 423 424 list_with_oldest = Int; 425 } 426 427 if (!readyFloatInsts.empty() && 428 float_issued < floatWidth) { 429 430 insts_available = true; 431 432 float_head_inst = readyFloatInsts.top(); 433 434 if (float_head_inst->isSquashed()) { 435 readyFloatInsts.pop(); 436 437 ++iqLoopSquashStalls; 438 439 continue; 440 } else if (float_head_inst->seqNum < oldest_inst) { 441 oldest_inst = float_head_inst->seqNum; 442 443 list_with_oldest = Float; 444 } 445 } 446 447 if (!readyBranchInsts.empty() && 448 branch_issued < branchWidth) { 449 450 insts_available = true; 451 452 branch_head_inst = readyBranchInsts.top(); 453 454 if (branch_head_inst->isSquashed()) { 455 readyBranchInsts.pop(); 456 457 ++iqLoopSquashStalls; 458 459 continue; 460 } else if (branch_head_inst->seqNum < oldest_inst) { 461 oldest_inst = branch_head_inst->seqNum; 462 463 list_with_oldest = Branch; 464 } 465 466 } 467 468 if (!memDepUnit.empty() && 469 memory_issued < memoryWidth) { 470 471 insts_available = true; 472 473 mem_head_inst = memDepUnit.top(); 474 475 if (mem_head_inst->isSquashed()) { 476 memDepUnit.pop(); 477 478 ++iqLoopSquashStalls; 479 480 continue; 481 } else if (mem_head_inst->seqNum < oldest_inst) { 482 oldest_inst = mem_head_inst->seqNum; 483 484 list_with_oldest = Memory; 485 } 486 } 487 488 if (!readyMiscInsts.empty()) { 489 490 insts_available = true; 491 492 misc_head_inst = readyMiscInsts.top(); 493 494 if (misc_head_inst->isSquashed()) { 495 readyMiscInsts.pop(); 496 497 ++iqLoopSquashStalls; 498 499 continue; 500 } else if (misc_head_inst->seqNum < oldest_inst) { 501 oldest_inst = misc_head_inst->seqNum; 502 503 list_with_oldest = Misc; 504 } 505 } 506 507 if (!squashedInsts.empty()) { 508 509 insts_available = true; 510 511 squashed_head_inst = squashedInsts.top(); 512 513 if (squashed_head_inst->seqNum < oldest_inst) { 514 list_with_oldest = Squashed; 515 } 516 517 } 518 519 DynInstPtr issuing_inst = NULL; 520 521 switch (list_with_oldest) { 522 case None: 523 DPRINTF(IQ, "IQ: Not able to schedule any instructions. Issuing " 524 "inst is %#x.\n", issuing_inst); 525 break; 526 527 case Int: 528 issuing_inst = int_head_inst; 529 readyIntInsts.pop(); 530 ++int_issued; 531 DPRINTF(IQ, "IQ: Issuing integer instruction PC %#x.\n", 532 issuing_inst->readPC()); 533 break; 534 535 case Float: 536 issuing_inst = float_head_inst; 537 readyFloatInsts.pop(); 538 ++float_issued; 539 DPRINTF(IQ, "IQ: Issuing float instruction PC %#x.\n", 540 issuing_inst->readPC()); 541 break; 542 543 case Branch: 544 issuing_inst = branch_head_inst; 545 readyBranchInsts.pop(); 546 ++branch_issued; 547 DPRINTF(IQ, "IQ: Issuing branch instruction PC %#x.\n", 548 issuing_inst->readPC()); 549 break; 550 551 case Memory: 552 issuing_inst = mem_head_inst; 553 554 memDepUnit.pop(); 555 ++memory_issued; 556 DPRINTF(IQ, "IQ: Issuing memory instruction PC %#x.\n", 557 issuing_inst->readPC()); 558 break; 559 560 case Misc: 561 issuing_inst = misc_head_inst; 562 readyMiscInsts.pop(); 563 564 ++iqMiscInstsIssued; 565 566 DPRINTF(IQ, "IQ: Issuing a miscellaneous instruction PC %#x.\n", 567 issuing_inst->readPC()); 568 break; 569 570 case Squashed: 571 issuing_inst = squashed_head_inst; 572 squashedInsts.pop(); 573 ++squashed_issued; 574 DPRINTF(IQ, "IQ: Issuing squashed instruction PC %#x.\n", 575 issuing_inst->readPC()); 576 break; 577 } 578 579 if (list_with_oldest != None) { 580 i2e_info->insts[total_issued] = issuing_inst; 581 i2e_info->size++; 582 583 issuing_inst->setIssued(); 584 585 ++freeEntries; 586 ++total_issued; 587 } 588 589 assert(freeEntries == (numEntries - countInsts())); 590 } 591 592 iqIntInstsIssued += int_issued; 593 iqFloatInstsIssued += float_issued; 594 iqBranchInstsIssued += branch_issued; 595 iqMemInstsIssued += memory_issued; 596 iqSquashedInstsIssued += squashed_issued; 597} 598 599template <class Impl> 600void 601InstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 602{ 603 DPRINTF(IQ, "IQ: Marking nonspeculative instruction with sequence " 604 "number %i as ready to execute.\n", inst); 605 606 non_spec_it_t inst_it = nonSpecInsts.find(inst); 607 608 assert(inst_it != nonSpecInsts.end()); 609 610 // Mark this instruction as ready to issue. 611 (*inst_it).second->setCanIssue(); 612 613 // Now schedule the instruction. 614 if (!(*inst_it).second->isMemRef()) { 615 addIfReady((*inst_it).second); 616 } else { 617 memDepUnit.nonSpecInstReady((*inst_it).second); 618 } 619 620 nonSpecInsts.erase(inst_it); 621} 622 623template <class Impl> 624void 625InstructionQueue<Impl>::violation(DynInstPtr &store, 626 DynInstPtr &faulting_load) 627{ 628 memDepUnit.violation(store, faulting_load); 629} 630 631template <class Impl> 632void 633InstructionQueue<Impl>::squash() 634{ 635 DPRINTF(IQ, "IQ: Starting to squash instructions in the IQ.\n"); 636 637 // Read instruction sequence number of last instruction out of the 638 // time buffer. 639 squashedSeqNum = fromCommit->commitInfo.doneSeqNum; 640 641 // Setup the squash iterator to point to the tail. 642 squashIt = tail; 643 644 // Call doSquash. 645 doSquash(); 646 647 // Also tell the memory dependence unit to squash. 648 memDepUnit.squash(squashedSeqNum); 649} 650 651template <class Impl> 652void 653InstructionQueue<Impl>::doSquash() 654{ 655 // Make sure the squash iterator isn't pointing to nothing. 656 assert(squashIt != cpu->instList.end()); 657 // Make sure the squashed sequence number is valid. 658 assert(squashedSeqNum != 0); 659 660 DPRINTF(IQ, "IQ: Squashing instructions in the IQ.\n"); 661 662 // Squash any instructions younger than the squashed sequence number 663 // given. 664 while ((*squashIt)->seqNum > squashedSeqNum) { 665 DynInstPtr squashed_inst = (*squashIt); 666 667 // Only handle the instruction if it actually is in the IQ and 668 // hasn't already been squashed in the IQ. 669 if (!squashed_inst->isIssued() && 670 !squashed_inst->isSquashedInIQ()) { 671 672 // Remove the instruction from the dependency list. 673 // Hack for now: These below don't add themselves to the 674 // dependency list, so don't try to remove them. 675 if (!squashed_inst->isNonSpeculative() && 676 !squashed_inst->isStore()) { 677 int8_t total_src_regs = squashed_inst->numSrcRegs(); 678 679 for (int src_reg_idx = 0; 680 src_reg_idx < total_src_regs; 681 src_reg_idx++) 682 { 683 PhysRegIndex src_reg = 684 squashed_inst->renamedSrcRegIdx(src_reg_idx); 685 686 // Only remove it from the dependency graph if it was 687 // placed there in the first place. 688 // HACK: This assumes that instructions woken up from the 689 // dependency chain aren't informed that a specific src 690 // register has become ready. This may not always be true 691 // in the future. 692 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 693 src_reg < numPhysRegs) { 694 dependGraph[src_reg].remove(squashed_inst); 695 } 696 697 ++iqSquashedOperandsExamined; 698 } 699 700 // Might want to remove producers as well. 701 } else { 702 nonSpecInsts.erase(squashed_inst->seqNum); 703 704 ++iqSquashedNonSpecRemoved; 705 } 706 707 // Might want to also clear out the head of the dependency graph. 708 709 // Mark it as squashed within the IQ. 710 squashed_inst->setSquashedInIQ(); 711 712 squashedInsts.push(squashed_inst); 713 714 DPRINTF(IQ, "IQ: Instruction PC %#x squashed.\n", 715 squashed_inst->readPC()); 716 } 717 718 --squashIt; 719 ++iqSquashedInstsExamined; 720 } 721} 722 723template <class Impl> 724void 725InstructionQueue<Impl>::stopSquash() 726{ 727 // Clear up the squash variables to ensure that squashing doesn't 728 // get called improperly. 729 squashedSeqNum = 0; 730 731 squashIt = cpu->instList.end(); 732} 733 734template <class Impl> 735void 736InstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 737{ 738 DPRINTF(IQ, "IQ: Waking dependents of completed instruction.\n"); 739 //Look at the physical destination register of the DynInst 740 //and look it up on the dependency graph. Then mark as ready 741 //any instructions within the instruction queue. 742 int8_t total_dest_regs = completed_inst->numDestRegs(); 743 744 DependencyEntry *curr; 745 746 // Tell the memory dependence unit to wake any dependents on this 747 // instruction if it is a memory instruction. 748 749 if (completed_inst->isMemRef()) { 750 memDepUnit.wakeDependents(completed_inst); 751 } 752 753 for (int dest_reg_idx = 0; 754 dest_reg_idx < total_dest_regs; 755 dest_reg_idx++) 756 { 757 PhysRegIndex dest_reg = 758 completed_inst->renamedDestRegIdx(dest_reg_idx); 759 760 // Special case of uniq or control registers. They are not 761 // handled by the IQ and thus have no dependency graph entry. 762 // @todo Figure out a cleaner way to handle thie. 763 if (dest_reg >= numPhysRegs) { 764 continue; 765 } 766 767 DPRINTF(IQ, "IQ: Waking any dependents on register %i.\n", 768 (int) dest_reg); 769 770 //Maybe abstract this part into a function. 771 //Go through the dependency chain, marking the registers as ready 772 //within the waiting instructions. 773 while (dependGraph[dest_reg].next) { 774 775 curr = dependGraph[dest_reg].next; 776 777 DPRINTF(IQ, "IQ: Waking up a dependent instruction, PC%#x.\n", 778 curr->inst->readPC()); 779 780 // Might want to give more information to the instruction 781 // so that it knows which of its source registers is ready. 782 // However that would mean that the dependency graph entries 783 // would need to hold the src_reg_idx. 784 curr->inst->markSrcRegReady(); 785 786 addIfReady(curr->inst); 787 788 dependGraph[dest_reg].next = curr->next; 789 790 DependencyEntry::mem_alloc_counter--; 791 792 delete curr; 793 } 794 795 // Reset the head node now that all of its dependents have been woken 796 // up. 797 dependGraph[dest_reg].next = NULL; 798 dependGraph[dest_reg].inst = NULL; 799 800 // Mark the scoreboard as having that register ready. 801 regScoreboard[dest_reg] = true; 802 } 803} 804 805template <class Impl> 806bool 807InstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 808{ 809 // Loop through the instruction's source registers, adding 810 // them to the dependency list if they are not ready. 811 int8_t total_src_regs = new_inst->numSrcRegs(); 812 bool return_val = false; 813 814 for (int src_reg_idx = 0; 815 src_reg_idx < total_src_regs; 816 src_reg_idx++) 817 { 818 // Only add it to the dependency graph if it's not ready. 819 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 820 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 821 822 // Check the IQ's scoreboard to make sure the register 823 // hasn't become ready while the instruction was in flight 824 // between stages. Only if it really isn't ready should 825 // it be added to the dependency graph. 826 if (src_reg >= numPhysRegs) { 827 continue; 828 } else if (regScoreboard[src_reg] == false) { 829 DPRINTF(IQ, "IQ: Instruction PC %#x has src reg %i that " 830 "is being added to the dependency chain.\n", 831 new_inst->readPC(), src_reg); 832 833 dependGraph[src_reg].insert(new_inst); 834 835 // Change the return value to indicate that something 836 // was added to the dependency graph. 837 return_val = true; 838 } else { 839 DPRINTF(IQ, "IQ: Instruction PC %#x has src reg %i that " 840 "became ready before it reached the IQ.\n", 841 new_inst->readPC(), src_reg); 842 // Mark a register ready within the instruction. 843 new_inst->markSrcRegReady(); 844 } 845 } 846 } 847 848 return return_val; 849} 850 851template <class Impl> 852void 853InstructionQueue<Impl>::createDependency(DynInstPtr &new_inst) 854{ 855 //Actually nothing really needs to be marked when an 856 //instruction becomes the producer of a register's value, 857 //but for convenience a ptr to the producing instruction will 858 //be placed in the head node of the dependency links. 859 int8_t total_dest_regs = new_inst->numDestRegs(); 860 861 for (int dest_reg_idx = 0; 862 dest_reg_idx < total_dest_regs; 863 dest_reg_idx++) 864 { 865 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 866 867 // Instructions that use the misc regs will have a reg number 868 // higher than the normal physical registers. In this case these 869 // registers are not renamed, and there is no need to track 870 // dependencies as these instructions must be executed at commit. 871 if (dest_reg >= numPhysRegs) { 872 continue; 873 } 874 875 dependGraph[dest_reg].inst = new_inst; 876 877 assert(!dependGraph[dest_reg].next); 878 879 // Mark the scoreboard to say it's not yet ready. 880 regScoreboard[dest_reg] = false; 881 } 882} 883 884template <class Impl> 885void 886InstructionQueue<Impl>::DependencyEntry::insert(DynInstPtr &new_inst) 887{ 888 //Add this new, dependent instruction at the head of the dependency 889 //chain. 890 891 // First create the entry that will be added to the head of the 892 // dependency chain. 893 DependencyEntry *new_entry = new DependencyEntry; 894 new_entry->next = this->next; 895 new_entry->inst = new_inst; 896 897 // Then actually add it to the chain. 898 this->next = new_entry; 899 900 ++mem_alloc_counter; 901} 902 903template <class Impl> 904void 905InstructionQueue<Impl>::DependencyEntry::remove(DynInstPtr &inst_to_remove) 906{ 907 DependencyEntry *prev = this; 908 DependencyEntry *curr = this->next; 909 910 // Make sure curr isn't NULL. Because this instruction is being 911 // removed from a dependency list, it must have been placed there at 912 // an earlier time. The dependency chain should not be empty, 913 // unless the instruction dependent upon it is already ready. 914 if (curr == NULL) { 915 return; 916 } 917 918 // Find the instruction to remove within the dependency linked list. 919 while(curr->inst != inst_to_remove) 920 { 921 prev = curr; 922 curr = curr->next; 923 924 assert(curr != NULL); 925 } 926 927 // Now remove this instruction from the list. 928 prev->next = curr->next; 929 930 --mem_alloc_counter; 931 932 delete curr; 933} 934 935template <class Impl> 936void 937InstructionQueue<Impl>::dumpDependGraph() 938{ 939 DependencyEntry *curr; 940 941 for (int i = 0; i < numPhysRegs; ++i) 942 { 943 curr = &dependGraph[i]; 944 945 if (curr->inst) { 946 cprintf("dependGraph[%i]: producer: %#x consumer: ", i, 947 curr->inst->readPC()); 948 } else { 949 cprintf("dependGraph[%i]: No producer. consumer: ", i); 950 } 951 952 while (curr->next != NULL) { 953 curr = curr->next; 954 955 cprintf("%#x ", curr->inst->readPC()); 956 } 957 958 cprintf("\n"); 959 } 960} 961 962template <class Impl> 963void 964InstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 965{ 966 //If the instruction now has all of its source registers 967 // available, then add it to the list of ready instructions. 968 if (inst->readyToIssue()) { 969 970 //Add the instruction to the proper ready list. 971 if (inst->isControl()) { 972 973 DPRINTF(IQ, "IQ: Branch instruction is ready to issue, " 974 "putting it onto the ready list, PC %#x.\n", 975 inst->readPC()); 976 readyBranchInsts.push(inst); 977 978 } else if (inst->isMemRef()) { 979 980 DPRINTF(IQ, "IQ: Checking if memory instruction can issue.\n"); 981 982 // Message to the mem dependence unit that this instruction has 983 // its registers ready. 984 985 memDepUnit.regsReady(inst); 986 987#if 0 988 if (memDepUnit.readyToIssue(inst)) { 989 DPRINTF(IQ, "IQ: Memory instruction is ready to issue, " 990 "putting it onto the ready list, PC %#x.\n", 991 inst->readPC()); 992 readyMemInsts.push(inst); 993 } else { 994 // Make dependent on the store. 995 // Will need some way to get the store instruction it should 996 // be dependent upon; then when the store issues it can 997 // put the instruction on the ready list. 998 // Yet another tree? 999 assert(0 && "Instruction has no way to actually issue"); 1000 } 1001#endif 1002 1003 } else if (inst->isInteger()) { 1004 1005 DPRINTF(IQ, "IQ: Integer instruction is ready to issue, " 1006 "putting it onto the ready list, PC %#x.\n", 1007 inst->readPC()); 1008 readyIntInsts.push(inst); 1009 1010 } else if (inst->isFloating()) { 1011 1012 DPRINTF(IQ, "IQ: Floating instruction is ready to issue, " 1013 "putting it onto the ready list, PC %#x.\n", 1014 inst->readPC()); 1015 readyFloatInsts.push(inst); 1016 1017 } else { 1018 DPRINTF(IQ, "IQ: Miscellaneous instruction is ready to issue, " 1019 "putting it onto the ready list, PC %#x..\n", 1020 inst->readPC()); 1021 1022 readyMiscInsts.push(inst); 1023 } 1024 } 1025} 1026 1027template <class Impl> 1028int 1029InstructionQueue<Impl>::countInsts() 1030{ 1031 ListIt count_it = cpu->instList.begin(); 1032 int total_insts = 0; 1033 1034 while (count_it != tail) { 1035 if (!(*count_it)->isIssued()) { 1036 ++total_insts; 1037 } 1038 1039 ++count_it; 1040 1041 assert(count_it != cpu->instList.end()); 1042 } 1043 1044 // Need to count the tail iterator as well. 1045 if (count_it != cpu->instList.end() && 1046 (*count_it) && 1047 !(*count_it)->isIssued()) { 1048 ++total_insts; 1049 } 1050 1051 return total_insts; 1052} 1053 1054template <class Impl> 1055void 1056InstructionQueue<Impl>::dumpLists() 1057{ 1058 cprintf("Ready integer list size: %i\n", readyIntInsts.size()); 1059 1060 cprintf("Ready float list size: %i\n", readyFloatInsts.size()); 1061 1062 cprintf("Ready branch list size: %i\n", readyBranchInsts.size()); 1063 1064// cprintf("Ready memory list size: %i\n", readyMemInsts.size()); 1065 1066 cprintf("Ready misc list size: %i\n", readyMiscInsts.size()); 1067 1068 cprintf("Squashed list size: %i\n", squashedInsts.size()); 1069 1070 cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 1071 1072 non_spec_it_t non_spec_it = nonSpecInsts.begin(); 1073 1074 cprintf("Non speculative list: "); 1075 1076 while (non_spec_it != nonSpecInsts.end()) { 1077 cprintf("%#x ", (*non_spec_it).second->readPC()); 1078 ++non_spec_it; 1079 } 1080 1081 cprintf("\n"); 1082 1083} 1084 1085#endif // __INST_QUEUE_IMPL_HH__ 1086