inst_queue_impl.hh revision 9920
11689SN/A/* 29444SAndreas.Sandberg@ARM.com * Copyright (c) 2011-2012 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422831Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 452064SN/A#include <limits> 461060SN/A#include <vector> 471060SN/A 482292SN/A#include "cpu/o3/fu_pool.hh" 491717SN/A#include "cpu/o3/inst_queue.hh" 508232Snate@binkert.org#include "debug/IQ.hh" 514762Snate@binkert.org#include "enums/OpClass.hh" 526221Snate@binkert.org#include "params/DerivO3CPU.hh" 534762Snate@binkert.org#include "sim/core.hh" 541060SN/A 558737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 568737Skoansin.tan@gmail.com// we open up the entire namespace std 578737Skoansin.tan@gmail.comusing std::list; 585529Snate@binkert.org 591061SN/Atemplate <class Impl> 602292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 615606Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 628581Ssteve.reinhardt@amd.com : Event(Stat_Event_Pri, AutoDelete), 638581Ssteve.reinhardt@amd.com inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 641060SN/A{ 652292SN/A} 662292SN/A 672292SN/Atemplate <class Impl> 682292SN/Avoid 692292SN/AInstructionQueue<Impl>::FUCompletion::process() 702292SN/A{ 712326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 722292SN/A inst = NULL; 732292SN/A} 742292SN/A 752292SN/A 762292SN/Atemplate <class Impl> 772292SN/Aconst char * 785336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const 792292SN/A{ 804873Sstever@eecs.umich.edu return "Functional unit completion"; 812292SN/A} 822292SN/A 832292SN/Atemplate <class Impl> 844329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 855529Snate@binkert.org DerivO3CPUParams *params) 864329Sktlim@umich.edu : cpu(cpu_ptr), 874329Sktlim@umich.edu iewStage(iew_ptr), 884329Sktlim@umich.edu fuPool(params->fuPool), 892292SN/A numEntries(params->numIQEntries), 902292SN/A totalWidth(params->issueWidth), 912292SN/A commitToIEWDelay(params->commitToIEWDelay) 922292SN/A{ 932292SN/A assert(fuPool); 942292SN/A 955529Snate@binkert.org numThreads = params->numThreads; 961060SN/A 979920Syasuko.eckert@amd.com // Set the number of total physical registers 989920Syasuko.eckert@amd.com numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 999920Syasuko.eckert@amd.com params->numPhysCCRegs; 1001060SN/A 1011060SN/A //Create an entry for each physical register within the 1021060SN/A //dependency graph. 1032326SN/A dependGraph.resize(numPhysRegs); 1041060SN/A 1051060SN/A // Resize the register scoreboard. 1061060SN/A regScoreboard.resize(numPhysRegs); 1071060SN/A 1082292SN/A //Initialize Mem Dependence Units 1096221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1106221Snate@binkert.org memDepUnit[tid].init(params, tid); 1116221Snate@binkert.org memDepUnit[tid].setIQ(this); 1121060SN/A } 1131060SN/A 1142307SN/A resetState(); 1152292SN/A 1162980Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1172292SN/A 1182292SN/A //Convert string to lowercase 1192292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1202292SN/A (int(*)(int)) tolower); 1212292SN/A 1222292SN/A //Figure out resource sharing policy 1232292SN/A if (policy == "dynamic") { 1242292SN/A iqPolicy = Dynamic; 1252292SN/A 1262292SN/A //Set Max Entries to Total ROB Capacity 1276221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1286221Snate@binkert.org maxEntries[tid] = numEntries; 1292292SN/A } 1302292SN/A 1312292SN/A } else if (policy == "partitioned") { 1322292SN/A iqPolicy = Partitioned; 1332292SN/A 1342292SN/A //@todo:make work if part_amt doesnt divide evenly. 1352292SN/A int part_amt = numEntries / numThreads; 1362292SN/A 1372292SN/A //Divide ROB up evenly 1386221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1396221Snate@binkert.org maxEntries[tid] = part_amt; 1402292SN/A } 1412292SN/A 1422831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1432292SN/A "%i entries per thread.\n",part_amt); 1442292SN/A } else if (policy == "threshold") { 1452292SN/A iqPolicy = Threshold; 1462292SN/A 1472292SN/A double threshold = (double)params->smtIQThreshold / 100; 1482292SN/A 1492292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1502292SN/A 1512292SN/A //Divide up by threshold amount 1526221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1536221Snate@binkert.org maxEntries[tid] = thresholdIQ; 1542292SN/A } 1552292SN/A 1562831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1572292SN/A "%i entries per thread.\n",thresholdIQ); 1582292SN/A } else { 1592292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1602292SN/A "Partitioned, Threshold}"); 1612292SN/A } 1622292SN/A} 1632292SN/A 1642292SN/Atemplate <class Impl> 1652292SN/AInstructionQueue<Impl>::~InstructionQueue() 1662292SN/A{ 1672326SN/A dependGraph.reset(); 1682348SN/A#ifdef DEBUG 1692326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1702326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1712348SN/A#endif 1722292SN/A} 1732292SN/A 1742292SN/Atemplate <class Impl> 1752292SN/Astd::string 1762292SN/AInstructionQueue<Impl>::name() const 1772292SN/A{ 1782292SN/A return cpu->name() + ".iq"; 1791060SN/A} 1801060SN/A 1811061SN/Atemplate <class Impl> 1821060SN/Avoid 1831062SN/AInstructionQueue<Impl>::regStats() 1841062SN/A{ 1852301SN/A using namespace Stats; 1861062SN/A iqInstsAdded 1871062SN/A .name(name() + ".iqInstsAdded") 1881062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1891062SN/A .prereq(iqInstsAdded); 1901062SN/A 1911062SN/A iqNonSpecInstsAdded 1921062SN/A .name(name() + ".iqNonSpecInstsAdded") 1931062SN/A .desc("Number of non-speculative instructions added to the IQ") 1941062SN/A .prereq(iqNonSpecInstsAdded); 1951062SN/A 1962301SN/A iqInstsIssued 1972301SN/A .name(name() + ".iqInstsIssued") 1982301SN/A .desc("Number of instructions issued") 1992301SN/A .prereq(iqInstsIssued); 2001062SN/A 2011062SN/A iqIntInstsIssued 2021062SN/A .name(name() + ".iqIntInstsIssued") 2031062SN/A .desc("Number of integer instructions issued") 2041062SN/A .prereq(iqIntInstsIssued); 2051062SN/A 2061062SN/A iqFloatInstsIssued 2071062SN/A .name(name() + ".iqFloatInstsIssued") 2081062SN/A .desc("Number of float instructions issued") 2091062SN/A .prereq(iqFloatInstsIssued); 2101062SN/A 2111062SN/A iqBranchInstsIssued 2121062SN/A .name(name() + ".iqBranchInstsIssued") 2131062SN/A .desc("Number of branch instructions issued") 2141062SN/A .prereq(iqBranchInstsIssued); 2151062SN/A 2161062SN/A iqMemInstsIssued 2171062SN/A .name(name() + ".iqMemInstsIssued") 2181062SN/A .desc("Number of memory instructions issued") 2191062SN/A .prereq(iqMemInstsIssued); 2201062SN/A 2211062SN/A iqMiscInstsIssued 2221062SN/A .name(name() + ".iqMiscInstsIssued") 2231062SN/A .desc("Number of miscellaneous instructions issued") 2241062SN/A .prereq(iqMiscInstsIssued); 2251062SN/A 2261062SN/A iqSquashedInstsIssued 2271062SN/A .name(name() + ".iqSquashedInstsIssued") 2281062SN/A .desc("Number of squashed instructions issued") 2291062SN/A .prereq(iqSquashedInstsIssued); 2301062SN/A 2311062SN/A iqSquashedInstsExamined 2321062SN/A .name(name() + ".iqSquashedInstsExamined") 2331062SN/A .desc("Number of squashed instructions iterated over during squash;" 2341062SN/A " mainly for profiling") 2351062SN/A .prereq(iqSquashedInstsExamined); 2361062SN/A 2371062SN/A iqSquashedOperandsExamined 2381062SN/A .name(name() + ".iqSquashedOperandsExamined") 2391062SN/A .desc("Number of squashed operands that are examined and possibly " 2401062SN/A "removed from graph") 2411062SN/A .prereq(iqSquashedOperandsExamined); 2421062SN/A 2431062SN/A iqSquashedNonSpecRemoved 2441062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2451062SN/A .desc("Number of squashed non-spec instructions that were removed") 2461062SN/A .prereq(iqSquashedNonSpecRemoved); 2472361SN/A/* 2482326SN/A queueResDist 2492301SN/A .init(Num_OpClasses, 0, 99, 2) 2502301SN/A .name(name() + ".IQ:residence:") 2512301SN/A .desc("cycles from dispatch to issue") 2522301SN/A .flags(total | pdf | cdf ) 2532301SN/A ; 2542301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2552326SN/A queueResDist.subname(i, opClassStrings[i]); 2562301SN/A } 2572361SN/A*/ 2582326SN/A numIssuedDist 2592307SN/A .init(0,totalWidth,1) 2608240Snate@binkert.org .name(name() + ".issued_per_cycle") 2612301SN/A .desc("Number of insts issued each cycle") 2622307SN/A .flags(pdf) 2632301SN/A ; 2642301SN/A/* 2652301SN/A dist_unissued 2662301SN/A .init(Num_OpClasses+2) 2678240Snate@binkert.org .name(name() + ".unissued_cause") 2682301SN/A .desc("Reason ready instruction not issued") 2692301SN/A .flags(pdf | dist) 2702301SN/A ; 2712301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2722301SN/A dist_unissued.subname(i, unissued_names[i]); 2732301SN/A } 2742301SN/A*/ 2752326SN/A statIssuedInstType 2764762Snate@binkert.org .init(numThreads,Enums::Num_OpClass) 2778240Snate@binkert.org .name(name() + ".FU_type") 2782301SN/A .desc("Type of FU issued") 2792301SN/A .flags(total | pdf | dist) 2802301SN/A ; 2814762Snate@binkert.org statIssuedInstType.ysubnames(Enums::OpClassStrings); 2822301SN/A 2832301SN/A // 2842301SN/A // How long did instructions for a particular FU type wait prior to issue 2852301SN/A // 2862361SN/A/* 2872326SN/A issueDelayDist 2882301SN/A .init(Num_OpClasses,0,99,2) 2898240Snate@binkert.org .name(name() + ".") 2902301SN/A .desc("cycles from operands ready to issue") 2912301SN/A .flags(pdf | cdf) 2922301SN/A ; 2932301SN/A 2942301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2952980Sgblack@eecs.umich.edu std::stringstream subname; 2962301SN/A subname << opClassStrings[i] << "_delay"; 2972326SN/A issueDelayDist.subname(i, subname.str()); 2982301SN/A } 2992361SN/A*/ 3002326SN/A issueRate 3018240Snate@binkert.org .name(name() + ".rate") 3022301SN/A .desc("Inst issue rate") 3032301SN/A .flags(total) 3042301SN/A ; 3052326SN/A issueRate = iqInstsIssued / cpu->numCycles; 3062727Sktlim@umich.edu 3072326SN/A statFuBusy 3082301SN/A .init(Num_OpClasses) 3098240Snate@binkert.org .name(name() + ".fu_full") 3102301SN/A .desc("attempts to use FU when none available") 3112301SN/A .flags(pdf | dist) 3122301SN/A ; 3132301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3144762Snate@binkert.org statFuBusy.subname(i, Enums::OpClassStrings[i]); 3152301SN/A } 3162301SN/A 3172326SN/A fuBusy 3182301SN/A .init(numThreads) 3198240Snate@binkert.org .name(name() + ".fu_busy_cnt") 3202301SN/A .desc("FU busy when requested") 3212301SN/A .flags(total) 3222301SN/A ; 3232301SN/A 3242326SN/A fuBusyRate 3258240Snate@binkert.org .name(name() + ".fu_busy_rate") 3262301SN/A .desc("FU busy rate (busy events/executed inst)") 3272301SN/A .flags(total) 3282301SN/A ; 3292326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3302301SN/A 3316221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3322292SN/A // Tell mem dependence unit to reg stats as well. 3336221Snate@binkert.org memDepUnit[tid].regStats(); 3342292SN/A } 3357897Shestness@cs.utexas.edu 3367897Shestness@cs.utexas.edu intInstQueueReads 3377897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3387897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3397897Shestness@cs.utexas.edu .flags(total); 3407897Shestness@cs.utexas.edu 3417897Shestness@cs.utexas.edu intInstQueueWrites 3427897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3437897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3447897Shestness@cs.utexas.edu .flags(total); 3457897Shestness@cs.utexas.edu 3467897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3477897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3487897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3497897Shestness@cs.utexas.edu .flags(total); 3507897Shestness@cs.utexas.edu 3517897Shestness@cs.utexas.edu fpInstQueueReads 3527897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3537897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3547897Shestness@cs.utexas.edu .flags(total); 3557897Shestness@cs.utexas.edu 3567897Shestness@cs.utexas.edu fpInstQueueWrites 3577897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3587897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3597897Shestness@cs.utexas.edu .flags(total); 3607897Shestness@cs.utexas.edu 3617897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses 3627897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3637897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3647897Shestness@cs.utexas.edu .flags(total); 3657897Shestness@cs.utexas.edu 3667897Shestness@cs.utexas.edu intAluAccesses 3677897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 3687897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 3697897Shestness@cs.utexas.edu .flags(total); 3707897Shestness@cs.utexas.edu 3717897Shestness@cs.utexas.edu fpAluAccesses 3727897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 3737897Shestness@cs.utexas.edu .desc("Number of floating point alu accesses") 3747897Shestness@cs.utexas.edu .flags(total); 3757897Shestness@cs.utexas.edu 3761062SN/A} 3771062SN/A 3781062SN/Atemplate <class Impl> 3791062SN/Avoid 3802307SN/AInstructionQueue<Impl>::resetState() 3811060SN/A{ 3822307SN/A //Initialize thread IQ counts 3836221Snate@binkert.org for (ThreadID tid = 0; tid <numThreads; tid++) { 3846221Snate@binkert.org count[tid] = 0; 3856221Snate@binkert.org instList[tid].clear(); 3862307SN/A } 3871060SN/A 3882307SN/A // Initialize the number of free IQ entries. 3892307SN/A freeEntries = numEntries; 3902307SN/A 3912307SN/A // Note that in actuality, the registers corresponding to the logical 3922307SN/A // registers start off as ready. However this doesn't matter for the 3932307SN/A // IQ as the instruction should have been correctly told if those 3942307SN/A // registers are ready in rename. Thus it can all be initialized as 3952307SN/A // unready. 3962307SN/A for (int i = 0; i < numPhysRegs; ++i) { 3972307SN/A regScoreboard[i] = false; 3982307SN/A } 3992307SN/A 4006221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 4016221Snate@binkert.org squashedSeqNum[tid] = 0; 4022307SN/A } 4032307SN/A 4042307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4052307SN/A while (!readyInsts[i].empty()) 4062307SN/A readyInsts[i].pop(); 4072307SN/A queueOnList[i] = false; 4082307SN/A readyIt[i] = listOrder.end(); 4092307SN/A } 4102307SN/A nonSpecInsts.clear(); 4112307SN/A listOrder.clear(); 4127944SGiacomo.Gabrielli@arm.com deferredMemInsts.clear(); 4131060SN/A} 4141060SN/A 4151061SN/Atemplate <class Impl> 4161060SN/Avoid 4176221Snate@binkert.orgInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4181060SN/A{ 4192292SN/A activeThreads = at_ptr; 4202064SN/A} 4212064SN/A 4222064SN/Atemplate <class Impl> 4232064SN/Avoid 4242292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4252064SN/A{ 4264318Sktlim@umich.edu issueToExecuteQueue = i2e_ptr; 4271060SN/A} 4281060SN/A 4291061SN/Atemplate <class Impl> 4301060SN/Avoid 4311060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4321060SN/A{ 4331060SN/A timeBuffer = tb_ptr; 4341060SN/A 4351060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4361060SN/A} 4371060SN/A 4381684SN/Atemplate <class Impl> 4392307SN/Avoid 4409444SAndreas.Sandberg@ARM.comInstructionQueue<Impl>::drainSanityCheck() const 4412307SN/A{ 4429444SAndreas.Sandberg@ARM.com assert(dependGraph.empty()); 4439444SAndreas.Sandberg@ARM.com assert(instsToExecute.empty()); 4449444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; ++tid) 4459444SAndreas.Sandberg@ARM.com memDepUnit[tid].drainSanityCheck(); 4462307SN/A} 4472307SN/A 4482307SN/Atemplate <class Impl> 4492307SN/Avoid 4502307SN/AInstructionQueue<Impl>::takeOverFrom() 4512307SN/A{ 4529444SAndreas.Sandberg@ARM.com resetState(); 4532307SN/A} 4542307SN/A 4552307SN/Atemplate <class Impl> 4562292SN/Aint 4576221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4582292SN/A{ 4592292SN/A if (iqPolicy == Partitioned) { 4602292SN/A return numEntries / num_threads; 4612292SN/A } else { 4622292SN/A return 0; 4632292SN/A } 4642292SN/A} 4652292SN/A 4662292SN/A 4672292SN/Atemplate <class Impl> 4682292SN/Avoid 4692292SN/AInstructionQueue<Impl>::resetEntries() 4702292SN/A{ 4712292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4723867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 4732292SN/A 4746221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4756221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4762292SN/A 4773867Sbinkertn@umich.edu while (threads != end) { 4786221Snate@binkert.org ThreadID tid = *threads++; 4793867Sbinkertn@umich.edu 4802292SN/A if (iqPolicy == Partitioned) { 4813867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 4822292SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4833867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 4842292SN/A } 4852292SN/A } 4862292SN/A } 4872292SN/A} 4882292SN/A 4892292SN/Atemplate <class Impl> 4901684SN/Aunsigned 4911684SN/AInstructionQueue<Impl>::numFreeEntries() 4921684SN/A{ 4931684SN/A return freeEntries; 4941684SN/A} 4951684SN/A 4962292SN/Atemplate <class Impl> 4972292SN/Aunsigned 4986221Snate@binkert.orgInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 4992292SN/A{ 5002292SN/A return maxEntries[tid] - count[tid]; 5012292SN/A} 5022292SN/A 5031060SN/A// Might want to do something more complex if it knows how many instructions 5041060SN/A// will be issued this cycle. 5051061SN/Atemplate <class Impl> 5061060SN/Abool 5071060SN/AInstructionQueue<Impl>::isFull() 5081060SN/A{ 5091060SN/A if (freeEntries == 0) { 5101060SN/A return(true); 5111060SN/A } else { 5121060SN/A return(false); 5131060SN/A } 5141060SN/A} 5151060SN/A 5161061SN/Atemplate <class Impl> 5172292SN/Abool 5186221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid) 5192292SN/A{ 5202292SN/A if (numFreeEntries(tid) == 0) { 5212292SN/A return(true); 5222292SN/A } else { 5232292SN/A return(false); 5242292SN/A } 5252292SN/A} 5262292SN/A 5272292SN/Atemplate <class Impl> 5282292SN/Abool 5292292SN/AInstructionQueue<Impl>::hasReadyInsts() 5302292SN/A{ 5312292SN/A if (!listOrder.empty()) { 5322292SN/A return true; 5332292SN/A } 5342292SN/A 5352292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5362292SN/A if (!readyInsts[i].empty()) { 5372292SN/A return true; 5382292SN/A } 5392292SN/A } 5402292SN/A 5412292SN/A return false; 5422292SN/A} 5432292SN/A 5442292SN/Atemplate <class Impl> 5451060SN/Avoid 5461061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5471060SN/A{ 5487897Shestness@cs.utexas.edu new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5491060SN/A // Make sure the instruction is valid 5501060SN/A assert(new_inst); 5511060SN/A 5527720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5537720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 5541060SN/A 5551060SN/A assert(freeEntries != 0); 5561060SN/A 5572292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5581060SN/A 5592064SN/A --freeEntries; 5601060SN/A 5612292SN/A new_inst->setInIQ(); 5621060SN/A 5631060SN/A // Look through its source registers (physical regs), and mark any 5641060SN/A // dependencies. 5651060SN/A addToDependents(new_inst); 5661060SN/A 5671060SN/A // Have this instruction set itself as the producer of its destination 5681060SN/A // register(s). 5692326SN/A addToProducers(new_inst); 5701060SN/A 5711061SN/A if (new_inst->isMemRef()) { 5722292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5731062SN/A } else { 5741062SN/A addIfReady(new_inst); 5751061SN/A } 5761061SN/A 5771062SN/A ++iqInstsAdded; 5781060SN/A 5792292SN/A count[new_inst->threadNumber]++; 5802292SN/A 5811060SN/A assert(freeEntries == (numEntries - countInsts())); 5821060SN/A} 5831060SN/A 5841061SN/Atemplate <class Impl> 5851061SN/Avoid 5862292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5871061SN/A{ 5881061SN/A // @todo: Clean up this code; can do it by setting inst as unable 5891061SN/A // to issue, then calling normal insert on the inst. 5907897Shestness@cs.utexas.edu new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5911061SN/A 5922292SN/A assert(new_inst); 5931061SN/A 5942292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 5951061SN/A 5967720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 5972326SN/A "to the IQ.\n", 5987720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 5992064SN/A 6001061SN/A assert(freeEntries != 0); 6011061SN/A 6022292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6031061SN/A 6042064SN/A --freeEntries; 6051061SN/A 6062292SN/A new_inst->setInIQ(); 6071061SN/A 6081061SN/A // Have this instruction set itself as the producer of its destination 6091061SN/A // register(s). 6102326SN/A addToProducers(new_inst); 6111061SN/A 6121061SN/A // If it's a memory instruction, add it to the memory dependency 6131061SN/A // unit. 6142292SN/A if (new_inst->isMemRef()) { 6152292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6161061SN/A } 6171062SN/A 6181062SN/A ++iqNonSpecInstsAdded; 6192292SN/A 6202292SN/A count[new_inst->threadNumber]++; 6212292SN/A 6222292SN/A assert(freeEntries == (numEntries - countInsts())); 6231061SN/A} 6241061SN/A 6251061SN/Atemplate <class Impl> 6261060SN/Avoid 6272292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 6281060SN/A{ 6292292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6301060SN/A 6312292SN/A insertNonSpec(barr_inst); 6322292SN/A} 6331060SN/A 6342064SN/Atemplate <class Impl> 6352333SN/Atypename Impl::DynInstPtr 6362333SN/AInstructionQueue<Impl>::getInstToExecute() 6372333SN/A{ 6382333SN/A assert(!instsToExecute.empty()); 6392333SN/A DynInstPtr inst = instsToExecute.front(); 6402333SN/A instsToExecute.pop_front(); 6417897Shestness@cs.utexas.edu if (inst->isFloating()){ 6427897Shestness@cs.utexas.edu fpInstQueueReads++; 6437897Shestness@cs.utexas.edu } else { 6447897Shestness@cs.utexas.edu intInstQueueReads++; 6457897Shestness@cs.utexas.edu } 6462333SN/A return inst; 6472333SN/A} 6481060SN/A 6492333SN/Atemplate <class Impl> 6502064SN/Avoid 6512292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6522292SN/A{ 6532292SN/A assert(!readyInsts[op_class].empty()); 6542292SN/A 6552292SN/A ListOrderEntry queue_entry; 6562292SN/A 6572292SN/A queue_entry.queueType = op_class; 6582292SN/A 6592292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6602292SN/A 6612292SN/A ListOrderIt list_it = listOrder.begin(); 6622292SN/A ListOrderIt list_end_it = listOrder.end(); 6632292SN/A 6642292SN/A while (list_it != list_end_it) { 6652292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6662292SN/A break; 6672292SN/A } 6682292SN/A 6692292SN/A list_it++; 6701060SN/A } 6711060SN/A 6722292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6732292SN/A queueOnList[op_class] = true; 6742292SN/A} 6751060SN/A 6762292SN/Atemplate <class Impl> 6772292SN/Avoid 6782292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6792292SN/A{ 6802292SN/A // Get iterator of next item on the list 6812292SN/A // Delete the original iterator 6822292SN/A // Determine if the next item is either the end of the list or younger 6832292SN/A // than the new instruction. If so, then add in a new iterator right here. 6842292SN/A // If not, then move along. 6852292SN/A ListOrderEntry queue_entry; 6862292SN/A OpClass op_class = (*list_order_it).queueType; 6872292SN/A ListOrderIt next_it = list_order_it; 6882292SN/A 6892292SN/A ++next_it; 6902292SN/A 6912292SN/A queue_entry.queueType = op_class; 6922292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6932292SN/A 6942292SN/A while (next_it != listOrder.end() && 6952292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 6962292SN/A ++next_it; 6971060SN/A } 6981060SN/A 6992292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7001060SN/A} 7011060SN/A 7022292SN/Atemplate <class Impl> 7032292SN/Avoid 7042292SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 7052292SN/A{ 7062367SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7079444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 7082292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7092292SN/A // long latency op). Wake it if it was. This may be overkill. 7102292SN/A iewStage->wakeCPU(); 7112292SN/A 7122326SN/A if (fu_idx > -1) 7132326SN/A fuPool->freeUnitNextCycle(fu_idx); 7142292SN/A 7152326SN/A // @todo: Ensure that these FU Completions happen at the beginning 7162326SN/A // of a cycle, otherwise they could add too many instructions to 7172326SN/A // the queue. 7185327Smengke97@hotmail.com issueToExecuteQueue->access(-1)->size++; 7192333SN/A instsToExecute.push_back(inst); 7202292SN/A} 7212292SN/A 7221061SN/A// @todo: Figure out a better way to remove the squashed items from the 7231061SN/A// lists. Checking the top item of each list to see if it's squashed 7241061SN/A// wastes time and forces jumps. 7251061SN/Atemplate <class Impl> 7261060SN/Avoid 7271060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7281060SN/A{ 7292292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7302292SN/A "the IQ.\n"); 7311060SN/A 7321060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7331060SN/A 7347944SGiacomo.Gabrielli@arm.com DynInstPtr deferred_mem_inst; 7357944SGiacomo.Gabrielli@arm.com int total_deferred_mem_issued = 0; 7367944SGiacomo.Gabrielli@arm.com while (total_deferred_mem_issued < totalWidth && 7377962Ssaidi@eecs.umich.edu (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { 7387944SGiacomo.Gabrielli@arm.com issueToExecuteQueue->access(0)->size++; 7397944SGiacomo.Gabrielli@arm.com instsToExecute.push_back(deferred_mem_inst); 7407944SGiacomo.Gabrielli@arm.com total_deferred_mem_issued++; 7417944SGiacomo.Gabrielli@arm.com } 7427944SGiacomo.Gabrielli@arm.com 7432292SN/A // Have iterator to head of the list 7442292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7452292SN/A // Try to get a FU that can do what this op needs. 7462292SN/A // If successful, change the oldestInst to the new top of the list, put 7472292SN/A // the queue in the proper place in the list. 7482292SN/A // Increment the iterator. 7492292SN/A // This will avoid trying to schedule a certain op class if there are no 7502292SN/A // FUs that handle it. 7512292SN/A ListOrderIt order_it = listOrder.begin(); 7522292SN/A ListOrderIt order_end_it = listOrder.end(); 7532292SN/A int total_issued = 0; 7541060SN/A 7557944SGiacomo.Gabrielli@arm.com while (total_issued < (totalWidth - total_deferred_mem_issued) && 7562820Sktlim@umich.edu iewStage->canIssue() && 7572326SN/A order_it != order_end_it) { 7582292SN/A OpClass op_class = (*order_it).queueType; 7591060SN/A 7602292SN/A assert(!readyInsts[op_class].empty()); 7611060SN/A 7622292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7631060SN/A 7647897Shestness@cs.utexas.edu issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 7657897Shestness@cs.utexas.edu 7662292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 7671060SN/A 7682292SN/A if (issuing_inst->isSquashed()) { 7692292SN/A readyInsts[op_class].pop(); 7701060SN/A 7712292SN/A if (!readyInsts[op_class].empty()) { 7722292SN/A moveToYoungerInst(order_it); 7732292SN/A } else { 7742292SN/A readyIt[op_class] = listOrder.end(); 7752292SN/A queueOnList[op_class] = false; 7761060SN/A } 7771060SN/A 7782292SN/A listOrder.erase(order_it++); 7791060SN/A 7802292SN/A ++iqSquashedInstsIssued; 7812292SN/A 7822292SN/A continue; 7831060SN/A } 7841060SN/A 7852326SN/A int idx = -2; 7869184Sandreas.hansson@arm.com Cycles op_latency = Cycles(1); 7876221Snate@binkert.org ThreadID tid = issuing_inst->threadNumber; 7881060SN/A 7892326SN/A if (op_class != No_OpClass) { 7902326SN/A idx = fuPool->getUnit(op_class); 7917897Shestness@cs.utexas.edu issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 7922326SN/A if (idx > -1) { 7932326SN/A op_latency = fuPool->getOpLatency(op_class); 7941060SN/A } 7951060SN/A } 7961060SN/A 7972348SN/A // If we have an instruction that doesn't require a FU, or a 7982348SN/A // valid FU, then schedule for execution. 7992326SN/A if (idx == -2 || idx != -1) { 8009184Sandreas.hansson@arm.com if (op_latency == Cycles(1)) { 8012292SN/A i2e_info->size++; 8022333SN/A instsToExecute.push_back(issuing_inst); 8031060SN/A 8042326SN/A // Add the FU onto the list of FU's to be freed next 8052326SN/A // cycle if we used one. 8062326SN/A if (idx >= 0) 8072326SN/A fuPool->freeUnitNextCycle(idx); 8082292SN/A } else { 8099184Sandreas.hansson@arm.com Cycles issue_latency = fuPool->getIssueLatency(op_class); 8102326SN/A // Generate completion event for the FU 8112326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8122326SN/A idx, this); 8131060SN/A 8149180Sandreas.hansson@arm.com cpu->schedule(execution, 8159180Sandreas.hansson@arm.com cpu->clockEdge(Cycles(op_latency - 1))); 8161060SN/A 8172326SN/A // @todo: Enforce that issue_latency == 1 or op_latency 8189184Sandreas.hansson@arm.com if (issue_latency > Cycles(1)) { 8192348SN/A // If FU isn't pipelined, then it must be freed 8202348SN/A // upon the execution completing. 8212326SN/A execution->setFreeFU(); 8222292SN/A } else { 8232292SN/A // Add the FU onto the list of FU's to be freed next cycle. 8242326SN/A fuPool->freeUnitNextCycle(idx); 8252292SN/A } 8261060SN/A } 8271060SN/A 8287720Sgblack@eecs.umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8292292SN/A "[sn:%lli]\n", 8307720Sgblack@eecs.umich.edu tid, issuing_inst->pcState(), 8312292SN/A issuing_inst->seqNum); 8321060SN/A 8332292SN/A readyInsts[op_class].pop(); 8341061SN/A 8352292SN/A if (!readyInsts[op_class].empty()) { 8362292SN/A moveToYoungerInst(order_it); 8372292SN/A } else { 8382292SN/A readyIt[op_class] = listOrder.end(); 8392292SN/A queueOnList[op_class] = false; 8401060SN/A } 8411060SN/A 8422064SN/A issuing_inst->setIssued(); 8432292SN/A ++total_issued; 8442064SN/A 8458471SGiacomo.Gabrielli@arm.com#if TRACING_ON 8469046SAli.Saidi@ARM.com issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 8478471SGiacomo.Gabrielli@arm.com#endif 8488471SGiacomo.Gabrielli@arm.com 8492292SN/A if (!issuing_inst->isMemRef()) { 8502292SN/A // Memory instructions can not be freed from the IQ until they 8512292SN/A // complete. 8522292SN/A ++freeEntries; 8532301SN/A count[tid]--; 8542731Sktlim@umich.edu issuing_inst->clearInIQ(); 8552292SN/A } else { 8562301SN/A memDepUnit[tid].issue(issuing_inst); 8572292SN/A } 8582292SN/A 8592292SN/A listOrder.erase(order_it++); 8602326SN/A statIssuedInstType[tid][op_class]++; 8612820Sktlim@umich.edu iewStage->incrWb(issuing_inst->seqNum); 8622292SN/A } else { 8632326SN/A statFuBusy[op_class]++; 8642326SN/A fuBusy[tid]++; 8652292SN/A ++order_it; 8661060SN/A } 8671060SN/A } 8681062SN/A 8692326SN/A numIssuedDist.sample(total_issued); 8702326SN/A iqInstsIssued+= total_issued; 8712307SN/A 8722348SN/A // If we issued any instructions, tell the CPU we had activity. 8738071SAli.Saidi@ARM.com // @todo If the way deferred memory instructions are handeled due to 8748071SAli.Saidi@ARM.com // translation changes then the deferredMemInsts condition should be removed 8758071SAli.Saidi@ARM.com // from the code below. 8768071SAli.Saidi@ARM.com if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) { 8772292SN/A cpu->activityThisCycle(); 8782292SN/A } else { 8792292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8802292SN/A } 8811060SN/A} 8821060SN/A 8831061SN/Atemplate <class Impl> 8841060SN/Avoid 8851061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 8861060SN/A{ 8872292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 8882292SN/A "to execute.\n", inst); 8891062SN/A 8902292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 8911060SN/A 8921061SN/A assert(inst_it != nonSpecInsts.end()); 8931060SN/A 8946221Snate@binkert.org ThreadID tid = (*inst_it).second->threadNumber; 8952292SN/A 8964033Sktlim@umich.edu (*inst_it).second->setAtCommit(); 8974033Sktlim@umich.edu 8981061SN/A (*inst_it).second->setCanIssue(); 8991060SN/A 9001062SN/A if (!(*inst_it).second->isMemRef()) { 9011062SN/A addIfReady((*inst_it).second); 9021062SN/A } else { 9032292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9041062SN/A } 9051060SN/A 9062292SN/A (*inst_it).second = NULL; 9072292SN/A 9081061SN/A nonSpecInsts.erase(inst_it); 9091060SN/A} 9101060SN/A 9111061SN/Atemplate <class Impl> 9121061SN/Avoid 9136221Snate@binkert.orgInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9142292SN/A{ 9152292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9162292SN/A tid,inst); 9172292SN/A 9182292SN/A ListIt iq_it = instList[tid].begin(); 9192292SN/A 9202292SN/A while (iq_it != instList[tid].end() && 9212292SN/A (*iq_it)->seqNum <= inst) { 9222292SN/A ++iq_it; 9232292SN/A instList[tid].pop_front(); 9242292SN/A } 9252292SN/A 9262292SN/A assert(freeEntries == (numEntries - countInsts())); 9272292SN/A} 9282292SN/A 9292292SN/Atemplate <class Impl> 9302301SN/Aint 9311684SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 9321684SN/A{ 9332301SN/A int dependents = 0; 9342301SN/A 9357897Shestness@cs.utexas.edu // The instruction queue here takes care of both floating and int ops 9367897Shestness@cs.utexas.edu if (completed_inst->isFloating()) { 9377897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses++; 9387897Shestness@cs.utexas.edu } else { 9397897Shestness@cs.utexas.edu intInstQueueWakeupAccesses++; 9407897Shestness@cs.utexas.edu } 9417897Shestness@cs.utexas.edu 9422292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 9432292SN/A 9442292SN/A assert(!completed_inst->isSquashed()); 9451684SN/A 9461684SN/A // Tell the memory dependence unit to wake any dependents on this 9472292SN/A // instruction if it is a memory instruction. Also complete the memory 9482326SN/A // instruction at this point since we know it executed without issues. 9492326SN/A // @todo: Might want to rename "completeMemInst" to something that 9502326SN/A // indicates that it won't need to be replayed, and call this 9512326SN/A // earlier. Might not be a big deal. 9521684SN/A if (completed_inst->isMemRef()) { 9532292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 9542292SN/A completeMemInst(completed_inst); 9552292SN/A } else if (completed_inst->isMemBarrier() || 9562292SN/A completed_inst->isWriteBarrier()) { 9572292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 9581684SN/A } 9591684SN/A 9601684SN/A for (int dest_reg_idx = 0; 9611684SN/A dest_reg_idx < completed_inst->numDestRegs(); 9621684SN/A dest_reg_idx++) 9631684SN/A { 9641684SN/A PhysRegIndex dest_reg = 9651684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 9661684SN/A 9671684SN/A // Special case of uniq or control registers. They are not 9681684SN/A // handled by the IQ and thus have no dependency graph entry. 9691684SN/A // @todo Figure out a cleaner way to handle this. 9701684SN/A if (dest_reg >= numPhysRegs) { 9717599Sminkyu.jeong@arm.com DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 9727599Sminkyu.jeong@arm.com numPhysRegs); 9731684SN/A continue; 9741684SN/A } 9751684SN/A 9762292SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 9771684SN/A (int) dest_reg); 9781684SN/A 9792326SN/A //Go through the dependency chain, marking the registers as 9802326SN/A //ready within the waiting instructions. 9812326SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg); 9821684SN/A 9832326SN/A while (dep_inst) { 9847599Sminkyu.jeong@arm.com DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 9857720Sgblack@eecs.umich.edu "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 9861684SN/A 9871684SN/A // Might want to give more information to the instruction 9882326SN/A // so that it knows which of its source registers is 9892326SN/A // ready. However that would mean that the dependency 9902326SN/A // graph entries would need to hold the src_reg_idx. 9912326SN/A dep_inst->markSrcRegReady(); 9921684SN/A 9932326SN/A addIfReady(dep_inst); 9941684SN/A 9952326SN/A dep_inst = dependGraph.pop(dest_reg); 9961684SN/A 9972301SN/A ++dependents; 9981684SN/A } 9991684SN/A 10002326SN/A // Reset the head node now that all of its dependents have 10012326SN/A // been woken up. 10022326SN/A assert(dependGraph.empty(dest_reg)); 10032326SN/A dependGraph.clearInst(dest_reg); 10041684SN/A 10051684SN/A // Mark the scoreboard as having that register ready. 10061684SN/A regScoreboard[dest_reg] = true; 10071684SN/A } 10082301SN/A return dependents; 10092064SN/A} 10102064SN/A 10112064SN/Atemplate <class Impl> 10122064SN/Avoid 10132292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 10142064SN/A{ 10152292SN/A OpClass op_class = ready_inst->opClass(); 10162292SN/A 10172292SN/A readyInsts[op_class].push(ready_inst); 10182292SN/A 10192326SN/A // Will need to reorder the list if either a queue is not on the list, 10202326SN/A // or it has an older instruction than last time. 10212326SN/A if (!queueOnList[op_class]) { 10222326SN/A addToOrderList(op_class); 10232326SN/A } else if (readyInsts[op_class].top()->seqNum < 10242326SN/A (*readyIt[op_class]).oldestInst) { 10252326SN/A listOrder.erase(readyIt[op_class]); 10262326SN/A addToOrderList(op_class); 10272326SN/A } 10282326SN/A 10292292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10307720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 10317720Sgblack@eecs.umich.edu ready_inst->pcState(), op_class, ready_inst->seqNum); 10322064SN/A} 10332064SN/A 10342064SN/Atemplate <class Impl> 10352064SN/Avoid 10362292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 10372064SN/A{ 10384033Sktlim@umich.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 10397944SGiacomo.Gabrielli@arm.com 10407944SGiacomo.Gabrielli@arm.com // Reset DTB translation state 10419046SAli.Saidi@ARM.com resched_inst->translationStarted(false); 10429046SAli.Saidi@ARM.com resched_inst->translationCompleted(false); 10437944SGiacomo.Gabrielli@arm.com 10444033Sktlim@umich.edu resched_inst->clearCanIssue(); 10452292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 10462064SN/A} 10472064SN/A 10482064SN/Atemplate <class Impl> 10492064SN/Avoid 10502292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 10512064SN/A{ 10522292SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 10532292SN/A} 10542292SN/A 10552292SN/Atemplate <class Impl> 10562292SN/Avoid 10572292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 10582292SN/A{ 10596221Snate@binkert.org ThreadID tid = completed_inst->threadNumber; 10602292SN/A 10617720Sgblack@eecs.umich.edu DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 10627720Sgblack@eecs.umich.edu completed_inst->pcState(), completed_inst->seqNum); 10632292SN/A 10642292SN/A ++freeEntries; 10652292SN/A 10669046SAli.Saidi@ARM.com completed_inst->memOpDone(true); 10672292SN/A 10682292SN/A memDepUnit[tid].completed(completed_inst); 10692292SN/A count[tid]--; 10701684SN/A} 10711684SN/A 10721684SN/Atemplate <class Impl> 10731684SN/Avoid 10747944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 10757944SGiacomo.Gabrielli@arm.com{ 10767944SGiacomo.Gabrielli@arm.com deferredMemInsts.push_back(deferred_inst); 10777944SGiacomo.Gabrielli@arm.com} 10787944SGiacomo.Gabrielli@arm.com 10797944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 10807944SGiacomo.Gabrielli@arm.comtypename Impl::DynInstPtr 10817944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::getDeferredMemInstToExecute() 10827944SGiacomo.Gabrielli@arm.com{ 10837944SGiacomo.Gabrielli@arm.com for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 10847944SGiacomo.Gabrielli@arm.com ++it) { 10859046SAli.Saidi@ARM.com if ((*it)->translationCompleted() || (*it)->isSquashed()) { 10867944SGiacomo.Gabrielli@arm.com DynInstPtr ret = *it; 10877944SGiacomo.Gabrielli@arm.com deferredMemInsts.erase(it); 10887944SGiacomo.Gabrielli@arm.com return ret; 10897944SGiacomo.Gabrielli@arm.com } 10907944SGiacomo.Gabrielli@arm.com } 10917944SGiacomo.Gabrielli@arm.com return NULL; 10927944SGiacomo.Gabrielli@arm.com} 10937944SGiacomo.Gabrielli@arm.com 10947944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 10957944SGiacomo.Gabrielli@arm.comvoid 10961061SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 10971061SN/A DynInstPtr &faulting_load) 10981061SN/A{ 10997897Shestness@cs.utexas.edu intInstQueueWrites++; 11002292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 11011061SN/A} 11021061SN/A 11031061SN/Atemplate <class Impl> 11041060SN/Avoid 11056221Snate@binkert.orgInstructionQueue<Impl>::squash(ThreadID tid) 11061060SN/A{ 11072292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 11082292SN/A "the IQ.\n", tid); 11091060SN/A 11101060SN/A // Read instruction sequence number of last instruction out of the 11111060SN/A // time buffer. 11122292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 11131060SN/A 11141681SN/A // Call doSquash if there are insts in the IQ 11152292SN/A if (count[tid] > 0) { 11162292SN/A doSquash(tid); 11171681SN/A } 11181061SN/A 11191061SN/A // Also tell the memory dependence unit to squash. 11202292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 11211060SN/A} 11221060SN/A 11231061SN/Atemplate <class Impl> 11241061SN/Avoid 11256221Snate@binkert.orgInstructionQueue<Impl>::doSquash(ThreadID tid) 11261061SN/A{ 11272326SN/A // Start at the tail. 11282326SN/A ListIt squash_it = instList[tid].end(); 11292326SN/A --squash_it; 11301061SN/A 11312292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 11322292SN/A tid, squashedSeqNum[tid]); 11331061SN/A 11341061SN/A // Squash any instructions younger than the squashed sequence number 11351061SN/A // given. 11362326SN/A while (squash_it != instList[tid].end() && 11372326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 11382292SN/A 11392326SN/A DynInstPtr squashed_inst = (*squash_it); 11407897Shestness@cs.utexas.edu squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 11411061SN/A 11421061SN/A // Only handle the instruction if it actually is in the IQ and 11431061SN/A // hasn't already been squashed in the IQ. 11442292SN/A if (squashed_inst->threadNumber != tid || 11452292SN/A squashed_inst->isSquashedInIQ()) { 11462326SN/A --squash_it; 11472292SN/A continue; 11482292SN/A } 11492292SN/A 11502292SN/A if (!squashed_inst->isIssued() || 11512292SN/A (squashed_inst->isMemRef() && 11529046SAli.Saidi@ARM.com !squashed_inst->memOpDone())) { 11531062SN/A 11547720Sgblack@eecs.umich.edu DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 11557720Sgblack@eecs.umich.edu tid, squashed_inst->seqNum, squashed_inst->pcState()); 11562367SN/A 11571061SN/A // Remove the instruction from the dependency list. 11582292SN/A if (!squashed_inst->isNonSpeculative() && 11592336SN/A !squashed_inst->isStoreConditional() && 11602292SN/A !squashed_inst->isMemBarrier() && 11612292SN/A !squashed_inst->isWriteBarrier()) { 11621061SN/A 11631061SN/A for (int src_reg_idx = 0; 11641681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 11651061SN/A src_reg_idx++) 11661061SN/A { 11671061SN/A PhysRegIndex src_reg = 11681061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 11691061SN/A 11702326SN/A // Only remove it from the dependency graph if it 11712326SN/A // was placed there in the first place. 11722326SN/A 11732326SN/A // Instead of doing a linked list traversal, we 11742326SN/A // can just remove these squashed instructions 11752326SN/A // either at issue time, or when the register is 11762326SN/A // overwritten. The only downside to this is it 11772326SN/A // leaves more room for error. 11782292SN/A 11791061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 11801061SN/A src_reg < numPhysRegs) { 11812326SN/A dependGraph.remove(src_reg, squashed_inst); 11821061SN/A } 11831062SN/A 11842292SN/A 11851062SN/A ++iqSquashedOperandsExamined; 11861061SN/A } 11874033Sktlim@umich.edu } else if (!squashed_inst->isStoreConditional() || 11884033Sktlim@umich.edu !squashed_inst->isCompleted()) { 11892292SN/A NonSpecMapIt ns_inst_it = 11902292SN/A nonSpecInsts.find(squashed_inst->seqNum); 11918275SAli.Saidi@ARM.com 11924033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 11934033Sktlim@umich.edu assert(squashed_inst->getFault() != NoFault); 11944033Sktlim@umich.edu } else { 11951062SN/A 11964033Sktlim@umich.edu (*ns_inst_it).second = NULL; 11971681SN/A 11984033Sktlim@umich.edu nonSpecInsts.erase(ns_inst_it); 11991062SN/A 12004033Sktlim@umich.edu ++iqSquashedNonSpecRemoved; 12014033Sktlim@umich.edu } 12021061SN/A } 12031061SN/A 12041061SN/A // Might want to also clear out the head of the dependency graph. 12051061SN/A 12061061SN/A // Mark it as squashed within the IQ. 12071061SN/A squashed_inst->setSquashedInIQ(); 12081061SN/A 12092292SN/A // @todo: Remove this hack where several statuses are set so the 12102292SN/A // inst will flow through the rest of the pipeline. 12111681SN/A squashed_inst->setIssued(); 12121681SN/A squashed_inst->setCanCommit(); 12132731Sktlim@umich.edu squashed_inst->clearInIQ(); 12142292SN/A 12152292SN/A //Update Thread IQ Count 12162292SN/A count[squashed_inst->threadNumber]--; 12171681SN/A 12181681SN/A ++freeEntries; 12191061SN/A } 12201061SN/A 12212326SN/A instList[tid].erase(squash_it--); 12221062SN/A ++iqSquashedInstsExamined; 12231061SN/A } 12241060SN/A} 12251060SN/A 12261061SN/Atemplate <class Impl> 12271060SN/Abool 12281061SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 12291060SN/A{ 12301060SN/A // Loop through the instruction's source registers, adding 12311060SN/A // them to the dependency list if they are not ready. 12321060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 12331060SN/A bool return_val = false; 12341060SN/A 12351060SN/A for (int src_reg_idx = 0; 12361060SN/A src_reg_idx < total_src_regs; 12371060SN/A src_reg_idx++) 12381060SN/A { 12391060SN/A // Only add it to the dependency graph if it's not ready. 12401060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 12411060SN/A PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 12421060SN/A 12431060SN/A // Check the IQ's scoreboard to make sure the register 12441060SN/A // hasn't become ready while the instruction was in flight 12451060SN/A // between stages. Only if it really isn't ready should 12461060SN/A // it be added to the dependency graph. 12471061SN/A if (src_reg >= numPhysRegs) { 12481061SN/A continue; 12491061SN/A } else if (regScoreboard[src_reg] == false) { 12507720Sgblack@eecs.umich.edu DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12511060SN/A "is being added to the dependency chain.\n", 12527720Sgblack@eecs.umich.edu new_inst->pcState(), src_reg); 12531060SN/A 12542326SN/A dependGraph.insert(src_reg, new_inst); 12551060SN/A 12561060SN/A // Change the return value to indicate that something 12571060SN/A // was added to the dependency graph. 12581060SN/A return_val = true; 12591060SN/A } else { 12607720Sgblack@eecs.umich.edu DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12611060SN/A "became ready before it reached the IQ.\n", 12627720Sgblack@eecs.umich.edu new_inst->pcState(), src_reg); 12631060SN/A // Mark a register ready within the instruction. 12642326SN/A new_inst->markSrcRegReady(src_reg_idx); 12651060SN/A } 12661060SN/A } 12671060SN/A } 12681060SN/A 12691060SN/A return return_val; 12701060SN/A} 12711060SN/A 12721061SN/Atemplate <class Impl> 12731060SN/Avoid 12742326SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 12751060SN/A{ 12762326SN/A // Nothing really needs to be marked when an instruction becomes 12772326SN/A // the producer of a register's value, but for convenience a ptr 12782326SN/A // to the producing instruction will be placed in the head node of 12792326SN/A // the dependency links. 12801060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 12811060SN/A 12821060SN/A for (int dest_reg_idx = 0; 12831060SN/A dest_reg_idx < total_dest_regs; 12841060SN/A dest_reg_idx++) 12851060SN/A { 12861061SN/A PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 12871061SN/A 12881061SN/A // Instructions that use the misc regs will have a reg number 12891061SN/A // higher than the normal physical registers. In this case these 12901061SN/A // registers are not renamed, and there is no need to track 12911061SN/A // dependencies as these instructions must be executed at commit. 12921061SN/A if (dest_reg >= numPhysRegs) { 12931061SN/A continue; 12941060SN/A } 12951060SN/A 12962326SN/A if (!dependGraph.empty(dest_reg)) { 12972326SN/A dependGraph.dump(); 12982292SN/A panic("Dependency graph %i not empty!", dest_reg); 12992064SN/A } 13001062SN/A 13012326SN/A dependGraph.setInst(dest_reg, new_inst); 13021062SN/A 13031060SN/A // Mark the scoreboard to say it's not yet ready. 13041060SN/A regScoreboard[dest_reg] = false; 13051060SN/A } 13061060SN/A} 13071060SN/A 13081061SN/Atemplate <class Impl> 13091060SN/Avoid 13101061SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 13111060SN/A{ 13122326SN/A // If the instruction now has all of its source registers 13131060SN/A // available, then add it to the list of ready instructions. 13141060SN/A if (inst->readyToIssue()) { 13151061SN/A 13161060SN/A //Add the instruction to the proper ready list. 13172292SN/A if (inst->isMemRef()) { 13181061SN/A 13192292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 13201061SN/A 13211062SN/A // Message to the mem dependence unit that this instruction has 13221062SN/A // its registers ready. 13232292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 13241062SN/A 13252292SN/A return; 13262292SN/A } 13271062SN/A 13282292SN/A OpClass op_class = inst->opClass(); 13291061SN/A 13302292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 13317720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 13327720Sgblack@eecs.umich.edu inst->pcState(), op_class, inst->seqNum); 13331061SN/A 13342292SN/A readyInsts[op_class].push(inst); 13351061SN/A 13362326SN/A // Will need to reorder the list if either a queue is not on the list, 13372326SN/A // or it has an older instruction than last time. 13382326SN/A if (!queueOnList[op_class]) { 13392326SN/A addToOrderList(op_class); 13402326SN/A } else if (readyInsts[op_class].top()->seqNum < 13412326SN/A (*readyIt[op_class]).oldestInst) { 13422326SN/A listOrder.erase(readyIt[op_class]); 13432326SN/A addToOrderList(op_class); 13441060SN/A } 13451060SN/A } 13461060SN/A} 13471060SN/A 13481061SN/Atemplate <class Impl> 13491061SN/Aint 13501061SN/AInstructionQueue<Impl>::countInsts() 13511061SN/A{ 13522698Sktlim@umich.edu#if 0 13532292SN/A //ksewell:This works but definitely could use a cleaner write 13542292SN/A //with a more intuitive way of counting. Right now it's 13552292SN/A //just brute force .... 13562698Sktlim@umich.edu // Change the #if if you want to use this method. 13571061SN/A int total_insts = 0; 13581061SN/A 13596221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 13606221Snate@binkert.org ListIt count_it = instList[tid].begin(); 13611681SN/A 13626221Snate@binkert.org while (count_it != instList[tid].end()) { 13632292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 13642292SN/A if (!(*count_it)->isIssued()) { 13652292SN/A ++total_insts; 13662292SN/A } else if ((*count_it)->isMemRef() && 13672292SN/A !(*count_it)->memOpDone) { 13682292SN/A // Loads that have not been marked as executed still count 13692292SN/A // towards the total instructions. 13702292SN/A ++total_insts; 13712292SN/A } 13722292SN/A } 13732292SN/A 13742292SN/A ++count_it; 13751061SN/A } 13761061SN/A } 13771061SN/A 13781061SN/A return total_insts; 13792292SN/A#else 13802292SN/A return numEntries - freeEntries; 13812292SN/A#endif 13821681SN/A} 13831681SN/A 13841681SN/Atemplate <class Impl> 13851681SN/Avoid 13861061SN/AInstructionQueue<Impl>::dumpLists() 13871061SN/A{ 13882292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 13892292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 13901061SN/A 13912292SN/A cprintf("\n"); 13922292SN/A } 13931061SN/A 13941061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 13951061SN/A 13962292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 13972292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 13981061SN/A 13991061SN/A cprintf("Non speculative list: "); 14001061SN/A 14012292SN/A while (non_spec_it != non_spec_end_it) { 14027720Sgblack@eecs.umich.edu cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 14032292SN/A (*non_spec_it).second->seqNum); 14041061SN/A ++non_spec_it; 14051061SN/A } 14061061SN/A 14071061SN/A cprintf("\n"); 14081061SN/A 14092292SN/A ListOrderIt list_order_it = listOrder.begin(); 14102292SN/A ListOrderIt list_order_end_it = listOrder.end(); 14112292SN/A int i = 1; 14122292SN/A 14132292SN/A cprintf("List order: "); 14142292SN/A 14152292SN/A while (list_order_it != list_order_end_it) { 14162292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 14172292SN/A (*list_order_it).oldestInst); 14182292SN/A 14192292SN/A ++list_order_it; 14202292SN/A ++i; 14212292SN/A } 14222292SN/A 14232292SN/A cprintf("\n"); 14241061SN/A} 14252292SN/A 14262292SN/A 14272292SN/Atemplate <class Impl> 14282292SN/Avoid 14292292SN/AInstructionQueue<Impl>::dumpInsts() 14302292SN/A{ 14316221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 14322292SN/A int num = 0; 14332292SN/A int valid_num = 0; 14346221Snate@binkert.org ListIt inst_list_it = instList[tid].begin(); 14352292SN/A 14366221Snate@binkert.org while (inst_list_it != instList[tid].end()) { 14376221Snate@binkert.org cprintf("Instruction:%i\n", num); 14382292SN/A if (!(*inst_list_it)->isSquashed()) { 14392292SN/A if (!(*inst_list_it)->isIssued()) { 14402292SN/A ++valid_num; 14412292SN/A cprintf("Count:%i\n", valid_num); 14422292SN/A } else if ((*inst_list_it)->isMemRef() && 14439046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 14442326SN/A // Loads that have not been marked as executed 14452326SN/A // still count towards the total instructions. 14462292SN/A ++valid_num; 14472292SN/A cprintf("Count:%i\n", valid_num); 14482292SN/A } 14492292SN/A } 14502292SN/A 14517720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 14522292SN/A "Issued:%i\nSquashed:%i\n", 14537720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 14542292SN/A (*inst_list_it)->seqNum, 14552292SN/A (*inst_list_it)->threadNumber, 14562292SN/A (*inst_list_it)->isIssued(), 14572292SN/A (*inst_list_it)->isSquashed()); 14582292SN/A 14592292SN/A if ((*inst_list_it)->isMemRef()) { 14609046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 14612292SN/A } 14622292SN/A 14632292SN/A cprintf("\n"); 14642292SN/A 14652292SN/A inst_list_it++; 14662292SN/A ++num; 14672292SN/A } 14682292SN/A } 14692348SN/A 14702348SN/A cprintf("Insts to Execute list:\n"); 14712348SN/A 14722348SN/A int num = 0; 14732348SN/A int valid_num = 0; 14742348SN/A ListIt inst_list_it = instsToExecute.begin(); 14752348SN/A 14762348SN/A while (inst_list_it != instsToExecute.end()) 14772348SN/A { 14782348SN/A cprintf("Instruction:%i\n", 14792348SN/A num); 14802348SN/A if (!(*inst_list_it)->isSquashed()) { 14812348SN/A if (!(*inst_list_it)->isIssued()) { 14822348SN/A ++valid_num; 14832348SN/A cprintf("Count:%i\n", valid_num); 14842348SN/A } else if ((*inst_list_it)->isMemRef() && 14859046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 14862348SN/A // Loads that have not been marked as executed 14872348SN/A // still count towards the total instructions. 14882348SN/A ++valid_num; 14892348SN/A cprintf("Count:%i\n", valid_num); 14902348SN/A } 14912348SN/A } 14922348SN/A 14937720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 14942348SN/A "Issued:%i\nSquashed:%i\n", 14957720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 14962348SN/A (*inst_list_it)->seqNum, 14972348SN/A (*inst_list_it)->threadNumber, 14982348SN/A (*inst_list_it)->isIssued(), 14992348SN/A (*inst_list_it)->isSquashed()); 15002348SN/A 15012348SN/A if ((*inst_list_it)->isMemRef()) { 15029046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 15032348SN/A } 15042348SN/A 15052348SN/A cprintf("\n"); 15062348SN/A 15072348SN/A inst_list_it++; 15082348SN/A ++num; 15092348SN/A } 15102292SN/A} 1511