inst_queue_impl.hh revision 7599
11689SN/A/*
22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
292831Sksewell@umich.edu *          Korey Sewell
301689SN/A */
311689SN/A
322064SN/A#include <limits>
331060SN/A#include <vector>
341060SN/A
352292SN/A#include "cpu/o3/fu_pool.hh"
361717SN/A#include "cpu/o3/inst_queue.hh"
374762Snate@binkert.org#include "enums/OpClass.hh"
386221Snate@binkert.org#include "params/DerivO3CPU.hh"
394762Snate@binkert.org#include "sim/core.hh"
401060SN/A
416221Snate@binkert.orgusing namespace std;
425529Snate@binkert.org
431061SN/Atemplate <class Impl>
442292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
455606Snate@binkert.org    int fu_idx, InstructionQueue<Impl> *iq_ptr)
465606Snate@binkert.org    : Event(Stat_Event_Pri), inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr),
475606Snate@binkert.org      freeFU(false)
481060SN/A{
492292SN/A    this->setFlags(Event::AutoDelete);
502292SN/A}
512292SN/A
522292SN/Atemplate <class Impl>
532292SN/Avoid
542292SN/AInstructionQueue<Impl>::FUCompletion::process()
552292SN/A{
562326SN/A    iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1);
572292SN/A    inst = NULL;
582292SN/A}
592292SN/A
602292SN/A
612292SN/Atemplate <class Impl>
622292SN/Aconst char *
635336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const
642292SN/A{
654873Sstever@eecs.umich.edu    return "Functional unit completion";
662292SN/A}
672292SN/A
682292SN/Atemplate <class Impl>
694329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr,
705529Snate@binkert.org                                         DerivO3CPUParams *params)
714329Sktlim@umich.edu    : cpu(cpu_ptr),
724329Sktlim@umich.edu      iewStage(iew_ptr),
734329Sktlim@umich.edu      fuPool(params->fuPool),
742292SN/A      numEntries(params->numIQEntries),
752292SN/A      totalWidth(params->issueWidth),
762292SN/A      numPhysIntRegs(params->numPhysIntRegs),
772292SN/A      numPhysFloatRegs(params->numPhysFloatRegs),
782292SN/A      commitToIEWDelay(params->commitToIEWDelay)
792292SN/A{
802292SN/A    assert(fuPool);
812292SN/A
822307SN/A    switchedOut = false;
832307SN/A
845529Snate@binkert.org    numThreads = params->numThreads;
851060SN/A
861060SN/A    // Set the number of physical registers as the number of int + float
871060SN/A    numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
881060SN/A
891060SN/A    //Create an entry for each physical register within the
901060SN/A    //dependency graph.
912326SN/A    dependGraph.resize(numPhysRegs);
921060SN/A
931060SN/A    // Resize the register scoreboard.
941060SN/A    regScoreboard.resize(numPhysRegs);
951060SN/A
962292SN/A    //Initialize Mem Dependence Units
976221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; tid++) {
986221Snate@binkert.org        memDepUnit[tid].init(params, tid);
996221Snate@binkert.org        memDepUnit[tid].setIQ(this);
1001060SN/A    }
1011060SN/A
1022307SN/A    resetState();
1032292SN/A
1042980Sgblack@eecs.umich.edu    std::string policy = params->smtIQPolicy;
1052292SN/A
1062292SN/A    //Convert string to lowercase
1072292SN/A    std::transform(policy.begin(), policy.end(), policy.begin(),
1082292SN/A                   (int(*)(int)) tolower);
1092292SN/A
1102292SN/A    //Figure out resource sharing policy
1112292SN/A    if (policy == "dynamic") {
1122292SN/A        iqPolicy = Dynamic;
1132292SN/A
1142292SN/A        //Set Max Entries to Total ROB Capacity
1156221Snate@binkert.org        for (ThreadID tid = 0; tid < numThreads; tid++) {
1166221Snate@binkert.org            maxEntries[tid] = numEntries;
1172292SN/A        }
1182292SN/A
1192292SN/A    } else if (policy == "partitioned") {
1202292SN/A        iqPolicy = Partitioned;
1212292SN/A
1222292SN/A        //@todo:make work if part_amt doesnt divide evenly.
1232292SN/A        int part_amt = numEntries / numThreads;
1242292SN/A
1252292SN/A        //Divide ROB up evenly
1266221Snate@binkert.org        for (ThreadID tid = 0; tid < numThreads; tid++) {
1276221Snate@binkert.org            maxEntries[tid] = part_amt;
1282292SN/A        }
1292292SN/A
1302831Sksewell@umich.edu        DPRINTF(IQ, "IQ sharing policy set to Partitioned:"
1312292SN/A                "%i entries per thread.\n",part_amt);
1322292SN/A    } else if (policy == "threshold") {
1332292SN/A        iqPolicy = Threshold;
1342292SN/A
1352292SN/A        double threshold =  (double)params->smtIQThreshold / 100;
1362292SN/A
1372292SN/A        int thresholdIQ = (int)((double)threshold * numEntries);
1382292SN/A
1392292SN/A        //Divide up by threshold amount
1406221Snate@binkert.org        for (ThreadID tid = 0; tid < numThreads; tid++) {
1416221Snate@binkert.org            maxEntries[tid] = thresholdIQ;
1422292SN/A        }
1432292SN/A
1442831Sksewell@umich.edu        DPRINTF(IQ, "IQ sharing policy set to Threshold:"
1452292SN/A                "%i entries per thread.\n",thresholdIQ);
1462292SN/A   } else {
1472292SN/A       assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
1482292SN/A              "Partitioned, Threshold}");
1492292SN/A   }
1502292SN/A}
1512292SN/A
1522292SN/Atemplate <class Impl>
1532292SN/AInstructionQueue<Impl>::~InstructionQueue()
1542292SN/A{
1552326SN/A    dependGraph.reset();
1562348SN/A#ifdef DEBUG
1572326SN/A    cprintf("Nodes traversed: %i, removed: %i\n",
1582326SN/A            dependGraph.nodesTraversed, dependGraph.nodesRemoved);
1592348SN/A#endif
1602292SN/A}
1612292SN/A
1622292SN/Atemplate <class Impl>
1632292SN/Astd::string
1642292SN/AInstructionQueue<Impl>::name() const
1652292SN/A{
1662292SN/A    return cpu->name() + ".iq";
1671060SN/A}
1681060SN/A
1691061SN/Atemplate <class Impl>
1701060SN/Avoid
1711062SN/AInstructionQueue<Impl>::regStats()
1721062SN/A{
1732301SN/A    using namespace Stats;
1741062SN/A    iqInstsAdded
1751062SN/A        .name(name() + ".iqInstsAdded")
1761062SN/A        .desc("Number of instructions added to the IQ (excludes non-spec)")
1771062SN/A        .prereq(iqInstsAdded);
1781062SN/A
1791062SN/A    iqNonSpecInstsAdded
1801062SN/A        .name(name() + ".iqNonSpecInstsAdded")
1811062SN/A        .desc("Number of non-speculative instructions added to the IQ")
1821062SN/A        .prereq(iqNonSpecInstsAdded);
1831062SN/A
1842301SN/A    iqInstsIssued
1852301SN/A        .name(name() + ".iqInstsIssued")
1862301SN/A        .desc("Number of instructions issued")
1872301SN/A        .prereq(iqInstsIssued);
1881062SN/A
1891062SN/A    iqIntInstsIssued
1901062SN/A        .name(name() + ".iqIntInstsIssued")
1911062SN/A        .desc("Number of integer instructions issued")
1921062SN/A        .prereq(iqIntInstsIssued);
1931062SN/A
1941062SN/A    iqFloatInstsIssued
1951062SN/A        .name(name() + ".iqFloatInstsIssued")
1961062SN/A        .desc("Number of float instructions issued")
1971062SN/A        .prereq(iqFloatInstsIssued);
1981062SN/A
1991062SN/A    iqBranchInstsIssued
2001062SN/A        .name(name() + ".iqBranchInstsIssued")
2011062SN/A        .desc("Number of branch instructions issued")
2021062SN/A        .prereq(iqBranchInstsIssued);
2031062SN/A
2041062SN/A    iqMemInstsIssued
2051062SN/A        .name(name() + ".iqMemInstsIssued")
2061062SN/A        .desc("Number of memory instructions issued")
2071062SN/A        .prereq(iqMemInstsIssued);
2081062SN/A
2091062SN/A    iqMiscInstsIssued
2101062SN/A        .name(name() + ".iqMiscInstsIssued")
2111062SN/A        .desc("Number of miscellaneous instructions issued")
2121062SN/A        .prereq(iqMiscInstsIssued);
2131062SN/A
2141062SN/A    iqSquashedInstsIssued
2151062SN/A        .name(name() + ".iqSquashedInstsIssued")
2161062SN/A        .desc("Number of squashed instructions issued")
2171062SN/A        .prereq(iqSquashedInstsIssued);
2181062SN/A
2191062SN/A    iqSquashedInstsExamined
2201062SN/A        .name(name() + ".iqSquashedInstsExamined")
2211062SN/A        .desc("Number of squashed instructions iterated over during squash;"
2221062SN/A              " mainly for profiling")
2231062SN/A        .prereq(iqSquashedInstsExamined);
2241062SN/A
2251062SN/A    iqSquashedOperandsExamined
2261062SN/A        .name(name() + ".iqSquashedOperandsExamined")
2271062SN/A        .desc("Number of squashed operands that are examined and possibly "
2281062SN/A              "removed from graph")
2291062SN/A        .prereq(iqSquashedOperandsExamined);
2301062SN/A
2311062SN/A    iqSquashedNonSpecRemoved
2321062SN/A        .name(name() + ".iqSquashedNonSpecRemoved")
2331062SN/A        .desc("Number of squashed non-spec instructions that were removed")
2341062SN/A        .prereq(iqSquashedNonSpecRemoved);
2352361SN/A/*
2362326SN/A    queueResDist
2372301SN/A        .init(Num_OpClasses, 0, 99, 2)
2382301SN/A        .name(name() + ".IQ:residence:")
2392301SN/A        .desc("cycles from dispatch to issue")
2402301SN/A        .flags(total | pdf | cdf )
2412301SN/A        ;
2422301SN/A    for (int i = 0; i < Num_OpClasses; ++i) {
2432326SN/A        queueResDist.subname(i, opClassStrings[i]);
2442301SN/A    }
2452361SN/A*/
2462326SN/A    numIssuedDist
2472307SN/A        .init(0,totalWidth,1)
2482301SN/A        .name(name() + ".ISSUE:issued_per_cycle")
2492301SN/A        .desc("Number of insts issued each cycle")
2502307SN/A        .flags(pdf)
2512301SN/A        ;
2522301SN/A/*
2532301SN/A    dist_unissued
2542301SN/A        .init(Num_OpClasses+2)
2552301SN/A        .name(name() + ".ISSUE:unissued_cause")
2562301SN/A        .desc("Reason ready instruction not issued")
2572301SN/A        .flags(pdf | dist)
2582301SN/A        ;
2592301SN/A    for (int i=0; i < (Num_OpClasses + 2); ++i) {
2602301SN/A        dist_unissued.subname(i, unissued_names[i]);
2612301SN/A    }
2622301SN/A*/
2632326SN/A    statIssuedInstType
2644762Snate@binkert.org        .init(numThreads,Enums::Num_OpClass)
2652301SN/A        .name(name() + ".ISSUE:FU_type")
2662301SN/A        .desc("Type of FU issued")
2672301SN/A        .flags(total | pdf | dist)
2682301SN/A        ;
2694762Snate@binkert.org    statIssuedInstType.ysubnames(Enums::OpClassStrings);
2702301SN/A
2712301SN/A    //
2722301SN/A    //  How long did instructions for a particular FU type wait prior to issue
2732301SN/A    //
2742361SN/A/*
2752326SN/A    issueDelayDist
2762301SN/A        .init(Num_OpClasses,0,99,2)
2772301SN/A        .name(name() + ".ISSUE:")
2782301SN/A        .desc("cycles from operands ready to issue")
2792301SN/A        .flags(pdf | cdf)
2802301SN/A        ;
2812301SN/A
2822301SN/A    for (int i=0; i<Num_OpClasses; ++i) {
2832980Sgblack@eecs.umich.edu        std::stringstream subname;
2842301SN/A        subname << opClassStrings[i] << "_delay";
2852326SN/A        issueDelayDist.subname(i, subname.str());
2862301SN/A    }
2872361SN/A*/
2882326SN/A    issueRate
2892301SN/A        .name(name() + ".ISSUE:rate")
2902301SN/A        .desc("Inst issue rate")
2912301SN/A        .flags(total)
2922301SN/A        ;
2932326SN/A    issueRate = iqInstsIssued / cpu->numCycles;
2942727Sktlim@umich.edu
2952326SN/A    statFuBusy
2962301SN/A        .init(Num_OpClasses)
2972301SN/A        .name(name() + ".ISSUE:fu_full")
2982301SN/A        .desc("attempts to use FU when none available")
2992301SN/A        .flags(pdf | dist)
3002301SN/A        ;
3012301SN/A    for (int i=0; i < Num_OpClasses; ++i) {
3024762Snate@binkert.org        statFuBusy.subname(i, Enums::OpClassStrings[i]);
3032301SN/A    }
3042301SN/A
3052326SN/A    fuBusy
3062301SN/A        .init(numThreads)
3072301SN/A        .name(name() + ".ISSUE:fu_busy_cnt")
3082301SN/A        .desc("FU busy when requested")
3092301SN/A        .flags(total)
3102301SN/A        ;
3112301SN/A
3122326SN/A    fuBusyRate
3132301SN/A        .name(name() + ".ISSUE:fu_busy_rate")
3142301SN/A        .desc("FU busy rate (busy events/executed inst)")
3152301SN/A        .flags(total)
3162301SN/A        ;
3172326SN/A    fuBusyRate = fuBusy / iqInstsIssued;
3182301SN/A
3196221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; tid++) {
3202292SN/A        // Tell mem dependence unit to reg stats as well.
3216221Snate@binkert.org        memDepUnit[tid].regStats();
3222292SN/A    }
3231062SN/A}
3241062SN/A
3251062SN/Atemplate <class Impl>
3261062SN/Avoid
3272307SN/AInstructionQueue<Impl>::resetState()
3281060SN/A{
3292307SN/A    //Initialize thread IQ counts
3306221Snate@binkert.org    for (ThreadID tid = 0; tid <numThreads; tid++) {
3316221Snate@binkert.org        count[tid] = 0;
3326221Snate@binkert.org        instList[tid].clear();
3332307SN/A    }
3341060SN/A
3352307SN/A    // Initialize the number of free IQ entries.
3362307SN/A    freeEntries = numEntries;
3372307SN/A
3382307SN/A    // Note that in actuality, the registers corresponding to the logical
3392307SN/A    // registers start off as ready.  However this doesn't matter for the
3402307SN/A    // IQ as the instruction should have been correctly told if those
3412307SN/A    // registers are ready in rename.  Thus it can all be initialized as
3422307SN/A    // unready.
3432307SN/A    for (int i = 0; i < numPhysRegs; ++i) {
3442307SN/A        regScoreboard[i] = false;
3452307SN/A    }
3462307SN/A
3476221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; ++tid) {
3486221Snate@binkert.org        squashedSeqNum[tid] = 0;
3492307SN/A    }
3502307SN/A
3512307SN/A    for (int i = 0; i < Num_OpClasses; ++i) {
3522307SN/A        while (!readyInsts[i].empty())
3532307SN/A            readyInsts[i].pop();
3542307SN/A        queueOnList[i] = false;
3552307SN/A        readyIt[i] = listOrder.end();
3562307SN/A    }
3572307SN/A    nonSpecInsts.clear();
3582307SN/A    listOrder.clear();
3591060SN/A}
3601060SN/A
3611061SN/Atemplate <class Impl>
3621060SN/Avoid
3636221Snate@binkert.orgInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
3641060SN/A{
3652292SN/A    activeThreads = at_ptr;
3662064SN/A}
3672064SN/A
3682064SN/Atemplate <class Impl>
3692064SN/Avoid
3702292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
3712064SN/A{
3724318Sktlim@umich.edu      issueToExecuteQueue = i2e_ptr;
3731060SN/A}
3741060SN/A
3751061SN/Atemplate <class Impl>
3761060SN/Avoid
3771060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
3781060SN/A{
3791060SN/A    timeBuffer = tb_ptr;
3801060SN/A
3811060SN/A    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
3821060SN/A}
3831060SN/A
3841684SN/Atemplate <class Impl>
3852307SN/Avoid
3862307SN/AInstructionQueue<Impl>::switchOut()
3872307SN/A{
3882367SN/A/*
3892367SN/A    if (!instList[0].empty() || (numEntries != freeEntries) ||
3902367SN/A        !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) {
3912367SN/A        dumpInsts();
3922367SN/A//        assert(0);
3932367SN/A    }
3942367SN/A*/
3952307SN/A    resetState();
3962326SN/A    dependGraph.reset();
3972367SN/A    instsToExecute.clear();
3982307SN/A    switchedOut = true;
3996221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; ++tid) {
4006221Snate@binkert.org        memDepUnit[tid].switchOut();
4012307SN/A    }
4022307SN/A}
4032307SN/A
4042307SN/Atemplate <class Impl>
4052307SN/Avoid
4062307SN/AInstructionQueue<Impl>::takeOverFrom()
4072307SN/A{
4082307SN/A    switchedOut = false;
4092307SN/A}
4102307SN/A
4112307SN/Atemplate <class Impl>
4122292SN/Aint
4136221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads)
4142292SN/A{
4152292SN/A    if (iqPolicy == Partitioned) {
4162292SN/A        return numEntries / num_threads;
4172292SN/A    } else {
4182292SN/A        return 0;
4192292SN/A    }
4202292SN/A}
4212292SN/A
4222292SN/A
4232292SN/Atemplate <class Impl>
4242292SN/Avoid
4252292SN/AInstructionQueue<Impl>::resetEntries()
4262292SN/A{
4272292SN/A    if (iqPolicy != Dynamic || numThreads > 1) {
4283867Sbinkertn@umich.edu        int active_threads = activeThreads->size();
4292292SN/A
4306221Snate@binkert.org        list<ThreadID>::iterator threads = activeThreads->begin();
4316221Snate@binkert.org        list<ThreadID>::iterator end = activeThreads->end();
4322292SN/A
4333867Sbinkertn@umich.edu        while (threads != end) {
4346221Snate@binkert.org            ThreadID tid = *threads++;
4353867Sbinkertn@umich.edu
4362292SN/A            if (iqPolicy == Partitioned) {
4373867Sbinkertn@umich.edu                maxEntries[tid] = numEntries / active_threads;
4382292SN/A            } else if(iqPolicy == Threshold && active_threads == 1) {
4393867Sbinkertn@umich.edu                maxEntries[tid] = numEntries;
4402292SN/A            }
4412292SN/A        }
4422292SN/A    }
4432292SN/A}
4442292SN/A
4452292SN/Atemplate <class Impl>
4461684SN/Aunsigned
4471684SN/AInstructionQueue<Impl>::numFreeEntries()
4481684SN/A{
4491684SN/A    return freeEntries;
4501684SN/A}
4511684SN/A
4522292SN/Atemplate <class Impl>
4532292SN/Aunsigned
4546221Snate@binkert.orgInstructionQueue<Impl>::numFreeEntries(ThreadID tid)
4552292SN/A{
4562292SN/A    return maxEntries[tid] - count[tid];
4572292SN/A}
4582292SN/A
4591060SN/A// Might want to do something more complex if it knows how many instructions
4601060SN/A// will be issued this cycle.
4611061SN/Atemplate <class Impl>
4621060SN/Abool
4631060SN/AInstructionQueue<Impl>::isFull()
4641060SN/A{
4651060SN/A    if (freeEntries == 0) {
4661060SN/A        return(true);
4671060SN/A    } else {
4681060SN/A        return(false);
4691060SN/A    }
4701060SN/A}
4711060SN/A
4721061SN/Atemplate <class Impl>
4732292SN/Abool
4746221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid)
4752292SN/A{
4762292SN/A    if (numFreeEntries(tid) == 0) {
4772292SN/A        return(true);
4782292SN/A    } else {
4792292SN/A        return(false);
4802292SN/A    }
4812292SN/A}
4822292SN/A
4832292SN/Atemplate <class Impl>
4842292SN/Abool
4852292SN/AInstructionQueue<Impl>::hasReadyInsts()
4862292SN/A{
4872292SN/A    if (!listOrder.empty()) {
4882292SN/A        return true;
4892292SN/A    }
4902292SN/A
4912292SN/A    for (int i = 0; i < Num_OpClasses; ++i) {
4922292SN/A        if (!readyInsts[i].empty()) {
4932292SN/A            return true;
4942292SN/A        }
4952292SN/A    }
4962292SN/A
4972292SN/A    return false;
4982292SN/A}
4992292SN/A
5002292SN/Atemplate <class Impl>
5011060SN/Avoid
5021061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst)
5031060SN/A{
5041060SN/A    // Make sure the instruction is valid
5051060SN/A    assert(new_inst);
5061060SN/A
5072326SN/A    DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n",
5082326SN/A            new_inst->seqNum, new_inst->readPC());
5091060SN/A
5101060SN/A    assert(freeEntries != 0);
5111060SN/A
5122292SN/A    instList[new_inst->threadNumber].push_back(new_inst);
5131060SN/A
5142064SN/A    --freeEntries;
5151060SN/A
5162292SN/A    new_inst->setInIQ();
5171060SN/A
5181060SN/A    // Look through its source registers (physical regs), and mark any
5191060SN/A    // dependencies.
5201060SN/A    addToDependents(new_inst);
5211060SN/A
5221060SN/A    // Have this instruction set itself as the producer of its destination
5231060SN/A    // register(s).
5242326SN/A    addToProducers(new_inst);
5251060SN/A
5261061SN/A    if (new_inst->isMemRef()) {
5272292SN/A        memDepUnit[new_inst->threadNumber].insert(new_inst);
5281062SN/A    } else {
5291062SN/A        addIfReady(new_inst);
5301061SN/A    }
5311061SN/A
5321062SN/A    ++iqInstsAdded;
5331060SN/A
5342292SN/A    count[new_inst->threadNumber]++;
5352292SN/A
5361060SN/A    assert(freeEntries == (numEntries - countInsts()));
5371060SN/A}
5381060SN/A
5391061SN/Atemplate <class Impl>
5401061SN/Avoid
5412292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
5421061SN/A{
5431061SN/A    // @todo: Clean up this code; can do it by setting inst as unable
5441061SN/A    // to issue, then calling normal insert on the inst.
5451061SN/A
5462292SN/A    assert(new_inst);
5471061SN/A
5482292SN/A    nonSpecInsts[new_inst->seqNum] = new_inst;
5491061SN/A
5502326SN/A    DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x "
5512326SN/A            "to the IQ.\n",
5522326SN/A            new_inst->seqNum, new_inst->readPC());
5532064SN/A
5541061SN/A    assert(freeEntries != 0);
5551061SN/A
5562292SN/A    instList[new_inst->threadNumber].push_back(new_inst);
5571061SN/A
5582064SN/A    --freeEntries;
5591061SN/A
5602292SN/A    new_inst->setInIQ();
5611061SN/A
5621061SN/A    // Have this instruction set itself as the producer of its destination
5631061SN/A    // register(s).
5642326SN/A    addToProducers(new_inst);
5651061SN/A
5661061SN/A    // If it's a memory instruction, add it to the memory dependency
5671061SN/A    // unit.
5682292SN/A    if (new_inst->isMemRef()) {
5692292SN/A        memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
5701061SN/A    }
5711062SN/A
5721062SN/A    ++iqNonSpecInstsAdded;
5732292SN/A
5742292SN/A    count[new_inst->threadNumber]++;
5752292SN/A
5762292SN/A    assert(freeEntries == (numEntries - countInsts()));
5771061SN/A}
5781061SN/A
5791061SN/Atemplate <class Impl>
5801060SN/Avoid
5812292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst)
5821060SN/A{
5832292SN/A    memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst);
5841060SN/A
5852292SN/A    insertNonSpec(barr_inst);
5862292SN/A}
5871060SN/A
5882064SN/Atemplate <class Impl>
5892333SN/Atypename Impl::DynInstPtr
5902333SN/AInstructionQueue<Impl>::getInstToExecute()
5912333SN/A{
5922333SN/A    assert(!instsToExecute.empty());
5932333SN/A    DynInstPtr inst = instsToExecute.front();
5942333SN/A    instsToExecute.pop_front();
5952333SN/A    return inst;
5962333SN/A}
5971060SN/A
5982333SN/Atemplate <class Impl>
5992064SN/Avoid
6002292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class)
6012292SN/A{
6022292SN/A    assert(!readyInsts[op_class].empty());
6032292SN/A
6042292SN/A    ListOrderEntry queue_entry;
6052292SN/A
6062292SN/A    queue_entry.queueType = op_class;
6072292SN/A
6082292SN/A    queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
6092292SN/A
6102292SN/A    ListOrderIt list_it = listOrder.begin();
6112292SN/A    ListOrderIt list_end_it = listOrder.end();
6122292SN/A
6132292SN/A    while (list_it != list_end_it) {
6142292SN/A        if ((*list_it).oldestInst > queue_entry.oldestInst) {
6152292SN/A            break;
6162292SN/A        }
6172292SN/A
6182292SN/A        list_it++;
6191060SN/A    }
6201060SN/A
6212292SN/A    readyIt[op_class] = listOrder.insert(list_it, queue_entry);
6222292SN/A    queueOnList[op_class] = true;
6232292SN/A}
6241060SN/A
6252292SN/Atemplate <class Impl>
6262292SN/Avoid
6272292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
6282292SN/A{
6292292SN/A    // Get iterator of next item on the list
6302292SN/A    // Delete the original iterator
6312292SN/A    // Determine if the next item is either the end of the list or younger
6322292SN/A    // than the new instruction.  If so, then add in a new iterator right here.
6332292SN/A    // If not, then move along.
6342292SN/A    ListOrderEntry queue_entry;
6352292SN/A    OpClass op_class = (*list_order_it).queueType;
6362292SN/A    ListOrderIt next_it = list_order_it;
6372292SN/A
6382292SN/A    ++next_it;
6392292SN/A
6402292SN/A    queue_entry.queueType = op_class;
6412292SN/A    queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
6422292SN/A
6432292SN/A    while (next_it != listOrder.end() &&
6442292SN/A           (*next_it).oldestInst < queue_entry.oldestInst) {
6452292SN/A        ++next_it;
6461060SN/A    }
6471060SN/A
6482292SN/A    readyIt[op_class] = listOrder.insert(next_it, queue_entry);
6491060SN/A}
6501060SN/A
6512292SN/Atemplate <class Impl>
6522292SN/Avoid
6532292SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
6542292SN/A{
6552367SN/A    DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum);
6562292SN/A    // The CPU could have been sleeping until this op completed (*extremely*
6572292SN/A    // long latency op).  Wake it if it was.  This may be overkill.
6582307SN/A    if (isSwitchedOut()) {
6592367SN/A        DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n",
6602367SN/A                inst->seqNum);
6612307SN/A        return;
6622307SN/A    }
6632307SN/A
6642292SN/A    iewStage->wakeCPU();
6652292SN/A
6662326SN/A    if (fu_idx > -1)
6672326SN/A        fuPool->freeUnitNextCycle(fu_idx);
6682292SN/A
6692326SN/A    // @todo: Ensure that these FU Completions happen at the beginning
6702326SN/A    // of a cycle, otherwise they could add too many instructions to
6712326SN/A    // the queue.
6725327Smengke97@hotmail.com    issueToExecuteQueue->access(-1)->size++;
6732333SN/A    instsToExecute.push_back(inst);
6742292SN/A}
6752292SN/A
6761061SN/A// @todo: Figure out a better way to remove the squashed items from the
6771061SN/A// lists.  Checking the top item of each list to see if it's squashed
6781061SN/A// wastes time and forces jumps.
6791061SN/Atemplate <class Impl>
6801060SN/Avoid
6811060SN/AInstructionQueue<Impl>::scheduleReadyInsts()
6821060SN/A{
6832292SN/A    DPRINTF(IQ, "Attempting to schedule ready instructions from "
6842292SN/A            "the IQ.\n");
6851060SN/A
6861060SN/A    IssueStruct *i2e_info = issueToExecuteQueue->access(0);
6871060SN/A
6882292SN/A    // Have iterator to head of the list
6892292SN/A    // While I haven't exceeded bandwidth or reached the end of the list,
6902292SN/A    // Try to get a FU that can do what this op needs.
6912292SN/A    // If successful, change the oldestInst to the new top of the list, put
6922292SN/A    // the queue in the proper place in the list.
6932292SN/A    // Increment the iterator.
6942292SN/A    // This will avoid trying to schedule a certain op class if there are no
6952292SN/A    // FUs that handle it.
6962292SN/A    ListOrderIt order_it = listOrder.begin();
6972292SN/A    ListOrderIt order_end_it = listOrder.end();
6982292SN/A    int total_issued = 0;
6991060SN/A
7002333SN/A    while (total_issued < totalWidth &&
7012820Sktlim@umich.edu           iewStage->canIssue() &&
7022326SN/A           order_it != order_end_it) {
7032292SN/A        OpClass op_class = (*order_it).queueType;
7041060SN/A
7052292SN/A        assert(!readyInsts[op_class].empty());
7061060SN/A
7072292SN/A        DynInstPtr issuing_inst = readyInsts[op_class].top();
7081060SN/A
7092292SN/A        assert(issuing_inst->seqNum == (*order_it).oldestInst);
7101060SN/A
7112292SN/A        if (issuing_inst->isSquashed()) {
7122292SN/A            readyInsts[op_class].pop();
7131060SN/A
7142292SN/A            if (!readyInsts[op_class].empty()) {
7152292SN/A                moveToYoungerInst(order_it);
7162292SN/A            } else {
7172292SN/A                readyIt[op_class] = listOrder.end();
7182292SN/A                queueOnList[op_class] = false;
7191060SN/A            }
7201060SN/A
7212292SN/A            listOrder.erase(order_it++);
7221060SN/A
7232292SN/A            ++iqSquashedInstsIssued;
7242292SN/A
7252292SN/A            continue;
7261060SN/A        }
7271060SN/A
7282326SN/A        int idx = -2;
7292326SN/A        int op_latency = 1;
7306221Snate@binkert.org        ThreadID tid = issuing_inst->threadNumber;
7311060SN/A
7322326SN/A        if (op_class != No_OpClass) {
7332326SN/A            idx = fuPool->getUnit(op_class);
7341060SN/A
7352326SN/A            if (idx > -1) {
7362326SN/A                op_latency = fuPool->getOpLatency(op_class);
7371060SN/A            }
7381060SN/A        }
7391060SN/A
7402348SN/A        // If we have an instruction that doesn't require a FU, or a
7412348SN/A        // valid FU, then schedule for execution.
7422326SN/A        if (idx == -2 || idx != -1) {
7432292SN/A            if (op_latency == 1) {
7442292SN/A                i2e_info->size++;
7452333SN/A                instsToExecute.push_back(issuing_inst);
7461060SN/A
7472326SN/A                // Add the FU onto the list of FU's to be freed next
7482326SN/A                // cycle if we used one.
7492326SN/A                if (idx >= 0)
7502326SN/A                    fuPool->freeUnitNextCycle(idx);
7512292SN/A            } else {
7522292SN/A                int issue_latency = fuPool->getIssueLatency(op_class);
7532326SN/A                // Generate completion event for the FU
7542326SN/A                FUCompletion *execution = new FUCompletion(issuing_inst,
7552326SN/A                                                           idx, this);
7561060SN/A
7575606Snate@binkert.org                cpu->schedule(execution, curTick + cpu->ticks(op_latency - 1));
7581060SN/A
7592326SN/A                // @todo: Enforce that issue_latency == 1 or op_latency
7602292SN/A                if (issue_latency > 1) {
7612348SN/A                    // If FU isn't pipelined, then it must be freed
7622348SN/A                    // upon the execution completing.
7632326SN/A                    execution->setFreeFU();
7642292SN/A                } else {
7652292SN/A                    // Add the FU onto the list of FU's to be freed next cycle.
7662326SN/A                    fuPool->freeUnitNextCycle(idx);
7672292SN/A                }
7681060SN/A            }
7691060SN/A
7702292SN/A            DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
7712292SN/A                    "[sn:%lli]\n",
7722301SN/A                    tid, issuing_inst->readPC(),
7732292SN/A                    issuing_inst->seqNum);
7741060SN/A
7752292SN/A            readyInsts[op_class].pop();
7761061SN/A
7772292SN/A            if (!readyInsts[op_class].empty()) {
7782292SN/A                moveToYoungerInst(order_it);
7792292SN/A            } else {
7802292SN/A                readyIt[op_class] = listOrder.end();
7812292SN/A                queueOnList[op_class] = false;
7821060SN/A            }
7831060SN/A
7842064SN/A            issuing_inst->setIssued();
7852292SN/A            ++total_issued;
7862064SN/A
7872292SN/A            if (!issuing_inst->isMemRef()) {
7882292SN/A                // Memory instructions can not be freed from the IQ until they
7892292SN/A                // complete.
7902292SN/A                ++freeEntries;
7912301SN/A                count[tid]--;
7922731Sktlim@umich.edu                issuing_inst->clearInIQ();
7932292SN/A            } else {
7942301SN/A                memDepUnit[tid].issue(issuing_inst);
7952292SN/A            }
7962292SN/A
7972292SN/A            listOrder.erase(order_it++);
7982326SN/A            statIssuedInstType[tid][op_class]++;
7992820Sktlim@umich.edu            iewStage->incrWb(issuing_inst->seqNum);
8002292SN/A        } else {
8012326SN/A            statFuBusy[op_class]++;
8022326SN/A            fuBusy[tid]++;
8032292SN/A            ++order_it;
8041060SN/A        }
8051060SN/A    }
8061062SN/A
8072326SN/A    numIssuedDist.sample(total_issued);
8082326SN/A    iqInstsIssued+= total_issued;
8092307SN/A
8102348SN/A    // If we issued any instructions, tell the CPU we had activity.
8112292SN/A    if (total_issued) {
8122292SN/A        cpu->activityThisCycle();
8132292SN/A    } else {
8142292SN/A        DPRINTF(IQ, "Not able to schedule any instructions.\n");
8152292SN/A    }
8161060SN/A}
8171060SN/A
8181061SN/Atemplate <class Impl>
8191060SN/Avoid
8201061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
8211060SN/A{
8222292SN/A    DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready "
8232292SN/A            "to execute.\n", inst);
8241062SN/A
8252292SN/A    NonSpecMapIt inst_it = nonSpecInsts.find(inst);
8261060SN/A
8271061SN/A    assert(inst_it != nonSpecInsts.end());
8281060SN/A
8296221Snate@binkert.org    ThreadID tid = (*inst_it).second->threadNumber;
8302292SN/A
8314033Sktlim@umich.edu    (*inst_it).second->setAtCommit();
8324033Sktlim@umich.edu
8331061SN/A    (*inst_it).second->setCanIssue();
8341060SN/A
8351062SN/A    if (!(*inst_it).second->isMemRef()) {
8361062SN/A        addIfReady((*inst_it).second);
8371062SN/A    } else {
8382292SN/A        memDepUnit[tid].nonSpecInstReady((*inst_it).second);
8391062SN/A    }
8401060SN/A
8412292SN/A    (*inst_it).second = NULL;
8422292SN/A
8431061SN/A    nonSpecInsts.erase(inst_it);
8441060SN/A}
8451060SN/A
8461061SN/Atemplate <class Impl>
8471061SN/Avoid
8486221Snate@binkert.orgInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid)
8492292SN/A{
8502292SN/A    DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
8512292SN/A            tid,inst);
8522292SN/A
8532292SN/A    ListIt iq_it = instList[tid].begin();
8542292SN/A
8552292SN/A    while (iq_it != instList[tid].end() &&
8562292SN/A           (*iq_it)->seqNum <= inst) {
8572292SN/A        ++iq_it;
8582292SN/A        instList[tid].pop_front();
8592292SN/A    }
8602292SN/A
8612292SN/A    assert(freeEntries == (numEntries - countInsts()));
8622292SN/A}
8632292SN/A
8642292SN/Atemplate <class Impl>
8652301SN/Aint
8661684SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
8671684SN/A{
8682301SN/A    int dependents = 0;
8692301SN/A
8702292SN/A    DPRINTF(IQ, "Waking dependents of completed instruction.\n");
8712292SN/A
8722292SN/A    assert(!completed_inst->isSquashed());
8731684SN/A
8741684SN/A    // Tell the memory dependence unit to wake any dependents on this
8752292SN/A    // instruction if it is a memory instruction.  Also complete the memory
8762326SN/A    // instruction at this point since we know it executed without issues.
8772326SN/A    // @todo: Might want to rename "completeMemInst" to something that
8782326SN/A    // indicates that it won't need to be replayed, and call this
8792326SN/A    // earlier.  Might not be a big deal.
8801684SN/A    if (completed_inst->isMemRef()) {
8812292SN/A        memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
8822292SN/A        completeMemInst(completed_inst);
8832292SN/A    } else if (completed_inst->isMemBarrier() ||
8842292SN/A               completed_inst->isWriteBarrier()) {
8852292SN/A        memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst);
8861684SN/A    }
8871684SN/A
8881684SN/A    for (int dest_reg_idx = 0;
8891684SN/A         dest_reg_idx < completed_inst->numDestRegs();
8901684SN/A         dest_reg_idx++)
8911684SN/A    {
8921684SN/A        PhysRegIndex dest_reg =
8931684SN/A            completed_inst->renamedDestRegIdx(dest_reg_idx);
8941684SN/A
8951684SN/A        // Special case of uniq or control registers.  They are not
8961684SN/A        // handled by the IQ and thus have no dependency graph entry.
8971684SN/A        // @todo Figure out a cleaner way to handle this.
8981684SN/A        if (dest_reg >= numPhysRegs) {
8997599Sminkyu.jeong@arm.com            DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg,
9007599Sminkyu.jeong@arm.com                    numPhysRegs);
9011684SN/A            continue;
9021684SN/A        }
9031684SN/A
9042292SN/A        DPRINTF(IQ, "Waking any dependents on register %i.\n",
9051684SN/A                (int) dest_reg);
9061684SN/A
9072326SN/A        //Go through the dependency chain, marking the registers as
9082326SN/A        //ready within the waiting instructions.
9092326SN/A        DynInstPtr dep_inst = dependGraph.pop(dest_reg);
9101684SN/A
9112326SN/A        while (dep_inst) {
9127599Sminkyu.jeong@arm.com            DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] "
9137599Sminkyu.jeong@arm.com                    "PC%#x.\n", dep_inst->seqNum, dep_inst->readPC());
9141684SN/A
9151684SN/A            // Might want to give more information to the instruction
9162326SN/A            // so that it knows which of its source registers is
9172326SN/A            // ready.  However that would mean that the dependency
9182326SN/A            // graph entries would need to hold the src_reg_idx.
9192326SN/A            dep_inst->markSrcRegReady();
9201684SN/A
9212326SN/A            addIfReady(dep_inst);
9221684SN/A
9232326SN/A            dep_inst = dependGraph.pop(dest_reg);
9241684SN/A
9252301SN/A            ++dependents;
9261684SN/A        }
9271684SN/A
9282326SN/A        // Reset the head node now that all of its dependents have
9292326SN/A        // been woken up.
9302326SN/A        assert(dependGraph.empty(dest_reg));
9312326SN/A        dependGraph.clearInst(dest_reg);
9321684SN/A
9331684SN/A        // Mark the scoreboard as having that register ready.
9341684SN/A        regScoreboard[dest_reg] = true;
9351684SN/A    }
9362301SN/A    return dependents;
9372064SN/A}
9382064SN/A
9392064SN/Atemplate <class Impl>
9402064SN/Avoid
9412292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
9422064SN/A{
9432292SN/A    OpClass op_class = ready_inst->opClass();
9442292SN/A
9452292SN/A    readyInsts[op_class].push(ready_inst);
9462292SN/A
9472326SN/A    // Will need to reorder the list if either a queue is not on the list,
9482326SN/A    // or it has an older instruction than last time.
9492326SN/A    if (!queueOnList[op_class]) {
9502326SN/A        addToOrderList(op_class);
9512326SN/A    } else if (readyInsts[op_class].top()->seqNum  <
9522326SN/A               (*readyIt[op_class]).oldestInst) {
9532326SN/A        listOrder.erase(readyIt[op_class]);
9542326SN/A        addToOrderList(op_class);
9552326SN/A    }
9562326SN/A
9572292SN/A    DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
9582292SN/A            "the ready list, PC %#x opclass:%i [sn:%lli].\n",
9592292SN/A            ready_inst->readPC(), op_class, ready_inst->seqNum);
9602064SN/A}
9612064SN/A
9622064SN/Atemplate <class Impl>
9632064SN/Avoid
9642292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
9652064SN/A{
9664033Sktlim@umich.edu    DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum);
9674033Sktlim@umich.edu    resched_inst->clearCanIssue();
9682292SN/A    memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
9692064SN/A}
9702064SN/A
9712064SN/Atemplate <class Impl>
9722064SN/Avoid
9732292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
9742064SN/A{
9752292SN/A    memDepUnit[replay_inst->threadNumber].replay(replay_inst);
9762292SN/A}
9772292SN/A
9782292SN/Atemplate <class Impl>
9792292SN/Avoid
9802292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
9812292SN/A{
9826221Snate@binkert.org    ThreadID tid = completed_inst->threadNumber;
9832292SN/A
9842292SN/A    DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
9852292SN/A            completed_inst->readPC(), completed_inst->seqNum);
9862292SN/A
9872292SN/A    ++freeEntries;
9882292SN/A
9892292SN/A    completed_inst->memOpDone = true;
9902292SN/A
9912292SN/A    memDepUnit[tid].completed(completed_inst);
9922292SN/A    count[tid]--;
9931684SN/A}
9941684SN/A
9951684SN/Atemplate <class Impl>
9961684SN/Avoid
9971061SN/AInstructionQueue<Impl>::violation(DynInstPtr &store,
9981061SN/A                                  DynInstPtr &faulting_load)
9991061SN/A{
10002292SN/A    memDepUnit[store->threadNumber].violation(store, faulting_load);
10011061SN/A}
10021061SN/A
10031061SN/Atemplate <class Impl>
10041060SN/Avoid
10056221Snate@binkert.orgInstructionQueue<Impl>::squash(ThreadID tid)
10061060SN/A{
10072292SN/A    DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
10082292SN/A            "the IQ.\n", tid);
10091060SN/A
10101060SN/A    // Read instruction sequence number of last instruction out of the
10111060SN/A    // time buffer.
10122292SN/A    squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
10131060SN/A
10141681SN/A    // Call doSquash if there are insts in the IQ
10152292SN/A    if (count[tid] > 0) {
10162292SN/A        doSquash(tid);
10171681SN/A    }
10181061SN/A
10191061SN/A    // Also tell the memory dependence unit to squash.
10202292SN/A    memDepUnit[tid].squash(squashedSeqNum[tid], tid);
10211060SN/A}
10221060SN/A
10231061SN/Atemplate <class Impl>
10241061SN/Avoid
10256221Snate@binkert.orgInstructionQueue<Impl>::doSquash(ThreadID tid)
10261061SN/A{
10272326SN/A    // Start at the tail.
10282326SN/A    ListIt squash_it = instList[tid].end();
10292326SN/A    --squash_it;
10301061SN/A
10312292SN/A    DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
10322292SN/A            tid, squashedSeqNum[tid]);
10331061SN/A
10341061SN/A    // Squash any instructions younger than the squashed sequence number
10351061SN/A    // given.
10362326SN/A    while (squash_it != instList[tid].end() &&
10372326SN/A           (*squash_it)->seqNum > squashedSeqNum[tid]) {
10382292SN/A
10392326SN/A        DynInstPtr squashed_inst = (*squash_it);
10401061SN/A
10411061SN/A        // Only handle the instruction if it actually is in the IQ and
10421061SN/A        // hasn't already been squashed in the IQ.
10432292SN/A        if (squashed_inst->threadNumber != tid ||
10442292SN/A            squashed_inst->isSquashedInIQ()) {
10452326SN/A            --squash_it;
10462292SN/A            continue;
10472292SN/A        }
10482292SN/A
10492292SN/A        if (!squashed_inst->isIssued() ||
10502292SN/A            (squashed_inst->isMemRef() &&
10512292SN/A             !squashed_inst->memOpDone)) {
10521062SN/A
10532367SN/A            DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x "
10542367SN/A                    "squashed.\n",
10552367SN/A                    tid, squashed_inst->seqNum, squashed_inst->readPC());
10562367SN/A
10571061SN/A            // Remove the instruction from the dependency list.
10582292SN/A            if (!squashed_inst->isNonSpeculative() &&
10592336SN/A                !squashed_inst->isStoreConditional() &&
10602292SN/A                !squashed_inst->isMemBarrier() &&
10612292SN/A                !squashed_inst->isWriteBarrier()) {
10621061SN/A
10631061SN/A                for (int src_reg_idx = 0;
10641681SN/A                     src_reg_idx < squashed_inst->numSrcRegs();
10651061SN/A                     src_reg_idx++)
10661061SN/A                {
10671061SN/A                    PhysRegIndex src_reg =
10681061SN/A                        squashed_inst->renamedSrcRegIdx(src_reg_idx);
10691061SN/A
10702326SN/A                    // Only remove it from the dependency graph if it
10712326SN/A                    // was placed there in the first place.
10722326SN/A
10732326SN/A                    // Instead of doing a linked list traversal, we
10742326SN/A                    // can just remove these squashed instructions
10752326SN/A                    // either at issue time, or when the register is
10762326SN/A                    // overwritten.  The only downside to this is it
10772326SN/A                    // leaves more room for error.
10782292SN/A
10791061SN/A                    if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
10801061SN/A                        src_reg < numPhysRegs) {
10812326SN/A                        dependGraph.remove(src_reg, squashed_inst);
10821061SN/A                    }
10831062SN/A
10842292SN/A
10851062SN/A                    ++iqSquashedOperandsExamined;
10861061SN/A                }
10874033Sktlim@umich.edu            } else if (!squashed_inst->isStoreConditional() ||
10884033Sktlim@umich.edu                       !squashed_inst->isCompleted()) {
10892292SN/A                NonSpecMapIt ns_inst_it =
10902292SN/A                    nonSpecInsts.find(squashed_inst->seqNum);
10912292SN/A                assert(ns_inst_it != nonSpecInsts.end());
10924033Sktlim@umich.edu                if (ns_inst_it == nonSpecInsts.end()) {
10934033Sktlim@umich.edu                    assert(squashed_inst->getFault() != NoFault);
10944033Sktlim@umich.edu                } else {
10951062SN/A
10964033Sktlim@umich.edu                    (*ns_inst_it).second = NULL;
10971681SN/A
10984033Sktlim@umich.edu                    nonSpecInsts.erase(ns_inst_it);
10991062SN/A
11004033Sktlim@umich.edu                    ++iqSquashedNonSpecRemoved;
11014033Sktlim@umich.edu                }
11021061SN/A            }
11031061SN/A
11041061SN/A            // Might want to also clear out the head of the dependency graph.
11051061SN/A
11061061SN/A            // Mark it as squashed within the IQ.
11071061SN/A            squashed_inst->setSquashedInIQ();
11081061SN/A
11092292SN/A            // @todo: Remove this hack where several statuses are set so the
11102292SN/A            // inst will flow through the rest of the pipeline.
11111681SN/A            squashed_inst->setIssued();
11121681SN/A            squashed_inst->setCanCommit();
11132731Sktlim@umich.edu            squashed_inst->clearInIQ();
11142292SN/A
11152292SN/A            //Update Thread IQ Count
11162292SN/A            count[squashed_inst->threadNumber]--;
11171681SN/A
11181681SN/A            ++freeEntries;
11191061SN/A        }
11201061SN/A
11212326SN/A        instList[tid].erase(squash_it--);
11221062SN/A        ++iqSquashedInstsExamined;
11231061SN/A    }
11241060SN/A}
11251060SN/A
11261061SN/Atemplate <class Impl>
11271060SN/Abool
11281061SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst)
11291060SN/A{
11301060SN/A    // Loop through the instruction's source registers, adding
11311060SN/A    // them to the dependency list if they are not ready.
11321060SN/A    int8_t total_src_regs = new_inst->numSrcRegs();
11331060SN/A    bool return_val = false;
11341060SN/A
11351060SN/A    for (int src_reg_idx = 0;
11361060SN/A         src_reg_idx < total_src_regs;
11371060SN/A         src_reg_idx++)
11381060SN/A    {
11391060SN/A        // Only add it to the dependency graph if it's not ready.
11401060SN/A        if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
11411060SN/A            PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
11421060SN/A
11431060SN/A            // Check the IQ's scoreboard to make sure the register
11441060SN/A            // hasn't become ready while the instruction was in flight
11451060SN/A            // between stages.  Only if it really isn't ready should
11461060SN/A            // it be added to the dependency graph.
11471061SN/A            if (src_reg >= numPhysRegs) {
11481061SN/A                continue;
11491061SN/A            } else if (regScoreboard[src_reg] == false) {
11502292SN/A                DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
11511060SN/A                        "is being added to the dependency chain.\n",
11521060SN/A                        new_inst->readPC(), src_reg);
11531060SN/A
11542326SN/A                dependGraph.insert(src_reg, new_inst);
11551060SN/A
11561060SN/A                // Change the return value to indicate that something
11571060SN/A                // was added to the dependency graph.
11581060SN/A                return_val = true;
11591060SN/A            } else {
11602292SN/A                DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
11611060SN/A                        "became ready before it reached the IQ.\n",
11621060SN/A                        new_inst->readPC(), src_reg);
11631060SN/A                // Mark a register ready within the instruction.
11642326SN/A                new_inst->markSrcRegReady(src_reg_idx);
11651060SN/A            }
11661060SN/A        }
11671060SN/A    }
11681060SN/A
11691060SN/A    return return_val;
11701060SN/A}
11711060SN/A
11721061SN/Atemplate <class Impl>
11731060SN/Avoid
11742326SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst)
11751060SN/A{
11762326SN/A    // Nothing really needs to be marked when an instruction becomes
11772326SN/A    // the producer of a register's value, but for convenience a ptr
11782326SN/A    // to the producing instruction will be placed in the head node of
11792326SN/A    // the dependency links.
11801060SN/A    int8_t total_dest_regs = new_inst->numDestRegs();
11811060SN/A
11821060SN/A    for (int dest_reg_idx = 0;
11831060SN/A         dest_reg_idx < total_dest_regs;
11841060SN/A         dest_reg_idx++)
11851060SN/A    {
11861061SN/A        PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
11871061SN/A
11881061SN/A        // Instructions that use the misc regs will have a reg number
11891061SN/A        // higher than the normal physical registers.  In this case these
11901061SN/A        // registers are not renamed, and there is no need to track
11911061SN/A        // dependencies as these instructions must be executed at commit.
11921061SN/A        if (dest_reg >= numPhysRegs) {
11931061SN/A            continue;
11941060SN/A        }
11951060SN/A
11962326SN/A        if (!dependGraph.empty(dest_reg)) {
11972326SN/A            dependGraph.dump();
11982292SN/A            panic("Dependency graph %i not empty!", dest_reg);
11992064SN/A        }
12001062SN/A
12012326SN/A        dependGraph.setInst(dest_reg, new_inst);
12021062SN/A
12031060SN/A        // Mark the scoreboard to say it's not yet ready.
12041060SN/A        regScoreboard[dest_reg] = false;
12051060SN/A    }
12061060SN/A}
12071060SN/A
12081061SN/Atemplate <class Impl>
12091060SN/Avoid
12101061SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst)
12111060SN/A{
12122326SN/A    // If the instruction now has all of its source registers
12131060SN/A    // available, then add it to the list of ready instructions.
12141060SN/A    if (inst->readyToIssue()) {
12151061SN/A
12161060SN/A        //Add the instruction to the proper ready list.
12172292SN/A        if (inst->isMemRef()) {
12181061SN/A
12192292SN/A            DPRINTF(IQ, "Checking if memory instruction can issue.\n");
12201061SN/A
12211062SN/A            // Message to the mem dependence unit that this instruction has
12221062SN/A            // its registers ready.
12232292SN/A            memDepUnit[inst->threadNumber].regsReady(inst);
12241062SN/A
12252292SN/A            return;
12262292SN/A        }
12271062SN/A
12282292SN/A        OpClass op_class = inst->opClass();
12291061SN/A
12302292SN/A        DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
12312292SN/A                "the ready list, PC %#x opclass:%i [sn:%lli].\n",
12322292SN/A                inst->readPC(), op_class, inst->seqNum);
12331061SN/A
12342292SN/A        readyInsts[op_class].push(inst);
12351061SN/A
12362326SN/A        // Will need to reorder the list if either a queue is not on the list,
12372326SN/A        // or it has an older instruction than last time.
12382326SN/A        if (!queueOnList[op_class]) {
12392326SN/A            addToOrderList(op_class);
12402326SN/A        } else if (readyInsts[op_class].top()->seqNum  <
12412326SN/A                   (*readyIt[op_class]).oldestInst) {
12422326SN/A            listOrder.erase(readyIt[op_class]);
12432326SN/A            addToOrderList(op_class);
12441060SN/A        }
12451060SN/A    }
12461060SN/A}
12471060SN/A
12481061SN/Atemplate <class Impl>
12491061SN/Aint
12501061SN/AInstructionQueue<Impl>::countInsts()
12511061SN/A{
12522698Sktlim@umich.edu#if 0
12532292SN/A    //ksewell:This works but definitely could use a cleaner write
12542292SN/A    //with a more intuitive way of counting. Right now it's
12552292SN/A    //just brute force ....
12562698Sktlim@umich.edu    // Change the #if if you want to use this method.
12571061SN/A    int total_insts = 0;
12581061SN/A
12596221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; ++tid) {
12606221Snate@binkert.org        ListIt count_it = instList[tid].begin();
12611681SN/A
12626221Snate@binkert.org        while (count_it != instList[tid].end()) {
12632292SN/A            if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
12642292SN/A                if (!(*count_it)->isIssued()) {
12652292SN/A                    ++total_insts;
12662292SN/A                } else if ((*count_it)->isMemRef() &&
12672292SN/A                           !(*count_it)->memOpDone) {
12682292SN/A                    // Loads that have not been marked as executed still count
12692292SN/A                    // towards the total instructions.
12702292SN/A                    ++total_insts;
12712292SN/A                }
12722292SN/A            }
12732292SN/A
12742292SN/A            ++count_it;
12751061SN/A        }
12761061SN/A    }
12771061SN/A
12781061SN/A    return total_insts;
12792292SN/A#else
12802292SN/A    return numEntries - freeEntries;
12812292SN/A#endif
12821681SN/A}
12831681SN/A
12841681SN/Atemplate <class Impl>
12851681SN/Avoid
12861061SN/AInstructionQueue<Impl>::dumpLists()
12871061SN/A{
12882292SN/A    for (int i = 0; i < Num_OpClasses; ++i) {
12892292SN/A        cprintf("Ready list %i size: %i\n", i, readyInsts[i].size());
12901061SN/A
12912292SN/A        cprintf("\n");
12922292SN/A    }
12931061SN/A
12941061SN/A    cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
12951061SN/A
12962292SN/A    NonSpecMapIt non_spec_it = nonSpecInsts.begin();
12972292SN/A    NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
12981061SN/A
12991061SN/A    cprintf("Non speculative list: ");
13001061SN/A
13012292SN/A    while (non_spec_it != non_spec_end_it) {
13022292SN/A        cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
13032292SN/A                (*non_spec_it).second->seqNum);
13041061SN/A        ++non_spec_it;
13051061SN/A    }
13061061SN/A
13071061SN/A    cprintf("\n");
13081061SN/A
13092292SN/A    ListOrderIt list_order_it = listOrder.begin();
13102292SN/A    ListOrderIt list_order_end_it = listOrder.end();
13112292SN/A    int i = 1;
13122292SN/A
13132292SN/A    cprintf("List order: ");
13142292SN/A
13152292SN/A    while (list_order_it != list_order_end_it) {
13162292SN/A        cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
13172292SN/A                (*list_order_it).oldestInst);
13182292SN/A
13192292SN/A        ++list_order_it;
13202292SN/A        ++i;
13212292SN/A    }
13222292SN/A
13232292SN/A    cprintf("\n");
13241061SN/A}
13252292SN/A
13262292SN/A
13272292SN/Atemplate <class Impl>
13282292SN/Avoid
13292292SN/AInstructionQueue<Impl>::dumpInsts()
13302292SN/A{
13316221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; ++tid) {
13322292SN/A        int num = 0;
13332292SN/A        int valid_num = 0;
13346221Snate@binkert.org        ListIt inst_list_it = instList[tid].begin();
13352292SN/A
13366221Snate@binkert.org        while (inst_list_it != instList[tid].end()) {
13376221Snate@binkert.org            cprintf("Instruction:%i\n", num);
13382292SN/A            if (!(*inst_list_it)->isSquashed()) {
13392292SN/A                if (!(*inst_list_it)->isIssued()) {
13402292SN/A                    ++valid_num;
13412292SN/A                    cprintf("Count:%i\n", valid_num);
13422292SN/A                } else if ((*inst_list_it)->isMemRef() &&
13432292SN/A                           !(*inst_list_it)->memOpDone) {
13442326SN/A                    // Loads that have not been marked as executed
13452326SN/A                    // still count towards the total instructions.
13462292SN/A                    ++valid_num;
13472292SN/A                    cprintf("Count:%i\n", valid_num);
13482292SN/A                }
13492292SN/A            }
13502292SN/A
13512292SN/A            cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
13522292SN/A                    "Issued:%i\nSquashed:%i\n",
13532292SN/A                    (*inst_list_it)->readPC(),
13542292SN/A                    (*inst_list_it)->seqNum,
13552292SN/A                    (*inst_list_it)->threadNumber,
13562292SN/A                    (*inst_list_it)->isIssued(),
13572292SN/A                    (*inst_list_it)->isSquashed());
13582292SN/A
13592292SN/A            if ((*inst_list_it)->isMemRef()) {
13602292SN/A                cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
13612292SN/A            }
13622292SN/A
13632292SN/A            cprintf("\n");
13642292SN/A
13652292SN/A            inst_list_it++;
13662292SN/A            ++num;
13672292SN/A        }
13682292SN/A    }
13692348SN/A
13702348SN/A    cprintf("Insts to Execute list:\n");
13712348SN/A
13722348SN/A    int num = 0;
13732348SN/A    int valid_num = 0;
13742348SN/A    ListIt inst_list_it = instsToExecute.begin();
13752348SN/A
13762348SN/A    while (inst_list_it != instsToExecute.end())
13772348SN/A    {
13782348SN/A        cprintf("Instruction:%i\n",
13792348SN/A                num);
13802348SN/A        if (!(*inst_list_it)->isSquashed()) {
13812348SN/A            if (!(*inst_list_it)->isIssued()) {
13822348SN/A                ++valid_num;
13832348SN/A                cprintf("Count:%i\n", valid_num);
13842348SN/A            } else if ((*inst_list_it)->isMemRef() &&
13852348SN/A                       !(*inst_list_it)->memOpDone) {
13862348SN/A                // Loads that have not been marked as executed
13872348SN/A                // still count towards the total instructions.
13882348SN/A                ++valid_num;
13892348SN/A                cprintf("Count:%i\n", valid_num);
13902348SN/A            }
13912348SN/A        }
13922348SN/A
13932348SN/A        cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
13942348SN/A                "Issued:%i\nSquashed:%i\n",
13952348SN/A                (*inst_list_it)->readPC(),
13962348SN/A                (*inst_list_it)->seqNum,
13972348SN/A                (*inst_list_it)->threadNumber,
13982348SN/A                (*inst_list_it)->isIssued(),
13992348SN/A                (*inst_list_it)->isSquashed());
14002348SN/A
14012348SN/A        if ((*inst_list_it)->isMemRef()) {
14022348SN/A            cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
14032348SN/A        }
14042348SN/A
14052348SN/A        cprintf("\n");
14062348SN/A
14072348SN/A        inst_list_it++;
14082348SN/A        ++num;
14092348SN/A    }
14102292SN/A}
1411