inst_queue_impl.hh revision 5606
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292831Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322064SN/A#include <limits> 331060SN/A#include <vector> 341060SN/A 352292SN/A#include "cpu/o3/fu_pool.hh" 361717SN/A#include "cpu/o3/inst_queue.hh" 374762Snate@binkert.org#include "enums/OpClass.hh" 384762Snate@binkert.org#include "sim/core.hh" 391060SN/A 405529Snate@binkert.org#include "params/DerivO3CPU.hh" 415529Snate@binkert.org 421061SN/Atemplate <class Impl> 432292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 445606Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 455606Snate@binkert.org : Event(Stat_Event_Pri), inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), 465606Snate@binkert.org freeFU(false) 471060SN/A{ 482292SN/A this->setFlags(Event::AutoDelete); 492292SN/A} 502292SN/A 512292SN/Atemplate <class Impl> 522292SN/Avoid 532292SN/AInstructionQueue<Impl>::FUCompletion::process() 542292SN/A{ 552326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 562292SN/A inst = NULL; 572292SN/A} 582292SN/A 592292SN/A 602292SN/Atemplate <class Impl> 612292SN/Aconst char * 625336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const 632292SN/A{ 644873Sstever@eecs.umich.edu return "Functional unit completion"; 652292SN/A} 662292SN/A 672292SN/Atemplate <class Impl> 684329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 695529Snate@binkert.org DerivO3CPUParams *params) 704329Sktlim@umich.edu : cpu(cpu_ptr), 714329Sktlim@umich.edu iewStage(iew_ptr), 724329Sktlim@umich.edu fuPool(params->fuPool), 732292SN/A numEntries(params->numIQEntries), 742292SN/A totalWidth(params->issueWidth), 752292SN/A numPhysIntRegs(params->numPhysIntRegs), 762292SN/A numPhysFloatRegs(params->numPhysFloatRegs), 772292SN/A commitToIEWDelay(params->commitToIEWDelay) 782292SN/A{ 792292SN/A assert(fuPool); 802292SN/A 812307SN/A switchedOut = false; 822307SN/A 835529Snate@binkert.org numThreads = params->numThreads; 841060SN/A 851060SN/A // Set the number of physical registers as the number of int + float 861060SN/A numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 871060SN/A 881060SN/A //Create an entry for each physical register within the 891060SN/A //dependency graph. 902326SN/A dependGraph.resize(numPhysRegs); 911060SN/A 921060SN/A // Resize the register scoreboard. 931060SN/A regScoreboard.resize(numPhysRegs); 941060SN/A 952292SN/A //Initialize Mem Dependence Units 962292SN/A for (int i = 0; i < numThreads; i++) { 972292SN/A memDepUnit[i].init(params,i); 982292SN/A memDepUnit[i].setIQ(this); 991060SN/A } 1001060SN/A 1012307SN/A resetState(); 1022292SN/A 1032980Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1042292SN/A 1052292SN/A //Convert string to lowercase 1062292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1072292SN/A (int(*)(int)) tolower); 1082292SN/A 1092292SN/A //Figure out resource sharing policy 1102292SN/A if (policy == "dynamic") { 1112292SN/A iqPolicy = Dynamic; 1122292SN/A 1132292SN/A //Set Max Entries to Total ROB Capacity 1142292SN/A for (int i = 0; i < numThreads; i++) { 1152292SN/A maxEntries[i] = numEntries; 1162292SN/A } 1172292SN/A 1182292SN/A } else if (policy == "partitioned") { 1192292SN/A iqPolicy = Partitioned; 1202292SN/A 1212292SN/A //@todo:make work if part_amt doesnt divide evenly. 1222292SN/A int part_amt = numEntries / numThreads; 1232292SN/A 1242292SN/A //Divide ROB up evenly 1252292SN/A for (int i = 0; i < numThreads; i++) { 1262292SN/A maxEntries[i] = part_amt; 1272292SN/A } 1282292SN/A 1292831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1302292SN/A "%i entries per thread.\n",part_amt); 1312292SN/A } else if (policy == "threshold") { 1322292SN/A iqPolicy = Threshold; 1332292SN/A 1342292SN/A double threshold = (double)params->smtIQThreshold / 100; 1352292SN/A 1362292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1372292SN/A 1382292SN/A //Divide up by threshold amount 1392292SN/A for (int i = 0; i < numThreads; i++) { 1402292SN/A maxEntries[i] = thresholdIQ; 1412292SN/A } 1422292SN/A 1432831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1442292SN/A "%i entries per thread.\n",thresholdIQ); 1452292SN/A } else { 1462292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1472292SN/A "Partitioned, Threshold}"); 1482292SN/A } 1492292SN/A} 1502292SN/A 1512292SN/Atemplate <class Impl> 1522292SN/AInstructionQueue<Impl>::~InstructionQueue() 1532292SN/A{ 1542326SN/A dependGraph.reset(); 1552348SN/A#ifdef DEBUG 1562326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1572326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1582348SN/A#endif 1592292SN/A} 1602292SN/A 1612292SN/Atemplate <class Impl> 1622292SN/Astd::string 1632292SN/AInstructionQueue<Impl>::name() const 1642292SN/A{ 1652292SN/A return cpu->name() + ".iq"; 1661060SN/A} 1671060SN/A 1681061SN/Atemplate <class Impl> 1691060SN/Avoid 1701062SN/AInstructionQueue<Impl>::regStats() 1711062SN/A{ 1722301SN/A using namespace Stats; 1731062SN/A iqInstsAdded 1741062SN/A .name(name() + ".iqInstsAdded") 1751062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1761062SN/A .prereq(iqInstsAdded); 1771062SN/A 1781062SN/A iqNonSpecInstsAdded 1791062SN/A .name(name() + ".iqNonSpecInstsAdded") 1801062SN/A .desc("Number of non-speculative instructions added to the IQ") 1811062SN/A .prereq(iqNonSpecInstsAdded); 1821062SN/A 1832301SN/A iqInstsIssued 1842301SN/A .name(name() + ".iqInstsIssued") 1852301SN/A .desc("Number of instructions issued") 1862301SN/A .prereq(iqInstsIssued); 1871062SN/A 1881062SN/A iqIntInstsIssued 1891062SN/A .name(name() + ".iqIntInstsIssued") 1901062SN/A .desc("Number of integer instructions issued") 1911062SN/A .prereq(iqIntInstsIssued); 1921062SN/A 1931062SN/A iqFloatInstsIssued 1941062SN/A .name(name() + ".iqFloatInstsIssued") 1951062SN/A .desc("Number of float instructions issued") 1961062SN/A .prereq(iqFloatInstsIssued); 1971062SN/A 1981062SN/A iqBranchInstsIssued 1991062SN/A .name(name() + ".iqBranchInstsIssued") 2001062SN/A .desc("Number of branch instructions issued") 2011062SN/A .prereq(iqBranchInstsIssued); 2021062SN/A 2031062SN/A iqMemInstsIssued 2041062SN/A .name(name() + ".iqMemInstsIssued") 2051062SN/A .desc("Number of memory instructions issued") 2061062SN/A .prereq(iqMemInstsIssued); 2071062SN/A 2081062SN/A iqMiscInstsIssued 2091062SN/A .name(name() + ".iqMiscInstsIssued") 2101062SN/A .desc("Number of miscellaneous instructions issued") 2111062SN/A .prereq(iqMiscInstsIssued); 2121062SN/A 2131062SN/A iqSquashedInstsIssued 2141062SN/A .name(name() + ".iqSquashedInstsIssued") 2151062SN/A .desc("Number of squashed instructions issued") 2161062SN/A .prereq(iqSquashedInstsIssued); 2171062SN/A 2181062SN/A iqSquashedInstsExamined 2191062SN/A .name(name() + ".iqSquashedInstsExamined") 2201062SN/A .desc("Number of squashed instructions iterated over during squash;" 2211062SN/A " mainly for profiling") 2221062SN/A .prereq(iqSquashedInstsExamined); 2231062SN/A 2241062SN/A iqSquashedOperandsExamined 2251062SN/A .name(name() + ".iqSquashedOperandsExamined") 2261062SN/A .desc("Number of squashed operands that are examined and possibly " 2271062SN/A "removed from graph") 2281062SN/A .prereq(iqSquashedOperandsExamined); 2291062SN/A 2301062SN/A iqSquashedNonSpecRemoved 2311062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2321062SN/A .desc("Number of squashed non-spec instructions that were removed") 2331062SN/A .prereq(iqSquashedNonSpecRemoved); 2342361SN/A/* 2352326SN/A queueResDist 2362301SN/A .init(Num_OpClasses, 0, 99, 2) 2372301SN/A .name(name() + ".IQ:residence:") 2382301SN/A .desc("cycles from dispatch to issue") 2392301SN/A .flags(total | pdf | cdf ) 2402301SN/A ; 2412301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2422326SN/A queueResDist.subname(i, opClassStrings[i]); 2432301SN/A } 2442361SN/A*/ 2452326SN/A numIssuedDist 2462307SN/A .init(0,totalWidth,1) 2472301SN/A .name(name() + ".ISSUE:issued_per_cycle") 2482301SN/A .desc("Number of insts issued each cycle") 2492307SN/A .flags(pdf) 2502301SN/A ; 2512301SN/A/* 2522301SN/A dist_unissued 2532301SN/A .init(Num_OpClasses+2) 2542301SN/A .name(name() + ".ISSUE:unissued_cause") 2552301SN/A .desc("Reason ready instruction not issued") 2562301SN/A .flags(pdf | dist) 2572301SN/A ; 2582301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2592301SN/A dist_unissued.subname(i, unissued_names[i]); 2602301SN/A } 2612301SN/A*/ 2622326SN/A statIssuedInstType 2634762Snate@binkert.org .init(numThreads,Enums::Num_OpClass) 2642301SN/A .name(name() + ".ISSUE:FU_type") 2652301SN/A .desc("Type of FU issued") 2662301SN/A .flags(total | pdf | dist) 2672301SN/A ; 2684762Snate@binkert.org statIssuedInstType.ysubnames(Enums::OpClassStrings); 2692301SN/A 2702301SN/A // 2712301SN/A // How long did instructions for a particular FU type wait prior to issue 2722301SN/A // 2732361SN/A/* 2742326SN/A issueDelayDist 2752301SN/A .init(Num_OpClasses,0,99,2) 2762301SN/A .name(name() + ".ISSUE:") 2772301SN/A .desc("cycles from operands ready to issue") 2782301SN/A .flags(pdf | cdf) 2792301SN/A ; 2802301SN/A 2812301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2822980Sgblack@eecs.umich.edu std::stringstream subname; 2832301SN/A subname << opClassStrings[i] << "_delay"; 2842326SN/A issueDelayDist.subname(i, subname.str()); 2852301SN/A } 2862361SN/A*/ 2872326SN/A issueRate 2882301SN/A .name(name() + ".ISSUE:rate") 2892301SN/A .desc("Inst issue rate") 2902301SN/A .flags(total) 2912301SN/A ; 2922326SN/A issueRate = iqInstsIssued / cpu->numCycles; 2932727Sktlim@umich.edu 2942326SN/A statFuBusy 2952301SN/A .init(Num_OpClasses) 2962301SN/A .name(name() + ".ISSUE:fu_full") 2972301SN/A .desc("attempts to use FU when none available") 2982301SN/A .flags(pdf | dist) 2992301SN/A ; 3002301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3014762Snate@binkert.org statFuBusy.subname(i, Enums::OpClassStrings[i]); 3022301SN/A } 3032301SN/A 3042326SN/A fuBusy 3052301SN/A .init(numThreads) 3062301SN/A .name(name() + ".ISSUE:fu_busy_cnt") 3072301SN/A .desc("FU busy when requested") 3082301SN/A .flags(total) 3092301SN/A ; 3102301SN/A 3112326SN/A fuBusyRate 3122301SN/A .name(name() + ".ISSUE:fu_busy_rate") 3132301SN/A .desc("FU busy rate (busy events/executed inst)") 3142301SN/A .flags(total) 3152301SN/A ; 3162326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3172301SN/A 3182292SN/A for ( int i=0; i < numThreads; i++) { 3192292SN/A // Tell mem dependence unit to reg stats as well. 3202292SN/A memDepUnit[i].regStats(); 3212292SN/A } 3221062SN/A} 3231062SN/A 3241062SN/Atemplate <class Impl> 3251062SN/Avoid 3262307SN/AInstructionQueue<Impl>::resetState() 3271060SN/A{ 3282307SN/A //Initialize thread IQ counts 3292307SN/A for (int i = 0; i <numThreads; i++) { 3302307SN/A count[i] = 0; 3312307SN/A instList[i].clear(); 3322307SN/A } 3331060SN/A 3342307SN/A // Initialize the number of free IQ entries. 3352307SN/A freeEntries = numEntries; 3362307SN/A 3372307SN/A // Note that in actuality, the registers corresponding to the logical 3382307SN/A // registers start off as ready. However this doesn't matter for the 3392307SN/A // IQ as the instruction should have been correctly told if those 3402307SN/A // registers are ready in rename. Thus it can all be initialized as 3412307SN/A // unready. 3422307SN/A for (int i = 0; i < numPhysRegs; ++i) { 3432307SN/A regScoreboard[i] = false; 3442307SN/A } 3452307SN/A 3462307SN/A for (int i = 0; i < numThreads; ++i) { 3472307SN/A squashedSeqNum[i] = 0; 3482307SN/A } 3492307SN/A 3502307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 3512307SN/A while (!readyInsts[i].empty()) 3522307SN/A readyInsts[i].pop(); 3532307SN/A queueOnList[i] = false; 3542307SN/A readyIt[i] = listOrder.end(); 3552307SN/A } 3562307SN/A nonSpecInsts.clear(); 3572307SN/A listOrder.clear(); 3581060SN/A} 3591060SN/A 3601061SN/Atemplate <class Impl> 3611060SN/Avoid 3622980Sgblack@eecs.umich.eduInstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 3631060SN/A{ 3642292SN/A activeThreads = at_ptr; 3652064SN/A} 3662064SN/A 3672064SN/Atemplate <class Impl> 3682064SN/Avoid 3692292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 3702064SN/A{ 3714318Sktlim@umich.edu issueToExecuteQueue = i2e_ptr; 3721060SN/A} 3731060SN/A 3741061SN/Atemplate <class Impl> 3751060SN/Avoid 3761060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3771060SN/A{ 3781060SN/A timeBuffer = tb_ptr; 3791060SN/A 3801060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3811060SN/A} 3821060SN/A 3831684SN/Atemplate <class Impl> 3842307SN/Avoid 3852307SN/AInstructionQueue<Impl>::switchOut() 3862307SN/A{ 3872367SN/A/* 3882367SN/A if (!instList[0].empty() || (numEntries != freeEntries) || 3892367SN/A !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) { 3902367SN/A dumpInsts(); 3912367SN/A// assert(0); 3922367SN/A } 3932367SN/A*/ 3942307SN/A resetState(); 3952326SN/A dependGraph.reset(); 3962367SN/A instsToExecute.clear(); 3972307SN/A switchedOut = true; 3982307SN/A for (int i = 0; i < numThreads; ++i) { 3992307SN/A memDepUnit[i].switchOut(); 4002307SN/A } 4012307SN/A} 4022307SN/A 4032307SN/Atemplate <class Impl> 4042307SN/Avoid 4052307SN/AInstructionQueue<Impl>::takeOverFrom() 4062307SN/A{ 4072307SN/A switchedOut = false; 4082307SN/A} 4092307SN/A 4102307SN/Atemplate <class Impl> 4112292SN/Aint 4122292SN/AInstructionQueue<Impl>::entryAmount(int num_threads) 4132292SN/A{ 4142292SN/A if (iqPolicy == Partitioned) { 4152292SN/A return numEntries / num_threads; 4162292SN/A } else { 4172292SN/A return 0; 4182292SN/A } 4192292SN/A} 4202292SN/A 4212292SN/A 4222292SN/Atemplate <class Impl> 4232292SN/Avoid 4242292SN/AInstructionQueue<Impl>::resetEntries() 4252292SN/A{ 4262292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4273867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 4282292SN/A 4293867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 4303867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 4312292SN/A 4323867Sbinkertn@umich.edu while (threads != end) { 4333867Sbinkertn@umich.edu unsigned tid = *threads++; 4343867Sbinkertn@umich.edu 4352292SN/A if (iqPolicy == Partitioned) { 4363867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 4372292SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4383867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 4392292SN/A } 4402292SN/A } 4412292SN/A } 4422292SN/A} 4432292SN/A 4442292SN/Atemplate <class Impl> 4451684SN/Aunsigned 4461684SN/AInstructionQueue<Impl>::numFreeEntries() 4471684SN/A{ 4481684SN/A return freeEntries; 4491684SN/A} 4501684SN/A 4512292SN/Atemplate <class Impl> 4522292SN/Aunsigned 4532292SN/AInstructionQueue<Impl>::numFreeEntries(unsigned tid) 4542292SN/A{ 4552292SN/A return maxEntries[tid] - count[tid]; 4562292SN/A} 4572292SN/A 4581060SN/A// Might want to do something more complex if it knows how many instructions 4591060SN/A// will be issued this cycle. 4601061SN/Atemplate <class Impl> 4611060SN/Abool 4621060SN/AInstructionQueue<Impl>::isFull() 4631060SN/A{ 4641060SN/A if (freeEntries == 0) { 4651060SN/A return(true); 4661060SN/A } else { 4671060SN/A return(false); 4681060SN/A } 4691060SN/A} 4701060SN/A 4711061SN/Atemplate <class Impl> 4722292SN/Abool 4732292SN/AInstructionQueue<Impl>::isFull(unsigned tid) 4742292SN/A{ 4752292SN/A if (numFreeEntries(tid) == 0) { 4762292SN/A return(true); 4772292SN/A } else { 4782292SN/A return(false); 4792292SN/A } 4802292SN/A} 4812292SN/A 4822292SN/Atemplate <class Impl> 4832292SN/Abool 4842292SN/AInstructionQueue<Impl>::hasReadyInsts() 4852292SN/A{ 4862292SN/A if (!listOrder.empty()) { 4872292SN/A return true; 4882292SN/A } 4892292SN/A 4902292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4912292SN/A if (!readyInsts[i].empty()) { 4922292SN/A return true; 4932292SN/A } 4942292SN/A } 4952292SN/A 4962292SN/A return false; 4972292SN/A} 4982292SN/A 4992292SN/Atemplate <class Impl> 5001060SN/Avoid 5011061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5021060SN/A{ 5031060SN/A // Make sure the instruction is valid 5041060SN/A assert(new_inst); 5051060SN/A 5062326SN/A DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n", 5072326SN/A new_inst->seqNum, new_inst->readPC()); 5081060SN/A 5091060SN/A assert(freeEntries != 0); 5101060SN/A 5112292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5121060SN/A 5132064SN/A --freeEntries; 5141060SN/A 5152292SN/A new_inst->setInIQ(); 5161060SN/A 5171060SN/A // Look through its source registers (physical regs), and mark any 5181060SN/A // dependencies. 5191060SN/A addToDependents(new_inst); 5201060SN/A 5211060SN/A // Have this instruction set itself as the producer of its destination 5221060SN/A // register(s). 5232326SN/A addToProducers(new_inst); 5241060SN/A 5251061SN/A if (new_inst->isMemRef()) { 5262292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5271062SN/A } else { 5281062SN/A addIfReady(new_inst); 5291061SN/A } 5301061SN/A 5311062SN/A ++iqInstsAdded; 5321060SN/A 5332292SN/A count[new_inst->threadNumber]++; 5342292SN/A 5351060SN/A assert(freeEntries == (numEntries - countInsts())); 5361060SN/A} 5371060SN/A 5381061SN/Atemplate <class Impl> 5391061SN/Avoid 5402292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5411061SN/A{ 5421061SN/A // @todo: Clean up this code; can do it by setting inst as unable 5431061SN/A // to issue, then calling normal insert on the inst. 5441061SN/A 5452292SN/A assert(new_inst); 5461061SN/A 5472292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 5481061SN/A 5492326SN/A DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x " 5502326SN/A "to the IQ.\n", 5512326SN/A new_inst->seqNum, new_inst->readPC()); 5522064SN/A 5531061SN/A assert(freeEntries != 0); 5541061SN/A 5552292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5561061SN/A 5572064SN/A --freeEntries; 5581061SN/A 5592292SN/A new_inst->setInIQ(); 5601061SN/A 5611061SN/A // Have this instruction set itself as the producer of its destination 5621061SN/A // register(s). 5632326SN/A addToProducers(new_inst); 5641061SN/A 5651061SN/A // If it's a memory instruction, add it to the memory dependency 5661061SN/A // unit. 5672292SN/A if (new_inst->isMemRef()) { 5682292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 5691061SN/A } 5701062SN/A 5711062SN/A ++iqNonSpecInstsAdded; 5722292SN/A 5732292SN/A count[new_inst->threadNumber]++; 5742292SN/A 5752292SN/A assert(freeEntries == (numEntries - countInsts())); 5761061SN/A} 5771061SN/A 5781061SN/Atemplate <class Impl> 5791060SN/Avoid 5802292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 5811060SN/A{ 5822292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 5831060SN/A 5842292SN/A insertNonSpec(barr_inst); 5852292SN/A} 5861060SN/A 5872064SN/Atemplate <class Impl> 5882333SN/Atypename Impl::DynInstPtr 5892333SN/AInstructionQueue<Impl>::getInstToExecute() 5902333SN/A{ 5912333SN/A assert(!instsToExecute.empty()); 5922333SN/A DynInstPtr inst = instsToExecute.front(); 5932333SN/A instsToExecute.pop_front(); 5942333SN/A return inst; 5952333SN/A} 5961060SN/A 5972333SN/Atemplate <class Impl> 5982064SN/Avoid 5992292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6002292SN/A{ 6012292SN/A assert(!readyInsts[op_class].empty()); 6022292SN/A 6032292SN/A ListOrderEntry queue_entry; 6042292SN/A 6052292SN/A queue_entry.queueType = op_class; 6062292SN/A 6072292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6082292SN/A 6092292SN/A ListOrderIt list_it = listOrder.begin(); 6102292SN/A ListOrderIt list_end_it = listOrder.end(); 6112292SN/A 6122292SN/A while (list_it != list_end_it) { 6132292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6142292SN/A break; 6152292SN/A } 6162292SN/A 6172292SN/A list_it++; 6181060SN/A } 6191060SN/A 6202292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6212292SN/A queueOnList[op_class] = true; 6222292SN/A} 6231060SN/A 6242292SN/Atemplate <class Impl> 6252292SN/Avoid 6262292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6272292SN/A{ 6282292SN/A // Get iterator of next item on the list 6292292SN/A // Delete the original iterator 6302292SN/A // Determine if the next item is either the end of the list or younger 6312292SN/A // than the new instruction. If so, then add in a new iterator right here. 6322292SN/A // If not, then move along. 6332292SN/A ListOrderEntry queue_entry; 6342292SN/A OpClass op_class = (*list_order_it).queueType; 6352292SN/A ListOrderIt next_it = list_order_it; 6362292SN/A 6372292SN/A ++next_it; 6382292SN/A 6392292SN/A queue_entry.queueType = op_class; 6402292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6412292SN/A 6422292SN/A while (next_it != listOrder.end() && 6432292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 6442292SN/A ++next_it; 6451060SN/A } 6461060SN/A 6472292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 6481060SN/A} 6491060SN/A 6502292SN/Atemplate <class Impl> 6512292SN/Avoid 6522292SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 6532292SN/A{ 6542367SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 6552292SN/A // The CPU could have been sleeping until this op completed (*extremely* 6562292SN/A // long latency op). Wake it if it was. This may be overkill. 6572307SN/A if (isSwitchedOut()) { 6582367SN/A DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n", 6592367SN/A inst->seqNum); 6602307SN/A return; 6612307SN/A } 6622307SN/A 6632292SN/A iewStage->wakeCPU(); 6642292SN/A 6652326SN/A if (fu_idx > -1) 6662326SN/A fuPool->freeUnitNextCycle(fu_idx); 6672292SN/A 6682326SN/A // @todo: Ensure that these FU Completions happen at the beginning 6692326SN/A // of a cycle, otherwise they could add too many instructions to 6702326SN/A // the queue. 6715327Smengke97@hotmail.com issueToExecuteQueue->access(-1)->size++; 6722333SN/A instsToExecute.push_back(inst); 6732292SN/A} 6742292SN/A 6751061SN/A// @todo: Figure out a better way to remove the squashed items from the 6761061SN/A// lists. Checking the top item of each list to see if it's squashed 6771061SN/A// wastes time and forces jumps. 6781061SN/Atemplate <class Impl> 6791060SN/Avoid 6801060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 6811060SN/A{ 6822292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 6832292SN/A "the IQ.\n"); 6841060SN/A 6851060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 6861060SN/A 6872292SN/A // Have iterator to head of the list 6882292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 6892292SN/A // Try to get a FU that can do what this op needs. 6902292SN/A // If successful, change the oldestInst to the new top of the list, put 6912292SN/A // the queue in the proper place in the list. 6922292SN/A // Increment the iterator. 6932292SN/A // This will avoid trying to schedule a certain op class if there are no 6942292SN/A // FUs that handle it. 6952292SN/A ListOrderIt order_it = listOrder.begin(); 6962292SN/A ListOrderIt order_end_it = listOrder.end(); 6972292SN/A int total_issued = 0; 6981060SN/A 6992333SN/A while (total_issued < totalWidth && 7002820Sktlim@umich.edu iewStage->canIssue() && 7012326SN/A order_it != order_end_it) { 7022292SN/A OpClass op_class = (*order_it).queueType; 7031060SN/A 7042292SN/A assert(!readyInsts[op_class].empty()); 7051060SN/A 7062292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7071060SN/A 7082292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 7091060SN/A 7102292SN/A if (issuing_inst->isSquashed()) { 7112292SN/A readyInsts[op_class].pop(); 7121060SN/A 7132292SN/A if (!readyInsts[op_class].empty()) { 7142292SN/A moveToYoungerInst(order_it); 7152292SN/A } else { 7162292SN/A readyIt[op_class] = listOrder.end(); 7172292SN/A queueOnList[op_class] = false; 7181060SN/A } 7191060SN/A 7202292SN/A listOrder.erase(order_it++); 7211060SN/A 7222292SN/A ++iqSquashedInstsIssued; 7232292SN/A 7242292SN/A continue; 7251060SN/A } 7261060SN/A 7272326SN/A int idx = -2; 7282326SN/A int op_latency = 1; 7292301SN/A int tid = issuing_inst->threadNumber; 7301060SN/A 7312326SN/A if (op_class != No_OpClass) { 7322326SN/A idx = fuPool->getUnit(op_class); 7331060SN/A 7342326SN/A if (idx > -1) { 7352326SN/A op_latency = fuPool->getOpLatency(op_class); 7361060SN/A } 7371060SN/A } 7381060SN/A 7392348SN/A // If we have an instruction that doesn't require a FU, or a 7402348SN/A // valid FU, then schedule for execution. 7412326SN/A if (idx == -2 || idx != -1) { 7422292SN/A if (op_latency == 1) { 7432292SN/A i2e_info->size++; 7442333SN/A instsToExecute.push_back(issuing_inst); 7451060SN/A 7462326SN/A // Add the FU onto the list of FU's to be freed next 7472326SN/A // cycle if we used one. 7482326SN/A if (idx >= 0) 7492326SN/A fuPool->freeUnitNextCycle(idx); 7502292SN/A } else { 7512292SN/A int issue_latency = fuPool->getIssueLatency(op_class); 7522326SN/A // Generate completion event for the FU 7532326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 7542326SN/A idx, this); 7551060SN/A 7565606Snate@binkert.org cpu->schedule(execution, curTick + cpu->ticks(op_latency - 1)); 7571060SN/A 7582326SN/A // @todo: Enforce that issue_latency == 1 or op_latency 7592292SN/A if (issue_latency > 1) { 7602348SN/A // If FU isn't pipelined, then it must be freed 7612348SN/A // upon the execution completing. 7622326SN/A execution->setFreeFU(); 7632292SN/A } else { 7642292SN/A // Add the FU onto the list of FU's to be freed next cycle. 7652326SN/A fuPool->freeUnitNextCycle(idx); 7662292SN/A } 7671060SN/A } 7681060SN/A 7692292SN/A DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x " 7702292SN/A "[sn:%lli]\n", 7712301SN/A tid, issuing_inst->readPC(), 7722292SN/A issuing_inst->seqNum); 7731060SN/A 7742292SN/A readyInsts[op_class].pop(); 7751061SN/A 7762292SN/A if (!readyInsts[op_class].empty()) { 7772292SN/A moveToYoungerInst(order_it); 7782292SN/A } else { 7792292SN/A readyIt[op_class] = listOrder.end(); 7802292SN/A queueOnList[op_class] = false; 7811060SN/A } 7821060SN/A 7832064SN/A issuing_inst->setIssued(); 7842292SN/A ++total_issued; 7852064SN/A 7862292SN/A if (!issuing_inst->isMemRef()) { 7872292SN/A // Memory instructions can not be freed from the IQ until they 7882292SN/A // complete. 7892292SN/A ++freeEntries; 7902301SN/A count[tid]--; 7912731Sktlim@umich.edu issuing_inst->clearInIQ(); 7922292SN/A } else { 7932301SN/A memDepUnit[tid].issue(issuing_inst); 7942292SN/A } 7952292SN/A 7962292SN/A listOrder.erase(order_it++); 7972326SN/A statIssuedInstType[tid][op_class]++; 7982820Sktlim@umich.edu iewStage->incrWb(issuing_inst->seqNum); 7992292SN/A } else { 8002326SN/A statFuBusy[op_class]++; 8012326SN/A fuBusy[tid]++; 8022292SN/A ++order_it; 8031060SN/A } 8041060SN/A } 8051062SN/A 8062326SN/A numIssuedDist.sample(total_issued); 8072326SN/A iqInstsIssued+= total_issued; 8082307SN/A 8092348SN/A // If we issued any instructions, tell the CPU we had activity. 8102292SN/A if (total_issued) { 8112292SN/A cpu->activityThisCycle(); 8122292SN/A } else { 8132292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8142292SN/A } 8151060SN/A} 8161060SN/A 8171061SN/Atemplate <class Impl> 8181060SN/Avoid 8191061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 8201060SN/A{ 8212292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 8222292SN/A "to execute.\n", inst); 8231062SN/A 8242292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 8251060SN/A 8261061SN/A assert(inst_it != nonSpecInsts.end()); 8271060SN/A 8282292SN/A unsigned tid = (*inst_it).second->threadNumber; 8292292SN/A 8304033Sktlim@umich.edu (*inst_it).second->setAtCommit(); 8314033Sktlim@umich.edu 8321061SN/A (*inst_it).second->setCanIssue(); 8331060SN/A 8341062SN/A if (!(*inst_it).second->isMemRef()) { 8351062SN/A addIfReady((*inst_it).second); 8361062SN/A } else { 8372292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 8381062SN/A } 8391060SN/A 8402292SN/A (*inst_it).second = NULL; 8412292SN/A 8421061SN/A nonSpecInsts.erase(inst_it); 8431060SN/A} 8441060SN/A 8451061SN/Atemplate <class Impl> 8461061SN/Avoid 8472292SN/AInstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid) 8482292SN/A{ 8492292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 8502292SN/A tid,inst); 8512292SN/A 8522292SN/A ListIt iq_it = instList[tid].begin(); 8532292SN/A 8542292SN/A while (iq_it != instList[tid].end() && 8552292SN/A (*iq_it)->seqNum <= inst) { 8562292SN/A ++iq_it; 8572292SN/A instList[tid].pop_front(); 8582292SN/A } 8592292SN/A 8602292SN/A assert(freeEntries == (numEntries - countInsts())); 8612292SN/A} 8622292SN/A 8632292SN/Atemplate <class Impl> 8642301SN/Aint 8651684SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 8661684SN/A{ 8672301SN/A int dependents = 0; 8682301SN/A 8692292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 8702292SN/A 8712292SN/A assert(!completed_inst->isSquashed()); 8721684SN/A 8731684SN/A // Tell the memory dependence unit to wake any dependents on this 8742292SN/A // instruction if it is a memory instruction. Also complete the memory 8752326SN/A // instruction at this point since we know it executed without issues. 8762326SN/A // @todo: Might want to rename "completeMemInst" to something that 8772326SN/A // indicates that it won't need to be replayed, and call this 8782326SN/A // earlier. Might not be a big deal. 8791684SN/A if (completed_inst->isMemRef()) { 8802292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 8812292SN/A completeMemInst(completed_inst); 8822292SN/A } else if (completed_inst->isMemBarrier() || 8832292SN/A completed_inst->isWriteBarrier()) { 8842292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 8851684SN/A } 8861684SN/A 8871684SN/A for (int dest_reg_idx = 0; 8881684SN/A dest_reg_idx < completed_inst->numDestRegs(); 8891684SN/A dest_reg_idx++) 8901684SN/A { 8911684SN/A PhysRegIndex dest_reg = 8921684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 8931684SN/A 8941684SN/A // Special case of uniq or control registers. They are not 8951684SN/A // handled by the IQ and thus have no dependency graph entry. 8961684SN/A // @todo Figure out a cleaner way to handle this. 8971684SN/A if (dest_reg >= numPhysRegs) { 8981684SN/A continue; 8991684SN/A } 9001684SN/A 9012292SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 9021684SN/A (int) dest_reg); 9031684SN/A 9042326SN/A //Go through the dependency chain, marking the registers as 9052326SN/A //ready within the waiting instructions. 9062326SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg); 9071684SN/A 9082326SN/A while (dep_inst) { 9092292SN/A DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n", 9102326SN/A dep_inst->readPC()); 9111684SN/A 9121684SN/A // Might want to give more information to the instruction 9132326SN/A // so that it knows which of its source registers is 9142326SN/A // ready. However that would mean that the dependency 9152326SN/A // graph entries would need to hold the src_reg_idx. 9162326SN/A dep_inst->markSrcRegReady(); 9171684SN/A 9182326SN/A addIfReady(dep_inst); 9191684SN/A 9202326SN/A dep_inst = dependGraph.pop(dest_reg); 9211684SN/A 9222301SN/A ++dependents; 9231684SN/A } 9241684SN/A 9252326SN/A // Reset the head node now that all of its dependents have 9262326SN/A // been woken up. 9272326SN/A assert(dependGraph.empty(dest_reg)); 9282326SN/A dependGraph.clearInst(dest_reg); 9291684SN/A 9301684SN/A // Mark the scoreboard as having that register ready. 9311684SN/A regScoreboard[dest_reg] = true; 9321684SN/A } 9332301SN/A return dependents; 9342064SN/A} 9352064SN/A 9362064SN/Atemplate <class Impl> 9372064SN/Avoid 9382292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 9392064SN/A{ 9402292SN/A OpClass op_class = ready_inst->opClass(); 9412292SN/A 9422292SN/A readyInsts[op_class].push(ready_inst); 9432292SN/A 9442326SN/A // Will need to reorder the list if either a queue is not on the list, 9452326SN/A // or it has an older instruction than last time. 9462326SN/A if (!queueOnList[op_class]) { 9472326SN/A addToOrderList(op_class); 9482326SN/A } else if (readyInsts[op_class].top()->seqNum < 9492326SN/A (*readyIt[op_class]).oldestInst) { 9502326SN/A listOrder.erase(readyIt[op_class]); 9512326SN/A addToOrderList(op_class); 9522326SN/A } 9532326SN/A 9542292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 9552292SN/A "the ready list, PC %#x opclass:%i [sn:%lli].\n", 9562292SN/A ready_inst->readPC(), op_class, ready_inst->seqNum); 9572064SN/A} 9582064SN/A 9592064SN/Atemplate <class Impl> 9602064SN/Avoid 9612292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 9622064SN/A{ 9634033Sktlim@umich.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 9644033Sktlim@umich.edu resched_inst->clearCanIssue(); 9652292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 9662064SN/A} 9672064SN/A 9682064SN/Atemplate <class Impl> 9692064SN/Avoid 9702292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 9712064SN/A{ 9722292SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 9732292SN/A} 9742292SN/A 9752292SN/Atemplate <class Impl> 9762292SN/Avoid 9772292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 9782292SN/A{ 9792292SN/A int tid = completed_inst->threadNumber; 9802292SN/A 9812292SN/A DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n", 9822292SN/A completed_inst->readPC(), completed_inst->seqNum); 9832292SN/A 9842292SN/A ++freeEntries; 9852292SN/A 9862292SN/A completed_inst->memOpDone = true; 9872292SN/A 9882292SN/A memDepUnit[tid].completed(completed_inst); 9892292SN/A count[tid]--; 9901684SN/A} 9911684SN/A 9921684SN/Atemplate <class Impl> 9931684SN/Avoid 9941061SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 9951061SN/A DynInstPtr &faulting_load) 9961061SN/A{ 9972292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 9981061SN/A} 9991061SN/A 10001061SN/Atemplate <class Impl> 10011060SN/Avoid 10022292SN/AInstructionQueue<Impl>::squash(unsigned tid) 10031060SN/A{ 10042292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 10052292SN/A "the IQ.\n", tid); 10061060SN/A 10071060SN/A // Read instruction sequence number of last instruction out of the 10081060SN/A // time buffer. 10092292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 10101060SN/A 10111681SN/A // Call doSquash if there are insts in the IQ 10122292SN/A if (count[tid] > 0) { 10132292SN/A doSquash(tid); 10141681SN/A } 10151061SN/A 10161061SN/A // Also tell the memory dependence unit to squash. 10172292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 10181060SN/A} 10191060SN/A 10201061SN/Atemplate <class Impl> 10211061SN/Avoid 10222292SN/AInstructionQueue<Impl>::doSquash(unsigned tid) 10231061SN/A{ 10242326SN/A // Start at the tail. 10252326SN/A ListIt squash_it = instList[tid].end(); 10262326SN/A --squash_it; 10271061SN/A 10282292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 10292292SN/A tid, squashedSeqNum[tid]); 10301061SN/A 10311061SN/A // Squash any instructions younger than the squashed sequence number 10321061SN/A // given. 10332326SN/A while (squash_it != instList[tid].end() && 10342326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 10352292SN/A 10362326SN/A DynInstPtr squashed_inst = (*squash_it); 10371061SN/A 10381061SN/A // Only handle the instruction if it actually is in the IQ and 10391061SN/A // hasn't already been squashed in the IQ. 10402292SN/A if (squashed_inst->threadNumber != tid || 10412292SN/A squashed_inst->isSquashedInIQ()) { 10422326SN/A --squash_it; 10432292SN/A continue; 10442292SN/A } 10452292SN/A 10462292SN/A if (!squashed_inst->isIssued() || 10472292SN/A (squashed_inst->isMemRef() && 10482292SN/A !squashed_inst->memOpDone)) { 10491062SN/A 10502367SN/A DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x " 10512367SN/A "squashed.\n", 10522367SN/A tid, squashed_inst->seqNum, squashed_inst->readPC()); 10532367SN/A 10541061SN/A // Remove the instruction from the dependency list. 10552292SN/A if (!squashed_inst->isNonSpeculative() && 10562336SN/A !squashed_inst->isStoreConditional() && 10572292SN/A !squashed_inst->isMemBarrier() && 10582292SN/A !squashed_inst->isWriteBarrier()) { 10591061SN/A 10601061SN/A for (int src_reg_idx = 0; 10611681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 10621061SN/A src_reg_idx++) 10631061SN/A { 10641061SN/A PhysRegIndex src_reg = 10651061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 10661061SN/A 10672326SN/A // Only remove it from the dependency graph if it 10682326SN/A // was placed there in the first place. 10692326SN/A 10702326SN/A // Instead of doing a linked list traversal, we 10712326SN/A // can just remove these squashed instructions 10722326SN/A // either at issue time, or when the register is 10732326SN/A // overwritten. The only downside to this is it 10742326SN/A // leaves more room for error. 10752292SN/A 10761061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 10771061SN/A src_reg < numPhysRegs) { 10782326SN/A dependGraph.remove(src_reg, squashed_inst); 10791061SN/A } 10801062SN/A 10812292SN/A 10821062SN/A ++iqSquashedOperandsExamined; 10831061SN/A } 10844033Sktlim@umich.edu } else if (!squashed_inst->isStoreConditional() || 10854033Sktlim@umich.edu !squashed_inst->isCompleted()) { 10862292SN/A NonSpecMapIt ns_inst_it = 10872292SN/A nonSpecInsts.find(squashed_inst->seqNum); 10882292SN/A assert(ns_inst_it != nonSpecInsts.end()); 10894033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 10904033Sktlim@umich.edu assert(squashed_inst->getFault() != NoFault); 10914033Sktlim@umich.edu } else { 10921062SN/A 10934033Sktlim@umich.edu (*ns_inst_it).second = NULL; 10941681SN/A 10954033Sktlim@umich.edu nonSpecInsts.erase(ns_inst_it); 10961062SN/A 10974033Sktlim@umich.edu ++iqSquashedNonSpecRemoved; 10984033Sktlim@umich.edu } 10991061SN/A } 11001061SN/A 11011061SN/A // Might want to also clear out the head of the dependency graph. 11021061SN/A 11031061SN/A // Mark it as squashed within the IQ. 11041061SN/A squashed_inst->setSquashedInIQ(); 11051061SN/A 11062292SN/A // @todo: Remove this hack where several statuses are set so the 11072292SN/A // inst will flow through the rest of the pipeline. 11081681SN/A squashed_inst->setIssued(); 11091681SN/A squashed_inst->setCanCommit(); 11102731Sktlim@umich.edu squashed_inst->clearInIQ(); 11112292SN/A 11122292SN/A //Update Thread IQ Count 11132292SN/A count[squashed_inst->threadNumber]--; 11141681SN/A 11151681SN/A ++freeEntries; 11161061SN/A } 11171061SN/A 11182326SN/A instList[tid].erase(squash_it--); 11191062SN/A ++iqSquashedInstsExamined; 11201061SN/A } 11211060SN/A} 11221060SN/A 11231061SN/Atemplate <class Impl> 11241060SN/Abool 11251061SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 11261060SN/A{ 11271060SN/A // Loop through the instruction's source registers, adding 11281060SN/A // them to the dependency list if they are not ready. 11291060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 11301060SN/A bool return_val = false; 11311060SN/A 11321060SN/A for (int src_reg_idx = 0; 11331060SN/A src_reg_idx < total_src_regs; 11341060SN/A src_reg_idx++) 11351060SN/A { 11361060SN/A // Only add it to the dependency graph if it's not ready. 11371060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 11381060SN/A PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 11391060SN/A 11401060SN/A // Check the IQ's scoreboard to make sure the register 11411060SN/A // hasn't become ready while the instruction was in flight 11421060SN/A // between stages. Only if it really isn't ready should 11431060SN/A // it be added to the dependency graph. 11441061SN/A if (src_reg >= numPhysRegs) { 11451061SN/A continue; 11461061SN/A } else if (regScoreboard[src_reg] == false) { 11472292SN/A DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 11481060SN/A "is being added to the dependency chain.\n", 11491060SN/A new_inst->readPC(), src_reg); 11501060SN/A 11512326SN/A dependGraph.insert(src_reg, new_inst); 11521060SN/A 11531060SN/A // Change the return value to indicate that something 11541060SN/A // was added to the dependency graph. 11551060SN/A return_val = true; 11561060SN/A } else { 11572292SN/A DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 11581060SN/A "became ready before it reached the IQ.\n", 11591060SN/A new_inst->readPC(), src_reg); 11601060SN/A // Mark a register ready within the instruction. 11612326SN/A new_inst->markSrcRegReady(src_reg_idx); 11621060SN/A } 11631060SN/A } 11641060SN/A } 11651060SN/A 11661060SN/A return return_val; 11671060SN/A} 11681060SN/A 11691061SN/Atemplate <class Impl> 11701060SN/Avoid 11712326SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 11721060SN/A{ 11732326SN/A // Nothing really needs to be marked when an instruction becomes 11742326SN/A // the producer of a register's value, but for convenience a ptr 11752326SN/A // to the producing instruction will be placed in the head node of 11762326SN/A // the dependency links. 11771060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 11781060SN/A 11791060SN/A for (int dest_reg_idx = 0; 11801060SN/A dest_reg_idx < total_dest_regs; 11811060SN/A dest_reg_idx++) 11821060SN/A { 11831061SN/A PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 11841061SN/A 11851061SN/A // Instructions that use the misc regs will have a reg number 11861061SN/A // higher than the normal physical registers. In this case these 11871061SN/A // registers are not renamed, and there is no need to track 11881061SN/A // dependencies as these instructions must be executed at commit. 11891061SN/A if (dest_reg >= numPhysRegs) { 11901061SN/A continue; 11911060SN/A } 11921060SN/A 11932326SN/A if (!dependGraph.empty(dest_reg)) { 11942326SN/A dependGraph.dump(); 11952292SN/A panic("Dependency graph %i not empty!", dest_reg); 11962064SN/A } 11971062SN/A 11982326SN/A dependGraph.setInst(dest_reg, new_inst); 11991062SN/A 12001060SN/A // Mark the scoreboard to say it's not yet ready. 12011060SN/A regScoreboard[dest_reg] = false; 12021060SN/A } 12031060SN/A} 12041060SN/A 12051061SN/Atemplate <class Impl> 12061060SN/Avoid 12071061SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 12081060SN/A{ 12092326SN/A // If the instruction now has all of its source registers 12101060SN/A // available, then add it to the list of ready instructions. 12111060SN/A if (inst->readyToIssue()) { 12121061SN/A 12131060SN/A //Add the instruction to the proper ready list. 12142292SN/A if (inst->isMemRef()) { 12151061SN/A 12162292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 12171061SN/A 12181062SN/A // Message to the mem dependence unit that this instruction has 12191062SN/A // its registers ready. 12202292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 12211062SN/A 12222292SN/A return; 12232292SN/A } 12241062SN/A 12252292SN/A OpClass op_class = inst->opClass(); 12261061SN/A 12272292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 12282292SN/A "the ready list, PC %#x opclass:%i [sn:%lli].\n", 12292292SN/A inst->readPC(), op_class, inst->seqNum); 12301061SN/A 12312292SN/A readyInsts[op_class].push(inst); 12321061SN/A 12332326SN/A // Will need to reorder the list if either a queue is not on the list, 12342326SN/A // or it has an older instruction than last time. 12352326SN/A if (!queueOnList[op_class]) { 12362326SN/A addToOrderList(op_class); 12372326SN/A } else if (readyInsts[op_class].top()->seqNum < 12382326SN/A (*readyIt[op_class]).oldestInst) { 12392326SN/A listOrder.erase(readyIt[op_class]); 12402326SN/A addToOrderList(op_class); 12411060SN/A } 12421060SN/A } 12431060SN/A} 12441060SN/A 12451061SN/Atemplate <class Impl> 12461061SN/Aint 12471061SN/AInstructionQueue<Impl>::countInsts() 12481061SN/A{ 12492698Sktlim@umich.edu#if 0 12502292SN/A //ksewell:This works but definitely could use a cleaner write 12512292SN/A //with a more intuitive way of counting. Right now it's 12522292SN/A //just brute force .... 12532698Sktlim@umich.edu // Change the #if if you want to use this method. 12541061SN/A int total_insts = 0; 12551061SN/A 12562292SN/A for (int i = 0; i < numThreads; ++i) { 12572292SN/A ListIt count_it = instList[i].begin(); 12581681SN/A 12592292SN/A while (count_it != instList[i].end()) { 12602292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 12612292SN/A if (!(*count_it)->isIssued()) { 12622292SN/A ++total_insts; 12632292SN/A } else if ((*count_it)->isMemRef() && 12642292SN/A !(*count_it)->memOpDone) { 12652292SN/A // Loads that have not been marked as executed still count 12662292SN/A // towards the total instructions. 12672292SN/A ++total_insts; 12682292SN/A } 12692292SN/A } 12702292SN/A 12712292SN/A ++count_it; 12721061SN/A } 12731061SN/A } 12741061SN/A 12751061SN/A return total_insts; 12762292SN/A#else 12772292SN/A return numEntries - freeEntries; 12782292SN/A#endif 12791681SN/A} 12801681SN/A 12811681SN/Atemplate <class Impl> 12821681SN/Avoid 12831061SN/AInstructionQueue<Impl>::dumpLists() 12841061SN/A{ 12852292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 12862292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 12871061SN/A 12882292SN/A cprintf("\n"); 12892292SN/A } 12901061SN/A 12911061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 12921061SN/A 12932292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 12942292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 12951061SN/A 12961061SN/A cprintf("Non speculative list: "); 12971061SN/A 12982292SN/A while (non_spec_it != non_spec_end_it) { 12992292SN/A cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(), 13002292SN/A (*non_spec_it).second->seqNum); 13011061SN/A ++non_spec_it; 13021061SN/A } 13031061SN/A 13041061SN/A cprintf("\n"); 13051061SN/A 13062292SN/A ListOrderIt list_order_it = listOrder.begin(); 13072292SN/A ListOrderIt list_order_end_it = listOrder.end(); 13082292SN/A int i = 1; 13092292SN/A 13102292SN/A cprintf("List order: "); 13112292SN/A 13122292SN/A while (list_order_it != list_order_end_it) { 13132292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 13142292SN/A (*list_order_it).oldestInst); 13152292SN/A 13162292SN/A ++list_order_it; 13172292SN/A ++i; 13182292SN/A } 13192292SN/A 13202292SN/A cprintf("\n"); 13211061SN/A} 13222292SN/A 13232292SN/A 13242292SN/Atemplate <class Impl> 13252292SN/Avoid 13262292SN/AInstructionQueue<Impl>::dumpInsts() 13272292SN/A{ 13282292SN/A for (int i = 0; i < numThreads; ++i) { 13292292SN/A int num = 0; 13302292SN/A int valid_num = 0; 13312292SN/A ListIt inst_list_it = instList[i].begin(); 13322292SN/A 13332292SN/A while (inst_list_it != instList[i].end()) 13342292SN/A { 13352292SN/A cprintf("Instruction:%i\n", 13362292SN/A num); 13372292SN/A if (!(*inst_list_it)->isSquashed()) { 13382292SN/A if (!(*inst_list_it)->isIssued()) { 13392292SN/A ++valid_num; 13402292SN/A cprintf("Count:%i\n", valid_num); 13412292SN/A } else if ((*inst_list_it)->isMemRef() && 13422292SN/A !(*inst_list_it)->memOpDone) { 13432326SN/A // Loads that have not been marked as executed 13442326SN/A // still count towards the total instructions. 13452292SN/A ++valid_num; 13462292SN/A cprintf("Count:%i\n", valid_num); 13472292SN/A } 13482292SN/A } 13492292SN/A 13502292SN/A cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 13512292SN/A "Issued:%i\nSquashed:%i\n", 13522292SN/A (*inst_list_it)->readPC(), 13532292SN/A (*inst_list_it)->seqNum, 13542292SN/A (*inst_list_it)->threadNumber, 13552292SN/A (*inst_list_it)->isIssued(), 13562292SN/A (*inst_list_it)->isSquashed()); 13572292SN/A 13582292SN/A if ((*inst_list_it)->isMemRef()) { 13592292SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 13602292SN/A } 13612292SN/A 13622292SN/A cprintf("\n"); 13632292SN/A 13642292SN/A inst_list_it++; 13652292SN/A ++num; 13662292SN/A } 13672292SN/A } 13682348SN/A 13692348SN/A cprintf("Insts to Execute list:\n"); 13702348SN/A 13712348SN/A int num = 0; 13722348SN/A int valid_num = 0; 13732348SN/A ListIt inst_list_it = instsToExecute.begin(); 13742348SN/A 13752348SN/A while (inst_list_it != instsToExecute.end()) 13762348SN/A { 13772348SN/A cprintf("Instruction:%i\n", 13782348SN/A num); 13792348SN/A if (!(*inst_list_it)->isSquashed()) { 13802348SN/A if (!(*inst_list_it)->isIssued()) { 13812348SN/A ++valid_num; 13822348SN/A cprintf("Count:%i\n", valid_num); 13832348SN/A } else if ((*inst_list_it)->isMemRef() && 13842348SN/A !(*inst_list_it)->memOpDone) { 13852348SN/A // Loads that have not been marked as executed 13862348SN/A // still count towards the total instructions. 13872348SN/A ++valid_num; 13882348SN/A cprintf("Count:%i\n", valid_num); 13892348SN/A } 13902348SN/A } 13912348SN/A 13922348SN/A cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 13932348SN/A "Issued:%i\nSquashed:%i\n", 13942348SN/A (*inst_list_it)->readPC(), 13952348SN/A (*inst_list_it)->seqNum, 13962348SN/A (*inst_list_it)->threadNumber, 13972348SN/A (*inst_list_it)->isIssued(), 13982348SN/A (*inst_list_it)->isSquashed()); 13992348SN/A 14002348SN/A if ((*inst_list_it)->isMemRef()) { 14012348SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 14022348SN/A } 14032348SN/A 14042348SN/A cprintf("\n"); 14052348SN/A 14062348SN/A inst_list_it++; 14072348SN/A ++num; 14082348SN/A } 14092292SN/A} 1410