inst_queue_impl.hh revision 3867
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 292831Sksewell@umich.edu * Korey Sewell 301689SN/A */ 311689SN/A 322064SN/A#include <limits> 331060SN/A#include <vector> 341060SN/A 351696SN/A#include "sim/root.hh" 361689SN/A 372292SN/A#include "cpu/o3/fu_pool.hh" 381717SN/A#include "cpu/o3/inst_queue.hh" 391060SN/A 401061SN/Atemplate <class Impl> 412292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 422292SN/A int fu_idx, 432292SN/A InstructionQueue<Impl> *iq_ptr) 442292SN/A : Event(&mainEventQueue, Stat_Event_Pri), 452326SN/A inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 461060SN/A{ 472292SN/A this->setFlags(Event::AutoDelete); 482292SN/A} 492292SN/A 502292SN/Atemplate <class Impl> 512292SN/Avoid 522292SN/AInstructionQueue<Impl>::FUCompletion::process() 532292SN/A{ 542326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 552292SN/A inst = NULL; 562292SN/A} 572292SN/A 582292SN/A 592292SN/Atemplate <class Impl> 602292SN/Aconst char * 612292SN/AInstructionQueue<Impl>::FUCompletion::description() 622292SN/A{ 632292SN/A return "Functional unit completion event"; 642292SN/A} 652292SN/A 662292SN/Atemplate <class Impl> 672292SN/AInstructionQueue<Impl>::InstructionQueue(Params *params) 682669Sktlim@umich.edu : fuPool(params->fuPool), 692292SN/A numEntries(params->numIQEntries), 702292SN/A totalWidth(params->issueWidth), 712292SN/A numPhysIntRegs(params->numPhysIntRegs), 722292SN/A numPhysFloatRegs(params->numPhysFloatRegs), 732292SN/A commitToIEWDelay(params->commitToIEWDelay) 742292SN/A{ 752292SN/A assert(fuPool); 762292SN/A 772307SN/A switchedOut = false; 782307SN/A 792292SN/A numThreads = params->numberOfThreads; 801060SN/A 811060SN/A // Set the number of physical registers as the number of int + float 821060SN/A numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 831060SN/A 842292SN/A DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs); 851060SN/A 861060SN/A //Create an entry for each physical register within the 871060SN/A //dependency graph. 882326SN/A dependGraph.resize(numPhysRegs); 891060SN/A 901060SN/A // Resize the register scoreboard. 911060SN/A regScoreboard.resize(numPhysRegs); 921060SN/A 932292SN/A //Initialize Mem Dependence Units 942292SN/A for (int i = 0; i < numThreads; i++) { 952292SN/A memDepUnit[i].init(params,i); 962292SN/A memDepUnit[i].setIQ(this); 971060SN/A } 981060SN/A 992307SN/A resetState(); 1002292SN/A 1012980Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1022292SN/A 1032292SN/A //Convert string to lowercase 1042292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1052292SN/A (int(*)(int)) tolower); 1062292SN/A 1072292SN/A //Figure out resource sharing policy 1082292SN/A if (policy == "dynamic") { 1092292SN/A iqPolicy = Dynamic; 1102292SN/A 1112292SN/A //Set Max Entries to Total ROB Capacity 1122292SN/A for (int i = 0; i < numThreads; i++) { 1132292SN/A maxEntries[i] = numEntries; 1142292SN/A } 1152292SN/A 1162292SN/A } else if (policy == "partitioned") { 1172292SN/A iqPolicy = Partitioned; 1182292SN/A 1192292SN/A //@todo:make work if part_amt doesnt divide evenly. 1202292SN/A int part_amt = numEntries / numThreads; 1212292SN/A 1222292SN/A //Divide ROB up evenly 1232292SN/A for (int i = 0; i < numThreads; i++) { 1242292SN/A maxEntries[i] = part_amt; 1252292SN/A } 1262292SN/A 1272831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1282292SN/A "%i entries per thread.\n",part_amt); 1292292SN/A 1302292SN/A } else if (policy == "threshold") { 1312292SN/A iqPolicy = Threshold; 1322292SN/A 1332292SN/A double threshold = (double)params->smtIQThreshold / 100; 1342292SN/A 1352292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1362292SN/A 1372292SN/A //Divide up by threshold amount 1382292SN/A for (int i = 0; i < numThreads; i++) { 1392292SN/A maxEntries[i] = thresholdIQ; 1402292SN/A } 1412292SN/A 1422831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1432292SN/A "%i entries per thread.\n",thresholdIQ); 1442292SN/A } else { 1452292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1462292SN/A "Partitioned, Threshold}"); 1472292SN/A } 1482292SN/A} 1492292SN/A 1502292SN/Atemplate <class Impl> 1512292SN/AInstructionQueue<Impl>::~InstructionQueue() 1522292SN/A{ 1532326SN/A dependGraph.reset(); 1542348SN/A#ifdef DEBUG 1552326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1562326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1572348SN/A#endif 1582292SN/A} 1592292SN/A 1602292SN/Atemplate <class Impl> 1612292SN/Astd::string 1622292SN/AInstructionQueue<Impl>::name() const 1632292SN/A{ 1642292SN/A return cpu->name() + ".iq"; 1651060SN/A} 1661060SN/A 1671061SN/Atemplate <class Impl> 1681060SN/Avoid 1691062SN/AInstructionQueue<Impl>::regStats() 1701062SN/A{ 1712301SN/A using namespace Stats; 1721062SN/A iqInstsAdded 1731062SN/A .name(name() + ".iqInstsAdded") 1741062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1751062SN/A .prereq(iqInstsAdded); 1761062SN/A 1771062SN/A iqNonSpecInstsAdded 1781062SN/A .name(name() + ".iqNonSpecInstsAdded") 1791062SN/A .desc("Number of non-speculative instructions added to the IQ") 1801062SN/A .prereq(iqNonSpecInstsAdded); 1811062SN/A 1822301SN/A iqInstsIssued 1832301SN/A .name(name() + ".iqInstsIssued") 1842301SN/A .desc("Number of instructions issued") 1852301SN/A .prereq(iqInstsIssued); 1861062SN/A 1871062SN/A iqIntInstsIssued 1881062SN/A .name(name() + ".iqIntInstsIssued") 1891062SN/A .desc("Number of integer instructions issued") 1901062SN/A .prereq(iqIntInstsIssued); 1911062SN/A 1921062SN/A iqFloatInstsIssued 1931062SN/A .name(name() + ".iqFloatInstsIssued") 1941062SN/A .desc("Number of float instructions issued") 1951062SN/A .prereq(iqFloatInstsIssued); 1961062SN/A 1971062SN/A iqBranchInstsIssued 1981062SN/A .name(name() + ".iqBranchInstsIssued") 1991062SN/A .desc("Number of branch instructions issued") 2001062SN/A .prereq(iqBranchInstsIssued); 2011062SN/A 2021062SN/A iqMemInstsIssued 2031062SN/A .name(name() + ".iqMemInstsIssued") 2041062SN/A .desc("Number of memory instructions issued") 2051062SN/A .prereq(iqMemInstsIssued); 2061062SN/A 2071062SN/A iqMiscInstsIssued 2081062SN/A .name(name() + ".iqMiscInstsIssued") 2091062SN/A .desc("Number of miscellaneous instructions issued") 2101062SN/A .prereq(iqMiscInstsIssued); 2111062SN/A 2121062SN/A iqSquashedInstsIssued 2131062SN/A .name(name() + ".iqSquashedInstsIssued") 2141062SN/A .desc("Number of squashed instructions issued") 2151062SN/A .prereq(iqSquashedInstsIssued); 2161062SN/A 2171062SN/A iqSquashedInstsExamined 2181062SN/A .name(name() + ".iqSquashedInstsExamined") 2191062SN/A .desc("Number of squashed instructions iterated over during squash;" 2201062SN/A " mainly for profiling") 2211062SN/A .prereq(iqSquashedInstsExamined); 2221062SN/A 2231062SN/A iqSquashedOperandsExamined 2241062SN/A .name(name() + ".iqSquashedOperandsExamined") 2251062SN/A .desc("Number of squashed operands that are examined and possibly " 2261062SN/A "removed from graph") 2271062SN/A .prereq(iqSquashedOperandsExamined); 2281062SN/A 2291062SN/A iqSquashedNonSpecRemoved 2301062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2311062SN/A .desc("Number of squashed non-spec instructions that were removed") 2321062SN/A .prereq(iqSquashedNonSpecRemoved); 2332361SN/A/* 2342326SN/A queueResDist 2352301SN/A .init(Num_OpClasses, 0, 99, 2) 2362301SN/A .name(name() + ".IQ:residence:") 2372301SN/A .desc("cycles from dispatch to issue") 2382301SN/A .flags(total | pdf | cdf ) 2392301SN/A ; 2402301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2412326SN/A queueResDist.subname(i, opClassStrings[i]); 2422301SN/A } 2432361SN/A*/ 2442326SN/A numIssuedDist 2452307SN/A .init(0,totalWidth,1) 2462301SN/A .name(name() + ".ISSUE:issued_per_cycle") 2472301SN/A .desc("Number of insts issued each cycle") 2482307SN/A .flags(pdf) 2492301SN/A ; 2502301SN/A/* 2512301SN/A dist_unissued 2522301SN/A .init(Num_OpClasses+2) 2532301SN/A .name(name() + ".ISSUE:unissued_cause") 2542301SN/A .desc("Reason ready instruction not issued") 2552301SN/A .flags(pdf | dist) 2562301SN/A ; 2572301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2582301SN/A dist_unissued.subname(i, unissued_names[i]); 2592301SN/A } 2602301SN/A*/ 2612326SN/A statIssuedInstType 2622301SN/A .init(numThreads,Num_OpClasses) 2632301SN/A .name(name() + ".ISSUE:FU_type") 2642301SN/A .desc("Type of FU issued") 2652301SN/A .flags(total | pdf | dist) 2662301SN/A ; 2672326SN/A statIssuedInstType.ysubnames(opClassStrings); 2682301SN/A 2692301SN/A // 2702301SN/A // How long did instructions for a particular FU type wait prior to issue 2712301SN/A // 2722361SN/A/* 2732326SN/A issueDelayDist 2742301SN/A .init(Num_OpClasses,0,99,2) 2752301SN/A .name(name() + ".ISSUE:") 2762301SN/A .desc("cycles from operands ready to issue") 2772301SN/A .flags(pdf | cdf) 2782301SN/A ; 2792301SN/A 2802301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2812980Sgblack@eecs.umich.edu std::stringstream subname; 2822301SN/A subname << opClassStrings[i] << "_delay"; 2832326SN/A issueDelayDist.subname(i, subname.str()); 2842301SN/A } 2852361SN/A*/ 2862326SN/A issueRate 2872301SN/A .name(name() + ".ISSUE:rate") 2882301SN/A .desc("Inst issue rate") 2892301SN/A .flags(total) 2902301SN/A ; 2912326SN/A issueRate = iqInstsIssued / cpu->numCycles; 2922727Sktlim@umich.edu 2932326SN/A statFuBusy 2942301SN/A .init(Num_OpClasses) 2952301SN/A .name(name() + ".ISSUE:fu_full") 2962301SN/A .desc("attempts to use FU when none available") 2972301SN/A .flags(pdf | dist) 2982301SN/A ; 2992301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3002326SN/A statFuBusy.subname(i, opClassStrings[i]); 3012301SN/A } 3022301SN/A 3032326SN/A fuBusy 3042301SN/A .init(numThreads) 3052301SN/A .name(name() + ".ISSUE:fu_busy_cnt") 3062301SN/A .desc("FU busy when requested") 3072301SN/A .flags(total) 3082301SN/A ; 3092301SN/A 3102326SN/A fuBusyRate 3112301SN/A .name(name() + ".ISSUE:fu_busy_rate") 3122301SN/A .desc("FU busy rate (busy events/executed inst)") 3132301SN/A .flags(total) 3142301SN/A ; 3152326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3162301SN/A 3172292SN/A for ( int i=0; i < numThreads; i++) { 3182292SN/A // Tell mem dependence unit to reg stats as well. 3192292SN/A memDepUnit[i].regStats(); 3202292SN/A } 3211062SN/A} 3221062SN/A 3231062SN/Atemplate <class Impl> 3241062SN/Avoid 3252307SN/AInstructionQueue<Impl>::resetState() 3261060SN/A{ 3272307SN/A //Initialize thread IQ counts 3282307SN/A for (int i = 0; i <numThreads; i++) { 3292307SN/A count[i] = 0; 3302307SN/A instList[i].clear(); 3312307SN/A } 3321060SN/A 3332307SN/A // Initialize the number of free IQ entries. 3342307SN/A freeEntries = numEntries; 3352307SN/A 3362307SN/A // Note that in actuality, the registers corresponding to the logical 3372307SN/A // registers start off as ready. However this doesn't matter for the 3382307SN/A // IQ as the instruction should have been correctly told if those 3392307SN/A // registers are ready in rename. Thus it can all be initialized as 3402307SN/A // unready. 3412307SN/A for (int i = 0; i < numPhysRegs; ++i) { 3422307SN/A regScoreboard[i] = false; 3432307SN/A } 3442307SN/A 3452307SN/A for (int i = 0; i < numThreads; ++i) { 3462307SN/A squashedSeqNum[i] = 0; 3472307SN/A } 3482307SN/A 3492307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 3502307SN/A while (!readyInsts[i].empty()) 3512307SN/A readyInsts[i].pop(); 3522307SN/A queueOnList[i] = false; 3532307SN/A readyIt[i] = listOrder.end(); 3542307SN/A } 3552307SN/A nonSpecInsts.clear(); 3562307SN/A listOrder.clear(); 3571060SN/A} 3581060SN/A 3591061SN/Atemplate <class Impl> 3601060SN/Avoid 3612980Sgblack@eecs.umich.eduInstructionQueue<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 3621060SN/A{ 3632292SN/A DPRINTF(IQ, "Setting active threads list pointer.\n"); 3642292SN/A activeThreads = at_ptr; 3652064SN/A} 3662064SN/A 3672064SN/Atemplate <class Impl> 3682064SN/Avoid 3692292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 3702064SN/A{ 3712292SN/A DPRINTF(IQ, "Set the issue to execute queue.\n"); 3721060SN/A issueToExecuteQueue = i2e_ptr; 3731060SN/A} 3741060SN/A 3751061SN/Atemplate <class Impl> 3761060SN/Avoid 3771060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3781060SN/A{ 3792292SN/A DPRINTF(IQ, "Set the time buffer.\n"); 3801060SN/A timeBuffer = tb_ptr; 3811060SN/A 3821060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3831060SN/A} 3841060SN/A 3851684SN/Atemplate <class Impl> 3862307SN/Avoid 3872307SN/AInstructionQueue<Impl>::switchOut() 3882307SN/A{ 3892367SN/A/* 3902367SN/A if (!instList[0].empty() || (numEntries != freeEntries) || 3912367SN/A !readyInsts[0].empty() || !nonSpecInsts.empty() || !listOrder.empty()) { 3922367SN/A dumpInsts(); 3932367SN/A// assert(0); 3942367SN/A } 3952367SN/A*/ 3962307SN/A resetState(); 3972326SN/A dependGraph.reset(); 3982367SN/A instsToExecute.clear(); 3992307SN/A switchedOut = true; 4002307SN/A for (int i = 0; i < numThreads; ++i) { 4012307SN/A memDepUnit[i].switchOut(); 4022307SN/A } 4032307SN/A} 4042307SN/A 4052307SN/Atemplate <class Impl> 4062307SN/Avoid 4072307SN/AInstructionQueue<Impl>::takeOverFrom() 4082307SN/A{ 4092307SN/A switchedOut = false; 4102307SN/A} 4112307SN/A 4122307SN/Atemplate <class Impl> 4132292SN/Aint 4142292SN/AInstructionQueue<Impl>::entryAmount(int num_threads) 4152292SN/A{ 4162292SN/A if (iqPolicy == Partitioned) { 4172292SN/A return numEntries / num_threads; 4182292SN/A } else { 4192292SN/A return 0; 4202292SN/A } 4212292SN/A} 4222292SN/A 4232292SN/A 4242292SN/Atemplate <class Impl> 4252292SN/Avoid 4262292SN/AInstructionQueue<Impl>::resetEntries() 4272292SN/A{ 4282292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4293867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 4302292SN/A 4313867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 4323867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 4332292SN/A 4343867Sbinkertn@umich.edu while (threads != end) { 4353867Sbinkertn@umich.edu unsigned tid = *threads++; 4363867Sbinkertn@umich.edu 4372292SN/A if (iqPolicy == Partitioned) { 4383867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 4392292SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4403867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 4412292SN/A } 4422292SN/A } 4432292SN/A } 4442292SN/A} 4452292SN/A 4462292SN/Atemplate <class Impl> 4471684SN/Aunsigned 4481684SN/AInstructionQueue<Impl>::numFreeEntries() 4491684SN/A{ 4501684SN/A return freeEntries; 4511684SN/A} 4521684SN/A 4532292SN/Atemplate <class Impl> 4542292SN/Aunsigned 4552292SN/AInstructionQueue<Impl>::numFreeEntries(unsigned tid) 4562292SN/A{ 4572292SN/A return maxEntries[tid] - count[tid]; 4582292SN/A} 4592292SN/A 4601060SN/A// Might want to do something more complex if it knows how many instructions 4611060SN/A// will be issued this cycle. 4621061SN/Atemplate <class Impl> 4631060SN/Abool 4641060SN/AInstructionQueue<Impl>::isFull() 4651060SN/A{ 4661060SN/A if (freeEntries == 0) { 4671060SN/A return(true); 4681060SN/A } else { 4691060SN/A return(false); 4701060SN/A } 4711060SN/A} 4721060SN/A 4731061SN/Atemplate <class Impl> 4742292SN/Abool 4752292SN/AInstructionQueue<Impl>::isFull(unsigned tid) 4762292SN/A{ 4772292SN/A if (numFreeEntries(tid) == 0) { 4782292SN/A return(true); 4792292SN/A } else { 4802292SN/A return(false); 4812292SN/A } 4822292SN/A} 4832292SN/A 4842292SN/Atemplate <class Impl> 4852292SN/Abool 4862292SN/AInstructionQueue<Impl>::hasReadyInsts() 4872292SN/A{ 4882292SN/A if (!listOrder.empty()) { 4892292SN/A return true; 4902292SN/A } 4912292SN/A 4922292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4932292SN/A if (!readyInsts[i].empty()) { 4942292SN/A return true; 4952292SN/A } 4962292SN/A } 4972292SN/A 4982292SN/A return false; 4992292SN/A} 5002292SN/A 5012292SN/Atemplate <class Impl> 5021060SN/Avoid 5031061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5041060SN/A{ 5051060SN/A // Make sure the instruction is valid 5061060SN/A assert(new_inst); 5071060SN/A 5082326SN/A DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n", 5092326SN/A new_inst->seqNum, new_inst->readPC()); 5101060SN/A 5111060SN/A assert(freeEntries != 0); 5121060SN/A 5132292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5141060SN/A 5152064SN/A --freeEntries; 5161060SN/A 5172292SN/A new_inst->setInIQ(); 5181060SN/A 5191060SN/A // Look through its source registers (physical regs), and mark any 5201060SN/A // dependencies. 5211060SN/A addToDependents(new_inst); 5221060SN/A 5231060SN/A // Have this instruction set itself as the producer of its destination 5241060SN/A // register(s). 5252326SN/A addToProducers(new_inst); 5261060SN/A 5271061SN/A if (new_inst->isMemRef()) { 5282292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5291062SN/A } else { 5301062SN/A addIfReady(new_inst); 5311061SN/A } 5321061SN/A 5331062SN/A ++iqInstsAdded; 5341060SN/A 5352292SN/A count[new_inst->threadNumber]++; 5362292SN/A 5371060SN/A assert(freeEntries == (numEntries - countInsts())); 5381060SN/A} 5391060SN/A 5401061SN/Atemplate <class Impl> 5411061SN/Avoid 5422292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5431061SN/A{ 5441061SN/A // @todo: Clean up this code; can do it by setting inst as unable 5451061SN/A // to issue, then calling normal insert on the inst. 5461061SN/A 5472292SN/A assert(new_inst); 5481061SN/A 5492292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 5501061SN/A 5512326SN/A DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x " 5522326SN/A "to the IQ.\n", 5532326SN/A new_inst->seqNum, new_inst->readPC()); 5542064SN/A 5551061SN/A assert(freeEntries != 0); 5561061SN/A 5572292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5581061SN/A 5592064SN/A --freeEntries; 5601061SN/A 5612292SN/A new_inst->setInIQ(); 5621061SN/A 5631061SN/A // Have this instruction set itself as the producer of its destination 5641061SN/A // register(s). 5652326SN/A addToProducers(new_inst); 5661061SN/A 5671061SN/A // If it's a memory instruction, add it to the memory dependency 5681061SN/A // unit. 5692292SN/A if (new_inst->isMemRef()) { 5702292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 5711061SN/A } 5721062SN/A 5731062SN/A ++iqNonSpecInstsAdded; 5742292SN/A 5752292SN/A count[new_inst->threadNumber]++; 5762292SN/A 5772292SN/A assert(freeEntries == (numEntries - countInsts())); 5781061SN/A} 5791061SN/A 5801061SN/Atemplate <class Impl> 5811060SN/Avoid 5822292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 5831060SN/A{ 5842292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 5851060SN/A 5862292SN/A insertNonSpec(barr_inst); 5872292SN/A} 5881060SN/A 5892064SN/Atemplate <class Impl> 5902333SN/Atypename Impl::DynInstPtr 5912333SN/AInstructionQueue<Impl>::getInstToExecute() 5922333SN/A{ 5932333SN/A assert(!instsToExecute.empty()); 5942333SN/A DynInstPtr inst = instsToExecute.front(); 5952333SN/A instsToExecute.pop_front(); 5962333SN/A return inst; 5972333SN/A} 5981060SN/A 5992333SN/Atemplate <class Impl> 6002064SN/Avoid 6012292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6022292SN/A{ 6032292SN/A assert(!readyInsts[op_class].empty()); 6042292SN/A 6052292SN/A ListOrderEntry queue_entry; 6062292SN/A 6072292SN/A queue_entry.queueType = op_class; 6082292SN/A 6092292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6102292SN/A 6112292SN/A ListOrderIt list_it = listOrder.begin(); 6122292SN/A ListOrderIt list_end_it = listOrder.end(); 6132292SN/A 6142292SN/A while (list_it != list_end_it) { 6152292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6162292SN/A break; 6172292SN/A } 6182292SN/A 6192292SN/A list_it++; 6201060SN/A } 6211060SN/A 6222292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6232292SN/A queueOnList[op_class] = true; 6242292SN/A} 6251060SN/A 6262292SN/Atemplate <class Impl> 6272292SN/Avoid 6282292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6292292SN/A{ 6302292SN/A // Get iterator of next item on the list 6312292SN/A // Delete the original iterator 6322292SN/A // Determine if the next item is either the end of the list or younger 6332292SN/A // than the new instruction. If so, then add in a new iterator right here. 6342292SN/A // If not, then move along. 6352292SN/A ListOrderEntry queue_entry; 6362292SN/A OpClass op_class = (*list_order_it).queueType; 6372292SN/A ListOrderIt next_it = list_order_it; 6382292SN/A 6392292SN/A ++next_it; 6402292SN/A 6412292SN/A queue_entry.queueType = op_class; 6422292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6432292SN/A 6442292SN/A while (next_it != listOrder.end() && 6452292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 6462292SN/A ++next_it; 6471060SN/A } 6481060SN/A 6492292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 6501060SN/A} 6511060SN/A 6522292SN/Atemplate <class Impl> 6532292SN/Avoid 6542292SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 6552292SN/A{ 6562367SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 6572292SN/A // The CPU could have been sleeping until this op completed (*extremely* 6582292SN/A // long latency op). Wake it if it was. This may be overkill. 6592307SN/A if (isSwitchedOut()) { 6602367SN/A DPRINTF(IQ, "FU completion not processed, IQ is switched out [sn:%lli]\n", 6612367SN/A inst->seqNum); 6622307SN/A return; 6632307SN/A } 6642307SN/A 6652292SN/A iewStage->wakeCPU(); 6662292SN/A 6672326SN/A if (fu_idx > -1) 6682326SN/A fuPool->freeUnitNextCycle(fu_idx); 6692292SN/A 6702326SN/A // @todo: Ensure that these FU Completions happen at the beginning 6712326SN/A // of a cycle, otherwise they could add too many instructions to 6722326SN/A // the queue. 6732333SN/A issueToExecuteQueue->access(0)->size++; 6742333SN/A instsToExecute.push_back(inst); 6752292SN/A} 6762292SN/A 6771061SN/A// @todo: Figure out a better way to remove the squashed items from the 6781061SN/A// lists. Checking the top item of each list to see if it's squashed 6791061SN/A// wastes time and forces jumps. 6801061SN/Atemplate <class Impl> 6811060SN/Avoid 6821060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 6831060SN/A{ 6842292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 6852292SN/A "the IQ.\n"); 6861060SN/A 6871060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 6881060SN/A 6892292SN/A // Have iterator to head of the list 6902292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 6912292SN/A // Try to get a FU that can do what this op needs. 6922292SN/A // If successful, change the oldestInst to the new top of the list, put 6932292SN/A // the queue in the proper place in the list. 6942292SN/A // Increment the iterator. 6952292SN/A // This will avoid trying to schedule a certain op class if there are no 6962292SN/A // FUs that handle it. 6972292SN/A ListOrderIt order_it = listOrder.begin(); 6982292SN/A ListOrderIt order_end_it = listOrder.end(); 6992292SN/A int total_issued = 0; 7001060SN/A 7012333SN/A while (total_issued < totalWidth && 7022820Sktlim@umich.edu iewStage->canIssue() && 7032326SN/A order_it != order_end_it) { 7042292SN/A OpClass op_class = (*order_it).queueType; 7051060SN/A 7062292SN/A assert(!readyInsts[op_class].empty()); 7071060SN/A 7082292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7091060SN/A 7102292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 7111060SN/A 7122292SN/A if (issuing_inst->isSquashed()) { 7132292SN/A readyInsts[op_class].pop(); 7141060SN/A 7152292SN/A if (!readyInsts[op_class].empty()) { 7162292SN/A moveToYoungerInst(order_it); 7172292SN/A } else { 7182292SN/A readyIt[op_class] = listOrder.end(); 7192292SN/A queueOnList[op_class] = false; 7201060SN/A } 7211060SN/A 7222292SN/A listOrder.erase(order_it++); 7231060SN/A 7242292SN/A ++iqSquashedInstsIssued; 7252292SN/A 7262292SN/A continue; 7271060SN/A } 7281060SN/A 7292326SN/A int idx = -2; 7302326SN/A int op_latency = 1; 7312301SN/A int tid = issuing_inst->threadNumber; 7321060SN/A 7332326SN/A if (op_class != No_OpClass) { 7342326SN/A idx = fuPool->getUnit(op_class); 7351060SN/A 7362326SN/A if (idx > -1) { 7372326SN/A op_latency = fuPool->getOpLatency(op_class); 7381060SN/A } 7391060SN/A } 7401060SN/A 7412348SN/A // If we have an instruction that doesn't require a FU, or a 7422348SN/A // valid FU, then schedule for execution. 7432326SN/A if (idx == -2 || idx != -1) { 7442292SN/A if (op_latency == 1) { 7452292SN/A i2e_info->size++; 7462333SN/A instsToExecute.push_back(issuing_inst); 7471060SN/A 7482326SN/A // Add the FU onto the list of FU's to be freed next 7492326SN/A // cycle if we used one. 7502326SN/A if (idx >= 0) 7512326SN/A fuPool->freeUnitNextCycle(idx); 7522292SN/A } else { 7532292SN/A int issue_latency = fuPool->getIssueLatency(op_class); 7542326SN/A // Generate completion event for the FU 7552326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 7562326SN/A idx, this); 7571060SN/A 7582326SN/A execution->schedule(curTick + cpu->cycles(issue_latency - 1)); 7591060SN/A 7602326SN/A // @todo: Enforce that issue_latency == 1 or op_latency 7612292SN/A if (issue_latency > 1) { 7622348SN/A // If FU isn't pipelined, then it must be freed 7632348SN/A // upon the execution completing. 7642326SN/A execution->setFreeFU(); 7652292SN/A } else { 7662292SN/A // Add the FU onto the list of FU's to be freed next cycle. 7672326SN/A fuPool->freeUnitNextCycle(idx); 7682292SN/A } 7691060SN/A } 7701060SN/A 7712292SN/A DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x " 7722292SN/A "[sn:%lli]\n", 7732301SN/A tid, issuing_inst->readPC(), 7742292SN/A issuing_inst->seqNum); 7751060SN/A 7762292SN/A readyInsts[op_class].pop(); 7771061SN/A 7782292SN/A if (!readyInsts[op_class].empty()) { 7792292SN/A moveToYoungerInst(order_it); 7802292SN/A } else { 7812292SN/A readyIt[op_class] = listOrder.end(); 7822292SN/A queueOnList[op_class] = false; 7831060SN/A } 7841060SN/A 7852064SN/A issuing_inst->setIssued(); 7862292SN/A ++total_issued; 7872064SN/A 7882292SN/A if (!issuing_inst->isMemRef()) { 7892292SN/A // Memory instructions can not be freed from the IQ until they 7902292SN/A // complete. 7912292SN/A ++freeEntries; 7922301SN/A count[tid]--; 7932731Sktlim@umich.edu issuing_inst->clearInIQ(); 7942292SN/A } else { 7952301SN/A memDepUnit[tid].issue(issuing_inst); 7962292SN/A } 7972292SN/A 7982292SN/A listOrder.erase(order_it++); 7992326SN/A statIssuedInstType[tid][op_class]++; 8002820Sktlim@umich.edu iewStage->incrWb(issuing_inst->seqNum); 8012292SN/A } else { 8022326SN/A statFuBusy[op_class]++; 8032326SN/A fuBusy[tid]++; 8042292SN/A ++order_it; 8051060SN/A } 8061060SN/A } 8071062SN/A 8082326SN/A numIssuedDist.sample(total_issued); 8092326SN/A iqInstsIssued+= total_issued; 8102307SN/A 8112348SN/A // If we issued any instructions, tell the CPU we had activity. 8122292SN/A if (total_issued) { 8132292SN/A cpu->activityThisCycle(); 8142292SN/A } else { 8152292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8162292SN/A } 8171060SN/A} 8181060SN/A 8191061SN/Atemplate <class Impl> 8201060SN/Avoid 8211061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 8221060SN/A{ 8232292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 8242292SN/A "to execute.\n", inst); 8251062SN/A 8262292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 8271060SN/A 8281061SN/A assert(inst_it != nonSpecInsts.end()); 8291060SN/A 8302292SN/A unsigned tid = (*inst_it).second->threadNumber; 8312292SN/A 8321061SN/A (*inst_it).second->setCanIssue(); 8331060SN/A 8341062SN/A if (!(*inst_it).second->isMemRef()) { 8351062SN/A addIfReady((*inst_it).second); 8361062SN/A } else { 8372292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 8381062SN/A } 8391060SN/A 8402292SN/A (*inst_it).second = NULL; 8412292SN/A 8421061SN/A nonSpecInsts.erase(inst_it); 8431060SN/A} 8441060SN/A 8451061SN/Atemplate <class Impl> 8461061SN/Avoid 8472292SN/AInstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid) 8482292SN/A{ 8492292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 8502292SN/A tid,inst); 8512292SN/A 8522292SN/A ListIt iq_it = instList[tid].begin(); 8532292SN/A 8542292SN/A while (iq_it != instList[tid].end() && 8552292SN/A (*iq_it)->seqNum <= inst) { 8562292SN/A ++iq_it; 8572292SN/A instList[tid].pop_front(); 8582292SN/A } 8592292SN/A 8602292SN/A assert(freeEntries == (numEntries - countInsts())); 8612292SN/A} 8622292SN/A 8632292SN/Atemplate <class Impl> 8642301SN/Aint 8651684SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 8661684SN/A{ 8672301SN/A int dependents = 0; 8682301SN/A 8692292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 8702292SN/A 8712292SN/A assert(!completed_inst->isSquashed()); 8721684SN/A 8731684SN/A // Tell the memory dependence unit to wake any dependents on this 8742292SN/A // instruction if it is a memory instruction. Also complete the memory 8752326SN/A // instruction at this point since we know it executed without issues. 8762326SN/A // @todo: Might want to rename "completeMemInst" to something that 8772326SN/A // indicates that it won't need to be replayed, and call this 8782326SN/A // earlier. Might not be a big deal. 8791684SN/A if (completed_inst->isMemRef()) { 8802292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 8812292SN/A completeMemInst(completed_inst); 8822292SN/A } else if (completed_inst->isMemBarrier() || 8832292SN/A completed_inst->isWriteBarrier()) { 8842292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 8851684SN/A } 8861684SN/A 8871684SN/A for (int dest_reg_idx = 0; 8881684SN/A dest_reg_idx < completed_inst->numDestRegs(); 8891684SN/A dest_reg_idx++) 8901684SN/A { 8911684SN/A PhysRegIndex dest_reg = 8921684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 8931684SN/A 8941684SN/A // Special case of uniq or control registers. They are not 8951684SN/A // handled by the IQ and thus have no dependency graph entry. 8961684SN/A // @todo Figure out a cleaner way to handle this. 8971684SN/A if (dest_reg >= numPhysRegs) { 8981684SN/A continue; 8991684SN/A } 9001684SN/A 9012292SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 9021684SN/A (int) dest_reg); 9031684SN/A 9042326SN/A //Go through the dependency chain, marking the registers as 9052326SN/A //ready within the waiting instructions. 9062326SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg); 9071684SN/A 9082326SN/A while (dep_inst) { 9092292SN/A DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n", 9102326SN/A dep_inst->readPC()); 9111684SN/A 9121684SN/A // Might want to give more information to the instruction 9132326SN/A // so that it knows which of its source registers is 9142326SN/A // ready. However that would mean that the dependency 9152326SN/A // graph entries would need to hold the src_reg_idx. 9162326SN/A dep_inst->markSrcRegReady(); 9171684SN/A 9182326SN/A addIfReady(dep_inst); 9191684SN/A 9202326SN/A dep_inst = dependGraph.pop(dest_reg); 9211684SN/A 9222301SN/A ++dependents; 9231684SN/A } 9241684SN/A 9252326SN/A // Reset the head node now that all of its dependents have 9262326SN/A // been woken up. 9272326SN/A assert(dependGraph.empty(dest_reg)); 9282326SN/A dependGraph.clearInst(dest_reg); 9291684SN/A 9301684SN/A // Mark the scoreboard as having that register ready. 9311684SN/A regScoreboard[dest_reg] = true; 9321684SN/A } 9332301SN/A return dependents; 9342064SN/A} 9352064SN/A 9362064SN/Atemplate <class Impl> 9372064SN/Avoid 9382292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 9392064SN/A{ 9402292SN/A OpClass op_class = ready_inst->opClass(); 9412292SN/A 9422292SN/A readyInsts[op_class].push(ready_inst); 9432292SN/A 9442326SN/A // Will need to reorder the list if either a queue is not on the list, 9452326SN/A // or it has an older instruction than last time. 9462326SN/A if (!queueOnList[op_class]) { 9472326SN/A addToOrderList(op_class); 9482326SN/A } else if (readyInsts[op_class].top()->seqNum < 9492326SN/A (*readyIt[op_class]).oldestInst) { 9502326SN/A listOrder.erase(readyIt[op_class]); 9512326SN/A addToOrderList(op_class); 9522326SN/A } 9532326SN/A 9542292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 9552292SN/A "the ready list, PC %#x opclass:%i [sn:%lli].\n", 9562292SN/A ready_inst->readPC(), op_class, ready_inst->seqNum); 9572064SN/A} 9582064SN/A 9592064SN/Atemplate <class Impl> 9602064SN/Avoid 9612292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 9622064SN/A{ 9632292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 9642064SN/A} 9652064SN/A 9662064SN/Atemplate <class Impl> 9672064SN/Avoid 9682292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 9692064SN/A{ 9702292SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 9712292SN/A} 9722292SN/A 9732292SN/Atemplate <class Impl> 9742292SN/Avoid 9752292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 9762292SN/A{ 9772292SN/A int tid = completed_inst->threadNumber; 9782292SN/A 9792292SN/A DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n", 9802292SN/A completed_inst->readPC(), completed_inst->seqNum); 9812292SN/A 9822292SN/A ++freeEntries; 9832292SN/A 9842292SN/A completed_inst->memOpDone = true; 9852292SN/A 9862292SN/A memDepUnit[tid].completed(completed_inst); 9872292SN/A 9882292SN/A count[tid]--; 9891684SN/A} 9901684SN/A 9911684SN/Atemplate <class Impl> 9921684SN/Avoid 9931061SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 9941061SN/A DynInstPtr &faulting_load) 9951061SN/A{ 9962292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 9971061SN/A} 9981061SN/A 9991061SN/Atemplate <class Impl> 10001060SN/Avoid 10012292SN/AInstructionQueue<Impl>::squash(unsigned tid) 10021060SN/A{ 10032292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 10042292SN/A "the IQ.\n", tid); 10051060SN/A 10061060SN/A // Read instruction sequence number of last instruction out of the 10071060SN/A // time buffer. 10083093Sksewell@umich.edu#if ISA_HAS_DELAY_SLOT 10093093Sksewell@umich.edu squashedSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 10103093Sksewell@umich.edu#else 10112292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 10122935Sksewell@umich.edu#endif 10131060SN/A 10141681SN/A // Call doSquash if there are insts in the IQ 10152292SN/A if (count[tid] > 0) { 10162292SN/A doSquash(tid); 10171681SN/A } 10181061SN/A 10191061SN/A // Also tell the memory dependence unit to squash. 10202292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 10211060SN/A} 10221060SN/A 10231061SN/Atemplate <class Impl> 10241061SN/Avoid 10252292SN/AInstructionQueue<Impl>::doSquash(unsigned tid) 10261061SN/A{ 10272326SN/A // Start at the tail. 10282326SN/A ListIt squash_it = instList[tid].end(); 10292326SN/A --squash_it; 10301061SN/A 10312292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 10322292SN/A tid, squashedSeqNum[tid]); 10331061SN/A 10341061SN/A // Squash any instructions younger than the squashed sequence number 10351061SN/A // given. 10362326SN/A while (squash_it != instList[tid].end() && 10372326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 10382292SN/A 10392326SN/A DynInstPtr squashed_inst = (*squash_it); 10401061SN/A 10411061SN/A // Only handle the instruction if it actually is in the IQ and 10421061SN/A // hasn't already been squashed in the IQ. 10432292SN/A if (squashed_inst->threadNumber != tid || 10442292SN/A squashed_inst->isSquashedInIQ()) { 10452326SN/A --squash_it; 10462292SN/A continue; 10472292SN/A } 10482292SN/A 10492292SN/A if (!squashed_inst->isIssued() || 10502292SN/A (squashed_inst->isMemRef() && 10512292SN/A !squashed_inst->memOpDone)) { 10521062SN/A 10532367SN/A DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x " 10542367SN/A "squashed.\n", 10552367SN/A tid, squashed_inst->seqNum, squashed_inst->readPC()); 10562367SN/A 10571061SN/A // Remove the instruction from the dependency list. 10582292SN/A if (!squashed_inst->isNonSpeculative() && 10592336SN/A !squashed_inst->isStoreConditional() && 10602292SN/A !squashed_inst->isMemBarrier() && 10612292SN/A !squashed_inst->isWriteBarrier()) { 10621061SN/A 10631061SN/A for (int src_reg_idx = 0; 10641681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 10651061SN/A src_reg_idx++) 10661061SN/A { 10671061SN/A PhysRegIndex src_reg = 10681061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 10691061SN/A 10702326SN/A // Only remove it from the dependency graph if it 10712326SN/A // was placed there in the first place. 10722326SN/A 10732326SN/A // Instead of doing a linked list traversal, we 10742326SN/A // can just remove these squashed instructions 10752326SN/A // either at issue time, or when the register is 10762326SN/A // overwritten. The only downside to this is it 10772326SN/A // leaves more room for error. 10782292SN/A 10791061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 10801061SN/A src_reg < numPhysRegs) { 10812326SN/A dependGraph.remove(src_reg, squashed_inst); 10821061SN/A } 10831062SN/A 10842292SN/A 10851062SN/A ++iqSquashedOperandsExamined; 10861061SN/A } 10872367SN/A } else if (!squashed_inst->isStoreConditional() || !squashed_inst->isCompleted()) { 10882292SN/A NonSpecMapIt ns_inst_it = 10892292SN/A nonSpecInsts.find(squashed_inst->seqNum); 10902292SN/A assert(ns_inst_it != nonSpecInsts.end()); 10911062SN/A 10922292SN/A (*ns_inst_it).second = NULL; 10931681SN/A 10942292SN/A nonSpecInsts.erase(ns_inst_it); 10951062SN/A 10961062SN/A ++iqSquashedNonSpecRemoved; 10971061SN/A } 10981061SN/A 10991061SN/A // Might want to also clear out the head of the dependency graph. 11001061SN/A 11011061SN/A // Mark it as squashed within the IQ. 11021061SN/A squashed_inst->setSquashedInIQ(); 11031061SN/A 11042292SN/A // @todo: Remove this hack where several statuses are set so the 11052292SN/A // inst will flow through the rest of the pipeline. 11061681SN/A squashed_inst->setIssued(); 11071681SN/A squashed_inst->setCanCommit(); 11082731Sktlim@umich.edu squashed_inst->clearInIQ(); 11092292SN/A 11102292SN/A //Update Thread IQ Count 11112292SN/A count[squashed_inst->threadNumber]--; 11121681SN/A 11131681SN/A ++freeEntries; 11141061SN/A } 11151061SN/A 11162326SN/A instList[tid].erase(squash_it--); 11171062SN/A ++iqSquashedInstsExamined; 11181061SN/A } 11191060SN/A} 11201060SN/A 11211061SN/Atemplate <class Impl> 11221060SN/Abool 11231061SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 11241060SN/A{ 11251060SN/A // Loop through the instruction's source registers, adding 11261060SN/A // them to the dependency list if they are not ready. 11271060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 11281060SN/A bool return_val = false; 11291060SN/A 11301060SN/A for (int src_reg_idx = 0; 11311060SN/A src_reg_idx < total_src_regs; 11321060SN/A src_reg_idx++) 11331060SN/A { 11341060SN/A // Only add it to the dependency graph if it's not ready. 11351060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 11361060SN/A PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 11371060SN/A 11381060SN/A // Check the IQ's scoreboard to make sure the register 11391060SN/A // hasn't become ready while the instruction was in flight 11401060SN/A // between stages. Only if it really isn't ready should 11411060SN/A // it be added to the dependency graph. 11421061SN/A if (src_reg >= numPhysRegs) { 11431061SN/A continue; 11441061SN/A } else if (regScoreboard[src_reg] == false) { 11452292SN/A DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 11461060SN/A "is being added to the dependency chain.\n", 11471060SN/A new_inst->readPC(), src_reg); 11481060SN/A 11492326SN/A dependGraph.insert(src_reg, new_inst); 11501060SN/A 11511060SN/A // Change the return value to indicate that something 11521060SN/A // was added to the dependency graph. 11531060SN/A return_val = true; 11541060SN/A } else { 11552292SN/A DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 11561060SN/A "became ready before it reached the IQ.\n", 11571060SN/A new_inst->readPC(), src_reg); 11581060SN/A // Mark a register ready within the instruction. 11592326SN/A new_inst->markSrcRegReady(src_reg_idx); 11601060SN/A } 11611060SN/A } 11621060SN/A } 11631060SN/A 11641060SN/A return return_val; 11651060SN/A} 11661060SN/A 11671061SN/Atemplate <class Impl> 11681060SN/Avoid 11692326SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 11701060SN/A{ 11712326SN/A // Nothing really needs to be marked when an instruction becomes 11722326SN/A // the producer of a register's value, but for convenience a ptr 11732326SN/A // to the producing instruction will be placed in the head node of 11742326SN/A // the dependency links. 11751060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 11761060SN/A 11771060SN/A for (int dest_reg_idx = 0; 11781060SN/A dest_reg_idx < total_dest_regs; 11791060SN/A dest_reg_idx++) 11801060SN/A { 11811061SN/A PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 11821061SN/A 11831061SN/A // Instructions that use the misc regs will have a reg number 11841061SN/A // higher than the normal physical registers. In this case these 11851061SN/A // registers are not renamed, and there is no need to track 11861061SN/A // dependencies as these instructions must be executed at commit. 11871061SN/A if (dest_reg >= numPhysRegs) { 11881061SN/A continue; 11891060SN/A } 11901060SN/A 11912326SN/A if (!dependGraph.empty(dest_reg)) { 11922326SN/A dependGraph.dump(); 11932292SN/A panic("Dependency graph %i not empty!", dest_reg); 11942064SN/A } 11951062SN/A 11962326SN/A dependGraph.setInst(dest_reg, new_inst); 11971062SN/A 11981060SN/A // Mark the scoreboard to say it's not yet ready. 11991060SN/A regScoreboard[dest_reg] = false; 12001060SN/A } 12011060SN/A} 12021060SN/A 12031061SN/Atemplate <class Impl> 12041060SN/Avoid 12051061SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 12061060SN/A{ 12072326SN/A // If the instruction now has all of its source registers 12081060SN/A // available, then add it to the list of ready instructions. 12091060SN/A if (inst->readyToIssue()) { 12101061SN/A 12111060SN/A //Add the instruction to the proper ready list. 12122292SN/A if (inst->isMemRef()) { 12131061SN/A 12142292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 12151061SN/A 12161062SN/A // Message to the mem dependence unit that this instruction has 12171062SN/A // its registers ready. 12182292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 12191062SN/A 12202292SN/A return; 12212292SN/A } 12221062SN/A 12232292SN/A OpClass op_class = inst->opClass(); 12241061SN/A 12252292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 12262292SN/A "the ready list, PC %#x opclass:%i [sn:%lli].\n", 12272292SN/A inst->readPC(), op_class, inst->seqNum); 12281061SN/A 12292292SN/A readyInsts[op_class].push(inst); 12301061SN/A 12312326SN/A // Will need to reorder the list if either a queue is not on the list, 12322326SN/A // or it has an older instruction than last time. 12332326SN/A if (!queueOnList[op_class]) { 12342326SN/A addToOrderList(op_class); 12352326SN/A } else if (readyInsts[op_class].top()->seqNum < 12362326SN/A (*readyIt[op_class]).oldestInst) { 12372326SN/A listOrder.erase(readyIt[op_class]); 12382326SN/A addToOrderList(op_class); 12391060SN/A } 12401060SN/A } 12411060SN/A} 12421060SN/A 12431061SN/Atemplate <class Impl> 12441061SN/Aint 12451061SN/AInstructionQueue<Impl>::countInsts() 12461061SN/A{ 12472698Sktlim@umich.edu#if 0 12482292SN/A //ksewell:This works but definitely could use a cleaner write 12492292SN/A //with a more intuitive way of counting. Right now it's 12502292SN/A //just brute force .... 12512698Sktlim@umich.edu // Change the #if if you want to use this method. 12521061SN/A int total_insts = 0; 12531061SN/A 12542292SN/A for (int i = 0; i < numThreads; ++i) { 12552292SN/A ListIt count_it = instList[i].begin(); 12561681SN/A 12572292SN/A while (count_it != instList[i].end()) { 12582292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 12592292SN/A if (!(*count_it)->isIssued()) { 12602292SN/A ++total_insts; 12612292SN/A } else if ((*count_it)->isMemRef() && 12622292SN/A !(*count_it)->memOpDone) { 12632292SN/A // Loads that have not been marked as executed still count 12642292SN/A // towards the total instructions. 12652292SN/A ++total_insts; 12662292SN/A } 12672292SN/A } 12682292SN/A 12692292SN/A ++count_it; 12701061SN/A } 12711061SN/A } 12721061SN/A 12731061SN/A return total_insts; 12742292SN/A#else 12752292SN/A return numEntries - freeEntries; 12762292SN/A#endif 12771681SN/A} 12781681SN/A 12791681SN/Atemplate <class Impl> 12801681SN/Avoid 12811061SN/AInstructionQueue<Impl>::dumpLists() 12821061SN/A{ 12832292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 12842292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 12851061SN/A 12862292SN/A cprintf("\n"); 12872292SN/A } 12881061SN/A 12891061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 12901061SN/A 12912292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 12922292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 12931061SN/A 12941061SN/A cprintf("Non speculative list: "); 12951061SN/A 12962292SN/A while (non_spec_it != non_spec_end_it) { 12972292SN/A cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(), 12982292SN/A (*non_spec_it).second->seqNum); 12991061SN/A ++non_spec_it; 13001061SN/A } 13011061SN/A 13021061SN/A cprintf("\n"); 13031061SN/A 13042292SN/A ListOrderIt list_order_it = listOrder.begin(); 13052292SN/A ListOrderIt list_order_end_it = listOrder.end(); 13062292SN/A int i = 1; 13072292SN/A 13082292SN/A cprintf("List order: "); 13092292SN/A 13102292SN/A while (list_order_it != list_order_end_it) { 13112292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 13122292SN/A (*list_order_it).oldestInst); 13132292SN/A 13142292SN/A ++list_order_it; 13152292SN/A ++i; 13162292SN/A } 13172292SN/A 13182292SN/A cprintf("\n"); 13191061SN/A} 13202292SN/A 13212292SN/A 13222292SN/Atemplate <class Impl> 13232292SN/Avoid 13242292SN/AInstructionQueue<Impl>::dumpInsts() 13252292SN/A{ 13262292SN/A for (int i = 0; i < numThreads; ++i) { 13272292SN/A int num = 0; 13282292SN/A int valid_num = 0; 13292292SN/A ListIt inst_list_it = instList[i].begin(); 13302292SN/A 13312292SN/A while (inst_list_it != instList[i].end()) 13322292SN/A { 13332292SN/A cprintf("Instruction:%i\n", 13342292SN/A num); 13352292SN/A if (!(*inst_list_it)->isSquashed()) { 13362292SN/A if (!(*inst_list_it)->isIssued()) { 13372292SN/A ++valid_num; 13382292SN/A cprintf("Count:%i\n", valid_num); 13392292SN/A } else if ((*inst_list_it)->isMemRef() && 13402292SN/A !(*inst_list_it)->memOpDone) { 13412326SN/A // Loads that have not been marked as executed 13422326SN/A // still count towards the total instructions. 13432292SN/A ++valid_num; 13442292SN/A cprintf("Count:%i\n", valid_num); 13452292SN/A } 13462292SN/A } 13472292SN/A 13482292SN/A cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 13492292SN/A "Issued:%i\nSquashed:%i\n", 13502292SN/A (*inst_list_it)->readPC(), 13512292SN/A (*inst_list_it)->seqNum, 13522292SN/A (*inst_list_it)->threadNumber, 13532292SN/A (*inst_list_it)->isIssued(), 13542292SN/A (*inst_list_it)->isSquashed()); 13552292SN/A 13562292SN/A if ((*inst_list_it)->isMemRef()) { 13572292SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 13582292SN/A } 13592292SN/A 13602292SN/A cprintf("\n"); 13612292SN/A 13622292SN/A inst_list_it++; 13632292SN/A ++num; 13642292SN/A } 13652292SN/A } 13662348SN/A 13672348SN/A cprintf("Insts to Execute list:\n"); 13682348SN/A 13692348SN/A int num = 0; 13702348SN/A int valid_num = 0; 13712348SN/A ListIt inst_list_it = instsToExecute.begin(); 13722348SN/A 13732348SN/A while (inst_list_it != instsToExecute.end()) 13742348SN/A { 13752348SN/A cprintf("Instruction:%i\n", 13762348SN/A num); 13772348SN/A if (!(*inst_list_it)->isSquashed()) { 13782348SN/A if (!(*inst_list_it)->isIssued()) { 13792348SN/A ++valid_num; 13802348SN/A cprintf("Count:%i\n", valid_num); 13812348SN/A } else if ((*inst_list_it)->isMemRef() && 13822348SN/A !(*inst_list_it)->memOpDone) { 13832348SN/A // Loads that have not been marked as executed 13842348SN/A // still count towards the total instructions. 13852348SN/A ++valid_num; 13862348SN/A cprintf("Count:%i\n", valid_num); 13872348SN/A } 13882348SN/A } 13892348SN/A 13902348SN/A cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 13912348SN/A "Issued:%i\nSquashed:%i\n", 13922348SN/A (*inst_list_it)->readPC(), 13932348SN/A (*inst_list_it)->seqNum, 13942348SN/A (*inst_list_it)->threadNumber, 13952348SN/A (*inst_list_it)->isIssued(), 13962348SN/A (*inst_list_it)->isSquashed()); 13972348SN/A 13982348SN/A if ((*inst_list_it)->isMemRef()) { 13992348SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 14002348SN/A } 14012348SN/A 14022348SN/A cprintf("\n"); 14032348SN/A 14042348SN/A inst_list_it++; 14052348SN/A ++num; 14062348SN/A } 14072292SN/A} 1408