inst_queue_impl.hh revision 2669
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 271689SN/A */ 281689SN/A 292064SN/A#include <limits> 301060SN/A#include <vector> 311060SN/A 321696SN/A#include "sim/root.hh" 331689SN/A 342292SN/A#include "cpu/o3/fu_pool.hh" 351717SN/A#include "cpu/o3/inst_queue.hh" 361060SN/A 372292SN/Ausing namespace std; 381060SN/A 391061SN/Atemplate <class Impl> 402292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 412292SN/A int fu_idx, 422292SN/A InstructionQueue<Impl> *iq_ptr) 432292SN/A : Event(&mainEventQueue, Stat_Event_Pri), 442326SN/A inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 451060SN/A{ 462292SN/A this->setFlags(Event::AutoDelete); 472292SN/A} 482292SN/A 492292SN/Atemplate <class Impl> 502292SN/Avoid 512292SN/AInstructionQueue<Impl>::FUCompletion::process() 522292SN/A{ 532326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 542292SN/A inst = NULL; 552292SN/A} 562292SN/A 572292SN/A 582292SN/Atemplate <class Impl> 592292SN/Aconst char * 602292SN/AInstructionQueue<Impl>::FUCompletion::description() 612292SN/A{ 622292SN/A return "Functional unit completion event"; 632292SN/A} 642292SN/A 652292SN/Atemplate <class Impl> 662292SN/AInstructionQueue<Impl>::InstructionQueue(Params *params) 672669Sktlim@umich.edu : fuPool(params->fuPool), 682292SN/A numEntries(params->numIQEntries), 692292SN/A totalWidth(params->issueWidth), 702292SN/A numPhysIntRegs(params->numPhysIntRegs), 712292SN/A numPhysFloatRegs(params->numPhysFloatRegs), 722292SN/A commitToIEWDelay(params->commitToIEWDelay) 732292SN/A{ 742292SN/A assert(fuPool); 752292SN/A 762307SN/A switchedOut = false; 772307SN/A 782292SN/A numThreads = params->numberOfThreads; 791060SN/A 801060SN/A // Set the number of physical registers as the number of int + float 811060SN/A numPhysRegs = numPhysIntRegs + numPhysFloatRegs; 821060SN/A 832292SN/A DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs); 841060SN/A 851060SN/A //Create an entry for each physical register within the 861060SN/A //dependency graph. 872326SN/A dependGraph.resize(numPhysRegs); 881060SN/A 891060SN/A // Resize the register scoreboard. 901060SN/A regScoreboard.resize(numPhysRegs); 911060SN/A 922292SN/A //Initialize Mem Dependence Units 932292SN/A for (int i = 0; i < numThreads; i++) { 942292SN/A memDepUnit[i].init(params,i); 952292SN/A memDepUnit[i].setIQ(this); 961060SN/A } 971060SN/A 982307SN/A resetState(); 992292SN/A 1002292SN/A string policy = params->smtIQPolicy; 1012292SN/A 1022292SN/A //Convert string to lowercase 1032292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1042292SN/A (int(*)(int)) tolower); 1052292SN/A 1062292SN/A //Figure out resource sharing policy 1072292SN/A if (policy == "dynamic") { 1082292SN/A iqPolicy = Dynamic; 1092292SN/A 1102292SN/A //Set Max Entries to Total ROB Capacity 1112292SN/A for (int i = 0; i < numThreads; i++) { 1122292SN/A maxEntries[i] = numEntries; 1132292SN/A } 1142292SN/A 1152292SN/A } else if (policy == "partitioned") { 1162292SN/A iqPolicy = Partitioned; 1172292SN/A 1182292SN/A //@todo:make work if part_amt doesnt divide evenly. 1192292SN/A int part_amt = numEntries / numThreads; 1202292SN/A 1212292SN/A //Divide ROB up evenly 1222292SN/A for (int i = 0; i < numThreads; i++) { 1232292SN/A maxEntries[i] = part_amt; 1242292SN/A } 1252292SN/A 1262292SN/A DPRINTF(Fetch, "IQ sharing policy set to Partitioned:" 1272292SN/A "%i entries per thread.\n",part_amt); 1282292SN/A 1292292SN/A } else if (policy == "threshold") { 1302292SN/A iqPolicy = Threshold; 1312292SN/A 1322292SN/A double threshold = (double)params->smtIQThreshold / 100; 1332292SN/A 1342292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1352292SN/A 1362292SN/A //Divide up by threshold amount 1372292SN/A for (int i = 0; i < numThreads; i++) { 1382292SN/A maxEntries[i] = thresholdIQ; 1392292SN/A } 1402292SN/A 1412292SN/A DPRINTF(Fetch, "IQ sharing policy set to Threshold:" 1422292SN/A "%i entries per thread.\n",thresholdIQ); 1432292SN/A } else { 1442292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1452292SN/A "Partitioned, Threshold}"); 1462292SN/A } 1472292SN/A} 1482292SN/A 1492292SN/Atemplate <class Impl> 1502292SN/AInstructionQueue<Impl>::~InstructionQueue() 1512292SN/A{ 1522326SN/A dependGraph.reset(); 1532326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1542326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1552292SN/A} 1562292SN/A 1572292SN/Atemplate <class Impl> 1582292SN/Astd::string 1592292SN/AInstructionQueue<Impl>::name() const 1602292SN/A{ 1612292SN/A return cpu->name() + ".iq"; 1621060SN/A} 1631060SN/A 1641061SN/Atemplate <class Impl> 1651060SN/Avoid 1661062SN/AInstructionQueue<Impl>::regStats() 1671062SN/A{ 1682301SN/A using namespace Stats; 1691062SN/A iqInstsAdded 1701062SN/A .name(name() + ".iqInstsAdded") 1711062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1721062SN/A .prereq(iqInstsAdded); 1731062SN/A 1741062SN/A iqNonSpecInstsAdded 1751062SN/A .name(name() + ".iqNonSpecInstsAdded") 1761062SN/A .desc("Number of non-speculative instructions added to the IQ") 1771062SN/A .prereq(iqNonSpecInstsAdded); 1781062SN/A 1792301SN/A iqInstsIssued 1802301SN/A .name(name() + ".iqInstsIssued") 1812301SN/A .desc("Number of instructions issued") 1822301SN/A .prereq(iqInstsIssued); 1831062SN/A 1841062SN/A iqIntInstsIssued 1851062SN/A .name(name() + ".iqIntInstsIssued") 1861062SN/A .desc("Number of integer instructions issued") 1871062SN/A .prereq(iqIntInstsIssued); 1881062SN/A 1891062SN/A iqFloatInstsIssued 1901062SN/A .name(name() + ".iqFloatInstsIssued") 1911062SN/A .desc("Number of float instructions issued") 1921062SN/A .prereq(iqFloatInstsIssued); 1931062SN/A 1941062SN/A iqBranchInstsIssued 1951062SN/A .name(name() + ".iqBranchInstsIssued") 1961062SN/A .desc("Number of branch instructions issued") 1971062SN/A .prereq(iqBranchInstsIssued); 1981062SN/A 1991062SN/A iqMemInstsIssued 2001062SN/A .name(name() + ".iqMemInstsIssued") 2011062SN/A .desc("Number of memory instructions issued") 2021062SN/A .prereq(iqMemInstsIssued); 2031062SN/A 2041062SN/A iqMiscInstsIssued 2051062SN/A .name(name() + ".iqMiscInstsIssued") 2061062SN/A .desc("Number of miscellaneous instructions issued") 2071062SN/A .prereq(iqMiscInstsIssued); 2081062SN/A 2091062SN/A iqSquashedInstsIssued 2101062SN/A .name(name() + ".iqSquashedInstsIssued") 2111062SN/A .desc("Number of squashed instructions issued") 2121062SN/A .prereq(iqSquashedInstsIssued); 2131062SN/A 2141062SN/A iqSquashedInstsExamined 2151062SN/A .name(name() + ".iqSquashedInstsExamined") 2161062SN/A .desc("Number of squashed instructions iterated over during squash;" 2171062SN/A " mainly for profiling") 2181062SN/A .prereq(iqSquashedInstsExamined); 2191062SN/A 2201062SN/A iqSquashedOperandsExamined 2211062SN/A .name(name() + ".iqSquashedOperandsExamined") 2221062SN/A .desc("Number of squashed operands that are examined and possibly " 2231062SN/A "removed from graph") 2241062SN/A .prereq(iqSquashedOperandsExamined); 2251062SN/A 2261062SN/A iqSquashedNonSpecRemoved 2271062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2281062SN/A .desc("Number of squashed non-spec instructions that were removed") 2291062SN/A .prereq(iqSquashedNonSpecRemoved); 2301062SN/A 2312326SN/A queueResDist 2322301SN/A .init(Num_OpClasses, 0, 99, 2) 2332301SN/A .name(name() + ".IQ:residence:") 2342301SN/A .desc("cycles from dispatch to issue") 2352301SN/A .flags(total | pdf | cdf ) 2362301SN/A ; 2372301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2382326SN/A queueResDist.subname(i, opClassStrings[i]); 2392301SN/A } 2402326SN/A numIssuedDist 2412307SN/A .init(0,totalWidth,1) 2422301SN/A .name(name() + ".ISSUE:issued_per_cycle") 2432301SN/A .desc("Number of insts issued each cycle") 2442307SN/A .flags(pdf) 2452301SN/A ; 2462301SN/A/* 2472301SN/A dist_unissued 2482301SN/A .init(Num_OpClasses+2) 2492301SN/A .name(name() + ".ISSUE:unissued_cause") 2502301SN/A .desc("Reason ready instruction not issued") 2512301SN/A .flags(pdf | dist) 2522301SN/A ; 2532301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2542301SN/A dist_unissued.subname(i, unissued_names[i]); 2552301SN/A } 2562301SN/A*/ 2572326SN/A statIssuedInstType 2582301SN/A .init(numThreads,Num_OpClasses) 2592301SN/A .name(name() + ".ISSUE:FU_type") 2602301SN/A .desc("Type of FU issued") 2612301SN/A .flags(total | pdf | dist) 2622301SN/A ; 2632326SN/A statIssuedInstType.ysubnames(opClassStrings); 2642301SN/A 2652301SN/A // 2662301SN/A // How long did instructions for a particular FU type wait prior to issue 2672301SN/A // 2682301SN/A 2692326SN/A issueDelayDist 2702301SN/A .init(Num_OpClasses,0,99,2) 2712301SN/A .name(name() + ".ISSUE:") 2722301SN/A .desc("cycles from operands ready to issue") 2732301SN/A .flags(pdf | cdf) 2742301SN/A ; 2752301SN/A 2762301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2772301SN/A stringstream subname; 2782301SN/A subname << opClassStrings[i] << "_delay"; 2792326SN/A issueDelayDist.subname(i, subname.str()); 2802301SN/A } 2812301SN/A 2822326SN/A issueRate 2832301SN/A .name(name() + ".ISSUE:rate") 2842301SN/A .desc("Inst issue rate") 2852301SN/A .flags(total) 2862301SN/A ; 2872326SN/A issueRate = iqInstsIssued / cpu->numCycles; 2882301SN/A/* 2892301SN/A issue_stores 2902301SN/A .name(name() + ".ISSUE:stores") 2912301SN/A .desc("Number of stores issued") 2922301SN/A .flags(total) 2932301SN/A ; 2942301SN/A issue_stores = exe_refs - exe_loads; 2952301SN/A*/ 2962301SN/A/* 2972301SN/A issue_op_rate 2982301SN/A .name(name() + ".ISSUE:op_rate") 2992301SN/A .desc("Operation issue rate") 3002301SN/A .flags(total) 3012301SN/A ; 3022301SN/A issue_op_rate = issued_ops / numCycles; 3032301SN/A*/ 3042326SN/A statFuBusy 3052301SN/A .init(Num_OpClasses) 3062301SN/A .name(name() + ".ISSUE:fu_full") 3072301SN/A .desc("attempts to use FU when none available") 3082301SN/A .flags(pdf | dist) 3092301SN/A ; 3102301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3112326SN/A statFuBusy.subname(i, opClassStrings[i]); 3122301SN/A } 3132301SN/A 3142326SN/A fuBusy 3152301SN/A .init(numThreads) 3162301SN/A .name(name() + ".ISSUE:fu_busy_cnt") 3172301SN/A .desc("FU busy when requested") 3182301SN/A .flags(total) 3192301SN/A ; 3202301SN/A 3212326SN/A fuBusyRate 3222301SN/A .name(name() + ".ISSUE:fu_busy_rate") 3232301SN/A .desc("FU busy rate (busy events/executed inst)") 3242301SN/A .flags(total) 3252301SN/A ; 3262326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3272301SN/A 3282292SN/A for ( int i=0; i < numThreads; i++) { 3292292SN/A // Tell mem dependence unit to reg stats as well. 3302292SN/A memDepUnit[i].regStats(); 3312292SN/A } 3321062SN/A} 3331062SN/A 3341062SN/Atemplate <class Impl> 3351062SN/Avoid 3362307SN/AInstructionQueue<Impl>::resetState() 3371060SN/A{ 3382307SN/A //Initialize thread IQ counts 3392307SN/A for (int i = 0; i <numThreads; i++) { 3402307SN/A count[i] = 0; 3412307SN/A instList[i].clear(); 3422307SN/A } 3431060SN/A 3442307SN/A // Initialize the number of free IQ entries. 3452307SN/A freeEntries = numEntries; 3462307SN/A 3472307SN/A // Note that in actuality, the registers corresponding to the logical 3482307SN/A // registers start off as ready. However this doesn't matter for the 3492307SN/A // IQ as the instruction should have been correctly told if those 3502307SN/A // registers are ready in rename. Thus it can all be initialized as 3512307SN/A // unready. 3522307SN/A for (int i = 0; i < numPhysRegs; ++i) { 3532307SN/A regScoreboard[i] = false; 3542307SN/A } 3552307SN/A 3562307SN/A for (int i = 0; i < numThreads; ++i) { 3572307SN/A squashedSeqNum[i] = 0; 3582307SN/A } 3592307SN/A 3602307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 3612307SN/A while (!readyInsts[i].empty()) 3622307SN/A readyInsts[i].pop(); 3632307SN/A queueOnList[i] = false; 3642307SN/A readyIt[i] = listOrder.end(); 3652307SN/A } 3662307SN/A nonSpecInsts.clear(); 3672307SN/A listOrder.clear(); 3681060SN/A} 3691060SN/A 3701061SN/Atemplate <class Impl> 3711060SN/Avoid 3722292SN/AInstructionQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr) 3731060SN/A{ 3742292SN/A DPRINTF(IQ, "Setting active threads list pointer.\n"); 3752292SN/A activeThreads = at_ptr; 3762064SN/A} 3772064SN/A 3782064SN/Atemplate <class Impl> 3792064SN/Avoid 3802292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 3812064SN/A{ 3822292SN/A DPRINTF(IQ, "Set the issue to execute queue.\n"); 3831060SN/A issueToExecuteQueue = i2e_ptr; 3841060SN/A} 3851060SN/A 3861061SN/Atemplate <class Impl> 3871060SN/Avoid 3881060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3891060SN/A{ 3902292SN/A DPRINTF(IQ, "Set the time buffer.\n"); 3911060SN/A timeBuffer = tb_ptr; 3921060SN/A 3931060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3941060SN/A} 3951060SN/A 3961684SN/Atemplate <class Impl> 3972307SN/Avoid 3982307SN/AInstructionQueue<Impl>::switchOut() 3992307SN/A{ 4002307SN/A resetState(); 4012326SN/A dependGraph.reset(); 4022307SN/A switchedOut = true; 4032307SN/A for (int i = 0; i < numThreads; ++i) { 4042307SN/A memDepUnit[i].switchOut(); 4052307SN/A } 4062307SN/A} 4072307SN/A 4082307SN/Atemplate <class Impl> 4092307SN/Avoid 4102307SN/AInstructionQueue<Impl>::takeOverFrom() 4112307SN/A{ 4122307SN/A switchedOut = false; 4132307SN/A} 4142307SN/A 4152307SN/Atemplate <class Impl> 4162292SN/Aint 4172292SN/AInstructionQueue<Impl>::entryAmount(int num_threads) 4182292SN/A{ 4192292SN/A if (iqPolicy == Partitioned) { 4202292SN/A return numEntries / num_threads; 4212292SN/A } else { 4222292SN/A return 0; 4232292SN/A } 4242292SN/A} 4252292SN/A 4262292SN/A 4272292SN/Atemplate <class Impl> 4282292SN/Avoid 4292292SN/AInstructionQueue<Impl>::resetEntries() 4302292SN/A{ 4312292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4322292SN/A int active_threads = (*activeThreads).size(); 4332292SN/A 4342292SN/A list<unsigned>::iterator threads = (*activeThreads).begin(); 4352292SN/A list<unsigned>::iterator list_end = (*activeThreads).end(); 4362292SN/A 4372292SN/A while (threads != list_end) { 4382292SN/A if (iqPolicy == Partitioned) { 4392292SN/A maxEntries[*threads++] = numEntries / active_threads; 4402292SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4412292SN/A maxEntries[*threads++] = numEntries; 4422292SN/A } 4432292SN/A } 4442292SN/A } 4452292SN/A} 4462292SN/A 4472292SN/Atemplate <class Impl> 4481684SN/Aunsigned 4491684SN/AInstructionQueue<Impl>::numFreeEntries() 4501684SN/A{ 4511684SN/A return freeEntries; 4521684SN/A} 4531684SN/A 4542292SN/Atemplate <class Impl> 4552292SN/Aunsigned 4562292SN/AInstructionQueue<Impl>::numFreeEntries(unsigned tid) 4572292SN/A{ 4582292SN/A return maxEntries[tid] - count[tid]; 4592292SN/A} 4602292SN/A 4611060SN/A// Might want to do something more complex if it knows how many instructions 4621060SN/A// will be issued this cycle. 4631061SN/Atemplate <class Impl> 4641060SN/Abool 4651060SN/AInstructionQueue<Impl>::isFull() 4661060SN/A{ 4671060SN/A if (freeEntries == 0) { 4681060SN/A return(true); 4691060SN/A } else { 4701060SN/A return(false); 4711060SN/A } 4721060SN/A} 4731060SN/A 4741061SN/Atemplate <class Impl> 4752292SN/Abool 4762292SN/AInstructionQueue<Impl>::isFull(unsigned tid) 4772292SN/A{ 4782292SN/A if (numFreeEntries(tid) == 0) { 4792292SN/A return(true); 4802292SN/A } else { 4812292SN/A return(false); 4822292SN/A } 4832292SN/A} 4842292SN/A 4852292SN/Atemplate <class Impl> 4862292SN/Abool 4872292SN/AInstructionQueue<Impl>::hasReadyInsts() 4882292SN/A{ 4892292SN/A if (!listOrder.empty()) { 4902292SN/A return true; 4912292SN/A } 4922292SN/A 4932292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4942292SN/A if (!readyInsts[i].empty()) { 4952292SN/A return true; 4962292SN/A } 4972292SN/A } 4982292SN/A 4992292SN/A return false; 5002292SN/A} 5012292SN/A 5022292SN/Atemplate <class Impl> 5031060SN/Avoid 5041061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5051060SN/A{ 5061060SN/A // Make sure the instruction is valid 5071060SN/A assert(new_inst); 5081060SN/A 5092326SN/A DPRINTF(IQ, "Adding instruction [sn:%lli] PC %#x to the IQ.\n", 5102326SN/A new_inst->seqNum, new_inst->readPC()); 5111060SN/A 5121060SN/A assert(freeEntries != 0); 5131060SN/A 5142292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5151060SN/A 5162064SN/A --freeEntries; 5171060SN/A 5182292SN/A new_inst->setInIQ(); 5191060SN/A 5201060SN/A // Look through its source registers (physical regs), and mark any 5211060SN/A // dependencies. 5221060SN/A addToDependents(new_inst); 5231060SN/A 5241060SN/A // Have this instruction set itself as the producer of its destination 5251060SN/A // register(s). 5262326SN/A addToProducers(new_inst); 5271060SN/A 5281061SN/A if (new_inst->isMemRef()) { 5292292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5301062SN/A } else { 5311062SN/A addIfReady(new_inst); 5321061SN/A } 5331061SN/A 5341062SN/A ++iqInstsAdded; 5351060SN/A 5362292SN/A count[new_inst->threadNumber]++; 5372292SN/A 5381060SN/A assert(freeEntries == (numEntries - countInsts())); 5391060SN/A} 5401060SN/A 5411061SN/Atemplate <class Impl> 5421061SN/Avoid 5432292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5441061SN/A{ 5451061SN/A // @todo: Clean up this code; can do it by setting inst as unable 5461061SN/A // to issue, then calling normal insert on the inst. 5471061SN/A 5482292SN/A assert(new_inst); 5491061SN/A 5502292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 5511061SN/A 5522326SN/A DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %#x " 5532326SN/A "to the IQ.\n", 5542326SN/A new_inst->seqNum, new_inst->readPC()); 5552064SN/A 5561061SN/A assert(freeEntries != 0); 5571061SN/A 5582292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5591061SN/A 5602064SN/A --freeEntries; 5611061SN/A 5622292SN/A new_inst->setInIQ(); 5631061SN/A 5641061SN/A // Have this instruction set itself as the producer of its destination 5651061SN/A // register(s). 5662326SN/A addToProducers(new_inst); 5671061SN/A 5681061SN/A // If it's a memory instruction, add it to the memory dependency 5691061SN/A // unit. 5702292SN/A if (new_inst->isMemRef()) { 5712292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 5721061SN/A } 5731062SN/A 5741062SN/A ++iqNonSpecInstsAdded; 5752292SN/A 5762292SN/A count[new_inst->threadNumber]++; 5772292SN/A 5782292SN/A assert(freeEntries == (numEntries - countInsts())); 5791061SN/A} 5801061SN/A 5811061SN/Atemplate <class Impl> 5821060SN/Avoid 5832292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 5841060SN/A{ 5852292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 5861060SN/A 5872292SN/A insertNonSpec(barr_inst); 5882292SN/A} 5891060SN/A 5902064SN/Atemplate <class Impl> 5912333SN/Atypename Impl::DynInstPtr 5922333SN/AInstructionQueue<Impl>::getInstToExecute() 5932333SN/A{ 5942333SN/A assert(!instsToExecute.empty()); 5952333SN/A DynInstPtr inst = instsToExecute.front(); 5962333SN/A instsToExecute.pop_front(); 5972333SN/A return inst; 5982333SN/A} 5991060SN/A 6002333SN/Atemplate <class Impl> 6012064SN/Avoid 6022292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6032292SN/A{ 6042292SN/A assert(!readyInsts[op_class].empty()); 6052292SN/A 6062292SN/A ListOrderEntry queue_entry; 6072292SN/A 6082292SN/A queue_entry.queueType = op_class; 6092292SN/A 6102292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6112292SN/A 6122292SN/A ListOrderIt list_it = listOrder.begin(); 6132292SN/A ListOrderIt list_end_it = listOrder.end(); 6142292SN/A 6152292SN/A while (list_it != list_end_it) { 6162292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6172292SN/A break; 6182292SN/A } 6192292SN/A 6202292SN/A list_it++; 6211060SN/A } 6221060SN/A 6232292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6242292SN/A queueOnList[op_class] = true; 6252292SN/A} 6261060SN/A 6272292SN/Atemplate <class Impl> 6282292SN/Avoid 6292292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6302292SN/A{ 6312292SN/A // Get iterator of next item on the list 6322292SN/A // Delete the original iterator 6332292SN/A // Determine if the next item is either the end of the list or younger 6342292SN/A // than the new instruction. If so, then add in a new iterator right here. 6352292SN/A // If not, then move along. 6362292SN/A ListOrderEntry queue_entry; 6372292SN/A OpClass op_class = (*list_order_it).queueType; 6382292SN/A ListOrderIt next_it = list_order_it; 6392292SN/A 6402292SN/A ++next_it; 6412292SN/A 6422292SN/A queue_entry.queueType = op_class; 6432292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6442292SN/A 6452292SN/A while (next_it != listOrder.end() && 6462292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 6472292SN/A ++next_it; 6481060SN/A } 6491060SN/A 6502292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 6511060SN/A} 6521060SN/A 6532292SN/Atemplate <class Impl> 6542292SN/Avoid 6552292SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 6562292SN/A{ 6572292SN/A // The CPU could have been sleeping until this op completed (*extremely* 6582292SN/A // long latency op). Wake it if it was. This may be overkill. 6592307SN/A if (isSwitchedOut()) { 6602307SN/A return; 6612307SN/A } 6622307SN/A 6632292SN/A iewStage->wakeCPU(); 6642292SN/A 6652326SN/A if (fu_idx > -1) 6662326SN/A fuPool->freeUnitNextCycle(fu_idx); 6672292SN/A 6682326SN/A // @todo: Ensure that these FU Completions happen at the beginning 6692326SN/A // of a cycle, otherwise they could add too many instructions to 6702326SN/A // the queue. 6712326SN/A // @todo: This could break if there's multiple multi-cycle ops 6722326SN/A // finishing on this cycle. Maybe implement something like 6732326SN/A // instToCommit in iew_impl.hh. 6742333SN/A issueToExecuteQueue->access(0)->size++; 6752333SN/A instsToExecute.push_back(inst); 6762333SN/A// int &size = issueToExecuteQueue->access(0)->size; 6772292SN/A 6782333SN/A// issueToExecuteQueue->access(0)->insts[size++] = inst; 6792292SN/A} 6802292SN/A 6811061SN/A// @todo: Figure out a better way to remove the squashed items from the 6821061SN/A// lists. Checking the top item of each list to see if it's squashed 6831061SN/A// wastes time and forces jumps. 6841061SN/Atemplate <class Impl> 6851060SN/Avoid 6861060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 6871060SN/A{ 6882292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 6892292SN/A "the IQ.\n"); 6901060SN/A 6911060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 6921060SN/A 6932292SN/A // Have iterator to head of the list 6942292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 6952292SN/A // Try to get a FU that can do what this op needs. 6962292SN/A // If successful, change the oldestInst to the new top of the list, put 6972292SN/A // the queue in the proper place in the list. 6982292SN/A // Increment the iterator. 6992292SN/A // This will avoid trying to schedule a certain op class if there are no 7002292SN/A // FUs that handle it. 7012292SN/A ListOrderIt order_it = listOrder.begin(); 7022292SN/A ListOrderIt order_end_it = listOrder.end(); 7032292SN/A int total_issued = 0; 7041060SN/A 7052333SN/A while (total_issued < totalWidth && 7062326SN/A order_it != order_end_it) { 7072292SN/A OpClass op_class = (*order_it).queueType; 7081060SN/A 7092292SN/A assert(!readyInsts[op_class].empty()); 7101060SN/A 7112292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7121060SN/A 7132292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 7141060SN/A 7152292SN/A if (issuing_inst->isSquashed()) { 7162292SN/A readyInsts[op_class].pop(); 7171060SN/A 7182292SN/A if (!readyInsts[op_class].empty()) { 7192292SN/A moveToYoungerInst(order_it); 7202292SN/A } else { 7212292SN/A readyIt[op_class] = listOrder.end(); 7222292SN/A queueOnList[op_class] = false; 7231060SN/A } 7241060SN/A 7252292SN/A listOrder.erase(order_it++); 7261060SN/A 7272292SN/A ++iqSquashedInstsIssued; 7282292SN/A 7292292SN/A continue; 7301060SN/A } 7311060SN/A 7322326SN/A int idx = -2; 7332326SN/A int op_latency = 1; 7342301SN/A int tid = issuing_inst->threadNumber; 7351060SN/A 7362326SN/A if (op_class != No_OpClass) { 7372326SN/A idx = fuPool->getUnit(op_class); 7381060SN/A 7392326SN/A if (idx > -1) { 7402326SN/A op_latency = fuPool->getOpLatency(op_class); 7411060SN/A } 7421060SN/A } 7431060SN/A 7442326SN/A if (idx == -2 || idx != -1) { 7452292SN/A if (op_latency == 1) { 7462333SN/A// i2e_info->insts[exec_queue_slot++] = issuing_inst; 7472292SN/A i2e_info->size++; 7482333SN/A instsToExecute.push_back(issuing_inst); 7491060SN/A 7502326SN/A // Add the FU onto the list of FU's to be freed next 7512326SN/A // cycle if we used one. 7522326SN/A if (idx >= 0) 7532326SN/A fuPool->freeUnitNextCycle(idx); 7542292SN/A } else { 7552292SN/A int issue_latency = fuPool->getIssueLatency(op_class); 7562326SN/A // Generate completion event for the FU 7572326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 7582326SN/A idx, this); 7591060SN/A 7602326SN/A execution->schedule(curTick + cpu->cycles(issue_latency - 1)); 7611060SN/A 7622326SN/A // @todo: Enforce that issue_latency == 1 or op_latency 7632292SN/A if (issue_latency > 1) { 7642326SN/A execution->setFreeFU(); 7652292SN/A } else { 7662326SN/A // @todo: Not sure I'm accounting for the 7672326SN/A // multi-cycle op in a pipelined FU properly, or 7682326SN/A // the number of instructions issued in one cycle. 7692326SN/A// i2e_info->insts[exec_queue_slot++] = issuing_inst; 7702326SN/A// i2e_info->size++; 7711062SN/A 7722292SN/A // Add the FU onto the list of FU's to be freed next cycle. 7732326SN/A fuPool->freeUnitNextCycle(idx); 7742292SN/A } 7751060SN/A } 7761060SN/A 7772292SN/A DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x " 7782292SN/A "[sn:%lli]\n", 7792301SN/A tid, issuing_inst->readPC(), 7802292SN/A issuing_inst->seqNum); 7811060SN/A 7822292SN/A readyInsts[op_class].pop(); 7831061SN/A 7842292SN/A if (!readyInsts[op_class].empty()) { 7852292SN/A moveToYoungerInst(order_it); 7862292SN/A } else { 7872292SN/A readyIt[op_class] = listOrder.end(); 7882292SN/A queueOnList[op_class] = false; 7891060SN/A } 7901060SN/A 7912064SN/A issuing_inst->setIssued(); 7922292SN/A ++total_issued; 7932064SN/A 7942292SN/A if (!issuing_inst->isMemRef()) { 7952292SN/A // Memory instructions can not be freed from the IQ until they 7962292SN/A // complete. 7972292SN/A ++freeEntries; 7982301SN/A count[tid]--; 7992292SN/A issuing_inst->removeInIQ(); 8002292SN/A } else { 8012301SN/A memDepUnit[tid].issue(issuing_inst); 8022292SN/A } 8032292SN/A 8042292SN/A listOrder.erase(order_it++); 8052326SN/A statIssuedInstType[tid][op_class]++; 8062292SN/A } else { 8072326SN/A statFuBusy[op_class]++; 8082326SN/A fuBusy[tid]++; 8092292SN/A ++order_it; 8101060SN/A } 8111060SN/A } 8121062SN/A 8132326SN/A numIssuedDist.sample(total_issued); 8142326SN/A iqInstsIssued+= total_issued; 8152307SN/A 8162292SN/A if (total_issued) { 8172292SN/A cpu->activityThisCycle(); 8182292SN/A } else { 8192292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8202292SN/A } 8211060SN/A} 8221060SN/A 8231061SN/Atemplate <class Impl> 8241060SN/Avoid 8251061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 8261060SN/A{ 8272292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 8282292SN/A "to execute.\n", inst); 8291062SN/A 8302292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 8311060SN/A 8321061SN/A assert(inst_it != nonSpecInsts.end()); 8331060SN/A 8342292SN/A unsigned tid = (*inst_it).second->threadNumber; 8352292SN/A 8361061SN/A (*inst_it).second->setCanIssue(); 8371060SN/A 8381062SN/A if (!(*inst_it).second->isMemRef()) { 8391062SN/A addIfReady((*inst_it).second); 8401062SN/A } else { 8412292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 8421062SN/A } 8431060SN/A 8442292SN/A (*inst_it).second = NULL; 8452292SN/A 8461061SN/A nonSpecInsts.erase(inst_it); 8471060SN/A} 8481060SN/A 8491061SN/Atemplate <class Impl> 8501061SN/Avoid 8512292SN/AInstructionQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid) 8522292SN/A{ 8532292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 8542292SN/A tid,inst); 8552292SN/A 8562292SN/A ListIt iq_it = instList[tid].begin(); 8572292SN/A 8582292SN/A while (iq_it != instList[tid].end() && 8592292SN/A (*iq_it)->seqNum <= inst) { 8602292SN/A ++iq_it; 8612292SN/A instList[tid].pop_front(); 8622292SN/A } 8632292SN/A 8642292SN/A assert(freeEntries == (numEntries - countInsts())); 8652292SN/A} 8662292SN/A 8672292SN/Atemplate <class Impl> 8682301SN/Aint 8691684SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 8701684SN/A{ 8712301SN/A int dependents = 0; 8722301SN/A 8732292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 8742292SN/A 8752292SN/A assert(!completed_inst->isSquashed()); 8761684SN/A 8771684SN/A // Tell the memory dependence unit to wake any dependents on this 8782292SN/A // instruction if it is a memory instruction. Also complete the memory 8792326SN/A // instruction at this point since we know it executed without issues. 8802326SN/A // @todo: Might want to rename "completeMemInst" to something that 8812326SN/A // indicates that it won't need to be replayed, and call this 8822326SN/A // earlier. Might not be a big deal. 8831684SN/A if (completed_inst->isMemRef()) { 8842292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 8852292SN/A completeMemInst(completed_inst); 8862292SN/A } else if (completed_inst->isMemBarrier() || 8872292SN/A completed_inst->isWriteBarrier()) { 8882292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 8891684SN/A } 8901684SN/A 8911684SN/A for (int dest_reg_idx = 0; 8921684SN/A dest_reg_idx < completed_inst->numDestRegs(); 8931684SN/A dest_reg_idx++) 8941684SN/A { 8951684SN/A PhysRegIndex dest_reg = 8961684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 8971684SN/A 8981684SN/A // Special case of uniq or control registers. They are not 8991684SN/A // handled by the IQ and thus have no dependency graph entry. 9001684SN/A // @todo Figure out a cleaner way to handle this. 9011684SN/A if (dest_reg >= numPhysRegs) { 9021684SN/A continue; 9031684SN/A } 9041684SN/A 9052292SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 9061684SN/A (int) dest_reg); 9071684SN/A 9082326SN/A //Go through the dependency chain, marking the registers as 9092326SN/A //ready within the waiting instructions. 9102326SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg); 9111684SN/A 9122326SN/A while (dep_inst) { 9132292SN/A DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n", 9142326SN/A dep_inst->readPC()); 9151684SN/A 9161684SN/A // Might want to give more information to the instruction 9172326SN/A // so that it knows which of its source registers is 9182326SN/A // ready. However that would mean that the dependency 9192326SN/A // graph entries would need to hold the src_reg_idx. 9202326SN/A dep_inst->markSrcRegReady(); 9211684SN/A 9222326SN/A addIfReady(dep_inst); 9231684SN/A 9242326SN/A dep_inst = dependGraph.pop(dest_reg); 9251684SN/A 9262301SN/A ++dependents; 9271684SN/A } 9281684SN/A 9292326SN/A // Reset the head node now that all of its dependents have 9302326SN/A // been woken up. 9312326SN/A assert(dependGraph.empty(dest_reg)); 9322326SN/A dependGraph.clearInst(dest_reg); 9331684SN/A 9341684SN/A // Mark the scoreboard as having that register ready. 9351684SN/A regScoreboard[dest_reg] = true; 9361684SN/A } 9372301SN/A return dependents; 9382064SN/A} 9392064SN/A 9402064SN/Atemplate <class Impl> 9412064SN/Avoid 9422292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 9432064SN/A{ 9442292SN/A OpClass op_class = ready_inst->opClass(); 9452292SN/A 9462292SN/A readyInsts[op_class].push(ready_inst); 9472292SN/A 9482326SN/A // Will need to reorder the list if either a queue is not on the list, 9492326SN/A // or it has an older instruction than last time. 9502326SN/A if (!queueOnList[op_class]) { 9512326SN/A addToOrderList(op_class); 9522326SN/A } else if (readyInsts[op_class].top()->seqNum < 9532326SN/A (*readyIt[op_class]).oldestInst) { 9542326SN/A listOrder.erase(readyIt[op_class]); 9552326SN/A addToOrderList(op_class); 9562326SN/A } 9572326SN/A 9582292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 9592292SN/A "the ready list, PC %#x opclass:%i [sn:%lli].\n", 9602292SN/A ready_inst->readPC(), op_class, ready_inst->seqNum); 9612064SN/A} 9622064SN/A 9632064SN/Atemplate <class Impl> 9642064SN/Avoid 9652292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 9662064SN/A{ 9672292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 9682064SN/A} 9692064SN/A 9702064SN/Atemplate <class Impl> 9712064SN/Avoid 9722292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 9732064SN/A{ 9742292SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 9752292SN/A} 9762292SN/A 9772292SN/Atemplate <class Impl> 9782292SN/Avoid 9792292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 9802292SN/A{ 9812292SN/A int tid = completed_inst->threadNumber; 9822292SN/A 9832292SN/A DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n", 9842292SN/A completed_inst->readPC(), completed_inst->seqNum); 9852292SN/A 9862292SN/A ++freeEntries; 9872292SN/A 9882292SN/A completed_inst->memOpDone = true; 9892292SN/A 9902292SN/A memDepUnit[tid].completed(completed_inst); 9912292SN/A 9922292SN/A count[tid]--; 9931684SN/A} 9941684SN/A 9951684SN/Atemplate <class Impl> 9961684SN/Avoid 9971061SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 9981061SN/A DynInstPtr &faulting_load) 9991061SN/A{ 10002292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 10011061SN/A} 10021061SN/A 10031061SN/Atemplate <class Impl> 10041060SN/Avoid 10052292SN/AInstructionQueue<Impl>::squash(unsigned tid) 10061060SN/A{ 10072292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 10082292SN/A "the IQ.\n", tid); 10091060SN/A 10101060SN/A // Read instruction sequence number of last instruction out of the 10111060SN/A // time buffer. 10122292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 10131060SN/A 10141681SN/A // Call doSquash if there are insts in the IQ 10152292SN/A if (count[tid] > 0) { 10162292SN/A doSquash(tid); 10171681SN/A } 10181061SN/A 10191061SN/A // Also tell the memory dependence unit to squash. 10202292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 10211060SN/A} 10221060SN/A 10231061SN/Atemplate <class Impl> 10241061SN/Avoid 10252292SN/AInstructionQueue<Impl>::doSquash(unsigned tid) 10261061SN/A{ 10272326SN/A // Start at the tail. 10282326SN/A ListIt squash_it = instList[tid].end(); 10292326SN/A --squash_it; 10301061SN/A 10312292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 10322292SN/A tid, squashedSeqNum[tid]); 10331061SN/A 10341061SN/A // Squash any instructions younger than the squashed sequence number 10351061SN/A // given. 10362326SN/A while (squash_it != instList[tid].end() && 10372326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 10382292SN/A 10392326SN/A DynInstPtr squashed_inst = (*squash_it); 10401061SN/A 10411061SN/A // Only handle the instruction if it actually is in the IQ and 10421061SN/A // hasn't already been squashed in the IQ. 10432292SN/A if (squashed_inst->threadNumber != tid || 10442292SN/A squashed_inst->isSquashedInIQ()) { 10452326SN/A --squash_it; 10462292SN/A continue; 10472292SN/A } 10482292SN/A 10492292SN/A if (!squashed_inst->isIssued() || 10502292SN/A (squashed_inst->isMemRef() && 10512292SN/A !squashed_inst->memOpDone)) { 10521062SN/A 10531061SN/A // Remove the instruction from the dependency list. 10542292SN/A if (!squashed_inst->isNonSpeculative() && 10552336SN/A !squashed_inst->isStoreConditional() && 10562292SN/A !squashed_inst->isMemBarrier() && 10572292SN/A !squashed_inst->isWriteBarrier()) { 10581061SN/A 10591061SN/A for (int src_reg_idx = 0; 10601681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 10611061SN/A src_reg_idx++) 10621061SN/A { 10631061SN/A PhysRegIndex src_reg = 10641061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 10651061SN/A 10662326SN/A // Only remove it from the dependency graph if it 10672326SN/A // was placed there in the first place. 10682326SN/A 10692326SN/A // Instead of doing a linked list traversal, we 10702326SN/A // can just remove these squashed instructions 10712326SN/A // either at issue time, or when the register is 10722326SN/A // overwritten. The only downside to this is it 10732326SN/A // leaves more room for error. 10742292SN/A 10751061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 10761061SN/A src_reg < numPhysRegs) { 10772326SN/A dependGraph.remove(src_reg, squashed_inst); 10781061SN/A } 10791062SN/A 10802292SN/A 10811062SN/A ++iqSquashedOperandsExamined; 10821061SN/A } 10832064SN/A } else { 10842292SN/A NonSpecMapIt ns_inst_it = 10852292SN/A nonSpecInsts.find(squashed_inst->seqNum); 10862292SN/A assert(ns_inst_it != nonSpecInsts.end()); 10871062SN/A 10882292SN/A (*ns_inst_it).second = NULL; 10891681SN/A 10902292SN/A nonSpecInsts.erase(ns_inst_it); 10911062SN/A 10921062SN/A ++iqSquashedNonSpecRemoved; 10931061SN/A } 10941061SN/A 10951061SN/A // Might want to also clear out the head of the dependency graph. 10961061SN/A 10971061SN/A // Mark it as squashed within the IQ. 10981061SN/A squashed_inst->setSquashedInIQ(); 10991061SN/A 11002292SN/A // @todo: Remove this hack where several statuses are set so the 11012292SN/A // inst will flow through the rest of the pipeline. 11021681SN/A squashed_inst->setIssued(); 11031681SN/A squashed_inst->setCanCommit(); 11042292SN/A squashed_inst->removeInIQ(); 11052292SN/A 11062292SN/A //Update Thread IQ Count 11072292SN/A count[squashed_inst->threadNumber]--; 11081681SN/A 11091681SN/A ++freeEntries; 11101061SN/A 11112326SN/A DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %#x " 11122326SN/A "squashed.\n", 11132326SN/A tid, squashed_inst->seqNum, squashed_inst->readPC()); 11141061SN/A } 11151061SN/A 11162326SN/A instList[tid].erase(squash_it--); 11171062SN/A ++iqSquashedInstsExamined; 11181061SN/A } 11191060SN/A} 11201060SN/A 11211061SN/Atemplate <class Impl> 11221060SN/Abool 11231061SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 11241060SN/A{ 11251060SN/A // Loop through the instruction's source registers, adding 11261060SN/A // them to the dependency list if they are not ready. 11271060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 11281060SN/A bool return_val = false; 11291060SN/A 11301060SN/A for (int src_reg_idx = 0; 11311060SN/A src_reg_idx < total_src_regs; 11321060SN/A src_reg_idx++) 11331060SN/A { 11341060SN/A // Only add it to the dependency graph if it's not ready. 11351060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 11361060SN/A PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 11371060SN/A 11381060SN/A // Check the IQ's scoreboard to make sure the register 11391060SN/A // hasn't become ready while the instruction was in flight 11401060SN/A // between stages. Only if it really isn't ready should 11411060SN/A // it be added to the dependency graph. 11421061SN/A if (src_reg >= numPhysRegs) { 11431061SN/A continue; 11441061SN/A } else if (regScoreboard[src_reg] == false) { 11452292SN/A DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 11461060SN/A "is being added to the dependency chain.\n", 11471060SN/A new_inst->readPC(), src_reg); 11481060SN/A 11492326SN/A dependGraph.insert(src_reg, new_inst); 11501060SN/A 11511060SN/A // Change the return value to indicate that something 11521060SN/A // was added to the dependency graph. 11531060SN/A return_val = true; 11541060SN/A } else { 11552292SN/A DPRINTF(IQ, "Instruction PC %#x has src reg %i that " 11561060SN/A "became ready before it reached the IQ.\n", 11571060SN/A new_inst->readPC(), src_reg); 11581060SN/A // Mark a register ready within the instruction. 11592326SN/A new_inst->markSrcRegReady(src_reg_idx); 11601060SN/A } 11611060SN/A } 11621060SN/A } 11631060SN/A 11641060SN/A return return_val; 11651060SN/A} 11661060SN/A 11671061SN/Atemplate <class Impl> 11681060SN/Avoid 11692326SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 11701060SN/A{ 11712326SN/A // Nothing really needs to be marked when an instruction becomes 11722326SN/A // the producer of a register's value, but for convenience a ptr 11732326SN/A // to the producing instruction will be placed in the head node of 11742326SN/A // the dependency links. 11751060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 11761060SN/A 11771060SN/A for (int dest_reg_idx = 0; 11781060SN/A dest_reg_idx < total_dest_regs; 11791060SN/A dest_reg_idx++) 11801060SN/A { 11811061SN/A PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 11821061SN/A 11831061SN/A // Instructions that use the misc regs will have a reg number 11841061SN/A // higher than the normal physical registers. In this case these 11851061SN/A // registers are not renamed, and there is no need to track 11861061SN/A // dependencies as these instructions must be executed at commit. 11871061SN/A if (dest_reg >= numPhysRegs) { 11881061SN/A continue; 11891060SN/A } 11901060SN/A 11912326SN/A if (!dependGraph.empty(dest_reg)) { 11922326SN/A dependGraph.dump(); 11932292SN/A panic("Dependency graph %i not empty!", dest_reg); 11942064SN/A } 11951062SN/A 11962326SN/A dependGraph.setInst(dest_reg, new_inst); 11971062SN/A 11981060SN/A // Mark the scoreboard to say it's not yet ready. 11991060SN/A regScoreboard[dest_reg] = false; 12001060SN/A } 12011060SN/A} 12021060SN/A 12031061SN/Atemplate <class Impl> 12041060SN/Avoid 12051061SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 12061060SN/A{ 12072326SN/A // If the instruction now has all of its source registers 12081060SN/A // available, then add it to the list of ready instructions. 12091060SN/A if (inst->readyToIssue()) { 12101061SN/A 12111060SN/A //Add the instruction to the proper ready list. 12122292SN/A if (inst->isMemRef()) { 12131061SN/A 12142292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 12151061SN/A 12161062SN/A // Message to the mem dependence unit that this instruction has 12171062SN/A // its registers ready. 12182292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 12191062SN/A 12202292SN/A return; 12212292SN/A } 12221062SN/A 12232292SN/A OpClass op_class = inst->opClass(); 12241061SN/A 12252292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 12262292SN/A "the ready list, PC %#x opclass:%i [sn:%lli].\n", 12272292SN/A inst->readPC(), op_class, inst->seqNum); 12281061SN/A 12292292SN/A readyInsts[op_class].push(inst); 12301061SN/A 12312326SN/A // Will need to reorder the list if either a queue is not on the list, 12322326SN/A // or it has an older instruction than last time. 12332326SN/A if (!queueOnList[op_class]) { 12342326SN/A addToOrderList(op_class); 12352326SN/A } else if (readyInsts[op_class].top()->seqNum < 12362326SN/A (*readyIt[op_class]).oldestInst) { 12372326SN/A listOrder.erase(readyIt[op_class]); 12382326SN/A addToOrderList(op_class); 12391060SN/A } 12401060SN/A } 12411060SN/A} 12421060SN/A 12431061SN/Atemplate <class Impl> 12441061SN/Aint 12451061SN/AInstructionQueue<Impl>::countInsts() 12461061SN/A{ 12472292SN/A //ksewell:This works but definitely could use a cleaner write 12482292SN/A //with a more intuitive way of counting. Right now it's 12492292SN/A //just brute force .... 12502292SN/A 12512292SN/A#if 0 12521061SN/A int total_insts = 0; 12531061SN/A 12542292SN/A for (int i = 0; i < numThreads; ++i) { 12552292SN/A ListIt count_it = instList[i].begin(); 12561681SN/A 12572292SN/A while (count_it != instList[i].end()) { 12582292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 12592292SN/A if (!(*count_it)->isIssued()) { 12602292SN/A ++total_insts; 12612292SN/A } else if ((*count_it)->isMemRef() && 12622292SN/A !(*count_it)->memOpDone) { 12632292SN/A // Loads that have not been marked as executed still count 12642292SN/A // towards the total instructions. 12652292SN/A ++total_insts; 12662292SN/A } 12672292SN/A } 12682292SN/A 12692292SN/A ++count_it; 12701061SN/A } 12711061SN/A } 12721061SN/A 12731061SN/A return total_insts; 12742292SN/A#else 12752292SN/A return numEntries - freeEntries; 12762292SN/A#endif 12771681SN/A} 12781681SN/A 12791681SN/Atemplate <class Impl> 12801681SN/Avoid 12811061SN/AInstructionQueue<Impl>::dumpLists() 12821061SN/A{ 12832292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 12842292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 12851061SN/A 12862292SN/A cprintf("\n"); 12872292SN/A } 12881061SN/A 12891061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 12901061SN/A 12912292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 12922292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 12931061SN/A 12941061SN/A cprintf("Non speculative list: "); 12951061SN/A 12962292SN/A while (non_spec_it != non_spec_end_it) { 12972292SN/A cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(), 12982292SN/A (*non_spec_it).second->seqNum); 12991061SN/A ++non_spec_it; 13001061SN/A } 13011061SN/A 13021061SN/A cprintf("\n"); 13031061SN/A 13042292SN/A ListOrderIt list_order_it = listOrder.begin(); 13052292SN/A ListOrderIt list_order_end_it = listOrder.end(); 13062292SN/A int i = 1; 13072292SN/A 13082292SN/A cprintf("List order: "); 13092292SN/A 13102292SN/A while (list_order_it != list_order_end_it) { 13112292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 13122292SN/A (*list_order_it).oldestInst); 13132292SN/A 13142292SN/A ++list_order_it; 13152292SN/A ++i; 13162292SN/A } 13172292SN/A 13182292SN/A cprintf("\n"); 13191061SN/A} 13202292SN/A 13212292SN/A 13222292SN/Atemplate <class Impl> 13232292SN/Avoid 13242292SN/AInstructionQueue<Impl>::dumpInsts() 13252292SN/A{ 13262292SN/A for (int i = 0; i < numThreads; ++i) { 13272292SN/A int num = 0; 13282292SN/A int valid_num = 0; 13292292SN/A ListIt inst_list_it = instList[i].begin(); 13302292SN/A 13312292SN/A while (inst_list_it != instList[i].end()) 13322292SN/A { 13332292SN/A cprintf("Instruction:%i\n", 13342292SN/A num); 13352292SN/A if (!(*inst_list_it)->isSquashed()) { 13362292SN/A if (!(*inst_list_it)->isIssued()) { 13372292SN/A ++valid_num; 13382292SN/A cprintf("Count:%i\n", valid_num); 13392292SN/A } else if ((*inst_list_it)->isMemRef() && 13402292SN/A !(*inst_list_it)->memOpDone) { 13412326SN/A // Loads that have not been marked as executed 13422326SN/A // still count towards the total instructions. 13432292SN/A ++valid_num; 13442292SN/A cprintf("Count:%i\n", valid_num); 13452292SN/A } 13462292SN/A } 13472292SN/A 13482292SN/A cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n" 13492292SN/A "Issued:%i\nSquashed:%i\n", 13502292SN/A (*inst_list_it)->readPC(), 13512292SN/A (*inst_list_it)->seqNum, 13522292SN/A (*inst_list_it)->threadNumber, 13532292SN/A (*inst_list_it)->isIssued(), 13542292SN/A (*inst_list_it)->isSquashed()); 13552292SN/A 13562292SN/A if ((*inst_list_it)->isMemRef()) { 13572292SN/A cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone); 13582292SN/A } 13592292SN/A 13602292SN/A cprintf("\n"); 13612292SN/A 13622292SN/A inst_list_it++; 13632292SN/A ++num; 13642292SN/A } 13652292SN/A } 13662292SN/A} 1367