inst_queue_impl.hh revision 13561
11689SN/A/* 210333Smitch.hayenga@arm.com * Copyright (c) 2011-2014 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422831Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_INST_QUEUE_IMPL_HH__ 479944Smatt.horsnell@ARM.com 482064SN/A#include <limits> 491060SN/A#include <vector> 501060SN/A 5113449Sgabeblack@google.com#include "base/logging.hh" 522292SN/A#include "cpu/o3/fu_pool.hh" 531717SN/A#include "cpu/o3/inst_queue.hh" 548232Snate@binkert.org#include "debug/IQ.hh" 554762Snate@binkert.org#include "enums/OpClass.hh" 566221Snate@binkert.org#include "params/DerivO3CPU.hh" 574762Snate@binkert.org#include "sim/core.hh" 581060SN/A 598737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 608737Skoansin.tan@gmail.com// we open up the entire namespace std 618737Skoansin.tan@gmail.comusing std::list; 625529Snate@binkert.org 631061SN/Atemplate <class Impl> 6413429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::FUCompletion::FUCompletion(const DynInstPtr &_inst, 655606Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 668581Ssteve.reinhardt@amd.com : Event(Stat_Event_Pri, AutoDelete), 678581Ssteve.reinhardt@amd.com inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 681060SN/A{ 692292SN/A} 702292SN/A 712292SN/Atemplate <class Impl> 722292SN/Avoid 732292SN/AInstructionQueue<Impl>::FUCompletion::process() 742292SN/A{ 752326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 762292SN/A inst = NULL; 772292SN/A} 782292SN/A 792292SN/A 802292SN/Atemplate <class Impl> 812292SN/Aconst char * 825336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const 832292SN/A{ 844873Sstever@eecs.umich.edu return "Functional unit completion"; 852292SN/A} 862292SN/A 872292SN/Atemplate <class Impl> 884329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 895529Snate@binkert.org DerivO3CPUParams *params) 904329Sktlim@umich.edu : cpu(cpu_ptr), 914329Sktlim@umich.edu iewStage(iew_ptr), 924329Sktlim@umich.edu fuPool(params->fuPool), 9313561Snikos.nikoleris@arm.com iqPolicy(params->smtIQPolicy), 942292SN/A numEntries(params->numIQEntries), 952292SN/A totalWidth(params->issueWidth), 962292SN/A commitToIEWDelay(params->commitToIEWDelay) 972292SN/A{ 982292SN/A assert(fuPool); 992292SN/A 1005529Snate@binkert.org numThreads = params->numThreads; 1011060SN/A 1029920Syasuko.eckert@amd.com // Set the number of total physical registers 10312109SRekai.GonzalezAlberquilla@arm.com // As the vector registers have two addressing modes, they are added twice 1049920Syasuko.eckert@amd.com numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 10512109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs + 10612109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs * TheISA::NumVecElemPerVecReg + 10712109SRekai.GonzalezAlberquilla@arm.com params->numPhysCCRegs; 1081060SN/A 1091060SN/A //Create an entry for each physical register within the 1101060SN/A //dependency graph. 1112326SN/A dependGraph.resize(numPhysRegs); 1121060SN/A 1131060SN/A // Resize the register scoreboard. 1141060SN/A regScoreboard.resize(numPhysRegs); 1151060SN/A 1162292SN/A //Initialize Mem Dependence Units 11713453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 1186221Snate@binkert.org memDepUnit[tid].init(params, tid); 1196221Snate@binkert.org memDepUnit[tid].setIQ(this); 1201060SN/A } 1211060SN/A 1222307SN/A resetState(); 1232292SN/A 1242292SN/A //Figure out resource sharing policy 12513561Snikos.nikoleris@arm.com if (iqPolicy == SMTQueuePolicy::Dynamic) { 1262292SN/A //Set Max Entries to Total ROB Capacity 1276221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1286221Snate@binkert.org maxEntries[tid] = numEntries; 1292292SN/A } 1302292SN/A 13113561Snikos.nikoleris@arm.com } else if (iqPolicy == SMTQueuePolicy::Partitioned) { 1322292SN/A //@todo:make work if part_amt doesnt divide evenly. 1332292SN/A int part_amt = numEntries / numThreads; 1342292SN/A 1352292SN/A //Divide ROB up evenly 1366221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1376221Snate@binkert.org maxEntries[tid] = part_amt; 1382292SN/A } 1392292SN/A 1402831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1412292SN/A "%i entries per thread.\n",part_amt); 14213561Snikos.nikoleris@arm.com } else if (iqPolicy == SMTQueuePolicy::Threshold) { 1432292SN/A double threshold = (double)params->smtIQThreshold / 100; 1442292SN/A 1452292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1462292SN/A 1472292SN/A //Divide up by threshold amount 1486221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1496221Snate@binkert.org maxEntries[tid] = thresholdIQ; 1502292SN/A } 1512292SN/A 1522831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1532292SN/A "%i entries per thread.\n",thresholdIQ); 1542292SN/A } 15513453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) { 15613453Srekai.gonzalezalberquilla@arm.com maxEntries[tid] = 0; 15713453Srekai.gonzalezalberquilla@arm.com } 1582292SN/A} 1592292SN/A 1602292SN/Atemplate <class Impl> 1612292SN/AInstructionQueue<Impl>::~InstructionQueue() 1622292SN/A{ 1632326SN/A dependGraph.reset(); 1642348SN/A#ifdef DEBUG 1652326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1662326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1672348SN/A#endif 1682292SN/A} 1692292SN/A 1702292SN/Atemplate <class Impl> 1712292SN/Astd::string 1722292SN/AInstructionQueue<Impl>::name() const 1732292SN/A{ 1742292SN/A return cpu->name() + ".iq"; 1751060SN/A} 1761060SN/A 1771061SN/Atemplate <class Impl> 1781060SN/Avoid 1791062SN/AInstructionQueue<Impl>::regStats() 1801062SN/A{ 1812301SN/A using namespace Stats; 1821062SN/A iqInstsAdded 1831062SN/A .name(name() + ".iqInstsAdded") 1841062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1851062SN/A .prereq(iqInstsAdded); 1861062SN/A 1871062SN/A iqNonSpecInstsAdded 1881062SN/A .name(name() + ".iqNonSpecInstsAdded") 1891062SN/A .desc("Number of non-speculative instructions added to the IQ") 1901062SN/A .prereq(iqNonSpecInstsAdded); 1911062SN/A 1922301SN/A iqInstsIssued 1932301SN/A .name(name() + ".iqInstsIssued") 1942301SN/A .desc("Number of instructions issued") 1952301SN/A .prereq(iqInstsIssued); 1961062SN/A 1971062SN/A iqIntInstsIssued 1981062SN/A .name(name() + ".iqIntInstsIssued") 1991062SN/A .desc("Number of integer instructions issued") 2001062SN/A .prereq(iqIntInstsIssued); 2011062SN/A 2021062SN/A iqFloatInstsIssued 2031062SN/A .name(name() + ".iqFloatInstsIssued") 2041062SN/A .desc("Number of float instructions issued") 2051062SN/A .prereq(iqFloatInstsIssued); 2061062SN/A 2071062SN/A iqBranchInstsIssued 2081062SN/A .name(name() + ".iqBranchInstsIssued") 2091062SN/A .desc("Number of branch instructions issued") 2101062SN/A .prereq(iqBranchInstsIssued); 2111062SN/A 2121062SN/A iqMemInstsIssued 2131062SN/A .name(name() + ".iqMemInstsIssued") 2141062SN/A .desc("Number of memory instructions issued") 2151062SN/A .prereq(iqMemInstsIssued); 2161062SN/A 2171062SN/A iqMiscInstsIssued 2181062SN/A .name(name() + ".iqMiscInstsIssued") 2191062SN/A .desc("Number of miscellaneous instructions issued") 2201062SN/A .prereq(iqMiscInstsIssued); 2211062SN/A 2221062SN/A iqSquashedInstsIssued 2231062SN/A .name(name() + ".iqSquashedInstsIssued") 2241062SN/A .desc("Number of squashed instructions issued") 2251062SN/A .prereq(iqSquashedInstsIssued); 2261062SN/A 2271062SN/A iqSquashedInstsExamined 2281062SN/A .name(name() + ".iqSquashedInstsExamined") 2291062SN/A .desc("Number of squashed instructions iterated over during squash;" 2301062SN/A " mainly for profiling") 2311062SN/A .prereq(iqSquashedInstsExamined); 2321062SN/A 2331062SN/A iqSquashedOperandsExamined 2341062SN/A .name(name() + ".iqSquashedOperandsExamined") 2351062SN/A .desc("Number of squashed operands that are examined and possibly " 2361062SN/A "removed from graph") 2371062SN/A .prereq(iqSquashedOperandsExamined); 2381062SN/A 2391062SN/A iqSquashedNonSpecRemoved 2401062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2411062SN/A .desc("Number of squashed non-spec instructions that were removed") 2421062SN/A .prereq(iqSquashedNonSpecRemoved); 2432361SN/A/* 2442326SN/A queueResDist 2452301SN/A .init(Num_OpClasses, 0, 99, 2) 2462301SN/A .name(name() + ".IQ:residence:") 2472301SN/A .desc("cycles from dispatch to issue") 2482301SN/A .flags(total | pdf | cdf ) 2492301SN/A ; 2502301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2512326SN/A queueResDist.subname(i, opClassStrings[i]); 2522301SN/A } 2532361SN/A*/ 2542326SN/A numIssuedDist 2552307SN/A .init(0,totalWidth,1) 2568240Snate@binkert.org .name(name() + ".issued_per_cycle") 2572301SN/A .desc("Number of insts issued each cycle") 2582307SN/A .flags(pdf) 2592301SN/A ; 2602301SN/A/* 2612301SN/A dist_unissued 2622301SN/A .init(Num_OpClasses+2) 2638240Snate@binkert.org .name(name() + ".unissued_cause") 2642301SN/A .desc("Reason ready instruction not issued") 2652301SN/A .flags(pdf | dist) 2662301SN/A ; 2672301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2682301SN/A dist_unissued.subname(i, unissued_names[i]); 2692301SN/A } 2702301SN/A*/ 2712326SN/A statIssuedInstType 2724762Snate@binkert.org .init(numThreads,Enums::Num_OpClass) 2738240Snate@binkert.org .name(name() + ".FU_type") 2742301SN/A .desc("Type of FU issued") 2752301SN/A .flags(total | pdf | dist) 2762301SN/A ; 2774762Snate@binkert.org statIssuedInstType.ysubnames(Enums::OpClassStrings); 2782301SN/A 2792301SN/A // 2802301SN/A // How long did instructions for a particular FU type wait prior to issue 2812301SN/A // 2822361SN/A/* 2832326SN/A issueDelayDist 2842301SN/A .init(Num_OpClasses,0,99,2) 2858240Snate@binkert.org .name(name() + ".") 2862301SN/A .desc("cycles from operands ready to issue") 2872301SN/A .flags(pdf | cdf) 2882301SN/A ; 2892301SN/A 2902301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2912980Sgblack@eecs.umich.edu std::stringstream subname; 2922301SN/A subname << opClassStrings[i] << "_delay"; 2932326SN/A issueDelayDist.subname(i, subname.str()); 2942301SN/A } 2952361SN/A*/ 2962326SN/A issueRate 2978240Snate@binkert.org .name(name() + ".rate") 2982301SN/A .desc("Inst issue rate") 2992301SN/A .flags(total) 3002301SN/A ; 3012326SN/A issueRate = iqInstsIssued / cpu->numCycles; 3022727Sktlim@umich.edu 3032326SN/A statFuBusy 3042301SN/A .init(Num_OpClasses) 3058240Snate@binkert.org .name(name() + ".fu_full") 3062301SN/A .desc("attempts to use FU when none available") 3072301SN/A .flags(pdf | dist) 3082301SN/A ; 3092301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3104762Snate@binkert.org statFuBusy.subname(i, Enums::OpClassStrings[i]); 3112301SN/A } 3122301SN/A 3132326SN/A fuBusy 3142301SN/A .init(numThreads) 3158240Snate@binkert.org .name(name() + ".fu_busy_cnt") 3162301SN/A .desc("FU busy when requested") 3172301SN/A .flags(total) 3182301SN/A ; 3192301SN/A 3202326SN/A fuBusyRate 3218240Snate@binkert.org .name(name() + ".fu_busy_rate") 3222301SN/A .desc("FU busy rate (busy events/executed inst)") 3232301SN/A .flags(total) 3242301SN/A ; 3252326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3262301SN/A 3276221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3282292SN/A // Tell mem dependence unit to reg stats as well. 3296221Snate@binkert.org memDepUnit[tid].regStats(); 3302292SN/A } 3317897Shestness@cs.utexas.edu 3327897Shestness@cs.utexas.edu intInstQueueReads 3337897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3347897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3357897Shestness@cs.utexas.edu .flags(total); 3367897Shestness@cs.utexas.edu 3377897Shestness@cs.utexas.edu intInstQueueWrites 3387897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3397897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3407897Shestness@cs.utexas.edu .flags(total); 3417897Shestness@cs.utexas.edu 3427897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3437897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3447897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3457897Shestness@cs.utexas.edu .flags(total); 3467897Shestness@cs.utexas.edu 3477897Shestness@cs.utexas.edu fpInstQueueReads 3487897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3497897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3507897Shestness@cs.utexas.edu .flags(total); 3517897Shestness@cs.utexas.edu 3527897Shestness@cs.utexas.edu fpInstQueueWrites 3537897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3547897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3557897Shestness@cs.utexas.edu .flags(total); 3567897Shestness@cs.utexas.edu 35712110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWakeupAccesses 3587897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3597897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3607897Shestness@cs.utexas.edu .flags(total); 3617897Shestness@cs.utexas.edu 36212319Sandreas.sandberg@arm.com vecInstQueueReads 36312319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_reads") 36412319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue reads") 36512319Sandreas.sandberg@arm.com .flags(total); 36612319Sandreas.sandberg@arm.com 36712319Sandreas.sandberg@arm.com vecInstQueueWrites 36812319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_writes") 36912319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue writes") 37012319Sandreas.sandberg@arm.com .flags(total); 37112319Sandreas.sandberg@arm.com 37212319Sandreas.sandberg@arm.com vecInstQueueWakeupAccesses 37312319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_wakeup_accesses") 37412319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue wakeup accesses") 37512319Sandreas.sandberg@arm.com .flags(total); 37612319Sandreas.sandberg@arm.com 3777897Shestness@cs.utexas.edu intAluAccesses 3787897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 3797897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 3807897Shestness@cs.utexas.edu .flags(total); 3817897Shestness@cs.utexas.edu 3827897Shestness@cs.utexas.edu fpAluAccesses 3837897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 3847897Shestness@cs.utexas.edu .desc("Number of floating point alu accesses") 3857897Shestness@cs.utexas.edu .flags(total); 3867897Shestness@cs.utexas.edu 38712319Sandreas.sandberg@arm.com vecAluAccesses 38812319Sandreas.sandberg@arm.com .name(name() + ".vec_alu_accesses") 38912319Sandreas.sandberg@arm.com .desc("Number of vector alu accesses") 39012319Sandreas.sandberg@arm.com .flags(total); 39112319Sandreas.sandberg@arm.com 3921062SN/A} 3931062SN/A 3941062SN/Atemplate <class Impl> 3951062SN/Avoid 3962307SN/AInstructionQueue<Impl>::resetState() 3971060SN/A{ 3982307SN/A //Initialize thread IQ counts 39913453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 4006221Snate@binkert.org count[tid] = 0; 4016221Snate@binkert.org instList[tid].clear(); 4022307SN/A } 4031060SN/A 4042307SN/A // Initialize the number of free IQ entries. 4052307SN/A freeEntries = numEntries; 4062307SN/A 4072307SN/A // Note that in actuality, the registers corresponding to the logical 4082307SN/A // registers start off as ready. However this doesn't matter for the 4092307SN/A // IQ as the instruction should have been correctly told if those 4102307SN/A // registers are ready in rename. Thus it can all be initialized as 4112307SN/A // unready. 4122307SN/A for (int i = 0; i < numPhysRegs; ++i) { 4132307SN/A regScoreboard[i] = false; 4142307SN/A } 4152307SN/A 41613453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; ++tid) { 4176221Snate@binkert.org squashedSeqNum[tid] = 0; 4182307SN/A } 4192307SN/A 4202307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4212307SN/A while (!readyInsts[i].empty()) 4222307SN/A readyInsts[i].pop(); 4232307SN/A queueOnList[i] = false; 4242307SN/A readyIt[i] = listOrder.end(); 4252307SN/A } 4262307SN/A nonSpecInsts.clear(); 4272307SN/A listOrder.clear(); 4287944SGiacomo.Gabrielli@arm.com deferredMemInsts.clear(); 42910333Smitch.hayenga@arm.com blockedMemInsts.clear(); 43010333Smitch.hayenga@arm.com retryMemInsts.clear(); 43110511Smitch.hayenga@arm.com wbOutstanding = 0; 4321060SN/A} 4331060SN/A 4341061SN/Atemplate <class Impl> 4351060SN/Avoid 4366221Snate@binkert.orgInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4371060SN/A{ 4382292SN/A activeThreads = at_ptr; 4392064SN/A} 4402064SN/A 4412064SN/Atemplate <class Impl> 4422064SN/Avoid 4432292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4442064SN/A{ 4454318Sktlim@umich.edu issueToExecuteQueue = i2e_ptr; 4461060SN/A} 4471060SN/A 4481061SN/Atemplate <class Impl> 4491060SN/Avoid 4501060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4511060SN/A{ 4521060SN/A timeBuffer = tb_ptr; 4531060SN/A 4541060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4551060SN/A} 4561060SN/A 4571684SN/Atemplate <class Impl> 45810510Smitch.hayenga@arm.combool 45910510Smitch.hayenga@arm.comInstructionQueue<Impl>::isDrained() const 46010510Smitch.hayenga@arm.com{ 46110511Smitch.hayenga@arm.com bool drained = dependGraph.empty() && 46210511Smitch.hayenga@arm.com instsToExecute.empty() && 46310511Smitch.hayenga@arm.com wbOutstanding == 0; 46410510Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) 46510510Smitch.hayenga@arm.com drained = drained && memDepUnit[tid].isDrained(); 46610510Smitch.hayenga@arm.com 46710510Smitch.hayenga@arm.com return drained; 46810510Smitch.hayenga@arm.com} 46910510Smitch.hayenga@arm.com 47010510Smitch.hayenga@arm.comtemplate <class Impl> 4712307SN/Avoid 4729444SAndreas.Sandberg@ARM.comInstructionQueue<Impl>::drainSanityCheck() const 4732307SN/A{ 4749444SAndreas.Sandberg@ARM.com assert(dependGraph.empty()); 4759444SAndreas.Sandberg@ARM.com assert(instsToExecute.empty()); 4769444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; ++tid) 4779444SAndreas.Sandberg@ARM.com memDepUnit[tid].drainSanityCheck(); 4782307SN/A} 4792307SN/A 4802307SN/Atemplate <class Impl> 4812307SN/Avoid 4822307SN/AInstructionQueue<Impl>::takeOverFrom() 4832307SN/A{ 4849444SAndreas.Sandberg@ARM.com resetState(); 4852307SN/A} 4862307SN/A 4872307SN/Atemplate <class Impl> 4882292SN/Aint 4896221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4902292SN/A{ 49113561Snikos.nikoleris@arm.com if (iqPolicy == SMTQueuePolicy::Partitioned) { 4922292SN/A return numEntries / num_threads; 4932292SN/A } else { 4942292SN/A return 0; 4952292SN/A } 4962292SN/A} 4972292SN/A 4982292SN/A 4992292SN/Atemplate <class Impl> 5002292SN/Avoid 5012292SN/AInstructionQueue<Impl>::resetEntries() 5022292SN/A{ 50313561Snikos.nikoleris@arm.com if (iqPolicy != SMTQueuePolicy::Dynamic || numThreads > 1) { 5043867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 5052292SN/A 5066221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5076221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5082292SN/A 5093867Sbinkertn@umich.edu while (threads != end) { 5106221Snate@binkert.org ThreadID tid = *threads++; 5113867Sbinkertn@umich.edu 51213561Snikos.nikoleris@arm.com if (iqPolicy == SMTQueuePolicy::Partitioned) { 5133867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 51413561Snikos.nikoleris@arm.com } else if (iqPolicy == SMTQueuePolicy::Threshold && 51513561Snikos.nikoleris@arm.com active_threads == 1) { 5163867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 5172292SN/A } 5182292SN/A } 5192292SN/A } 5202292SN/A} 5212292SN/A 5222292SN/Atemplate <class Impl> 5231684SN/Aunsigned 5241684SN/AInstructionQueue<Impl>::numFreeEntries() 5251684SN/A{ 5261684SN/A return freeEntries; 5271684SN/A} 5281684SN/A 5292292SN/Atemplate <class Impl> 5302292SN/Aunsigned 5316221Snate@binkert.orgInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5322292SN/A{ 5332292SN/A return maxEntries[tid] - count[tid]; 5342292SN/A} 5352292SN/A 5361060SN/A// Might want to do something more complex if it knows how many instructions 5371060SN/A// will be issued this cycle. 5381061SN/Atemplate <class Impl> 5391060SN/Abool 5401060SN/AInstructionQueue<Impl>::isFull() 5411060SN/A{ 5421060SN/A if (freeEntries == 0) { 5431060SN/A return(true); 5441060SN/A } else { 5451060SN/A return(false); 5461060SN/A } 5471060SN/A} 5481060SN/A 5491061SN/Atemplate <class Impl> 5502292SN/Abool 5516221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid) 5522292SN/A{ 5532292SN/A if (numFreeEntries(tid) == 0) { 5542292SN/A return(true); 5552292SN/A } else { 5562292SN/A return(false); 5572292SN/A } 5582292SN/A} 5592292SN/A 5602292SN/Atemplate <class Impl> 5612292SN/Abool 5622292SN/AInstructionQueue<Impl>::hasReadyInsts() 5632292SN/A{ 5642292SN/A if (!listOrder.empty()) { 5652292SN/A return true; 5662292SN/A } 5672292SN/A 5682292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5692292SN/A if (!readyInsts[i].empty()) { 5702292SN/A return true; 5712292SN/A } 5722292SN/A } 5732292SN/A 5742292SN/A return false; 5752292SN/A} 5762292SN/A 5772292SN/Atemplate <class Impl> 5781060SN/Avoid 57913429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insert(const DynInstPtr &new_inst) 5801060SN/A{ 58112110SRekai.GonzalezAlberquilla@arm.com if (new_inst->isFloating()) { 58212110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 58312110SRekai.GonzalezAlberquilla@arm.com } else if (new_inst->isVector()) { 58412110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 58512110SRekai.GonzalezAlberquilla@arm.com } else { 58612110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 58712110SRekai.GonzalezAlberquilla@arm.com } 5881060SN/A // Make sure the instruction is valid 5891060SN/A assert(new_inst); 5901060SN/A 5917720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5927720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 5931060SN/A 5941060SN/A assert(freeEntries != 0); 5951060SN/A 5962292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5971060SN/A 5982064SN/A --freeEntries; 5991060SN/A 6002292SN/A new_inst->setInIQ(); 6011060SN/A 6021060SN/A // Look through its source registers (physical regs), and mark any 6031060SN/A // dependencies. 6041060SN/A addToDependents(new_inst); 6051060SN/A 6061060SN/A // Have this instruction set itself as the producer of its destination 6071060SN/A // register(s). 6082326SN/A addToProducers(new_inst); 6091060SN/A 6101061SN/A if (new_inst->isMemRef()) { 6112292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 6121062SN/A } else { 6131062SN/A addIfReady(new_inst); 6141061SN/A } 6151061SN/A 6161062SN/A ++iqInstsAdded; 6171060SN/A 6182292SN/A count[new_inst->threadNumber]++; 6192292SN/A 6201060SN/A assert(freeEntries == (numEntries - countInsts())); 6211060SN/A} 6221060SN/A 6231061SN/Atemplate <class Impl> 6241061SN/Avoid 62513429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insertNonSpec(const DynInstPtr &new_inst) 6261061SN/A{ 6271061SN/A // @todo: Clean up this code; can do it by setting inst as unable 6281061SN/A // to issue, then calling normal insert on the inst. 62912110SRekai.GonzalezAlberquilla@arm.com if (new_inst->isFloating()) { 63012110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 63112110SRekai.GonzalezAlberquilla@arm.com } else if (new_inst->isVector()) { 63212110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 63312110SRekai.GonzalezAlberquilla@arm.com } else { 63412110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 63512110SRekai.GonzalezAlberquilla@arm.com } 6361061SN/A 6372292SN/A assert(new_inst); 6381061SN/A 6392292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 6401061SN/A 6417720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6422326SN/A "to the IQ.\n", 6437720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 6442064SN/A 6451061SN/A assert(freeEntries != 0); 6461061SN/A 6472292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6481061SN/A 6492064SN/A --freeEntries; 6501061SN/A 6512292SN/A new_inst->setInIQ(); 6521061SN/A 6531061SN/A // Have this instruction set itself as the producer of its destination 6541061SN/A // register(s). 6552326SN/A addToProducers(new_inst); 6561061SN/A 6571061SN/A // If it's a memory instruction, add it to the memory dependency 6581061SN/A // unit. 6592292SN/A if (new_inst->isMemRef()) { 6602292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6611061SN/A } 6621062SN/A 6631062SN/A ++iqNonSpecInstsAdded; 6642292SN/A 6652292SN/A count[new_inst->threadNumber]++; 6662292SN/A 6672292SN/A assert(freeEntries == (numEntries - countInsts())); 6681061SN/A} 6691061SN/A 6701061SN/Atemplate <class Impl> 6711060SN/Avoid 67213429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insertBarrier(const DynInstPtr &barr_inst) 6731060SN/A{ 6742292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6751060SN/A 6762292SN/A insertNonSpec(barr_inst); 6772292SN/A} 6781060SN/A 6792064SN/Atemplate <class Impl> 6802333SN/Atypename Impl::DynInstPtr 6812333SN/AInstructionQueue<Impl>::getInstToExecute() 6822333SN/A{ 6832333SN/A assert(!instsToExecute.empty()); 68413429Srekai.gonzalezalberquilla@arm.com DynInstPtr inst = std::move(instsToExecute.front()); 6852333SN/A instsToExecute.pop_front(); 68612110SRekai.GonzalezAlberquilla@arm.com if (inst->isFloating()) { 6877897Shestness@cs.utexas.edu fpInstQueueReads++; 68812110SRekai.GonzalezAlberquilla@arm.com } else if (inst->isVector()) { 68912110SRekai.GonzalezAlberquilla@arm.com vecInstQueueReads++; 6907897Shestness@cs.utexas.edu } else { 6917897Shestness@cs.utexas.edu intInstQueueReads++; 6927897Shestness@cs.utexas.edu } 6932333SN/A return inst; 6942333SN/A} 6951060SN/A 6962333SN/Atemplate <class Impl> 6972064SN/Avoid 6982292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6992292SN/A{ 7002292SN/A assert(!readyInsts[op_class].empty()); 7012292SN/A 7022292SN/A ListOrderEntry queue_entry; 7032292SN/A 7042292SN/A queue_entry.queueType = op_class; 7052292SN/A 7062292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7072292SN/A 7082292SN/A ListOrderIt list_it = listOrder.begin(); 7092292SN/A ListOrderIt list_end_it = listOrder.end(); 7102292SN/A 7112292SN/A while (list_it != list_end_it) { 7122292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 7132292SN/A break; 7142292SN/A } 7152292SN/A 7162292SN/A list_it++; 7171060SN/A } 7181060SN/A 7192292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 7202292SN/A queueOnList[op_class] = true; 7212292SN/A} 7221060SN/A 7232292SN/Atemplate <class Impl> 7242292SN/Avoid 7252292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 7262292SN/A{ 7272292SN/A // Get iterator of next item on the list 7282292SN/A // Delete the original iterator 7292292SN/A // Determine if the next item is either the end of the list or younger 7302292SN/A // than the new instruction. If so, then add in a new iterator right here. 7312292SN/A // If not, then move along. 7322292SN/A ListOrderEntry queue_entry; 7332292SN/A OpClass op_class = (*list_order_it).queueType; 7342292SN/A ListOrderIt next_it = list_order_it; 7352292SN/A 7362292SN/A ++next_it; 7372292SN/A 7382292SN/A queue_entry.queueType = op_class; 7392292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7402292SN/A 7412292SN/A while (next_it != listOrder.end() && 7422292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 7432292SN/A ++next_it; 7441060SN/A } 7451060SN/A 7462292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7471060SN/A} 7481060SN/A 7492292SN/Atemplate <class Impl> 7502292SN/Avoid 75113429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::processFUCompletion(const DynInstPtr &inst, int fu_idx) 7522292SN/A{ 7532367SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7549444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 7552292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7562292SN/A // long latency op). Wake it if it was. This may be overkill. 75710511Smitch.hayenga@arm.com --wbOutstanding; 7582292SN/A iewStage->wakeCPU(); 7592292SN/A 7602326SN/A if (fu_idx > -1) 7612326SN/A fuPool->freeUnitNextCycle(fu_idx); 7622292SN/A 7632326SN/A // @todo: Ensure that these FU Completions happen at the beginning 7642326SN/A // of a cycle, otherwise they could add too many instructions to 7652326SN/A // the queue. 7665327Smengke97@hotmail.com issueToExecuteQueue->access(-1)->size++; 7672333SN/A instsToExecute.push_back(inst); 7682292SN/A} 7692292SN/A 7701061SN/A// @todo: Figure out a better way to remove the squashed items from the 7711061SN/A// lists. Checking the top item of each list to see if it's squashed 7721061SN/A// wastes time and forces jumps. 7731061SN/Atemplate <class Impl> 7741060SN/Avoid 7751060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7761060SN/A{ 7772292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7782292SN/A "the IQ.\n"); 7791060SN/A 7801060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7811060SN/A 78210333Smitch.hayenga@arm.com DynInstPtr mem_inst; 78313429Srekai.gonzalezalberquilla@arm.com while (mem_inst = std::move(getDeferredMemInstToExecute())) { 78410333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 78510333Smitch.hayenga@arm.com } 78610333Smitch.hayenga@arm.com 78710333Smitch.hayenga@arm.com // See if any cache blocked instructions are able to be executed 78813429Srekai.gonzalezalberquilla@arm.com while (mem_inst = std::move(getBlockedMemInstToExecute())) { 78910333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 7907944SGiacomo.Gabrielli@arm.com } 7917944SGiacomo.Gabrielli@arm.com 7922292SN/A // Have iterator to head of the list 7932292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7942292SN/A // Try to get a FU that can do what this op needs. 7952292SN/A // If successful, change the oldestInst to the new top of the list, put 7962292SN/A // the queue in the proper place in the list. 7972292SN/A // Increment the iterator. 7982292SN/A // This will avoid trying to schedule a certain op class if there are no 7992292SN/A // FUs that handle it. 80010333Smitch.hayenga@arm.com int total_issued = 0; 8012292SN/A ListOrderIt order_it = listOrder.begin(); 8022292SN/A ListOrderIt order_end_it = listOrder.end(); 8031060SN/A 80410333Smitch.hayenga@arm.com while (total_issued < totalWidth && order_it != order_end_it) { 8052292SN/A OpClass op_class = (*order_it).queueType; 8061060SN/A 8072292SN/A assert(!readyInsts[op_class].empty()); 8081060SN/A 8092292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 8101060SN/A 81112110SRekai.GonzalezAlberquilla@arm.com if (issuing_inst->isFloating()) { 81212110SRekai.GonzalezAlberquilla@arm.com fpInstQueueReads++; 81312110SRekai.GonzalezAlberquilla@arm.com } else if (issuing_inst->isVector()) { 81412110SRekai.GonzalezAlberquilla@arm.com vecInstQueueReads++; 81512110SRekai.GonzalezAlberquilla@arm.com } else { 81612110SRekai.GonzalezAlberquilla@arm.com intInstQueueReads++; 81712110SRekai.GonzalezAlberquilla@arm.com } 8187897Shestness@cs.utexas.edu 8192292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 8201060SN/A 8212292SN/A if (issuing_inst->isSquashed()) { 8222292SN/A readyInsts[op_class].pop(); 8231060SN/A 8242292SN/A if (!readyInsts[op_class].empty()) { 8252292SN/A moveToYoungerInst(order_it); 8262292SN/A } else { 8272292SN/A readyIt[op_class] = listOrder.end(); 8282292SN/A queueOnList[op_class] = false; 8291060SN/A } 8301060SN/A 8312292SN/A listOrder.erase(order_it++); 8321060SN/A 8332292SN/A ++iqSquashedInstsIssued; 8342292SN/A 8352292SN/A continue; 8361060SN/A } 8371060SN/A 83811365SRekai.GonzalezAlberquilla@arm.com int idx = FUPool::NoCapableFU; 8399184Sandreas.hansson@arm.com Cycles op_latency = Cycles(1); 8406221Snate@binkert.org ThreadID tid = issuing_inst->threadNumber; 8411060SN/A 8422326SN/A if (op_class != No_OpClass) { 8432326SN/A idx = fuPool->getUnit(op_class); 84412110SRekai.GonzalezAlberquilla@arm.com if (issuing_inst->isFloating()) { 84512110SRekai.GonzalezAlberquilla@arm.com fpAluAccesses++; 84612110SRekai.GonzalezAlberquilla@arm.com } else if (issuing_inst->isVector()) { 84712110SRekai.GonzalezAlberquilla@arm.com vecAluAccesses++; 84812110SRekai.GonzalezAlberquilla@arm.com } else { 84912110SRekai.GonzalezAlberquilla@arm.com intAluAccesses++; 85012110SRekai.GonzalezAlberquilla@arm.com } 85111365SRekai.GonzalezAlberquilla@arm.com if (idx > FUPool::NoFreeFU) { 8522326SN/A op_latency = fuPool->getOpLatency(op_class); 8531060SN/A } 8541060SN/A } 8551060SN/A 8562348SN/A // If we have an instruction that doesn't require a FU, or a 8572348SN/A // valid FU, then schedule for execution. 85811365SRekai.GonzalezAlberquilla@arm.com if (idx != FUPool::NoFreeFU) { 8599184Sandreas.hansson@arm.com if (op_latency == Cycles(1)) { 8602292SN/A i2e_info->size++; 8612333SN/A instsToExecute.push_back(issuing_inst); 8621060SN/A 8632326SN/A // Add the FU onto the list of FU's to be freed next 8642326SN/A // cycle if we used one. 8652326SN/A if (idx >= 0) 8662326SN/A fuPool->freeUnitNextCycle(idx); 8672292SN/A } else { 86810807Snilay@cs.wisc.edu bool pipelined = fuPool->isPipelined(op_class); 8692326SN/A // Generate completion event for the FU 87010511Smitch.hayenga@arm.com ++wbOutstanding; 8712326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8722326SN/A idx, this); 8731060SN/A 8749180Sandreas.hansson@arm.com cpu->schedule(execution, 8759180Sandreas.hansson@arm.com cpu->clockEdge(Cycles(op_latency - 1))); 8761060SN/A 87710807Snilay@cs.wisc.edu if (!pipelined) { 8782348SN/A // If FU isn't pipelined, then it must be freed 8792348SN/A // upon the execution completing. 8802326SN/A execution->setFreeFU(); 8812292SN/A } else { 8822292SN/A // Add the FU onto the list of FU's to be freed next cycle. 8832326SN/A fuPool->freeUnitNextCycle(idx); 8842292SN/A } 8851060SN/A } 8861060SN/A 8877720Sgblack@eecs.umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8882292SN/A "[sn:%lli]\n", 8897720Sgblack@eecs.umich.edu tid, issuing_inst->pcState(), 8902292SN/A issuing_inst->seqNum); 8911060SN/A 8922292SN/A readyInsts[op_class].pop(); 8931061SN/A 8942292SN/A if (!readyInsts[op_class].empty()) { 8952292SN/A moveToYoungerInst(order_it); 8962292SN/A } else { 8972292SN/A readyIt[op_class] = listOrder.end(); 8982292SN/A queueOnList[op_class] = false; 8991060SN/A } 9001060SN/A 9012064SN/A issuing_inst->setIssued(); 9022292SN/A ++total_issued; 9032064SN/A 9048471SGiacomo.Gabrielli@arm.com#if TRACING_ON 9059046SAli.Saidi@ARM.com issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 9068471SGiacomo.Gabrielli@arm.com#endif 9078471SGiacomo.Gabrielli@arm.com 9082292SN/A if (!issuing_inst->isMemRef()) { 9092292SN/A // Memory instructions can not be freed from the IQ until they 9102292SN/A // complete. 9112292SN/A ++freeEntries; 9122301SN/A count[tid]--; 9132731Sktlim@umich.edu issuing_inst->clearInIQ(); 9142292SN/A } else { 9152301SN/A memDepUnit[tid].issue(issuing_inst); 9162292SN/A } 9172292SN/A 9182292SN/A listOrder.erase(order_it++); 9192326SN/A statIssuedInstType[tid][op_class]++; 9202292SN/A } else { 9212326SN/A statFuBusy[op_class]++; 9222326SN/A fuBusy[tid]++; 9232292SN/A ++order_it; 9241060SN/A } 9251060SN/A } 9261062SN/A 9272326SN/A numIssuedDist.sample(total_issued); 9282326SN/A iqInstsIssued+= total_issued; 9292307SN/A 9302348SN/A // If we issued any instructions, tell the CPU we had activity. 9318071SAli.Saidi@ARM.com // @todo If the way deferred memory instructions are handeled due to 9328071SAli.Saidi@ARM.com // translation changes then the deferredMemInsts condition should be removed 9338071SAli.Saidi@ARM.com // from the code below. 93410333Smitch.hayenga@arm.com if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) { 9352292SN/A cpu->activityThisCycle(); 9362292SN/A } else { 9372292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 9382292SN/A } 9391060SN/A} 9401060SN/A 9411061SN/Atemplate <class Impl> 9421060SN/Avoid 9431061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 9441060SN/A{ 9452292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 9462292SN/A "to execute.\n", inst); 9471062SN/A 9482292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9491060SN/A 9501061SN/A assert(inst_it != nonSpecInsts.end()); 9511060SN/A 9526221Snate@binkert.org ThreadID tid = (*inst_it).second->threadNumber; 9532292SN/A 9544033Sktlim@umich.edu (*inst_it).second->setAtCommit(); 9554033Sktlim@umich.edu 9561061SN/A (*inst_it).second->setCanIssue(); 9571060SN/A 9581062SN/A if (!(*inst_it).second->isMemRef()) { 9591062SN/A addIfReady((*inst_it).second); 9601062SN/A } else { 9612292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9621062SN/A } 9631060SN/A 9642292SN/A (*inst_it).second = NULL; 9652292SN/A 9661061SN/A nonSpecInsts.erase(inst_it); 9671060SN/A} 9681060SN/A 9691061SN/Atemplate <class Impl> 9701061SN/Avoid 9716221Snate@binkert.orgInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9722292SN/A{ 9732292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9742292SN/A tid,inst); 9752292SN/A 9762292SN/A ListIt iq_it = instList[tid].begin(); 9772292SN/A 9782292SN/A while (iq_it != instList[tid].end() && 9792292SN/A (*iq_it)->seqNum <= inst) { 9802292SN/A ++iq_it; 9812292SN/A instList[tid].pop_front(); 9822292SN/A } 9832292SN/A 9842292SN/A assert(freeEntries == (numEntries - countInsts())); 9852292SN/A} 9862292SN/A 9872292SN/Atemplate <class Impl> 9882301SN/Aint 98913429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::wakeDependents(const DynInstPtr &completed_inst) 9901684SN/A{ 9912301SN/A int dependents = 0; 9922301SN/A 9937897Shestness@cs.utexas.edu // The instruction queue here takes care of both floating and int ops 9947897Shestness@cs.utexas.edu if (completed_inst->isFloating()) { 99512110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWakeupAccesses++; 99612110SRekai.GonzalezAlberquilla@arm.com } else if (completed_inst->isVector()) { 99712110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWakeupAccesses++; 9987897Shestness@cs.utexas.edu } else { 9997897Shestness@cs.utexas.edu intInstQueueWakeupAccesses++; 10007897Shestness@cs.utexas.edu } 10017897Shestness@cs.utexas.edu 10022292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 10032292SN/A 10042292SN/A assert(!completed_inst->isSquashed()); 10051684SN/A 10061684SN/A // Tell the memory dependence unit to wake any dependents on this 10072292SN/A // instruction if it is a memory instruction. Also complete the memory 10082326SN/A // instruction at this point since we know it executed without issues. 10092326SN/A // @todo: Might want to rename "completeMemInst" to something that 10102326SN/A // indicates that it won't need to be replayed, and call this 10112326SN/A // earlier. Might not be a big deal. 10121684SN/A if (completed_inst->isMemRef()) { 10132292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 10142292SN/A completeMemInst(completed_inst); 10152292SN/A } else if (completed_inst->isMemBarrier() || 10162292SN/A completed_inst->isWriteBarrier()) { 10172292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 10181684SN/A } 10191684SN/A 10201684SN/A for (int dest_reg_idx = 0; 10211684SN/A dest_reg_idx < completed_inst->numDestRegs(); 10221684SN/A dest_reg_idx++) 10231684SN/A { 102412105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = 10251684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 10261684SN/A 10271684SN/A // Special case of uniq or control registers. They are not 10281684SN/A // handled by the IQ and thus have no dependency graph entry. 102912105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 103012105Snathanael.premillieu@arm.com DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n", 103112106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className()); 10321684SN/A continue; 10331684SN/A } 10341684SN/A 103512105Snathanael.premillieu@arm.com DPRINTF(IQ, "Waking any dependents on register %i (%s).\n", 103612106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), 103712106SRekai.GonzalezAlberquilla@arm.com dest_reg->className()); 10381684SN/A 10392326SN/A //Go through the dependency chain, marking the registers as 10402326SN/A //ready within the waiting instructions. 104112106SRekai.GonzalezAlberquilla@arm.com DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10421684SN/A 10432326SN/A while (dep_inst) { 10447599Sminkyu.jeong@arm.com DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 10457720Sgblack@eecs.umich.edu "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 10461684SN/A 10471684SN/A // Might want to give more information to the instruction 10482326SN/A // so that it knows which of its source registers is 10492326SN/A // ready. However that would mean that the dependency 10502326SN/A // graph entries would need to hold the src_reg_idx. 10512326SN/A dep_inst->markSrcRegReady(); 10521684SN/A 10532326SN/A addIfReady(dep_inst); 10541684SN/A 105512106SRekai.GonzalezAlberquilla@arm.com dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10561684SN/A 10572301SN/A ++dependents; 10581684SN/A } 10591684SN/A 10602326SN/A // Reset the head node now that all of its dependents have 10612326SN/A // been woken up. 106212106SRekai.GonzalezAlberquilla@arm.com assert(dependGraph.empty(dest_reg->flatIndex())); 106312106SRekai.GonzalezAlberquilla@arm.com dependGraph.clearInst(dest_reg->flatIndex()); 10641684SN/A 10651684SN/A // Mark the scoreboard as having that register ready. 106612106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = true; 10671684SN/A } 10682301SN/A return dependents; 10692064SN/A} 10702064SN/A 10712064SN/Atemplate <class Impl> 10722064SN/Avoid 107313429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addReadyMemInst(const DynInstPtr &ready_inst) 10742064SN/A{ 10752292SN/A OpClass op_class = ready_inst->opClass(); 10762292SN/A 10772292SN/A readyInsts[op_class].push(ready_inst); 10782292SN/A 10792326SN/A // Will need to reorder the list if either a queue is not on the list, 10802326SN/A // or it has an older instruction than last time. 10812326SN/A if (!queueOnList[op_class]) { 10822326SN/A addToOrderList(op_class); 10832326SN/A } else if (readyInsts[op_class].top()->seqNum < 10842326SN/A (*readyIt[op_class]).oldestInst) { 10852326SN/A listOrder.erase(readyIt[op_class]); 10862326SN/A addToOrderList(op_class); 10872326SN/A } 10882326SN/A 10892292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10907720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 10917720Sgblack@eecs.umich.edu ready_inst->pcState(), op_class, ready_inst->seqNum); 10922064SN/A} 10932064SN/A 10942064SN/Atemplate <class Impl> 10952064SN/Avoid 109613429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::rescheduleMemInst(const DynInstPtr &resched_inst) 10972064SN/A{ 10984033Sktlim@umich.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 10997944SGiacomo.Gabrielli@arm.com 11007944SGiacomo.Gabrielli@arm.com // Reset DTB translation state 11019046SAli.Saidi@ARM.com resched_inst->translationStarted(false); 11029046SAli.Saidi@ARM.com resched_inst->translationCompleted(false); 11037944SGiacomo.Gabrielli@arm.com 11044033Sktlim@umich.edu resched_inst->clearCanIssue(); 11052292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 11062064SN/A} 11072064SN/A 11082064SN/Atemplate <class Impl> 11092064SN/Avoid 111013429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::replayMemInst(const DynInstPtr &replay_inst) 11112064SN/A{ 111210333Smitch.hayenga@arm.com memDepUnit[replay_inst->threadNumber].replay(); 11132292SN/A} 11142292SN/A 11152292SN/Atemplate <class Impl> 11162292SN/Avoid 111713429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::completeMemInst(const DynInstPtr &completed_inst) 11182292SN/A{ 11196221Snate@binkert.org ThreadID tid = completed_inst->threadNumber; 11202292SN/A 11217720Sgblack@eecs.umich.edu DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 11227720Sgblack@eecs.umich.edu completed_inst->pcState(), completed_inst->seqNum); 11232292SN/A 11242292SN/A ++freeEntries; 11252292SN/A 11269046SAli.Saidi@ARM.com completed_inst->memOpDone(true); 11272292SN/A 11282292SN/A memDepUnit[tid].completed(completed_inst); 11292292SN/A count[tid]--; 11301684SN/A} 11311684SN/A 11321684SN/Atemplate <class Impl> 11331684SN/Avoid 113413429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::deferMemInst(const DynInstPtr &deferred_inst) 11357944SGiacomo.Gabrielli@arm.com{ 11367944SGiacomo.Gabrielli@arm.com deferredMemInsts.push_back(deferred_inst); 11377944SGiacomo.Gabrielli@arm.com} 11387944SGiacomo.Gabrielli@arm.com 11397944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 114010333Smitch.hayenga@arm.comvoid 114113429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::blockMemInst(const DynInstPtr &blocked_inst) 114210333Smitch.hayenga@arm.com{ 114310333Smitch.hayenga@arm.com blocked_inst->translationStarted(false); 114410333Smitch.hayenga@arm.com blocked_inst->translationCompleted(false); 114510333Smitch.hayenga@arm.com 114610333Smitch.hayenga@arm.com blocked_inst->clearIssued(); 114710333Smitch.hayenga@arm.com blocked_inst->clearCanIssue(); 114810333Smitch.hayenga@arm.com blockedMemInsts.push_back(blocked_inst); 114910333Smitch.hayenga@arm.com} 115010333Smitch.hayenga@arm.com 115110333Smitch.hayenga@arm.comtemplate <class Impl> 115210333Smitch.hayenga@arm.comvoid 115310333Smitch.hayenga@arm.comInstructionQueue<Impl>::cacheUnblocked() 115410333Smitch.hayenga@arm.com{ 115510333Smitch.hayenga@arm.com retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts); 115610333Smitch.hayenga@arm.com // Get the CPU ticking again 115710333Smitch.hayenga@arm.com cpu->wakeCPU(); 115810333Smitch.hayenga@arm.com} 115910333Smitch.hayenga@arm.com 116010333Smitch.hayenga@arm.comtemplate <class Impl> 11617944SGiacomo.Gabrielli@arm.comtypename Impl::DynInstPtr 11627944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::getDeferredMemInstToExecute() 11637944SGiacomo.Gabrielli@arm.com{ 11647944SGiacomo.Gabrielli@arm.com for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 11657944SGiacomo.Gabrielli@arm.com ++it) { 11669046SAli.Saidi@ARM.com if ((*it)->translationCompleted() || (*it)->isSquashed()) { 116713429Srekai.gonzalezalberquilla@arm.com DynInstPtr mem_inst = std::move(*it); 11687944SGiacomo.Gabrielli@arm.com deferredMemInsts.erase(it); 116910333Smitch.hayenga@arm.com return mem_inst; 11707944SGiacomo.Gabrielli@arm.com } 11717944SGiacomo.Gabrielli@arm.com } 117210333Smitch.hayenga@arm.com return nullptr; 117310333Smitch.hayenga@arm.com} 117410333Smitch.hayenga@arm.com 117510333Smitch.hayenga@arm.comtemplate <class Impl> 117610333Smitch.hayenga@arm.comtypename Impl::DynInstPtr 117710333Smitch.hayenga@arm.comInstructionQueue<Impl>::getBlockedMemInstToExecute() 117810333Smitch.hayenga@arm.com{ 117910333Smitch.hayenga@arm.com if (retryMemInsts.empty()) { 118010333Smitch.hayenga@arm.com return nullptr; 118110333Smitch.hayenga@arm.com } else { 118213429Srekai.gonzalezalberquilla@arm.com DynInstPtr mem_inst = std::move(retryMemInsts.front()); 118310333Smitch.hayenga@arm.com retryMemInsts.pop_front(); 118410333Smitch.hayenga@arm.com return mem_inst; 118510333Smitch.hayenga@arm.com } 11867944SGiacomo.Gabrielli@arm.com} 11877944SGiacomo.Gabrielli@arm.com 11887944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 11897944SGiacomo.Gabrielli@arm.comvoid 119013429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::violation(const DynInstPtr &store, 119113429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &faulting_load) 11921061SN/A{ 11937897Shestness@cs.utexas.edu intInstQueueWrites++; 11942292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 11951061SN/A} 11961061SN/A 11971061SN/Atemplate <class Impl> 11981060SN/Avoid 11996221Snate@binkert.orgInstructionQueue<Impl>::squash(ThreadID tid) 12001060SN/A{ 12012292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 12022292SN/A "the IQ.\n", tid); 12031060SN/A 12041060SN/A // Read instruction sequence number of last instruction out of the 12051060SN/A // time buffer. 12062292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 12071060SN/A 120810797Sbrandon.potter@amd.com doSquash(tid); 12091061SN/A 12101061SN/A // Also tell the memory dependence unit to squash. 12112292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 12121060SN/A} 12131060SN/A 12141061SN/Atemplate <class Impl> 12151061SN/Avoid 12166221Snate@binkert.orgInstructionQueue<Impl>::doSquash(ThreadID tid) 12171061SN/A{ 12182326SN/A // Start at the tail. 12192326SN/A ListIt squash_it = instList[tid].end(); 12202326SN/A --squash_it; 12211061SN/A 12222292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 12232292SN/A tid, squashedSeqNum[tid]); 12241061SN/A 12251061SN/A // Squash any instructions younger than the squashed sequence number 12261061SN/A // given. 12272326SN/A while (squash_it != instList[tid].end() && 12282326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 12292292SN/A 12302326SN/A DynInstPtr squashed_inst = (*squash_it); 123112110SRekai.GonzalezAlberquilla@arm.com if (squashed_inst->isFloating()) { 123212110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 123312110SRekai.GonzalezAlberquilla@arm.com } else if (squashed_inst->isVector()) { 123412110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 123512110SRekai.GonzalezAlberquilla@arm.com } else { 123612110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 123712110SRekai.GonzalezAlberquilla@arm.com } 12381061SN/A 12391061SN/A // Only handle the instruction if it actually is in the IQ and 12401061SN/A // hasn't already been squashed in the IQ. 12412292SN/A if (squashed_inst->threadNumber != tid || 12422292SN/A squashed_inst->isSquashedInIQ()) { 12432326SN/A --squash_it; 12442292SN/A continue; 12452292SN/A } 12462292SN/A 12472292SN/A if (!squashed_inst->isIssued() || 12482292SN/A (squashed_inst->isMemRef() && 12499046SAli.Saidi@ARM.com !squashed_inst->memOpDone())) { 12501062SN/A 12517720Sgblack@eecs.umich.edu DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 12527720Sgblack@eecs.umich.edu tid, squashed_inst->seqNum, squashed_inst->pcState()); 12532367SN/A 125410032SGiacomo.Gabrielli@arm.com bool is_acq_rel = squashed_inst->isMemBarrier() && 125510032SGiacomo.Gabrielli@arm.com (squashed_inst->isLoad() || 125610032SGiacomo.Gabrielli@arm.com (squashed_inst->isStore() && 125710032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional())); 125810032SGiacomo.Gabrielli@arm.com 12591061SN/A // Remove the instruction from the dependency list. 126010032SGiacomo.Gabrielli@arm.com if (is_acq_rel || 126110032SGiacomo.Gabrielli@arm.com (!squashed_inst->isNonSpeculative() && 126210032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional() && 126310032SGiacomo.Gabrielli@arm.com !squashed_inst->isMemBarrier() && 126410032SGiacomo.Gabrielli@arm.com !squashed_inst->isWriteBarrier())) { 12651061SN/A 12661061SN/A for (int src_reg_idx = 0; 12671681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 12681061SN/A src_reg_idx++) 12691061SN/A { 127012105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = 12711061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 12721061SN/A 12732326SN/A // Only remove it from the dependency graph if it 12742326SN/A // was placed there in the first place. 12752326SN/A 12762326SN/A // Instead of doing a linked list traversal, we 12772326SN/A // can just remove these squashed instructions 12782326SN/A // either at issue time, or when the register is 12792326SN/A // overwritten. The only downside to this is it 12802326SN/A // leaves more room for error. 12812292SN/A 12821061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 128312105Snathanael.premillieu@arm.com !src_reg->isFixedMapping()) { 128412106SRekai.GonzalezAlberquilla@arm.com dependGraph.remove(src_reg->flatIndex(), 128512106SRekai.GonzalezAlberquilla@arm.com squashed_inst); 12861061SN/A } 12871062SN/A 12882292SN/A 12891062SN/A ++iqSquashedOperandsExamined; 12901061SN/A } 12914033Sktlim@umich.edu } else if (!squashed_inst->isStoreConditional() || 12924033Sktlim@umich.edu !squashed_inst->isCompleted()) { 12932292SN/A NonSpecMapIt ns_inst_it = 12942292SN/A nonSpecInsts.find(squashed_inst->seqNum); 12958275SAli.Saidi@ARM.com 129610017Sandreas.hansson@arm.com // we remove non-speculative instructions from 129710017Sandreas.hansson@arm.com // nonSpecInsts already when they are ready, and so we 129810017Sandreas.hansson@arm.com // cannot always expect to find them 12994033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 130010017Sandreas.hansson@arm.com // loads that became ready but stalled on a 130110017Sandreas.hansson@arm.com // blocked cache are alreayd removed from 130210017Sandreas.hansson@arm.com // nonSpecInsts, and have not faulted 130310017Sandreas.hansson@arm.com assert(squashed_inst->getFault() != NoFault || 130410017Sandreas.hansson@arm.com squashed_inst->isMemRef()); 13054033Sktlim@umich.edu } else { 13061062SN/A 13074033Sktlim@umich.edu (*ns_inst_it).second = NULL; 13081681SN/A 13094033Sktlim@umich.edu nonSpecInsts.erase(ns_inst_it); 13101062SN/A 13114033Sktlim@umich.edu ++iqSquashedNonSpecRemoved; 13124033Sktlim@umich.edu } 13131061SN/A } 13141061SN/A 13151061SN/A // Might want to also clear out the head of the dependency graph. 13161061SN/A 13171061SN/A // Mark it as squashed within the IQ. 13181061SN/A squashed_inst->setSquashedInIQ(); 13191061SN/A 13202292SN/A // @todo: Remove this hack where several statuses are set so the 13212292SN/A // inst will flow through the rest of the pipeline. 13221681SN/A squashed_inst->setIssued(); 13231681SN/A squashed_inst->setCanCommit(); 13242731Sktlim@umich.edu squashed_inst->clearInIQ(); 13252292SN/A 13262292SN/A //Update Thread IQ Count 13272292SN/A count[squashed_inst->threadNumber]--; 13281681SN/A 13291681SN/A ++freeEntries; 13301061SN/A } 13311061SN/A 133212833Sjang.hanhwi@gmail.com // IQ clears out the heads of the dependency graph only when 133312833Sjang.hanhwi@gmail.com // instructions reach writeback stage. If an instruction is squashed 133412833Sjang.hanhwi@gmail.com // before writeback stage, its head of dependency graph would not be 133512833Sjang.hanhwi@gmail.com // cleared out; it holds the instruction's DynInstPtr. This prevents 133612833Sjang.hanhwi@gmail.com // freeing the squashed instruction's DynInst. 133712833Sjang.hanhwi@gmail.com // Thus, we need to manually clear out the squashed instructions' heads 133812833Sjang.hanhwi@gmail.com // of dependency graph. 133912833Sjang.hanhwi@gmail.com for (int dest_reg_idx = 0; 134012833Sjang.hanhwi@gmail.com dest_reg_idx < squashed_inst->numDestRegs(); 134112833Sjang.hanhwi@gmail.com dest_reg_idx++) 134212833Sjang.hanhwi@gmail.com { 134312833Sjang.hanhwi@gmail.com PhysRegIdPtr dest_reg = 134412833Sjang.hanhwi@gmail.com squashed_inst->renamedDestRegIdx(dest_reg_idx); 134512833Sjang.hanhwi@gmail.com if (dest_reg->isFixedMapping()){ 134612833Sjang.hanhwi@gmail.com continue; 134712833Sjang.hanhwi@gmail.com } 134812833Sjang.hanhwi@gmail.com assert(dependGraph.empty(dest_reg->flatIndex())); 134912833Sjang.hanhwi@gmail.com dependGraph.clearInst(dest_reg->flatIndex()); 135012833Sjang.hanhwi@gmail.com } 13512326SN/A instList[tid].erase(squash_it--); 13521062SN/A ++iqSquashedInstsExamined; 13531061SN/A } 13541060SN/A} 13551060SN/A 13561061SN/Atemplate <class Impl> 13571060SN/Abool 135813429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addToDependents(const DynInstPtr &new_inst) 13591060SN/A{ 13601060SN/A // Loop through the instruction's source registers, adding 13611060SN/A // them to the dependency list if they are not ready. 13621060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 13631060SN/A bool return_val = false; 13641060SN/A 13651060SN/A for (int src_reg_idx = 0; 13661060SN/A src_reg_idx < total_src_regs; 13671060SN/A src_reg_idx++) 13681060SN/A { 13691060SN/A // Only add it to the dependency graph if it's not ready. 13701060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 137112105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 13721060SN/A 13731060SN/A // Check the IQ's scoreboard to make sure the register 13741060SN/A // hasn't become ready while the instruction was in flight 13751060SN/A // between stages. Only if it really isn't ready should 13761060SN/A // it be added to the dependency graph. 137712105Snathanael.premillieu@arm.com if (src_reg->isFixedMapping()) { 13781061SN/A continue; 137912106SRekai.GonzalezAlberquilla@arm.com } else if (!regScoreboard[src_reg->flatIndex()]) { 138012105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13811060SN/A "is being added to the dependency chain.\n", 138212106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 138312106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 13841060SN/A 138512106SRekai.GonzalezAlberquilla@arm.com dependGraph.insert(src_reg->flatIndex(), new_inst); 13861060SN/A 13871060SN/A // Change the return value to indicate that something 13881060SN/A // was added to the dependency graph. 13891060SN/A return_val = true; 13901060SN/A } else { 139112105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13921060SN/A "became ready before it reached the IQ.\n", 139312106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 139412106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 13951060SN/A // Mark a register ready within the instruction. 13962326SN/A new_inst->markSrcRegReady(src_reg_idx); 13971060SN/A } 13981060SN/A } 13991060SN/A } 14001060SN/A 14011060SN/A return return_val; 14021060SN/A} 14031060SN/A 14041061SN/Atemplate <class Impl> 14051060SN/Avoid 140613429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addToProducers(const DynInstPtr &new_inst) 14071060SN/A{ 14082326SN/A // Nothing really needs to be marked when an instruction becomes 14092326SN/A // the producer of a register's value, but for convenience a ptr 14102326SN/A // to the producing instruction will be placed in the head node of 14112326SN/A // the dependency links. 14121060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 14131060SN/A 14141060SN/A for (int dest_reg_idx = 0; 14151060SN/A dest_reg_idx < total_dest_regs; 14161060SN/A dest_reg_idx++) 14171060SN/A { 141812105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 14191061SN/A 142012105Snathanael.premillieu@arm.com // Some registers have fixed mapping, and there is no need to track 14211061SN/A // dependencies as these instructions must be executed at commit. 142212105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 14231061SN/A continue; 14241060SN/A } 14251060SN/A 142612106SRekai.GonzalezAlberquilla@arm.com if (!dependGraph.empty(dest_reg->flatIndex())) { 14272326SN/A dependGraph.dump(); 142812105Snathanael.premillieu@arm.com panic("Dependency graph %i (%s) (flat: %i) not empty!", 142912106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className(), 143012106SRekai.GonzalezAlberquilla@arm.com dest_reg->flatIndex()); 14312064SN/A } 14321062SN/A 143312106SRekai.GonzalezAlberquilla@arm.com dependGraph.setInst(dest_reg->flatIndex(), new_inst); 14341062SN/A 14351060SN/A // Mark the scoreboard to say it's not yet ready. 143612106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = false; 14371060SN/A } 14381060SN/A} 14391060SN/A 14401061SN/Atemplate <class Impl> 14411060SN/Avoid 144213429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addIfReady(const DynInstPtr &inst) 14431060SN/A{ 14442326SN/A // If the instruction now has all of its source registers 14451060SN/A // available, then add it to the list of ready instructions. 14461060SN/A if (inst->readyToIssue()) { 14471061SN/A 14481060SN/A //Add the instruction to the proper ready list. 14492292SN/A if (inst->isMemRef()) { 14501061SN/A 14512292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 14521061SN/A 14531062SN/A // Message to the mem dependence unit that this instruction has 14541062SN/A // its registers ready. 14552292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 14561062SN/A 14572292SN/A return; 14582292SN/A } 14591062SN/A 14602292SN/A OpClass op_class = inst->opClass(); 14611061SN/A 14622292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 14637720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 14647720Sgblack@eecs.umich.edu inst->pcState(), op_class, inst->seqNum); 14651061SN/A 14662292SN/A readyInsts[op_class].push(inst); 14671061SN/A 14682326SN/A // Will need to reorder the list if either a queue is not on the list, 14692326SN/A // or it has an older instruction than last time. 14702326SN/A if (!queueOnList[op_class]) { 14712326SN/A addToOrderList(op_class); 14722326SN/A } else if (readyInsts[op_class].top()->seqNum < 14732326SN/A (*readyIt[op_class]).oldestInst) { 14742326SN/A listOrder.erase(readyIt[op_class]); 14752326SN/A addToOrderList(op_class); 14761060SN/A } 14771060SN/A } 14781060SN/A} 14791060SN/A 14801061SN/Atemplate <class Impl> 14811061SN/Aint 14821061SN/AInstructionQueue<Impl>::countInsts() 14831061SN/A{ 14842698Sktlim@umich.edu#if 0 14852292SN/A //ksewell:This works but definitely could use a cleaner write 14862292SN/A //with a more intuitive way of counting. Right now it's 14872292SN/A //just brute force .... 14882698Sktlim@umich.edu // Change the #if if you want to use this method. 14891061SN/A int total_insts = 0; 14901061SN/A 14916221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 14926221Snate@binkert.org ListIt count_it = instList[tid].begin(); 14931681SN/A 14946221Snate@binkert.org while (count_it != instList[tid].end()) { 14952292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 14962292SN/A if (!(*count_it)->isIssued()) { 14972292SN/A ++total_insts; 14982292SN/A } else if ((*count_it)->isMemRef() && 14992292SN/A !(*count_it)->memOpDone) { 15002292SN/A // Loads that have not been marked as executed still count 15012292SN/A // towards the total instructions. 15022292SN/A ++total_insts; 15032292SN/A } 15042292SN/A } 15052292SN/A 15062292SN/A ++count_it; 15071061SN/A } 15081061SN/A } 15091061SN/A 15101061SN/A return total_insts; 15112292SN/A#else 15122292SN/A return numEntries - freeEntries; 15132292SN/A#endif 15141681SN/A} 15151681SN/A 15161681SN/Atemplate <class Impl> 15171681SN/Avoid 15181061SN/AInstructionQueue<Impl>::dumpLists() 15191061SN/A{ 15202292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 15212292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 15221061SN/A 15232292SN/A cprintf("\n"); 15242292SN/A } 15251061SN/A 15261061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 15271061SN/A 15282292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 15292292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 15301061SN/A 15311061SN/A cprintf("Non speculative list: "); 15321061SN/A 15332292SN/A while (non_spec_it != non_spec_end_it) { 15347720Sgblack@eecs.umich.edu cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 15352292SN/A (*non_spec_it).second->seqNum); 15361061SN/A ++non_spec_it; 15371061SN/A } 15381061SN/A 15391061SN/A cprintf("\n"); 15401061SN/A 15412292SN/A ListOrderIt list_order_it = listOrder.begin(); 15422292SN/A ListOrderIt list_order_end_it = listOrder.end(); 15432292SN/A int i = 1; 15442292SN/A 15452292SN/A cprintf("List order: "); 15462292SN/A 15472292SN/A while (list_order_it != list_order_end_it) { 15482292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 15492292SN/A (*list_order_it).oldestInst); 15502292SN/A 15512292SN/A ++list_order_it; 15522292SN/A ++i; 15532292SN/A } 15542292SN/A 15552292SN/A cprintf("\n"); 15561061SN/A} 15572292SN/A 15582292SN/A 15592292SN/Atemplate <class Impl> 15602292SN/Avoid 15612292SN/AInstructionQueue<Impl>::dumpInsts() 15622292SN/A{ 15636221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 15642292SN/A int num = 0; 15652292SN/A int valid_num = 0; 15666221Snate@binkert.org ListIt inst_list_it = instList[tid].begin(); 15672292SN/A 15686221Snate@binkert.org while (inst_list_it != instList[tid].end()) { 15696221Snate@binkert.org cprintf("Instruction:%i\n", num); 15702292SN/A if (!(*inst_list_it)->isSquashed()) { 15712292SN/A if (!(*inst_list_it)->isIssued()) { 15722292SN/A ++valid_num; 15732292SN/A cprintf("Count:%i\n", valid_num); 15742292SN/A } else if ((*inst_list_it)->isMemRef() && 15759046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 15762326SN/A // Loads that have not been marked as executed 15772326SN/A // still count towards the total instructions. 15782292SN/A ++valid_num; 15792292SN/A cprintf("Count:%i\n", valid_num); 15802292SN/A } 15812292SN/A } 15822292SN/A 15837720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 15842292SN/A "Issued:%i\nSquashed:%i\n", 15857720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 15862292SN/A (*inst_list_it)->seqNum, 15872292SN/A (*inst_list_it)->threadNumber, 15882292SN/A (*inst_list_it)->isIssued(), 15892292SN/A (*inst_list_it)->isSquashed()); 15902292SN/A 15912292SN/A if ((*inst_list_it)->isMemRef()) { 15929046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 15932292SN/A } 15942292SN/A 15952292SN/A cprintf("\n"); 15962292SN/A 15972292SN/A inst_list_it++; 15982292SN/A ++num; 15992292SN/A } 16002292SN/A } 16012348SN/A 16022348SN/A cprintf("Insts to Execute list:\n"); 16032348SN/A 16042348SN/A int num = 0; 16052348SN/A int valid_num = 0; 16062348SN/A ListIt inst_list_it = instsToExecute.begin(); 16072348SN/A 16082348SN/A while (inst_list_it != instsToExecute.end()) 16092348SN/A { 16102348SN/A cprintf("Instruction:%i\n", 16112348SN/A num); 16122348SN/A if (!(*inst_list_it)->isSquashed()) { 16132348SN/A if (!(*inst_list_it)->isIssued()) { 16142348SN/A ++valid_num; 16152348SN/A cprintf("Count:%i\n", valid_num); 16162348SN/A } else if ((*inst_list_it)->isMemRef() && 16179046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 16182348SN/A // Loads that have not been marked as executed 16192348SN/A // still count towards the total instructions. 16202348SN/A ++valid_num; 16212348SN/A cprintf("Count:%i\n", valid_num); 16222348SN/A } 16232348SN/A } 16242348SN/A 16257720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 16262348SN/A "Issued:%i\nSquashed:%i\n", 16277720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 16282348SN/A (*inst_list_it)->seqNum, 16292348SN/A (*inst_list_it)->threadNumber, 16302348SN/A (*inst_list_it)->isIssued(), 16312348SN/A (*inst_list_it)->isSquashed()); 16322348SN/A 16332348SN/A if ((*inst_list_it)->isMemRef()) { 16349046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 16352348SN/A } 16362348SN/A 16372348SN/A cprintf("\n"); 16382348SN/A 16392348SN/A inst_list_it++; 16402348SN/A ++num; 16412348SN/A } 16422292SN/A} 16439944Smatt.horsnell@ARM.com 16449944Smatt.horsnell@ARM.com#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1645