inst_queue_impl.hh revision 13453
11689SN/A/* 210333Smitch.hayenga@arm.com * Copyright (c) 2011-2014 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422831Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_INST_QUEUE_IMPL_HH__ 479944Smatt.horsnell@ARM.com 482064SN/A#include <limits> 491060SN/A#include <vector> 501060SN/A 5113449Sgabeblack@google.com#include "base/logging.hh" 522292SN/A#include "cpu/o3/fu_pool.hh" 531717SN/A#include "cpu/o3/inst_queue.hh" 548232Snate@binkert.org#include "debug/IQ.hh" 554762Snate@binkert.org#include "enums/OpClass.hh" 566221Snate@binkert.org#include "params/DerivO3CPU.hh" 574762Snate@binkert.org#include "sim/core.hh" 581060SN/A 598737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 608737Skoansin.tan@gmail.com// we open up the entire namespace std 618737Skoansin.tan@gmail.comusing std::list; 625529Snate@binkert.org 631061SN/Atemplate <class Impl> 6413429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::FUCompletion::FUCompletion(const DynInstPtr &_inst, 655606Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 668581Ssteve.reinhardt@amd.com : Event(Stat_Event_Pri, AutoDelete), 678581Ssteve.reinhardt@amd.com inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 681060SN/A{ 692292SN/A} 702292SN/A 712292SN/Atemplate <class Impl> 722292SN/Avoid 732292SN/AInstructionQueue<Impl>::FUCompletion::process() 742292SN/A{ 752326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 762292SN/A inst = NULL; 772292SN/A} 782292SN/A 792292SN/A 802292SN/Atemplate <class Impl> 812292SN/Aconst char * 825336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const 832292SN/A{ 844873Sstever@eecs.umich.edu return "Functional unit completion"; 852292SN/A} 862292SN/A 872292SN/Atemplate <class Impl> 884329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 895529Snate@binkert.org DerivO3CPUParams *params) 904329Sktlim@umich.edu : cpu(cpu_ptr), 914329Sktlim@umich.edu iewStage(iew_ptr), 924329Sktlim@umich.edu fuPool(params->fuPool), 932292SN/A numEntries(params->numIQEntries), 942292SN/A totalWidth(params->issueWidth), 952292SN/A commitToIEWDelay(params->commitToIEWDelay) 962292SN/A{ 972292SN/A assert(fuPool); 982292SN/A 995529Snate@binkert.org numThreads = params->numThreads; 1001060SN/A 1019920Syasuko.eckert@amd.com // Set the number of total physical registers 10212109SRekai.GonzalezAlberquilla@arm.com // As the vector registers have two addressing modes, they are added twice 1039920Syasuko.eckert@amd.com numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 10412109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs + 10512109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs * TheISA::NumVecElemPerVecReg + 10612109SRekai.GonzalezAlberquilla@arm.com params->numPhysCCRegs; 1071060SN/A 1081060SN/A //Create an entry for each physical register within the 1091060SN/A //dependency graph. 1102326SN/A dependGraph.resize(numPhysRegs); 1111060SN/A 1121060SN/A // Resize the register scoreboard. 1131060SN/A regScoreboard.resize(numPhysRegs); 1141060SN/A 1152292SN/A //Initialize Mem Dependence Units 11613453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 1176221Snate@binkert.org memDepUnit[tid].init(params, tid); 1186221Snate@binkert.org memDepUnit[tid].setIQ(this); 1191060SN/A } 1201060SN/A 1212307SN/A resetState(); 1222292SN/A 1232980Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1242292SN/A 1252292SN/A //Convert string to lowercase 1262292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1272292SN/A (int(*)(int)) tolower); 1282292SN/A 1292292SN/A //Figure out resource sharing policy 1302292SN/A if (policy == "dynamic") { 1312292SN/A iqPolicy = Dynamic; 1322292SN/A 1332292SN/A //Set Max Entries to Total ROB Capacity 1346221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1356221Snate@binkert.org maxEntries[tid] = numEntries; 1362292SN/A } 1372292SN/A 1382292SN/A } else if (policy == "partitioned") { 1392292SN/A iqPolicy = Partitioned; 1402292SN/A 1412292SN/A //@todo:make work if part_amt doesnt divide evenly. 1422292SN/A int part_amt = numEntries / numThreads; 1432292SN/A 1442292SN/A //Divide ROB up evenly 1456221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1466221Snate@binkert.org maxEntries[tid] = part_amt; 1472292SN/A } 1482292SN/A 1492831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1502292SN/A "%i entries per thread.\n",part_amt); 1512292SN/A } else if (policy == "threshold") { 1522292SN/A iqPolicy = Threshold; 1532292SN/A 1542292SN/A double threshold = (double)params->smtIQThreshold / 100; 1552292SN/A 1562292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1572292SN/A 1582292SN/A //Divide up by threshold amount 1596221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1606221Snate@binkert.org maxEntries[tid] = thresholdIQ; 1612292SN/A } 1622292SN/A 1632831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1642292SN/A "%i entries per thread.\n",thresholdIQ); 1652292SN/A } else { 16613449Sgabeblack@google.com panic("Invalid IQ sharing policy. Options are: Dynamic, " 16713449Sgabeblack@google.com "Partitioned, Threshold"); 1682292SN/A } 16913453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = numThreads; tid < Impl::MaxThreads; tid++) { 17013453Srekai.gonzalezalberquilla@arm.com maxEntries[tid] = 0; 17113453Srekai.gonzalezalberquilla@arm.com } 1722292SN/A} 1732292SN/A 1742292SN/Atemplate <class Impl> 1752292SN/AInstructionQueue<Impl>::~InstructionQueue() 1762292SN/A{ 1772326SN/A dependGraph.reset(); 1782348SN/A#ifdef DEBUG 1792326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1802326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1812348SN/A#endif 1822292SN/A} 1832292SN/A 1842292SN/Atemplate <class Impl> 1852292SN/Astd::string 1862292SN/AInstructionQueue<Impl>::name() const 1872292SN/A{ 1882292SN/A return cpu->name() + ".iq"; 1891060SN/A} 1901060SN/A 1911061SN/Atemplate <class Impl> 1921060SN/Avoid 1931062SN/AInstructionQueue<Impl>::regStats() 1941062SN/A{ 1952301SN/A using namespace Stats; 1961062SN/A iqInstsAdded 1971062SN/A .name(name() + ".iqInstsAdded") 1981062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1991062SN/A .prereq(iqInstsAdded); 2001062SN/A 2011062SN/A iqNonSpecInstsAdded 2021062SN/A .name(name() + ".iqNonSpecInstsAdded") 2031062SN/A .desc("Number of non-speculative instructions added to the IQ") 2041062SN/A .prereq(iqNonSpecInstsAdded); 2051062SN/A 2062301SN/A iqInstsIssued 2072301SN/A .name(name() + ".iqInstsIssued") 2082301SN/A .desc("Number of instructions issued") 2092301SN/A .prereq(iqInstsIssued); 2101062SN/A 2111062SN/A iqIntInstsIssued 2121062SN/A .name(name() + ".iqIntInstsIssued") 2131062SN/A .desc("Number of integer instructions issued") 2141062SN/A .prereq(iqIntInstsIssued); 2151062SN/A 2161062SN/A iqFloatInstsIssued 2171062SN/A .name(name() + ".iqFloatInstsIssued") 2181062SN/A .desc("Number of float instructions issued") 2191062SN/A .prereq(iqFloatInstsIssued); 2201062SN/A 2211062SN/A iqBranchInstsIssued 2221062SN/A .name(name() + ".iqBranchInstsIssued") 2231062SN/A .desc("Number of branch instructions issued") 2241062SN/A .prereq(iqBranchInstsIssued); 2251062SN/A 2261062SN/A iqMemInstsIssued 2271062SN/A .name(name() + ".iqMemInstsIssued") 2281062SN/A .desc("Number of memory instructions issued") 2291062SN/A .prereq(iqMemInstsIssued); 2301062SN/A 2311062SN/A iqMiscInstsIssued 2321062SN/A .name(name() + ".iqMiscInstsIssued") 2331062SN/A .desc("Number of miscellaneous instructions issued") 2341062SN/A .prereq(iqMiscInstsIssued); 2351062SN/A 2361062SN/A iqSquashedInstsIssued 2371062SN/A .name(name() + ".iqSquashedInstsIssued") 2381062SN/A .desc("Number of squashed instructions issued") 2391062SN/A .prereq(iqSquashedInstsIssued); 2401062SN/A 2411062SN/A iqSquashedInstsExamined 2421062SN/A .name(name() + ".iqSquashedInstsExamined") 2431062SN/A .desc("Number of squashed instructions iterated over during squash;" 2441062SN/A " mainly for profiling") 2451062SN/A .prereq(iqSquashedInstsExamined); 2461062SN/A 2471062SN/A iqSquashedOperandsExamined 2481062SN/A .name(name() + ".iqSquashedOperandsExamined") 2491062SN/A .desc("Number of squashed operands that are examined and possibly " 2501062SN/A "removed from graph") 2511062SN/A .prereq(iqSquashedOperandsExamined); 2521062SN/A 2531062SN/A iqSquashedNonSpecRemoved 2541062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2551062SN/A .desc("Number of squashed non-spec instructions that were removed") 2561062SN/A .prereq(iqSquashedNonSpecRemoved); 2572361SN/A/* 2582326SN/A queueResDist 2592301SN/A .init(Num_OpClasses, 0, 99, 2) 2602301SN/A .name(name() + ".IQ:residence:") 2612301SN/A .desc("cycles from dispatch to issue") 2622301SN/A .flags(total | pdf | cdf ) 2632301SN/A ; 2642301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2652326SN/A queueResDist.subname(i, opClassStrings[i]); 2662301SN/A } 2672361SN/A*/ 2682326SN/A numIssuedDist 2692307SN/A .init(0,totalWidth,1) 2708240Snate@binkert.org .name(name() + ".issued_per_cycle") 2712301SN/A .desc("Number of insts issued each cycle") 2722307SN/A .flags(pdf) 2732301SN/A ; 2742301SN/A/* 2752301SN/A dist_unissued 2762301SN/A .init(Num_OpClasses+2) 2778240Snate@binkert.org .name(name() + ".unissued_cause") 2782301SN/A .desc("Reason ready instruction not issued") 2792301SN/A .flags(pdf | dist) 2802301SN/A ; 2812301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2822301SN/A dist_unissued.subname(i, unissued_names[i]); 2832301SN/A } 2842301SN/A*/ 2852326SN/A statIssuedInstType 2864762Snate@binkert.org .init(numThreads,Enums::Num_OpClass) 2878240Snate@binkert.org .name(name() + ".FU_type") 2882301SN/A .desc("Type of FU issued") 2892301SN/A .flags(total | pdf | dist) 2902301SN/A ; 2914762Snate@binkert.org statIssuedInstType.ysubnames(Enums::OpClassStrings); 2922301SN/A 2932301SN/A // 2942301SN/A // How long did instructions for a particular FU type wait prior to issue 2952301SN/A // 2962361SN/A/* 2972326SN/A issueDelayDist 2982301SN/A .init(Num_OpClasses,0,99,2) 2998240Snate@binkert.org .name(name() + ".") 3002301SN/A .desc("cycles from operands ready to issue") 3012301SN/A .flags(pdf | cdf) 3022301SN/A ; 3032301SN/A 3042301SN/A for (int i=0; i<Num_OpClasses; ++i) { 3052980Sgblack@eecs.umich.edu std::stringstream subname; 3062301SN/A subname << opClassStrings[i] << "_delay"; 3072326SN/A issueDelayDist.subname(i, subname.str()); 3082301SN/A } 3092361SN/A*/ 3102326SN/A issueRate 3118240Snate@binkert.org .name(name() + ".rate") 3122301SN/A .desc("Inst issue rate") 3132301SN/A .flags(total) 3142301SN/A ; 3152326SN/A issueRate = iqInstsIssued / cpu->numCycles; 3162727Sktlim@umich.edu 3172326SN/A statFuBusy 3182301SN/A .init(Num_OpClasses) 3198240Snate@binkert.org .name(name() + ".fu_full") 3202301SN/A .desc("attempts to use FU when none available") 3212301SN/A .flags(pdf | dist) 3222301SN/A ; 3232301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3244762Snate@binkert.org statFuBusy.subname(i, Enums::OpClassStrings[i]); 3252301SN/A } 3262301SN/A 3272326SN/A fuBusy 3282301SN/A .init(numThreads) 3298240Snate@binkert.org .name(name() + ".fu_busy_cnt") 3302301SN/A .desc("FU busy when requested") 3312301SN/A .flags(total) 3322301SN/A ; 3332301SN/A 3342326SN/A fuBusyRate 3358240Snate@binkert.org .name(name() + ".fu_busy_rate") 3362301SN/A .desc("FU busy rate (busy events/executed inst)") 3372301SN/A .flags(total) 3382301SN/A ; 3392326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3402301SN/A 3416221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3422292SN/A // Tell mem dependence unit to reg stats as well. 3436221Snate@binkert.org memDepUnit[tid].regStats(); 3442292SN/A } 3457897Shestness@cs.utexas.edu 3467897Shestness@cs.utexas.edu intInstQueueReads 3477897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3487897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3497897Shestness@cs.utexas.edu .flags(total); 3507897Shestness@cs.utexas.edu 3517897Shestness@cs.utexas.edu intInstQueueWrites 3527897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3537897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3547897Shestness@cs.utexas.edu .flags(total); 3557897Shestness@cs.utexas.edu 3567897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3577897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3587897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3597897Shestness@cs.utexas.edu .flags(total); 3607897Shestness@cs.utexas.edu 3617897Shestness@cs.utexas.edu fpInstQueueReads 3627897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3637897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3647897Shestness@cs.utexas.edu .flags(total); 3657897Shestness@cs.utexas.edu 3667897Shestness@cs.utexas.edu fpInstQueueWrites 3677897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3687897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3697897Shestness@cs.utexas.edu .flags(total); 3707897Shestness@cs.utexas.edu 37112110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWakeupAccesses 3727897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3737897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3747897Shestness@cs.utexas.edu .flags(total); 3757897Shestness@cs.utexas.edu 37612319Sandreas.sandberg@arm.com vecInstQueueReads 37712319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_reads") 37812319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue reads") 37912319Sandreas.sandberg@arm.com .flags(total); 38012319Sandreas.sandberg@arm.com 38112319Sandreas.sandberg@arm.com vecInstQueueWrites 38212319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_writes") 38312319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue writes") 38412319Sandreas.sandberg@arm.com .flags(total); 38512319Sandreas.sandberg@arm.com 38612319Sandreas.sandberg@arm.com vecInstQueueWakeupAccesses 38712319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_wakeup_accesses") 38812319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue wakeup accesses") 38912319Sandreas.sandberg@arm.com .flags(total); 39012319Sandreas.sandberg@arm.com 3917897Shestness@cs.utexas.edu intAluAccesses 3927897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 3937897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 3947897Shestness@cs.utexas.edu .flags(total); 3957897Shestness@cs.utexas.edu 3967897Shestness@cs.utexas.edu fpAluAccesses 3977897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 3987897Shestness@cs.utexas.edu .desc("Number of floating point alu accesses") 3997897Shestness@cs.utexas.edu .flags(total); 4007897Shestness@cs.utexas.edu 40112319Sandreas.sandberg@arm.com vecAluAccesses 40212319Sandreas.sandberg@arm.com .name(name() + ".vec_alu_accesses") 40312319Sandreas.sandberg@arm.com .desc("Number of vector alu accesses") 40412319Sandreas.sandberg@arm.com .flags(total); 40512319Sandreas.sandberg@arm.com 4061062SN/A} 4071062SN/A 4081062SN/Atemplate <class Impl> 4091062SN/Avoid 4102307SN/AInstructionQueue<Impl>::resetState() 4111060SN/A{ 4122307SN/A //Initialize thread IQ counts 41313453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; tid++) { 4146221Snate@binkert.org count[tid] = 0; 4156221Snate@binkert.org instList[tid].clear(); 4162307SN/A } 4171060SN/A 4182307SN/A // Initialize the number of free IQ entries. 4192307SN/A freeEntries = numEntries; 4202307SN/A 4212307SN/A // Note that in actuality, the registers corresponding to the logical 4222307SN/A // registers start off as ready. However this doesn't matter for the 4232307SN/A // IQ as the instruction should have been correctly told if those 4242307SN/A // registers are ready in rename. Thus it can all be initialized as 4252307SN/A // unready. 4262307SN/A for (int i = 0; i < numPhysRegs; ++i) { 4272307SN/A regScoreboard[i] = false; 4282307SN/A } 4292307SN/A 43013453Srekai.gonzalezalberquilla@arm.com for (ThreadID tid = 0; tid < Impl::MaxThreads; ++tid) { 4316221Snate@binkert.org squashedSeqNum[tid] = 0; 4322307SN/A } 4332307SN/A 4342307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4352307SN/A while (!readyInsts[i].empty()) 4362307SN/A readyInsts[i].pop(); 4372307SN/A queueOnList[i] = false; 4382307SN/A readyIt[i] = listOrder.end(); 4392307SN/A } 4402307SN/A nonSpecInsts.clear(); 4412307SN/A listOrder.clear(); 4427944SGiacomo.Gabrielli@arm.com deferredMemInsts.clear(); 44310333Smitch.hayenga@arm.com blockedMemInsts.clear(); 44410333Smitch.hayenga@arm.com retryMemInsts.clear(); 44510511Smitch.hayenga@arm.com wbOutstanding = 0; 4461060SN/A} 4471060SN/A 4481061SN/Atemplate <class Impl> 4491060SN/Avoid 4506221Snate@binkert.orgInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4511060SN/A{ 4522292SN/A activeThreads = at_ptr; 4532064SN/A} 4542064SN/A 4552064SN/Atemplate <class Impl> 4562064SN/Avoid 4572292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4582064SN/A{ 4594318Sktlim@umich.edu issueToExecuteQueue = i2e_ptr; 4601060SN/A} 4611060SN/A 4621061SN/Atemplate <class Impl> 4631060SN/Avoid 4641060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4651060SN/A{ 4661060SN/A timeBuffer = tb_ptr; 4671060SN/A 4681060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4691060SN/A} 4701060SN/A 4711684SN/Atemplate <class Impl> 47210510Smitch.hayenga@arm.combool 47310510Smitch.hayenga@arm.comInstructionQueue<Impl>::isDrained() const 47410510Smitch.hayenga@arm.com{ 47510511Smitch.hayenga@arm.com bool drained = dependGraph.empty() && 47610511Smitch.hayenga@arm.com instsToExecute.empty() && 47710511Smitch.hayenga@arm.com wbOutstanding == 0; 47810510Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) 47910510Smitch.hayenga@arm.com drained = drained && memDepUnit[tid].isDrained(); 48010510Smitch.hayenga@arm.com 48110510Smitch.hayenga@arm.com return drained; 48210510Smitch.hayenga@arm.com} 48310510Smitch.hayenga@arm.com 48410510Smitch.hayenga@arm.comtemplate <class Impl> 4852307SN/Avoid 4869444SAndreas.Sandberg@ARM.comInstructionQueue<Impl>::drainSanityCheck() const 4872307SN/A{ 4889444SAndreas.Sandberg@ARM.com assert(dependGraph.empty()); 4899444SAndreas.Sandberg@ARM.com assert(instsToExecute.empty()); 4909444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; ++tid) 4919444SAndreas.Sandberg@ARM.com memDepUnit[tid].drainSanityCheck(); 4922307SN/A} 4932307SN/A 4942307SN/Atemplate <class Impl> 4952307SN/Avoid 4962307SN/AInstructionQueue<Impl>::takeOverFrom() 4972307SN/A{ 4989444SAndreas.Sandberg@ARM.com resetState(); 4992307SN/A} 5002307SN/A 5012307SN/Atemplate <class Impl> 5022292SN/Aint 5036221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 5042292SN/A{ 5052292SN/A if (iqPolicy == Partitioned) { 5062292SN/A return numEntries / num_threads; 5072292SN/A } else { 5082292SN/A return 0; 5092292SN/A } 5102292SN/A} 5112292SN/A 5122292SN/A 5132292SN/Atemplate <class Impl> 5142292SN/Avoid 5152292SN/AInstructionQueue<Impl>::resetEntries() 5162292SN/A{ 5172292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 5183867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 5192292SN/A 5206221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5216221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5222292SN/A 5233867Sbinkertn@umich.edu while (threads != end) { 5246221Snate@binkert.org ThreadID tid = *threads++; 5253867Sbinkertn@umich.edu 5262292SN/A if (iqPolicy == Partitioned) { 5273867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 52811321Ssteve.reinhardt@amd.com } else if (iqPolicy == Threshold && active_threads == 1) { 5293867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 5302292SN/A } 5312292SN/A } 5322292SN/A } 5332292SN/A} 5342292SN/A 5352292SN/Atemplate <class Impl> 5361684SN/Aunsigned 5371684SN/AInstructionQueue<Impl>::numFreeEntries() 5381684SN/A{ 5391684SN/A return freeEntries; 5401684SN/A} 5411684SN/A 5422292SN/Atemplate <class Impl> 5432292SN/Aunsigned 5446221Snate@binkert.orgInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5452292SN/A{ 5462292SN/A return maxEntries[tid] - count[tid]; 5472292SN/A} 5482292SN/A 5491060SN/A// Might want to do something more complex if it knows how many instructions 5501060SN/A// will be issued this cycle. 5511061SN/Atemplate <class Impl> 5521060SN/Abool 5531060SN/AInstructionQueue<Impl>::isFull() 5541060SN/A{ 5551060SN/A if (freeEntries == 0) { 5561060SN/A return(true); 5571060SN/A } else { 5581060SN/A return(false); 5591060SN/A } 5601060SN/A} 5611060SN/A 5621061SN/Atemplate <class Impl> 5632292SN/Abool 5646221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid) 5652292SN/A{ 5662292SN/A if (numFreeEntries(tid) == 0) { 5672292SN/A return(true); 5682292SN/A } else { 5692292SN/A return(false); 5702292SN/A } 5712292SN/A} 5722292SN/A 5732292SN/Atemplate <class Impl> 5742292SN/Abool 5752292SN/AInstructionQueue<Impl>::hasReadyInsts() 5762292SN/A{ 5772292SN/A if (!listOrder.empty()) { 5782292SN/A return true; 5792292SN/A } 5802292SN/A 5812292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5822292SN/A if (!readyInsts[i].empty()) { 5832292SN/A return true; 5842292SN/A } 5852292SN/A } 5862292SN/A 5872292SN/A return false; 5882292SN/A} 5892292SN/A 5902292SN/Atemplate <class Impl> 5911060SN/Avoid 59213429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insert(const DynInstPtr &new_inst) 5931060SN/A{ 59412110SRekai.GonzalezAlberquilla@arm.com if (new_inst->isFloating()) { 59512110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 59612110SRekai.GonzalezAlberquilla@arm.com } else if (new_inst->isVector()) { 59712110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 59812110SRekai.GonzalezAlberquilla@arm.com } else { 59912110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 60012110SRekai.GonzalezAlberquilla@arm.com } 6011060SN/A // Make sure the instruction is valid 6021060SN/A assert(new_inst); 6031060SN/A 6047720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 6057720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 6061060SN/A 6071060SN/A assert(freeEntries != 0); 6081060SN/A 6092292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6101060SN/A 6112064SN/A --freeEntries; 6121060SN/A 6132292SN/A new_inst->setInIQ(); 6141060SN/A 6151060SN/A // Look through its source registers (physical regs), and mark any 6161060SN/A // dependencies. 6171060SN/A addToDependents(new_inst); 6181060SN/A 6191060SN/A // Have this instruction set itself as the producer of its destination 6201060SN/A // register(s). 6212326SN/A addToProducers(new_inst); 6221060SN/A 6231061SN/A if (new_inst->isMemRef()) { 6242292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 6251062SN/A } else { 6261062SN/A addIfReady(new_inst); 6271061SN/A } 6281061SN/A 6291062SN/A ++iqInstsAdded; 6301060SN/A 6312292SN/A count[new_inst->threadNumber]++; 6322292SN/A 6331060SN/A assert(freeEntries == (numEntries - countInsts())); 6341060SN/A} 6351060SN/A 6361061SN/Atemplate <class Impl> 6371061SN/Avoid 63813429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insertNonSpec(const DynInstPtr &new_inst) 6391061SN/A{ 6401061SN/A // @todo: Clean up this code; can do it by setting inst as unable 6411061SN/A // to issue, then calling normal insert on the inst. 64212110SRekai.GonzalezAlberquilla@arm.com if (new_inst->isFloating()) { 64312110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 64412110SRekai.GonzalezAlberquilla@arm.com } else if (new_inst->isVector()) { 64512110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 64612110SRekai.GonzalezAlberquilla@arm.com } else { 64712110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 64812110SRekai.GonzalezAlberquilla@arm.com } 6491061SN/A 6502292SN/A assert(new_inst); 6511061SN/A 6522292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 6531061SN/A 6547720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6552326SN/A "to the IQ.\n", 6567720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 6572064SN/A 6581061SN/A assert(freeEntries != 0); 6591061SN/A 6602292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6611061SN/A 6622064SN/A --freeEntries; 6631061SN/A 6642292SN/A new_inst->setInIQ(); 6651061SN/A 6661061SN/A // Have this instruction set itself as the producer of its destination 6671061SN/A // register(s). 6682326SN/A addToProducers(new_inst); 6691061SN/A 6701061SN/A // If it's a memory instruction, add it to the memory dependency 6711061SN/A // unit. 6722292SN/A if (new_inst->isMemRef()) { 6732292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6741061SN/A } 6751062SN/A 6761062SN/A ++iqNonSpecInstsAdded; 6772292SN/A 6782292SN/A count[new_inst->threadNumber]++; 6792292SN/A 6802292SN/A assert(freeEntries == (numEntries - countInsts())); 6811061SN/A} 6821061SN/A 6831061SN/Atemplate <class Impl> 6841060SN/Avoid 68513429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insertBarrier(const DynInstPtr &barr_inst) 6861060SN/A{ 6872292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6881060SN/A 6892292SN/A insertNonSpec(barr_inst); 6902292SN/A} 6911060SN/A 6922064SN/Atemplate <class Impl> 6932333SN/Atypename Impl::DynInstPtr 6942333SN/AInstructionQueue<Impl>::getInstToExecute() 6952333SN/A{ 6962333SN/A assert(!instsToExecute.empty()); 69713429Srekai.gonzalezalberquilla@arm.com DynInstPtr inst = std::move(instsToExecute.front()); 6982333SN/A instsToExecute.pop_front(); 69912110SRekai.GonzalezAlberquilla@arm.com if (inst->isFloating()) { 7007897Shestness@cs.utexas.edu fpInstQueueReads++; 70112110SRekai.GonzalezAlberquilla@arm.com } else if (inst->isVector()) { 70212110SRekai.GonzalezAlberquilla@arm.com vecInstQueueReads++; 7037897Shestness@cs.utexas.edu } else { 7047897Shestness@cs.utexas.edu intInstQueueReads++; 7057897Shestness@cs.utexas.edu } 7062333SN/A return inst; 7072333SN/A} 7081060SN/A 7092333SN/Atemplate <class Impl> 7102064SN/Avoid 7112292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 7122292SN/A{ 7132292SN/A assert(!readyInsts[op_class].empty()); 7142292SN/A 7152292SN/A ListOrderEntry queue_entry; 7162292SN/A 7172292SN/A queue_entry.queueType = op_class; 7182292SN/A 7192292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7202292SN/A 7212292SN/A ListOrderIt list_it = listOrder.begin(); 7222292SN/A ListOrderIt list_end_it = listOrder.end(); 7232292SN/A 7242292SN/A while (list_it != list_end_it) { 7252292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 7262292SN/A break; 7272292SN/A } 7282292SN/A 7292292SN/A list_it++; 7301060SN/A } 7311060SN/A 7322292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 7332292SN/A queueOnList[op_class] = true; 7342292SN/A} 7351060SN/A 7362292SN/Atemplate <class Impl> 7372292SN/Avoid 7382292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 7392292SN/A{ 7402292SN/A // Get iterator of next item on the list 7412292SN/A // Delete the original iterator 7422292SN/A // Determine if the next item is either the end of the list or younger 7432292SN/A // than the new instruction. If so, then add in a new iterator right here. 7442292SN/A // If not, then move along. 7452292SN/A ListOrderEntry queue_entry; 7462292SN/A OpClass op_class = (*list_order_it).queueType; 7472292SN/A ListOrderIt next_it = list_order_it; 7482292SN/A 7492292SN/A ++next_it; 7502292SN/A 7512292SN/A queue_entry.queueType = op_class; 7522292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7532292SN/A 7542292SN/A while (next_it != listOrder.end() && 7552292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 7562292SN/A ++next_it; 7571060SN/A } 7581060SN/A 7592292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7601060SN/A} 7611060SN/A 7622292SN/Atemplate <class Impl> 7632292SN/Avoid 76413429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::processFUCompletion(const DynInstPtr &inst, int fu_idx) 7652292SN/A{ 7662367SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7679444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 7682292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7692292SN/A // long latency op). Wake it if it was. This may be overkill. 77010511Smitch.hayenga@arm.com --wbOutstanding; 7712292SN/A iewStage->wakeCPU(); 7722292SN/A 7732326SN/A if (fu_idx > -1) 7742326SN/A fuPool->freeUnitNextCycle(fu_idx); 7752292SN/A 7762326SN/A // @todo: Ensure that these FU Completions happen at the beginning 7772326SN/A // of a cycle, otherwise they could add too many instructions to 7782326SN/A // the queue. 7795327Smengke97@hotmail.com issueToExecuteQueue->access(-1)->size++; 7802333SN/A instsToExecute.push_back(inst); 7812292SN/A} 7822292SN/A 7831061SN/A// @todo: Figure out a better way to remove the squashed items from the 7841061SN/A// lists. Checking the top item of each list to see if it's squashed 7851061SN/A// wastes time and forces jumps. 7861061SN/Atemplate <class Impl> 7871060SN/Avoid 7881060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7891060SN/A{ 7902292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7912292SN/A "the IQ.\n"); 7921060SN/A 7931060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7941060SN/A 79510333Smitch.hayenga@arm.com DynInstPtr mem_inst; 79613429Srekai.gonzalezalberquilla@arm.com while (mem_inst = std::move(getDeferredMemInstToExecute())) { 79710333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 79810333Smitch.hayenga@arm.com } 79910333Smitch.hayenga@arm.com 80010333Smitch.hayenga@arm.com // See if any cache blocked instructions are able to be executed 80113429Srekai.gonzalezalberquilla@arm.com while (mem_inst = std::move(getBlockedMemInstToExecute())) { 80210333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 8037944SGiacomo.Gabrielli@arm.com } 8047944SGiacomo.Gabrielli@arm.com 8052292SN/A // Have iterator to head of the list 8062292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 8072292SN/A // Try to get a FU that can do what this op needs. 8082292SN/A // If successful, change the oldestInst to the new top of the list, put 8092292SN/A // the queue in the proper place in the list. 8102292SN/A // Increment the iterator. 8112292SN/A // This will avoid trying to schedule a certain op class if there are no 8122292SN/A // FUs that handle it. 81310333Smitch.hayenga@arm.com int total_issued = 0; 8142292SN/A ListOrderIt order_it = listOrder.begin(); 8152292SN/A ListOrderIt order_end_it = listOrder.end(); 8161060SN/A 81710333Smitch.hayenga@arm.com while (total_issued < totalWidth && order_it != order_end_it) { 8182292SN/A OpClass op_class = (*order_it).queueType; 8191060SN/A 8202292SN/A assert(!readyInsts[op_class].empty()); 8211060SN/A 8222292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 8231060SN/A 82412110SRekai.GonzalezAlberquilla@arm.com if (issuing_inst->isFloating()) { 82512110SRekai.GonzalezAlberquilla@arm.com fpInstQueueReads++; 82612110SRekai.GonzalezAlberquilla@arm.com } else if (issuing_inst->isVector()) { 82712110SRekai.GonzalezAlberquilla@arm.com vecInstQueueReads++; 82812110SRekai.GonzalezAlberquilla@arm.com } else { 82912110SRekai.GonzalezAlberquilla@arm.com intInstQueueReads++; 83012110SRekai.GonzalezAlberquilla@arm.com } 8317897Shestness@cs.utexas.edu 8322292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 8331060SN/A 8342292SN/A if (issuing_inst->isSquashed()) { 8352292SN/A readyInsts[op_class].pop(); 8361060SN/A 8372292SN/A if (!readyInsts[op_class].empty()) { 8382292SN/A moveToYoungerInst(order_it); 8392292SN/A } else { 8402292SN/A readyIt[op_class] = listOrder.end(); 8412292SN/A queueOnList[op_class] = false; 8421060SN/A } 8431060SN/A 8442292SN/A listOrder.erase(order_it++); 8451060SN/A 8462292SN/A ++iqSquashedInstsIssued; 8472292SN/A 8482292SN/A continue; 8491060SN/A } 8501060SN/A 85111365SRekai.GonzalezAlberquilla@arm.com int idx = FUPool::NoCapableFU; 8529184Sandreas.hansson@arm.com Cycles op_latency = Cycles(1); 8536221Snate@binkert.org ThreadID tid = issuing_inst->threadNumber; 8541060SN/A 8552326SN/A if (op_class != No_OpClass) { 8562326SN/A idx = fuPool->getUnit(op_class); 85712110SRekai.GonzalezAlberquilla@arm.com if (issuing_inst->isFloating()) { 85812110SRekai.GonzalezAlberquilla@arm.com fpAluAccesses++; 85912110SRekai.GonzalezAlberquilla@arm.com } else if (issuing_inst->isVector()) { 86012110SRekai.GonzalezAlberquilla@arm.com vecAluAccesses++; 86112110SRekai.GonzalezAlberquilla@arm.com } else { 86212110SRekai.GonzalezAlberquilla@arm.com intAluAccesses++; 86312110SRekai.GonzalezAlberquilla@arm.com } 86411365SRekai.GonzalezAlberquilla@arm.com if (idx > FUPool::NoFreeFU) { 8652326SN/A op_latency = fuPool->getOpLatency(op_class); 8661060SN/A } 8671060SN/A } 8681060SN/A 8692348SN/A // If we have an instruction that doesn't require a FU, or a 8702348SN/A // valid FU, then schedule for execution. 87111365SRekai.GonzalezAlberquilla@arm.com if (idx != FUPool::NoFreeFU) { 8729184Sandreas.hansson@arm.com if (op_latency == Cycles(1)) { 8732292SN/A i2e_info->size++; 8742333SN/A instsToExecute.push_back(issuing_inst); 8751060SN/A 8762326SN/A // Add the FU onto the list of FU's to be freed next 8772326SN/A // cycle if we used one. 8782326SN/A if (idx >= 0) 8792326SN/A fuPool->freeUnitNextCycle(idx); 8802292SN/A } else { 88110807Snilay@cs.wisc.edu bool pipelined = fuPool->isPipelined(op_class); 8822326SN/A // Generate completion event for the FU 88310511Smitch.hayenga@arm.com ++wbOutstanding; 8842326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8852326SN/A idx, this); 8861060SN/A 8879180Sandreas.hansson@arm.com cpu->schedule(execution, 8889180Sandreas.hansson@arm.com cpu->clockEdge(Cycles(op_latency - 1))); 8891060SN/A 89010807Snilay@cs.wisc.edu if (!pipelined) { 8912348SN/A // If FU isn't pipelined, then it must be freed 8922348SN/A // upon the execution completing. 8932326SN/A execution->setFreeFU(); 8942292SN/A } else { 8952292SN/A // Add the FU onto the list of FU's to be freed next cycle. 8962326SN/A fuPool->freeUnitNextCycle(idx); 8972292SN/A } 8981060SN/A } 8991060SN/A 9007720Sgblack@eecs.umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 9012292SN/A "[sn:%lli]\n", 9027720Sgblack@eecs.umich.edu tid, issuing_inst->pcState(), 9032292SN/A issuing_inst->seqNum); 9041060SN/A 9052292SN/A readyInsts[op_class].pop(); 9061061SN/A 9072292SN/A if (!readyInsts[op_class].empty()) { 9082292SN/A moveToYoungerInst(order_it); 9092292SN/A } else { 9102292SN/A readyIt[op_class] = listOrder.end(); 9112292SN/A queueOnList[op_class] = false; 9121060SN/A } 9131060SN/A 9142064SN/A issuing_inst->setIssued(); 9152292SN/A ++total_issued; 9162064SN/A 9178471SGiacomo.Gabrielli@arm.com#if TRACING_ON 9189046SAli.Saidi@ARM.com issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 9198471SGiacomo.Gabrielli@arm.com#endif 9208471SGiacomo.Gabrielli@arm.com 9212292SN/A if (!issuing_inst->isMemRef()) { 9222292SN/A // Memory instructions can not be freed from the IQ until they 9232292SN/A // complete. 9242292SN/A ++freeEntries; 9252301SN/A count[tid]--; 9262731Sktlim@umich.edu issuing_inst->clearInIQ(); 9272292SN/A } else { 9282301SN/A memDepUnit[tid].issue(issuing_inst); 9292292SN/A } 9302292SN/A 9312292SN/A listOrder.erase(order_it++); 9322326SN/A statIssuedInstType[tid][op_class]++; 9332292SN/A } else { 9342326SN/A statFuBusy[op_class]++; 9352326SN/A fuBusy[tid]++; 9362292SN/A ++order_it; 9371060SN/A } 9381060SN/A } 9391062SN/A 9402326SN/A numIssuedDist.sample(total_issued); 9412326SN/A iqInstsIssued+= total_issued; 9422307SN/A 9432348SN/A // If we issued any instructions, tell the CPU we had activity. 9448071SAli.Saidi@ARM.com // @todo If the way deferred memory instructions are handeled due to 9458071SAli.Saidi@ARM.com // translation changes then the deferredMemInsts condition should be removed 9468071SAli.Saidi@ARM.com // from the code below. 94710333Smitch.hayenga@arm.com if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) { 9482292SN/A cpu->activityThisCycle(); 9492292SN/A } else { 9502292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 9512292SN/A } 9521060SN/A} 9531060SN/A 9541061SN/Atemplate <class Impl> 9551060SN/Avoid 9561061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 9571060SN/A{ 9582292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 9592292SN/A "to execute.\n", inst); 9601062SN/A 9612292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9621060SN/A 9631061SN/A assert(inst_it != nonSpecInsts.end()); 9641060SN/A 9656221Snate@binkert.org ThreadID tid = (*inst_it).second->threadNumber; 9662292SN/A 9674033Sktlim@umich.edu (*inst_it).second->setAtCommit(); 9684033Sktlim@umich.edu 9691061SN/A (*inst_it).second->setCanIssue(); 9701060SN/A 9711062SN/A if (!(*inst_it).second->isMemRef()) { 9721062SN/A addIfReady((*inst_it).second); 9731062SN/A } else { 9742292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9751062SN/A } 9761060SN/A 9772292SN/A (*inst_it).second = NULL; 9782292SN/A 9791061SN/A nonSpecInsts.erase(inst_it); 9801060SN/A} 9811060SN/A 9821061SN/Atemplate <class Impl> 9831061SN/Avoid 9846221Snate@binkert.orgInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9852292SN/A{ 9862292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9872292SN/A tid,inst); 9882292SN/A 9892292SN/A ListIt iq_it = instList[tid].begin(); 9902292SN/A 9912292SN/A while (iq_it != instList[tid].end() && 9922292SN/A (*iq_it)->seqNum <= inst) { 9932292SN/A ++iq_it; 9942292SN/A instList[tid].pop_front(); 9952292SN/A } 9962292SN/A 9972292SN/A assert(freeEntries == (numEntries - countInsts())); 9982292SN/A} 9992292SN/A 10002292SN/Atemplate <class Impl> 10012301SN/Aint 100213429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::wakeDependents(const DynInstPtr &completed_inst) 10031684SN/A{ 10042301SN/A int dependents = 0; 10052301SN/A 10067897Shestness@cs.utexas.edu // The instruction queue here takes care of both floating and int ops 10077897Shestness@cs.utexas.edu if (completed_inst->isFloating()) { 100812110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWakeupAccesses++; 100912110SRekai.GonzalezAlberquilla@arm.com } else if (completed_inst->isVector()) { 101012110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWakeupAccesses++; 10117897Shestness@cs.utexas.edu } else { 10127897Shestness@cs.utexas.edu intInstQueueWakeupAccesses++; 10137897Shestness@cs.utexas.edu } 10147897Shestness@cs.utexas.edu 10152292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 10162292SN/A 10172292SN/A assert(!completed_inst->isSquashed()); 10181684SN/A 10191684SN/A // Tell the memory dependence unit to wake any dependents on this 10202292SN/A // instruction if it is a memory instruction. Also complete the memory 10212326SN/A // instruction at this point since we know it executed without issues. 10222326SN/A // @todo: Might want to rename "completeMemInst" to something that 10232326SN/A // indicates that it won't need to be replayed, and call this 10242326SN/A // earlier. Might not be a big deal. 10251684SN/A if (completed_inst->isMemRef()) { 10262292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 10272292SN/A completeMemInst(completed_inst); 10282292SN/A } else if (completed_inst->isMemBarrier() || 10292292SN/A completed_inst->isWriteBarrier()) { 10302292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 10311684SN/A } 10321684SN/A 10331684SN/A for (int dest_reg_idx = 0; 10341684SN/A dest_reg_idx < completed_inst->numDestRegs(); 10351684SN/A dest_reg_idx++) 10361684SN/A { 103712105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = 10381684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 10391684SN/A 10401684SN/A // Special case of uniq or control registers. They are not 10411684SN/A // handled by the IQ and thus have no dependency graph entry. 104212105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 104312105Snathanael.premillieu@arm.com DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n", 104412106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className()); 10451684SN/A continue; 10461684SN/A } 10471684SN/A 104812105Snathanael.premillieu@arm.com DPRINTF(IQ, "Waking any dependents on register %i (%s).\n", 104912106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), 105012106SRekai.GonzalezAlberquilla@arm.com dest_reg->className()); 10511684SN/A 10522326SN/A //Go through the dependency chain, marking the registers as 10532326SN/A //ready within the waiting instructions. 105412106SRekai.GonzalezAlberquilla@arm.com DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10551684SN/A 10562326SN/A while (dep_inst) { 10577599Sminkyu.jeong@arm.com DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 10587720Sgblack@eecs.umich.edu "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 10591684SN/A 10601684SN/A // Might want to give more information to the instruction 10612326SN/A // so that it knows which of its source registers is 10622326SN/A // ready. However that would mean that the dependency 10632326SN/A // graph entries would need to hold the src_reg_idx. 10642326SN/A dep_inst->markSrcRegReady(); 10651684SN/A 10662326SN/A addIfReady(dep_inst); 10671684SN/A 106812106SRekai.GonzalezAlberquilla@arm.com dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10691684SN/A 10702301SN/A ++dependents; 10711684SN/A } 10721684SN/A 10732326SN/A // Reset the head node now that all of its dependents have 10742326SN/A // been woken up. 107512106SRekai.GonzalezAlberquilla@arm.com assert(dependGraph.empty(dest_reg->flatIndex())); 107612106SRekai.GonzalezAlberquilla@arm.com dependGraph.clearInst(dest_reg->flatIndex()); 10771684SN/A 10781684SN/A // Mark the scoreboard as having that register ready. 107912106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = true; 10801684SN/A } 10812301SN/A return dependents; 10822064SN/A} 10832064SN/A 10842064SN/Atemplate <class Impl> 10852064SN/Avoid 108613429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addReadyMemInst(const DynInstPtr &ready_inst) 10872064SN/A{ 10882292SN/A OpClass op_class = ready_inst->opClass(); 10892292SN/A 10902292SN/A readyInsts[op_class].push(ready_inst); 10912292SN/A 10922326SN/A // Will need to reorder the list if either a queue is not on the list, 10932326SN/A // or it has an older instruction than last time. 10942326SN/A if (!queueOnList[op_class]) { 10952326SN/A addToOrderList(op_class); 10962326SN/A } else if (readyInsts[op_class].top()->seqNum < 10972326SN/A (*readyIt[op_class]).oldestInst) { 10982326SN/A listOrder.erase(readyIt[op_class]); 10992326SN/A addToOrderList(op_class); 11002326SN/A } 11012326SN/A 11022292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 11037720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 11047720Sgblack@eecs.umich.edu ready_inst->pcState(), op_class, ready_inst->seqNum); 11052064SN/A} 11062064SN/A 11072064SN/Atemplate <class Impl> 11082064SN/Avoid 110913429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::rescheduleMemInst(const DynInstPtr &resched_inst) 11102064SN/A{ 11114033Sktlim@umich.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 11127944SGiacomo.Gabrielli@arm.com 11137944SGiacomo.Gabrielli@arm.com // Reset DTB translation state 11149046SAli.Saidi@ARM.com resched_inst->translationStarted(false); 11159046SAli.Saidi@ARM.com resched_inst->translationCompleted(false); 11167944SGiacomo.Gabrielli@arm.com 11174033Sktlim@umich.edu resched_inst->clearCanIssue(); 11182292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 11192064SN/A} 11202064SN/A 11212064SN/Atemplate <class Impl> 11222064SN/Avoid 112313429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::replayMemInst(const DynInstPtr &replay_inst) 11242064SN/A{ 112510333Smitch.hayenga@arm.com memDepUnit[replay_inst->threadNumber].replay(); 11262292SN/A} 11272292SN/A 11282292SN/Atemplate <class Impl> 11292292SN/Avoid 113013429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::completeMemInst(const DynInstPtr &completed_inst) 11312292SN/A{ 11326221Snate@binkert.org ThreadID tid = completed_inst->threadNumber; 11332292SN/A 11347720Sgblack@eecs.umich.edu DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 11357720Sgblack@eecs.umich.edu completed_inst->pcState(), completed_inst->seqNum); 11362292SN/A 11372292SN/A ++freeEntries; 11382292SN/A 11399046SAli.Saidi@ARM.com completed_inst->memOpDone(true); 11402292SN/A 11412292SN/A memDepUnit[tid].completed(completed_inst); 11422292SN/A count[tid]--; 11431684SN/A} 11441684SN/A 11451684SN/Atemplate <class Impl> 11461684SN/Avoid 114713429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::deferMemInst(const DynInstPtr &deferred_inst) 11487944SGiacomo.Gabrielli@arm.com{ 11497944SGiacomo.Gabrielli@arm.com deferredMemInsts.push_back(deferred_inst); 11507944SGiacomo.Gabrielli@arm.com} 11517944SGiacomo.Gabrielli@arm.com 11527944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 115310333Smitch.hayenga@arm.comvoid 115413429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::blockMemInst(const DynInstPtr &blocked_inst) 115510333Smitch.hayenga@arm.com{ 115610333Smitch.hayenga@arm.com blocked_inst->translationStarted(false); 115710333Smitch.hayenga@arm.com blocked_inst->translationCompleted(false); 115810333Smitch.hayenga@arm.com 115910333Smitch.hayenga@arm.com blocked_inst->clearIssued(); 116010333Smitch.hayenga@arm.com blocked_inst->clearCanIssue(); 116110333Smitch.hayenga@arm.com blockedMemInsts.push_back(blocked_inst); 116210333Smitch.hayenga@arm.com} 116310333Smitch.hayenga@arm.com 116410333Smitch.hayenga@arm.comtemplate <class Impl> 116510333Smitch.hayenga@arm.comvoid 116610333Smitch.hayenga@arm.comInstructionQueue<Impl>::cacheUnblocked() 116710333Smitch.hayenga@arm.com{ 116810333Smitch.hayenga@arm.com retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts); 116910333Smitch.hayenga@arm.com // Get the CPU ticking again 117010333Smitch.hayenga@arm.com cpu->wakeCPU(); 117110333Smitch.hayenga@arm.com} 117210333Smitch.hayenga@arm.com 117310333Smitch.hayenga@arm.comtemplate <class Impl> 11747944SGiacomo.Gabrielli@arm.comtypename Impl::DynInstPtr 11757944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::getDeferredMemInstToExecute() 11767944SGiacomo.Gabrielli@arm.com{ 11777944SGiacomo.Gabrielli@arm.com for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 11787944SGiacomo.Gabrielli@arm.com ++it) { 11799046SAli.Saidi@ARM.com if ((*it)->translationCompleted() || (*it)->isSquashed()) { 118013429Srekai.gonzalezalberquilla@arm.com DynInstPtr mem_inst = std::move(*it); 11817944SGiacomo.Gabrielli@arm.com deferredMemInsts.erase(it); 118210333Smitch.hayenga@arm.com return mem_inst; 11837944SGiacomo.Gabrielli@arm.com } 11847944SGiacomo.Gabrielli@arm.com } 118510333Smitch.hayenga@arm.com return nullptr; 118610333Smitch.hayenga@arm.com} 118710333Smitch.hayenga@arm.com 118810333Smitch.hayenga@arm.comtemplate <class Impl> 118910333Smitch.hayenga@arm.comtypename Impl::DynInstPtr 119010333Smitch.hayenga@arm.comInstructionQueue<Impl>::getBlockedMemInstToExecute() 119110333Smitch.hayenga@arm.com{ 119210333Smitch.hayenga@arm.com if (retryMemInsts.empty()) { 119310333Smitch.hayenga@arm.com return nullptr; 119410333Smitch.hayenga@arm.com } else { 119513429Srekai.gonzalezalberquilla@arm.com DynInstPtr mem_inst = std::move(retryMemInsts.front()); 119610333Smitch.hayenga@arm.com retryMemInsts.pop_front(); 119710333Smitch.hayenga@arm.com return mem_inst; 119810333Smitch.hayenga@arm.com } 11997944SGiacomo.Gabrielli@arm.com} 12007944SGiacomo.Gabrielli@arm.com 12017944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 12027944SGiacomo.Gabrielli@arm.comvoid 120313429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::violation(const DynInstPtr &store, 120413429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &faulting_load) 12051061SN/A{ 12067897Shestness@cs.utexas.edu intInstQueueWrites++; 12072292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 12081061SN/A} 12091061SN/A 12101061SN/Atemplate <class Impl> 12111060SN/Avoid 12126221Snate@binkert.orgInstructionQueue<Impl>::squash(ThreadID tid) 12131060SN/A{ 12142292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 12152292SN/A "the IQ.\n", tid); 12161060SN/A 12171060SN/A // Read instruction sequence number of last instruction out of the 12181060SN/A // time buffer. 12192292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 12201060SN/A 122110797Sbrandon.potter@amd.com doSquash(tid); 12221061SN/A 12231061SN/A // Also tell the memory dependence unit to squash. 12242292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 12251060SN/A} 12261060SN/A 12271061SN/Atemplate <class Impl> 12281061SN/Avoid 12296221Snate@binkert.orgInstructionQueue<Impl>::doSquash(ThreadID tid) 12301061SN/A{ 12312326SN/A // Start at the tail. 12322326SN/A ListIt squash_it = instList[tid].end(); 12332326SN/A --squash_it; 12341061SN/A 12352292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 12362292SN/A tid, squashedSeqNum[tid]); 12371061SN/A 12381061SN/A // Squash any instructions younger than the squashed sequence number 12391061SN/A // given. 12402326SN/A while (squash_it != instList[tid].end() && 12412326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 12422292SN/A 12432326SN/A DynInstPtr squashed_inst = (*squash_it); 124412110SRekai.GonzalezAlberquilla@arm.com if (squashed_inst->isFloating()) { 124512110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 124612110SRekai.GonzalezAlberquilla@arm.com } else if (squashed_inst->isVector()) { 124712110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 124812110SRekai.GonzalezAlberquilla@arm.com } else { 124912110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 125012110SRekai.GonzalezAlberquilla@arm.com } 12511061SN/A 12521061SN/A // Only handle the instruction if it actually is in the IQ and 12531061SN/A // hasn't already been squashed in the IQ. 12542292SN/A if (squashed_inst->threadNumber != tid || 12552292SN/A squashed_inst->isSquashedInIQ()) { 12562326SN/A --squash_it; 12572292SN/A continue; 12582292SN/A } 12592292SN/A 12602292SN/A if (!squashed_inst->isIssued() || 12612292SN/A (squashed_inst->isMemRef() && 12629046SAli.Saidi@ARM.com !squashed_inst->memOpDone())) { 12631062SN/A 12647720Sgblack@eecs.umich.edu DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 12657720Sgblack@eecs.umich.edu tid, squashed_inst->seqNum, squashed_inst->pcState()); 12662367SN/A 126710032SGiacomo.Gabrielli@arm.com bool is_acq_rel = squashed_inst->isMemBarrier() && 126810032SGiacomo.Gabrielli@arm.com (squashed_inst->isLoad() || 126910032SGiacomo.Gabrielli@arm.com (squashed_inst->isStore() && 127010032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional())); 127110032SGiacomo.Gabrielli@arm.com 12721061SN/A // Remove the instruction from the dependency list. 127310032SGiacomo.Gabrielli@arm.com if (is_acq_rel || 127410032SGiacomo.Gabrielli@arm.com (!squashed_inst->isNonSpeculative() && 127510032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional() && 127610032SGiacomo.Gabrielli@arm.com !squashed_inst->isMemBarrier() && 127710032SGiacomo.Gabrielli@arm.com !squashed_inst->isWriteBarrier())) { 12781061SN/A 12791061SN/A for (int src_reg_idx = 0; 12801681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 12811061SN/A src_reg_idx++) 12821061SN/A { 128312105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = 12841061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 12851061SN/A 12862326SN/A // Only remove it from the dependency graph if it 12872326SN/A // was placed there in the first place. 12882326SN/A 12892326SN/A // Instead of doing a linked list traversal, we 12902326SN/A // can just remove these squashed instructions 12912326SN/A // either at issue time, or when the register is 12922326SN/A // overwritten. The only downside to this is it 12932326SN/A // leaves more room for error. 12942292SN/A 12951061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 129612105Snathanael.premillieu@arm.com !src_reg->isFixedMapping()) { 129712106SRekai.GonzalezAlberquilla@arm.com dependGraph.remove(src_reg->flatIndex(), 129812106SRekai.GonzalezAlberquilla@arm.com squashed_inst); 12991061SN/A } 13001062SN/A 13012292SN/A 13021062SN/A ++iqSquashedOperandsExamined; 13031061SN/A } 13044033Sktlim@umich.edu } else if (!squashed_inst->isStoreConditional() || 13054033Sktlim@umich.edu !squashed_inst->isCompleted()) { 13062292SN/A NonSpecMapIt ns_inst_it = 13072292SN/A nonSpecInsts.find(squashed_inst->seqNum); 13088275SAli.Saidi@ARM.com 130910017Sandreas.hansson@arm.com // we remove non-speculative instructions from 131010017Sandreas.hansson@arm.com // nonSpecInsts already when they are ready, and so we 131110017Sandreas.hansson@arm.com // cannot always expect to find them 13124033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 131310017Sandreas.hansson@arm.com // loads that became ready but stalled on a 131410017Sandreas.hansson@arm.com // blocked cache are alreayd removed from 131510017Sandreas.hansson@arm.com // nonSpecInsts, and have not faulted 131610017Sandreas.hansson@arm.com assert(squashed_inst->getFault() != NoFault || 131710017Sandreas.hansson@arm.com squashed_inst->isMemRef()); 13184033Sktlim@umich.edu } else { 13191062SN/A 13204033Sktlim@umich.edu (*ns_inst_it).second = NULL; 13211681SN/A 13224033Sktlim@umich.edu nonSpecInsts.erase(ns_inst_it); 13231062SN/A 13244033Sktlim@umich.edu ++iqSquashedNonSpecRemoved; 13254033Sktlim@umich.edu } 13261061SN/A } 13271061SN/A 13281061SN/A // Might want to also clear out the head of the dependency graph. 13291061SN/A 13301061SN/A // Mark it as squashed within the IQ. 13311061SN/A squashed_inst->setSquashedInIQ(); 13321061SN/A 13332292SN/A // @todo: Remove this hack where several statuses are set so the 13342292SN/A // inst will flow through the rest of the pipeline. 13351681SN/A squashed_inst->setIssued(); 13361681SN/A squashed_inst->setCanCommit(); 13372731Sktlim@umich.edu squashed_inst->clearInIQ(); 13382292SN/A 13392292SN/A //Update Thread IQ Count 13402292SN/A count[squashed_inst->threadNumber]--; 13411681SN/A 13421681SN/A ++freeEntries; 13431061SN/A } 13441061SN/A 134512833Sjang.hanhwi@gmail.com // IQ clears out the heads of the dependency graph only when 134612833Sjang.hanhwi@gmail.com // instructions reach writeback stage. If an instruction is squashed 134712833Sjang.hanhwi@gmail.com // before writeback stage, its head of dependency graph would not be 134812833Sjang.hanhwi@gmail.com // cleared out; it holds the instruction's DynInstPtr. This prevents 134912833Sjang.hanhwi@gmail.com // freeing the squashed instruction's DynInst. 135012833Sjang.hanhwi@gmail.com // Thus, we need to manually clear out the squashed instructions' heads 135112833Sjang.hanhwi@gmail.com // of dependency graph. 135212833Sjang.hanhwi@gmail.com for (int dest_reg_idx = 0; 135312833Sjang.hanhwi@gmail.com dest_reg_idx < squashed_inst->numDestRegs(); 135412833Sjang.hanhwi@gmail.com dest_reg_idx++) 135512833Sjang.hanhwi@gmail.com { 135612833Sjang.hanhwi@gmail.com PhysRegIdPtr dest_reg = 135712833Sjang.hanhwi@gmail.com squashed_inst->renamedDestRegIdx(dest_reg_idx); 135812833Sjang.hanhwi@gmail.com if (dest_reg->isFixedMapping()){ 135912833Sjang.hanhwi@gmail.com continue; 136012833Sjang.hanhwi@gmail.com } 136112833Sjang.hanhwi@gmail.com assert(dependGraph.empty(dest_reg->flatIndex())); 136212833Sjang.hanhwi@gmail.com dependGraph.clearInst(dest_reg->flatIndex()); 136312833Sjang.hanhwi@gmail.com } 13642326SN/A instList[tid].erase(squash_it--); 13651062SN/A ++iqSquashedInstsExamined; 13661061SN/A } 13671060SN/A} 13681060SN/A 13691061SN/Atemplate <class Impl> 13701060SN/Abool 137113429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addToDependents(const DynInstPtr &new_inst) 13721060SN/A{ 13731060SN/A // Loop through the instruction's source registers, adding 13741060SN/A // them to the dependency list if they are not ready. 13751060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 13761060SN/A bool return_val = false; 13771060SN/A 13781060SN/A for (int src_reg_idx = 0; 13791060SN/A src_reg_idx < total_src_regs; 13801060SN/A src_reg_idx++) 13811060SN/A { 13821060SN/A // Only add it to the dependency graph if it's not ready. 13831060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 138412105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 13851060SN/A 13861060SN/A // Check the IQ's scoreboard to make sure the register 13871060SN/A // hasn't become ready while the instruction was in flight 13881060SN/A // between stages. Only if it really isn't ready should 13891060SN/A // it be added to the dependency graph. 139012105Snathanael.premillieu@arm.com if (src_reg->isFixedMapping()) { 13911061SN/A continue; 139212106SRekai.GonzalezAlberquilla@arm.com } else if (!regScoreboard[src_reg->flatIndex()]) { 139312105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13941060SN/A "is being added to the dependency chain.\n", 139512106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 139612106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 13971060SN/A 139812106SRekai.GonzalezAlberquilla@arm.com dependGraph.insert(src_reg->flatIndex(), new_inst); 13991060SN/A 14001060SN/A // Change the return value to indicate that something 14011060SN/A // was added to the dependency graph. 14021060SN/A return_val = true; 14031060SN/A } else { 140412105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 14051060SN/A "became ready before it reached the IQ.\n", 140612106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 140712106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 14081060SN/A // Mark a register ready within the instruction. 14092326SN/A new_inst->markSrcRegReady(src_reg_idx); 14101060SN/A } 14111060SN/A } 14121060SN/A } 14131060SN/A 14141060SN/A return return_val; 14151060SN/A} 14161060SN/A 14171061SN/Atemplate <class Impl> 14181060SN/Avoid 141913429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addToProducers(const DynInstPtr &new_inst) 14201060SN/A{ 14212326SN/A // Nothing really needs to be marked when an instruction becomes 14222326SN/A // the producer of a register's value, but for convenience a ptr 14232326SN/A // to the producing instruction will be placed in the head node of 14242326SN/A // the dependency links. 14251060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 14261060SN/A 14271060SN/A for (int dest_reg_idx = 0; 14281060SN/A dest_reg_idx < total_dest_regs; 14291060SN/A dest_reg_idx++) 14301060SN/A { 143112105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 14321061SN/A 143312105Snathanael.premillieu@arm.com // Some registers have fixed mapping, and there is no need to track 14341061SN/A // dependencies as these instructions must be executed at commit. 143512105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 14361061SN/A continue; 14371060SN/A } 14381060SN/A 143912106SRekai.GonzalezAlberquilla@arm.com if (!dependGraph.empty(dest_reg->flatIndex())) { 14402326SN/A dependGraph.dump(); 144112105Snathanael.premillieu@arm.com panic("Dependency graph %i (%s) (flat: %i) not empty!", 144212106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className(), 144312106SRekai.GonzalezAlberquilla@arm.com dest_reg->flatIndex()); 14442064SN/A } 14451062SN/A 144612106SRekai.GonzalezAlberquilla@arm.com dependGraph.setInst(dest_reg->flatIndex(), new_inst); 14471062SN/A 14481060SN/A // Mark the scoreboard to say it's not yet ready. 144912106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = false; 14501060SN/A } 14511060SN/A} 14521060SN/A 14531061SN/Atemplate <class Impl> 14541060SN/Avoid 145513429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addIfReady(const DynInstPtr &inst) 14561060SN/A{ 14572326SN/A // If the instruction now has all of its source registers 14581060SN/A // available, then add it to the list of ready instructions. 14591060SN/A if (inst->readyToIssue()) { 14601061SN/A 14611060SN/A //Add the instruction to the proper ready list. 14622292SN/A if (inst->isMemRef()) { 14631061SN/A 14642292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 14651061SN/A 14661062SN/A // Message to the mem dependence unit that this instruction has 14671062SN/A // its registers ready. 14682292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 14691062SN/A 14702292SN/A return; 14712292SN/A } 14721062SN/A 14732292SN/A OpClass op_class = inst->opClass(); 14741061SN/A 14752292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 14767720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 14777720Sgblack@eecs.umich.edu inst->pcState(), op_class, inst->seqNum); 14781061SN/A 14792292SN/A readyInsts[op_class].push(inst); 14801061SN/A 14812326SN/A // Will need to reorder the list if either a queue is not on the list, 14822326SN/A // or it has an older instruction than last time. 14832326SN/A if (!queueOnList[op_class]) { 14842326SN/A addToOrderList(op_class); 14852326SN/A } else if (readyInsts[op_class].top()->seqNum < 14862326SN/A (*readyIt[op_class]).oldestInst) { 14872326SN/A listOrder.erase(readyIt[op_class]); 14882326SN/A addToOrderList(op_class); 14891060SN/A } 14901060SN/A } 14911060SN/A} 14921060SN/A 14931061SN/Atemplate <class Impl> 14941061SN/Aint 14951061SN/AInstructionQueue<Impl>::countInsts() 14961061SN/A{ 14972698Sktlim@umich.edu#if 0 14982292SN/A //ksewell:This works but definitely could use a cleaner write 14992292SN/A //with a more intuitive way of counting. Right now it's 15002292SN/A //just brute force .... 15012698Sktlim@umich.edu // Change the #if if you want to use this method. 15021061SN/A int total_insts = 0; 15031061SN/A 15046221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 15056221Snate@binkert.org ListIt count_it = instList[tid].begin(); 15061681SN/A 15076221Snate@binkert.org while (count_it != instList[tid].end()) { 15082292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 15092292SN/A if (!(*count_it)->isIssued()) { 15102292SN/A ++total_insts; 15112292SN/A } else if ((*count_it)->isMemRef() && 15122292SN/A !(*count_it)->memOpDone) { 15132292SN/A // Loads that have not been marked as executed still count 15142292SN/A // towards the total instructions. 15152292SN/A ++total_insts; 15162292SN/A } 15172292SN/A } 15182292SN/A 15192292SN/A ++count_it; 15201061SN/A } 15211061SN/A } 15221061SN/A 15231061SN/A return total_insts; 15242292SN/A#else 15252292SN/A return numEntries - freeEntries; 15262292SN/A#endif 15271681SN/A} 15281681SN/A 15291681SN/Atemplate <class Impl> 15301681SN/Avoid 15311061SN/AInstructionQueue<Impl>::dumpLists() 15321061SN/A{ 15332292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 15342292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 15351061SN/A 15362292SN/A cprintf("\n"); 15372292SN/A } 15381061SN/A 15391061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 15401061SN/A 15412292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 15422292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 15431061SN/A 15441061SN/A cprintf("Non speculative list: "); 15451061SN/A 15462292SN/A while (non_spec_it != non_spec_end_it) { 15477720Sgblack@eecs.umich.edu cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 15482292SN/A (*non_spec_it).second->seqNum); 15491061SN/A ++non_spec_it; 15501061SN/A } 15511061SN/A 15521061SN/A cprintf("\n"); 15531061SN/A 15542292SN/A ListOrderIt list_order_it = listOrder.begin(); 15552292SN/A ListOrderIt list_order_end_it = listOrder.end(); 15562292SN/A int i = 1; 15572292SN/A 15582292SN/A cprintf("List order: "); 15592292SN/A 15602292SN/A while (list_order_it != list_order_end_it) { 15612292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 15622292SN/A (*list_order_it).oldestInst); 15632292SN/A 15642292SN/A ++list_order_it; 15652292SN/A ++i; 15662292SN/A } 15672292SN/A 15682292SN/A cprintf("\n"); 15691061SN/A} 15702292SN/A 15712292SN/A 15722292SN/Atemplate <class Impl> 15732292SN/Avoid 15742292SN/AInstructionQueue<Impl>::dumpInsts() 15752292SN/A{ 15766221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 15772292SN/A int num = 0; 15782292SN/A int valid_num = 0; 15796221Snate@binkert.org ListIt inst_list_it = instList[tid].begin(); 15802292SN/A 15816221Snate@binkert.org while (inst_list_it != instList[tid].end()) { 15826221Snate@binkert.org cprintf("Instruction:%i\n", num); 15832292SN/A if (!(*inst_list_it)->isSquashed()) { 15842292SN/A if (!(*inst_list_it)->isIssued()) { 15852292SN/A ++valid_num; 15862292SN/A cprintf("Count:%i\n", valid_num); 15872292SN/A } else if ((*inst_list_it)->isMemRef() && 15889046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 15892326SN/A // Loads that have not been marked as executed 15902326SN/A // still count towards the total instructions. 15912292SN/A ++valid_num; 15922292SN/A cprintf("Count:%i\n", valid_num); 15932292SN/A } 15942292SN/A } 15952292SN/A 15967720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 15972292SN/A "Issued:%i\nSquashed:%i\n", 15987720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 15992292SN/A (*inst_list_it)->seqNum, 16002292SN/A (*inst_list_it)->threadNumber, 16012292SN/A (*inst_list_it)->isIssued(), 16022292SN/A (*inst_list_it)->isSquashed()); 16032292SN/A 16042292SN/A if ((*inst_list_it)->isMemRef()) { 16059046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 16062292SN/A } 16072292SN/A 16082292SN/A cprintf("\n"); 16092292SN/A 16102292SN/A inst_list_it++; 16112292SN/A ++num; 16122292SN/A } 16132292SN/A } 16142348SN/A 16152348SN/A cprintf("Insts to Execute list:\n"); 16162348SN/A 16172348SN/A int num = 0; 16182348SN/A int valid_num = 0; 16192348SN/A ListIt inst_list_it = instsToExecute.begin(); 16202348SN/A 16212348SN/A while (inst_list_it != instsToExecute.end()) 16222348SN/A { 16232348SN/A cprintf("Instruction:%i\n", 16242348SN/A num); 16252348SN/A if (!(*inst_list_it)->isSquashed()) { 16262348SN/A if (!(*inst_list_it)->isIssued()) { 16272348SN/A ++valid_num; 16282348SN/A cprintf("Count:%i\n", valid_num); 16292348SN/A } else if ((*inst_list_it)->isMemRef() && 16309046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 16312348SN/A // Loads that have not been marked as executed 16322348SN/A // still count towards the total instructions. 16332348SN/A ++valid_num; 16342348SN/A cprintf("Count:%i\n", valid_num); 16352348SN/A } 16362348SN/A } 16372348SN/A 16387720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 16392348SN/A "Issued:%i\nSquashed:%i\n", 16407720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 16412348SN/A (*inst_list_it)->seqNum, 16422348SN/A (*inst_list_it)->threadNumber, 16432348SN/A (*inst_list_it)->isIssued(), 16442348SN/A (*inst_list_it)->isSquashed()); 16452348SN/A 16462348SN/A if ((*inst_list_it)->isMemRef()) { 16479046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 16482348SN/A } 16492348SN/A 16502348SN/A cprintf("\n"); 16512348SN/A 16522348SN/A inst_list_it++; 16532348SN/A ++num; 16542348SN/A } 16552292SN/A} 16569944Smatt.horsnell@ARM.com 16579944Smatt.horsnell@ARM.com#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1658