inst_queue_impl.hh revision 13449
11689SN/A/* 210333Smitch.hayenga@arm.com * Copyright (c) 2011-2014 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422831Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_INST_QUEUE_IMPL_HH__ 479944Smatt.horsnell@ARM.com 482064SN/A#include <limits> 491060SN/A#include <vector> 501060SN/A 5113449Sgabeblack@google.com#include "base/logging.hh" 522292SN/A#include "cpu/o3/fu_pool.hh" 531717SN/A#include "cpu/o3/inst_queue.hh" 548232Snate@binkert.org#include "debug/IQ.hh" 554762Snate@binkert.org#include "enums/OpClass.hh" 566221Snate@binkert.org#include "params/DerivO3CPU.hh" 574762Snate@binkert.org#include "sim/core.hh" 581060SN/A 598737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 608737Skoansin.tan@gmail.com// we open up the entire namespace std 618737Skoansin.tan@gmail.comusing std::list; 625529Snate@binkert.org 631061SN/Atemplate <class Impl> 6413429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::FUCompletion::FUCompletion(const DynInstPtr &_inst, 655606Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 668581Ssteve.reinhardt@amd.com : Event(Stat_Event_Pri, AutoDelete), 678581Ssteve.reinhardt@amd.com inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 681060SN/A{ 692292SN/A} 702292SN/A 712292SN/Atemplate <class Impl> 722292SN/Avoid 732292SN/AInstructionQueue<Impl>::FUCompletion::process() 742292SN/A{ 752326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 762292SN/A inst = NULL; 772292SN/A} 782292SN/A 792292SN/A 802292SN/Atemplate <class Impl> 812292SN/Aconst char * 825336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const 832292SN/A{ 844873Sstever@eecs.umich.edu return "Functional unit completion"; 852292SN/A} 862292SN/A 872292SN/Atemplate <class Impl> 884329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 895529Snate@binkert.org DerivO3CPUParams *params) 904329Sktlim@umich.edu : cpu(cpu_ptr), 914329Sktlim@umich.edu iewStage(iew_ptr), 924329Sktlim@umich.edu fuPool(params->fuPool), 932292SN/A numEntries(params->numIQEntries), 942292SN/A totalWidth(params->issueWidth), 952292SN/A commitToIEWDelay(params->commitToIEWDelay) 962292SN/A{ 972292SN/A assert(fuPool); 982292SN/A 995529Snate@binkert.org numThreads = params->numThreads; 1001060SN/A 1019920Syasuko.eckert@amd.com // Set the number of total physical registers 10212109SRekai.GonzalezAlberquilla@arm.com // As the vector registers have two addressing modes, they are added twice 1039920Syasuko.eckert@amd.com numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 10412109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs + 10512109SRekai.GonzalezAlberquilla@arm.com params->numPhysVecRegs * TheISA::NumVecElemPerVecReg + 10612109SRekai.GonzalezAlberquilla@arm.com params->numPhysCCRegs; 1071060SN/A 1081060SN/A //Create an entry for each physical register within the 1091060SN/A //dependency graph. 1102326SN/A dependGraph.resize(numPhysRegs); 1111060SN/A 1121060SN/A // Resize the register scoreboard. 1131060SN/A regScoreboard.resize(numPhysRegs); 1141060SN/A 1152292SN/A //Initialize Mem Dependence Units 1166221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1176221Snate@binkert.org memDepUnit[tid].init(params, tid); 1186221Snate@binkert.org memDepUnit[tid].setIQ(this); 1191060SN/A } 1201060SN/A 1212307SN/A resetState(); 1222292SN/A 1232980Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1242292SN/A 1252292SN/A //Convert string to lowercase 1262292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1272292SN/A (int(*)(int)) tolower); 1282292SN/A 1292292SN/A //Figure out resource sharing policy 1302292SN/A if (policy == "dynamic") { 1312292SN/A iqPolicy = Dynamic; 1322292SN/A 1332292SN/A //Set Max Entries to Total ROB Capacity 1346221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1356221Snate@binkert.org maxEntries[tid] = numEntries; 1362292SN/A } 1372292SN/A 1382292SN/A } else if (policy == "partitioned") { 1392292SN/A iqPolicy = Partitioned; 1402292SN/A 1412292SN/A //@todo:make work if part_amt doesnt divide evenly. 1422292SN/A int part_amt = numEntries / numThreads; 1432292SN/A 1442292SN/A //Divide ROB up evenly 1456221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1466221Snate@binkert.org maxEntries[tid] = part_amt; 1472292SN/A } 1482292SN/A 1492831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1502292SN/A "%i entries per thread.\n",part_amt); 1512292SN/A } else if (policy == "threshold") { 1522292SN/A iqPolicy = Threshold; 1532292SN/A 1542292SN/A double threshold = (double)params->smtIQThreshold / 100; 1552292SN/A 1562292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1572292SN/A 1582292SN/A //Divide up by threshold amount 1596221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1606221Snate@binkert.org maxEntries[tid] = thresholdIQ; 1612292SN/A } 1622292SN/A 1632831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1642292SN/A "%i entries per thread.\n",thresholdIQ); 1652292SN/A } else { 16613449Sgabeblack@google.com panic("Invalid IQ sharing policy. Options are: Dynamic, " 16713449Sgabeblack@google.com "Partitioned, Threshold"); 1682292SN/A } 1692292SN/A} 1702292SN/A 1712292SN/Atemplate <class Impl> 1722292SN/AInstructionQueue<Impl>::~InstructionQueue() 1732292SN/A{ 1742326SN/A dependGraph.reset(); 1752348SN/A#ifdef DEBUG 1762326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1772326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1782348SN/A#endif 1792292SN/A} 1802292SN/A 1812292SN/Atemplate <class Impl> 1822292SN/Astd::string 1832292SN/AInstructionQueue<Impl>::name() const 1842292SN/A{ 1852292SN/A return cpu->name() + ".iq"; 1861060SN/A} 1871060SN/A 1881061SN/Atemplate <class Impl> 1891060SN/Avoid 1901062SN/AInstructionQueue<Impl>::regStats() 1911062SN/A{ 1922301SN/A using namespace Stats; 1931062SN/A iqInstsAdded 1941062SN/A .name(name() + ".iqInstsAdded") 1951062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1961062SN/A .prereq(iqInstsAdded); 1971062SN/A 1981062SN/A iqNonSpecInstsAdded 1991062SN/A .name(name() + ".iqNonSpecInstsAdded") 2001062SN/A .desc("Number of non-speculative instructions added to the IQ") 2011062SN/A .prereq(iqNonSpecInstsAdded); 2021062SN/A 2032301SN/A iqInstsIssued 2042301SN/A .name(name() + ".iqInstsIssued") 2052301SN/A .desc("Number of instructions issued") 2062301SN/A .prereq(iqInstsIssued); 2071062SN/A 2081062SN/A iqIntInstsIssued 2091062SN/A .name(name() + ".iqIntInstsIssued") 2101062SN/A .desc("Number of integer instructions issued") 2111062SN/A .prereq(iqIntInstsIssued); 2121062SN/A 2131062SN/A iqFloatInstsIssued 2141062SN/A .name(name() + ".iqFloatInstsIssued") 2151062SN/A .desc("Number of float instructions issued") 2161062SN/A .prereq(iqFloatInstsIssued); 2171062SN/A 2181062SN/A iqBranchInstsIssued 2191062SN/A .name(name() + ".iqBranchInstsIssued") 2201062SN/A .desc("Number of branch instructions issued") 2211062SN/A .prereq(iqBranchInstsIssued); 2221062SN/A 2231062SN/A iqMemInstsIssued 2241062SN/A .name(name() + ".iqMemInstsIssued") 2251062SN/A .desc("Number of memory instructions issued") 2261062SN/A .prereq(iqMemInstsIssued); 2271062SN/A 2281062SN/A iqMiscInstsIssued 2291062SN/A .name(name() + ".iqMiscInstsIssued") 2301062SN/A .desc("Number of miscellaneous instructions issued") 2311062SN/A .prereq(iqMiscInstsIssued); 2321062SN/A 2331062SN/A iqSquashedInstsIssued 2341062SN/A .name(name() + ".iqSquashedInstsIssued") 2351062SN/A .desc("Number of squashed instructions issued") 2361062SN/A .prereq(iqSquashedInstsIssued); 2371062SN/A 2381062SN/A iqSquashedInstsExamined 2391062SN/A .name(name() + ".iqSquashedInstsExamined") 2401062SN/A .desc("Number of squashed instructions iterated over during squash;" 2411062SN/A " mainly for profiling") 2421062SN/A .prereq(iqSquashedInstsExamined); 2431062SN/A 2441062SN/A iqSquashedOperandsExamined 2451062SN/A .name(name() + ".iqSquashedOperandsExamined") 2461062SN/A .desc("Number of squashed operands that are examined and possibly " 2471062SN/A "removed from graph") 2481062SN/A .prereq(iqSquashedOperandsExamined); 2491062SN/A 2501062SN/A iqSquashedNonSpecRemoved 2511062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2521062SN/A .desc("Number of squashed non-spec instructions that were removed") 2531062SN/A .prereq(iqSquashedNonSpecRemoved); 2542361SN/A/* 2552326SN/A queueResDist 2562301SN/A .init(Num_OpClasses, 0, 99, 2) 2572301SN/A .name(name() + ".IQ:residence:") 2582301SN/A .desc("cycles from dispatch to issue") 2592301SN/A .flags(total | pdf | cdf ) 2602301SN/A ; 2612301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2622326SN/A queueResDist.subname(i, opClassStrings[i]); 2632301SN/A } 2642361SN/A*/ 2652326SN/A numIssuedDist 2662307SN/A .init(0,totalWidth,1) 2678240Snate@binkert.org .name(name() + ".issued_per_cycle") 2682301SN/A .desc("Number of insts issued each cycle") 2692307SN/A .flags(pdf) 2702301SN/A ; 2712301SN/A/* 2722301SN/A dist_unissued 2732301SN/A .init(Num_OpClasses+2) 2748240Snate@binkert.org .name(name() + ".unissued_cause") 2752301SN/A .desc("Reason ready instruction not issued") 2762301SN/A .flags(pdf | dist) 2772301SN/A ; 2782301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2792301SN/A dist_unissued.subname(i, unissued_names[i]); 2802301SN/A } 2812301SN/A*/ 2822326SN/A statIssuedInstType 2834762Snate@binkert.org .init(numThreads,Enums::Num_OpClass) 2848240Snate@binkert.org .name(name() + ".FU_type") 2852301SN/A .desc("Type of FU issued") 2862301SN/A .flags(total | pdf | dist) 2872301SN/A ; 2884762Snate@binkert.org statIssuedInstType.ysubnames(Enums::OpClassStrings); 2892301SN/A 2902301SN/A // 2912301SN/A // How long did instructions for a particular FU type wait prior to issue 2922301SN/A // 2932361SN/A/* 2942326SN/A issueDelayDist 2952301SN/A .init(Num_OpClasses,0,99,2) 2968240Snate@binkert.org .name(name() + ".") 2972301SN/A .desc("cycles from operands ready to issue") 2982301SN/A .flags(pdf | cdf) 2992301SN/A ; 3002301SN/A 3012301SN/A for (int i=0; i<Num_OpClasses; ++i) { 3022980Sgblack@eecs.umich.edu std::stringstream subname; 3032301SN/A subname << opClassStrings[i] << "_delay"; 3042326SN/A issueDelayDist.subname(i, subname.str()); 3052301SN/A } 3062361SN/A*/ 3072326SN/A issueRate 3088240Snate@binkert.org .name(name() + ".rate") 3092301SN/A .desc("Inst issue rate") 3102301SN/A .flags(total) 3112301SN/A ; 3122326SN/A issueRate = iqInstsIssued / cpu->numCycles; 3132727Sktlim@umich.edu 3142326SN/A statFuBusy 3152301SN/A .init(Num_OpClasses) 3168240Snate@binkert.org .name(name() + ".fu_full") 3172301SN/A .desc("attempts to use FU when none available") 3182301SN/A .flags(pdf | dist) 3192301SN/A ; 3202301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3214762Snate@binkert.org statFuBusy.subname(i, Enums::OpClassStrings[i]); 3222301SN/A } 3232301SN/A 3242326SN/A fuBusy 3252301SN/A .init(numThreads) 3268240Snate@binkert.org .name(name() + ".fu_busy_cnt") 3272301SN/A .desc("FU busy when requested") 3282301SN/A .flags(total) 3292301SN/A ; 3302301SN/A 3312326SN/A fuBusyRate 3328240Snate@binkert.org .name(name() + ".fu_busy_rate") 3332301SN/A .desc("FU busy rate (busy events/executed inst)") 3342301SN/A .flags(total) 3352301SN/A ; 3362326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3372301SN/A 3386221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3392292SN/A // Tell mem dependence unit to reg stats as well. 3406221Snate@binkert.org memDepUnit[tid].regStats(); 3412292SN/A } 3427897Shestness@cs.utexas.edu 3437897Shestness@cs.utexas.edu intInstQueueReads 3447897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3457897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3467897Shestness@cs.utexas.edu .flags(total); 3477897Shestness@cs.utexas.edu 3487897Shestness@cs.utexas.edu intInstQueueWrites 3497897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3507897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3517897Shestness@cs.utexas.edu .flags(total); 3527897Shestness@cs.utexas.edu 3537897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3547897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3557897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3567897Shestness@cs.utexas.edu .flags(total); 3577897Shestness@cs.utexas.edu 3587897Shestness@cs.utexas.edu fpInstQueueReads 3597897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3607897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3617897Shestness@cs.utexas.edu .flags(total); 3627897Shestness@cs.utexas.edu 3637897Shestness@cs.utexas.edu fpInstQueueWrites 3647897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3657897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3667897Shestness@cs.utexas.edu .flags(total); 3677897Shestness@cs.utexas.edu 36812110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWakeupAccesses 3697897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3707897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3717897Shestness@cs.utexas.edu .flags(total); 3727897Shestness@cs.utexas.edu 37312319Sandreas.sandberg@arm.com vecInstQueueReads 37412319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_reads") 37512319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue reads") 37612319Sandreas.sandberg@arm.com .flags(total); 37712319Sandreas.sandberg@arm.com 37812319Sandreas.sandberg@arm.com vecInstQueueWrites 37912319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_writes") 38012319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue writes") 38112319Sandreas.sandberg@arm.com .flags(total); 38212319Sandreas.sandberg@arm.com 38312319Sandreas.sandberg@arm.com vecInstQueueWakeupAccesses 38412319Sandreas.sandberg@arm.com .name(name() + ".vec_inst_queue_wakeup_accesses") 38512319Sandreas.sandberg@arm.com .desc("Number of vector instruction queue wakeup accesses") 38612319Sandreas.sandberg@arm.com .flags(total); 38712319Sandreas.sandberg@arm.com 3887897Shestness@cs.utexas.edu intAluAccesses 3897897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 3907897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 3917897Shestness@cs.utexas.edu .flags(total); 3927897Shestness@cs.utexas.edu 3937897Shestness@cs.utexas.edu fpAluAccesses 3947897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 3957897Shestness@cs.utexas.edu .desc("Number of floating point alu accesses") 3967897Shestness@cs.utexas.edu .flags(total); 3977897Shestness@cs.utexas.edu 39812319Sandreas.sandberg@arm.com vecAluAccesses 39912319Sandreas.sandberg@arm.com .name(name() + ".vec_alu_accesses") 40012319Sandreas.sandberg@arm.com .desc("Number of vector alu accesses") 40112319Sandreas.sandberg@arm.com .flags(total); 40212319Sandreas.sandberg@arm.com 4031062SN/A} 4041062SN/A 4051062SN/Atemplate <class Impl> 4061062SN/Avoid 4072307SN/AInstructionQueue<Impl>::resetState() 4081060SN/A{ 4092307SN/A //Initialize thread IQ counts 4106221Snate@binkert.org for (ThreadID tid = 0; tid <numThreads; tid++) { 4116221Snate@binkert.org count[tid] = 0; 4126221Snate@binkert.org instList[tid].clear(); 4132307SN/A } 4141060SN/A 4152307SN/A // Initialize the number of free IQ entries. 4162307SN/A freeEntries = numEntries; 4172307SN/A 4182307SN/A // Note that in actuality, the registers corresponding to the logical 4192307SN/A // registers start off as ready. However this doesn't matter for the 4202307SN/A // IQ as the instruction should have been correctly told if those 4212307SN/A // registers are ready in rename. Thus it can all be initialized as 4222307SN/A // unready. 4232307SN/A for (int i = 0; i < numPhysRegs; ++i) { 4242307SN/A regScoreboard[i] = false; 4252307SN/A } 4262307SN/A 4276221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 4286221Snate@binkert.org squashedSeqNum[tid] = 0; 4292307SN/A } 4302307SN/A 4312307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4322307SN/A while (!readyInsts[i].empty()) 4332307SN/A readyInsts[i].pop(); 4342307SN/A queueOnList[i] = false; 4352307SN/A readyIt[i] = listOrder.end(); 4362307SN/A } 4372307SN/A nonSpecInsts.clear(); 4382307SN/A listOrder.clear(); 4397944SGiacomo.Gabrielli@arm.com deferredMemInsts.clear(); 44010333Smitch.hayenga@arm.com blockedMemInsts.clear(); 44110333Smitch.hayenga@arm.com retryMemInsts.clear(); 44210511Smitch.hayenga@arm.com wbOutstanding = 0; 4431060SN/A} 4441060SN/A 4451061SN/Atemplate <class Impl> 4461060SN/Avoid 4476221Snate@binkert.orgInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4481060SN/A{ 4492292SN/A activeThreads = at_ptr; 4502064SN/A} 4512064SN/A 4522064SN/Atemplate <class Impl> 4532064SN/Avoid 4542292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4552064SN/A{ 4564318Sktlim@umich.edu issueToExecuteQueue = i2e_ptr; 4571060SN/A} 4581060SN/A 4591061SN/Atemplate <class Impl> 4601060SN/Avoid 4611060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4621060SN/A{ 4631060SN/A timeBuffer = tb_ptr; 4641060SN/A 4651060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4661060SN/A} 4671060SN/A 4681684SN/Atemplate <class Impl> 46910510Smitch.hayenga@arm.combool 47010510Smitch.hayenga@arm.comInstructionQueue<Impl>::isDrained() const 47110510Smitch.hayenga@arm.com{ 47210511Smitch.hayenga@arm.com bool drained = dependGraph.empty() && 47310511Smitch.hayenga@arm.com instsToExecute.empty() && 47410511Smitch.hayenga@arm.com wbOutstanding == 0; 47510510Smitch.hayenga@arm.com for (ThreadID tid = 0; tid < numThreads; ++tid) 47610510Smitch.hayenga@arm.com drained = drained && memDepUnit[tid].isDrained(); 47710510Smitch.hayenga@arm.com 47810510Smitch.hayenga@arm.com return drained; 47910510Smitch.hayenga@arm.com} 48010510Smitch.hayenga@arm.com 48110510Smitch.hayenga@arm.comtemplate <class Impl> 4822307SN/Avoid 4839444SAndreas.Sandberg@ARM.comInstructionQueue<Impl>::drainSanityCheck() const 4842307SN/A{ 4859444SAndreas.Sandberg@ARM.com assert(dependGraph.empty()); 4869444SAndreas.Sandberg@ARM.com assert(instsToExecute.empty()); 4879444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; ++tid) 4889444SAndreas.Sandberg@ARM.com memDepUnit[tid].drainSanityCheck(); 4892307SN/A} 4902307SN/A 4912307SN/Atemplate <class Impl> 4922307SN/Avoid 4932307SN/AInstructionQueue<Impl>::takeOverFrom() 4942307SN/A{ 4959444SAndreas.Sandberg@ARM.com resetState(); 4962307SN/A} 4972307SN/A 4982307SN/Atemplate <class Impl> 4992292SN/Aint 5006221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 5012292SN/A{ 5022292SN/A if (iqPolicy == Partitioned) { 5032292SN/A return numEntries / num_threads; 5042292SN/A } else { 5052292SN/A return 0; 5062292SN/A } 5072292SN/A} 5082292SN/A 5092292SN/A 5102292SN/Atemplate <class Impl> 5112292SN/Avoid 5122292SN/AInstructionQueue<Impl>::resetEntries() 5132292SN/A{ 5142292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 5153867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 5162292SN/A 5176221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 5186221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 5192292SN/A 5203867Sbinkertn@umich.edu while (threads != end) { 5216221Snate@binkert.org ThreadID tid = *threads++; 5223867Sbinkertn@umich.edu 5232292SN/A if (iqPolicy == Partitioned) { 5243867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 52511321Ssteve.reinhardt@amd.com } else if (iqPolicy == Threshold && active_threads == 1) { 5263867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 5272292SN/A } 5282292SN/A } 5292292SN/A } 5302292SN/A} 5312292SN/A 5322292SN/Atemplate <class Impl> 5331684SN/Aunsigned 5341684SN/AInstructionQueue<Impl>::numFreeEntries() 5351684SN/A{ 5361684SN/A return freeEntries; 5371684SN/A} 5381684SN/A 5392292SN/Atemplate <class Impl> 5402292SN/Aunsigned 5416221Snate@binkert.orgInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5422292SN/A{ 5432292SN/A return maxEntries[tid] - count[tid]; 5442292SN/A} 5452292SN/A 5461060SN/A// Might want to do something more complex if it knows how many instructions 5471060SN/A// will be issued this cycle. 5481061SN/Atemplate <class Impl> 5491060SN/Abool 5501060SN/AInstructionQueue<Impl>::isFull() 5511060SN/A{ 5521060SN/A if (freeEntries == 0) { 5531060SN/A return(true); 5541060SN/A } else { 5551060SN/A return(false); 5561060SN/A } 5571060SN/A} 5581060SN/A 5591061SN/Atemplate <class Impl> 5602292SN/Abool 5616221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid) 5622292SN/A{ 5632292SN/A if (numFreeEntries(tid) == 0) { 5642292SN/A return(true); 5652292SN/A } else { 5662292SN/A return(false); 5672292SN/A } 5682292SN/A} 5692292SN/A 5702292SN/Atemplate <class Impl> 5712292SN/Abool 5722292SN/AInstructionQueue<Impl>::hasReadyInsts() 5732292SN/A{ 5742292SN/A if (!listOrder.empty()) { 5752292SN/A return true; 5762292SN/A } 5772292SN/A 5782292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5792292SN/A if (!readyInsts[i].empty()) { 5802292SN/A return true; 5812292SN/A } 5822292SN/A } 5832292SN/A 5842292SN/A return false; 5852292SN/A} 5862292SN/A 5872292SN/Atemplate <class Impl> 5881060SN/Avoid 58913429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insert(const DynInstPtr &new_inst) 5901060SN/A{ 59112110SRekai.GonzalezAlberquilla@arm.com if (new_inst->isFloating()) { 59212110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 59312110SRekai.GonzalezAlberquilla@arm.com } else if (new_inst->isVector()) { 59412110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 59512110SRekai.GonzalezAlberquilla@arm.com } else { 59612110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 59712110SRekai.GonzalezAlberquilla@arm.com } 5981060SN/A // Make sure the instruction is valid 5991060SN/A assert(new_inst); 6001060SN/A 6017720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 6027720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 6031060SN/A 6041060SN/A assert(freeEntries != 0); 6051060SN/A 6062292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6071060SN/A 6082064SN/A --freeEntries; 6091060SN/A 6102292SN/A new_inst->setInIQ(); 6111060SN/A 6121060SN/A // Look through its source registers (physical regs), and mark any 6131060SN/A // dependencies. 6141060SN/A addToDependents(new_inst); 6151060SN/A 6161060SN/A // Have this instruction set itself as the producer of its destination 6171060SN/A // register(s). 6182326SN/A addToProducers(new_inst); 6191060SN/A 6201061SN/A if (new_inst->isMemRef()) { 6212292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 6221062SN/A } else { 6231062SN/A addIfReady(new_inst); 6241061SN/A } 6251061SN/A 6261062SN/A ++iqInstsAdded; 6271060SN/A 6282292SN/A count[new_inst->threadNumber]++; 6292292SN/A 6301060SN/A assert(freeEntries == (numEntries - countInsts())); 6311060SN/A} 6321060SN/A 6331061SN/Atemplate <class Impl> 6341061SN/Avoid 63513429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insertNonSpec(const DynInstPtr &new_inst) 6361061SN/A{ 6371061SN/A // @todo: Clean up this code; can do it by setting inst as unable 6381061SN/A // to issue, then calling normal insert on the inst. 63912110SRekai.GonzalezAlberquilla@arm.com if (new_inst->isFloating()) { 64012110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 64112110SRekai.GonzalezAlberquilla@arm.com } else if (new_inst->isVector()) { 64212110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 64312110SRekai.GonzalezAlberquilla@arm.com } else { 64412110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 64512110SRekai.GonzalezAlberquilla@arm.com } 6461061SN/A 6472292SN/A assert(new_inst); 6481061SN/A 6492292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 6501061SN/A 6517720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6522326SN/A "to the IQ.\n", 6537720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 6542064SN/A 6551061SN/A assert(freeEntries != 0); 6561061SN/A 6572292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6581061SN/A 6592064SN/A --freeEntries; 6601061SN/A 6612292SN/A new_inst->setInIQ(); 6621061SN/A 6631061SN/A // Have this instruction set itself as the producer of its destination 6641061SN/A // register(s). 6652326SN/A addToProducers(new_inst); 6661061SN/A 6671061SN/A // If it's a memory instruction, add it to the memory dependency 6681061SN/A // unit. 6692292SN/A if (new_inst->isMemRef()) { 6702292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6711061SN/A } 6721062SN/A 6731062SN/A ++iqNonSpecInstsAdded; 6742292SN/A 6752292SN/A count[new_inst->threadNumber]++; 6762292SN/A 6772292SN/A assert(freeEntries == (numEntries - countInsts())); 6781061SN/A} 6791061SN/A 6801061SN/Atemplate <class Impl> 6811060SN/Avoid 68213429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::insertBarrier(const DynInstPtr &barr_inst) 6831060SN/A{ 6842292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6851060SN/A 6862292SN/A insertNonSpec(barr_inst); 6872292SN/A} 6881060SN/A 6892064SN/Atemplate <class Impl> 6902333SN/Atypename Impl::DynInstPtr 6912333SN/AInstructionQueue<Impl>::getInstToExecute() 6922333SN/A{ 6932333SN/A assert(!instsToExecute.empty()); 69413429Srekai.gonzalezalberquilla@arm.com DynInstPtr inst = std::move(instsToExecute.front()); 6952333SN/A instsToExecute.pop_front(); 69612110SRekai.GonzalezAlberquilla@arm.com if (inst->isFloating()) { 6977897Shestness@cs.utexas.edu fpInstQueueReads++; 69812110SRekai.GonzalezAlberquilla@arm.com } else if (inst->isVector()) { 69912110SRekai.GonzalezAlberquilla@arm.com vecInstQueueReads++; 7007897Shestness@cs.utexas.edu } else { 7017897Shestness@cs.utexas.edu intInstQueueReads++; 7027897Shestness@cs.utexas.edu } 7032333SN/A return inst; 7042333SN/A} 7051060SN/A 7062333SN/Atemplate <class Impl> 7072064SN/Avoid 7082292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 7092292SN/A{ 7102292SN/A assert(!readyInsts[op_class].empty()); 7112292SN/A 7122292SN/A ListOrderEntry queue_entry; 7132292SN/A 7142292SN/A queue_entry.queueType = op_class; 7152292SN/A 7162292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7172292SN/A 7182292SN/A ListOrderIt list_it = listOrder.begin(); 7192292SN/A ListOrderIt list_end_it = listOrder.end(); 7202292SN/A 7212292SN/A while (list_it != list_end_it) { 7222292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 7232292SN/A break; 7242292SN/A } 7252292SN/A 7262292SN/A list_it++; 7271060SN/A } 7281060SN/A 7292292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 7302292SN/A queueOnList[op_class] = true; 7312292SN/A} 7321060SN/A 7332292SN/Atemplate <class Impl> 7342292SN/Avoid 7352292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 7362292SN/A{ 7372292SN/A // Get iterator of next item on the list 7382292SN/A // Delete the original iterator 7392292SN/A // Determine if the next item is either the end of the list or younger 7402292SN/A // than the new instruction. If so, then add in a new iterator right here. 7412292SN/A // If not, then move along. 7422292SN/A ListOrderEntry queue_entry; 7432292SN/A OpClass op_class = (*list_order_it).queueType; 7442292SN/A ListOrderIt next_it = list_order_it; 7452292SN/A 7462292SN/A ++next_it; 7472292SN/A 7482292SN/A queue_entry.queueType = op_class; 7492292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 7502292SN/A 7512292SN/A while (next_it != listOrder.end() && 7522292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 7532292SN/A ++next_it; 7541060SN/A } 7551060SN/A 7562292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7571060SN/A} 7581060SN/A 7592292SN/Atemplate <class Impl> 7602292SN/Avoid 76113429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::processFUCompletion(const DynInstPtr &inst, int fu_idx) 7622292SN/A{ 7632367SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7649444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 7652292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7662292SN/A // long latency op). Wake it if it was. This may be overkill. 76710511Smitch.hayenga@arm.com --wbOutstanding; 7682292SN/A iewStage->wakeCPU(); 7692292SN/A 7702326SN/A if (fu_idx > -1) 7712326SN/A fuPool->freeUnitNextCycle(fu_idx); 7722292SN/A 7732326SN/A // @todo: Ensure that these FU Completions happen at the beginning 7742326SN/A // of a cycle, otherwise they could add too many instructions to 7752326SN/A // the queue. 7765327Smengke97@hotmail.com issueToExecuteQueue->access(-1)->size++; 7772333SN/A instsToExecute.push_back(inst); 7782292SN/A} 7792292SN/A 7801061SN/A// @todo: Figure out a better way to remove the squashed items from the 7811061SN/A// lists. Checking the top item of each list to see if it's squashed 7821061SN/A// wastes time and forces jumps. 7831061SN/Atemplate <class Impl> 7841060SN/Avoid 7851060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7861060SN/A{ 7872292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7882292SN/A "the IQ.\n"); 7891060SN/A 7901060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7911060SN/A 79210333Smitch.hayenga@arm.com DynInstPtr mem_inst; 79313429Srekai.gonzalezalberquilla@arm.com while (mem_inst = std::move(getDeferredMemInstToExecute())) { 79410333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 79510333Smitch.hayenga@arm.com } 79610333Smitch.hayenga@arm.com 79710333Smitch.hayenga@arm.com // See if any cache blocked instructions are able to be executed 79813429Srekai.gonzalezalberquilla@arm.com while (mem_inst = std::move(getBlockedMemInstToExecute())) { 79910333Smitch.hayenga@arm.com addReadyMemInst(mem_inst); 8007944SGiacomo.Gabrielli@arm.com } 8017944SGiacomo.Gabrielli@arm.com 8022292SN/A // Have iterator to head of the list 8032292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 8042292SN/A // Try to get a FU that can do what this op needs. 8052292SN/A // If successful, change the oldestInst to the new top of the list, put 8062292SN/A // the queue in the proper place in the list. 8072292SN/A // Increment the iterator. 8082292SN/A // This will avoid trying to schedule a certain op class if there are no 8092292SN/A // FUs that handle it. 81010333Smitch.hayenga@arm.com int total_issued = 0; 8112292SN/A ListOrderIt order_it = listOrder.begin(); 8122292SN/A ListOrderIt order_end_it = listOrder.end(); 8131060SN/A 81410333Smitch.hayenga@arm.com while (total_issued < totalWidth && order_it != order_end_it) { 8152292SN/A OpClass op_class = (*order_it).queueType; 8161060SN/A 8172292SN/A assert(!readyInsts[op_class].empty()); 8181060SN/A 8192292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 8201060SN/A 82112110SRekai.GonzalezAlberquilla@arm.com if (issuing_inst->isFloating()) { 82212110SRekai.GonzalezAlberquilla@arm.com fpInstQueueReads++; 82312110SRekai.GonzalezAlberquilla@arm.com } else if (issuing_inst->isVector()) { 82412110SRekai.GonzalezAlberquilla@arm.com vecInstQueueReads++; 82512110SRekai.GonzalezAlberquilla@arm.com } else { 82612110SRekai.GonzalezAlberquilla@arm.com intInstQueueReads++; 82712110SRekai.GonzalezAlberquilla@arm.com } 8287897Shestness@cs.utexas.edu 8292292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 8301060SN/A 8312292SN/A if (issuing_inst->isSquashed()) { 8322292SN/A readyInsts[op_class].pop(); 8331060SN/A 8342292SN/A if (!readyInsts[op_class].empty()) { 8352292SN/A moveToYoungerInst(order_it); 8362292SN/A } else { 8372292SN/A readyIt[op_class] = listOrder.end(); 8382292SN/A queueOnList[op_class] = false; 8391060SN/A } 8401060SN/A 8412292SN/A listOrder.erase(order_it++); 8421060SN/A 8432292SN/A ++iqSquashedInstsIssued; 8442292SN/A 8452292SN/A continue; 8461060SN/A } 8471060SN/A 84811365SRekai.GonzalezAlberquilla@arm.com int idx = FUPool::NoCapableFU; 8499184Sandreas.hansson@arm.com Cycles op_latency = Cycles(1); 8506221Snate@binkert.org ThreadID tid = issuing_inst->threadNumber; 8511060SN/A 8522326SN/A if (op_class != No_OpClass) { 8532326SN/A idx = fuPool->getUnit(op_class); 85412110SRekai.GonzalezAlberquilla@arm.com if (issuing_inst->isFloating()) { 85512110SRekai.GonzalezAlberquilla@arm.com fpAluAccesses++; 85612110SRekai.GonzalezAlberquilla@arm.com } else if (issuing_inst->isVector()) { 85712110SRekai.GonzalezAlberquilla@arm.com vecAluAccesses++; 85812110SRekai.GonzalezAlberquilla@arm.com } else { 85912110SRekai.GonzalezAlberquilla@arm.com intAluAccesses++; 86012110SRekai.GonzalezAlberquilla@arm.com } 86111365SRekai.GonzalezAlberquilla@arm.com if (idx > FUPool::NoFreeFU) { 8622326SN/A op_latency = fuPool->getOpLatency(op_class); 8631060SN/A } 8641060SN/A } 8651060SN/A 8662348SN/A // If we have an instruction that doesn't require a FU, or a 8672348SN/A // valid FU, then schedule for execution. 86811365SRekai.GonzalezAlberquilla@arm.com if (idx != FUPool::NoFreeFU) { 8699184Sandreas.hansson@arm.com if (op_latency == Cycles(1)) { 8702292SN/A i2e_info->size++; 8712333SN/A instsToExecute.push_back(issuing_inst); 8721060SN/A 8732326SN/A // Add the FU onto the list of FU's to be freed next 8742326SN/A // cycle if we used one. 8752326SN/A if (idx >= 0) 8762326SN/A fuPool->freeUnitNextCycle(idx); 8772292SN/A } else { 87810807Snilay@cs.wisc.edu bool pipelined = fuPool->isPipelined(op_class); 8792326SN/A // Generate completion event for the FU 88010511Smitch.hayenga@arm.com ++wbOutstanding; 8812326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8822326SN/A idx, this); 8831060SN/A 8849180Sandreas.hansson@arm.com cpu->schedule(execution, 8859180Sandreas.hansson@arm.com cpu->clockEdge(Cycles(op_latency - 1))); 8861060SN/A 88710807Snilay@cs.wisc.edu if (!pipelined) { 8882348SN/A // If FU isn't pipelined, then it must be freed 8892348SN/A // upon the execution completing. 8902326SN/A execution->setFreeFU(); 8912292SN/A } else { 8922292SN/A // Add the FU onto the list of FU's to be freed next cycle. 8932326SN/A fuPool->freeUnitNextCycle(idx); 8942292SN/A } 8951060SN/A } 8961060SN/A 8977720Sgblack@eecs.umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8982292SN/A "[sn:%lli]\n", 8997720Sgblack@eecs.umich.edu tid, issuing_inst->pcState(), 9002292SN/A issuing_inst->seqNum); 9011060SN/A 9022292SN/A readyInsts[op_class].pop(); 9031061SN/A 9042292SN/A if (!readyInsts[op_class].empty()) { 9052292SN/A moveToYoungerInst(order_it); 9062292SN/A } else { 9072292SN/A readyIt[op_class] = listOrder.end(); 9082292SN/A queueOnList[op_class] = false; 9091060SN/A } 9101060SN/A 9112064SN/A issuing_inst->setIssued(); 9122292SN/A ++total_issued; 9132064SN/A 9148471SGiacomo.Gabrielli@arm.com#if TRACING_ON 9159046SAli.Saidi@ARM.com issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 9168471SGiacomo.Gabrielli@arm.com#endif 9178471SGiacomo.Gabrielli@arm.com 9182292SN/A if (!issuing_inst->isMemRef()) { 9192292SN/A // Memory instructions can not be freed from the IQ until they 9202292SN/A // complete. 9212292SN/A ++freeEntries; 9222301SN/A count[tid]--; 9232731Sktlim@umich.edu issuing_inst->clearInIQ(); 9242292SN/A } else { 9252301SN/A memDepUnit[tid].issue(issuing_inst); 9262292SN/A } 9272292SN/A 9282292SN/A listOrder.erase(order_it++); 9292326SN/A statIssuedInstType[tid][op_class]++; 9302292SN/A } else { 9312326SN/A statFuBusy[op_class]++; 9322326SN/A fuBusy[tid]++; 9332292SN/A ++order_it; 9341060SN/A } 9351060SN/A } 9361062SN/A 9372326SN/A numIssuedDist.sample(total_issued); 9382326SN/A iqInstsIssued+= total_issued; 9392307SN/A 9402348SN/A // If we issued any instructions, tell the CPU we had activity. 9418071SAli.Saidi@ARM.com // @todo If the way deferred memory instructions are handeled due to 9428071SAli.Saidi@ARM.com // translation changes then the deferredMemInsts condition should be removed 9438071SAli.Saidi@ARM.com // from the code below. 94410333Smitch.hayenga@arm.com if (total_issued || !retryMemInsts.empty() || !deferredMemInsts.empty()) { 9452292SN/A cpu->activityThisCycle(); 9462292SN/A } else { 9472292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 9482292SN/A } 9491060SN/A} 9501060SN/A 9511061SN/Atemplate <class Impl> 9521060SN/Avoid 9531061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 9541060SN/A{ 9552292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 9562292SN/A "to execute.\n", inst); 9571062SN/A 9582292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 9591060SN/A 9601061SN/A assert(inst_it != nonSpecInsts.end()); 9611060SN/A 9626221Snate@binkert.org ThreadID tid = (*inst_it).second->threadNumber; 9632292SN/A 9644033Sktlim@umich.edu (*inst_it).second->setAtCommit(); 9654033Sktlim@umich.edu 9661061SN/A (*inst_it).second->setCanIssue(); 9671060SN/A 9681062SN/A if (!(*inst_it).second->isMemRef()) { 9691062SN/A addIfReady((*inst_it).second); 9701062SN/A } else { 9712292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9721062SN/A } 9731060SN/A 9742292SN/A (*inst_it).second = NULL; 9752292SN/A 9761061SN/A nonSpecInsts.erase(inst_it); 9771060SN/A} 9781060SN/A 9791061SN/Atemplate <class Impl> 9801061SN/Avoid 9816221Snate@binkert.orgInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9822292SN/A{ 9832292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9842292SN/A tid,inst); 9852292SN/A 9862292SN/A ListIt iq_it = instList[tid].begin(); 9872292SN/A 9882292SN/A while (iq_it != instList[tid].end() && 9892292SN/A (*iq_it)->seqNum <= inst) { 9902292SN/A ++iq_it; 9912292SN/A instList[tid].pop_front(); 9922292SN/A } 9932292SN/A 9942292SN/A assert(freeEntries == (numEntries - countInsts())); 9952292SN/A} 9962292SN/A 9972292SN/Atemplate <class Impl> 9982301SN/Aint 99913429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::wakeDependents(const DynInstPtr &completed_inst) 10001684SN/A{ 10012301SN/A int dependents = 0; 10022301SN/A 10037897Shestness@cs.utexas.edu // The instruction queue here takes care of both floating and int ops 10047897Shestness@cs.utexas.edu if (completed_inst->isFloating()) { 100512110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWakeupAccesses++; 100612110SRekai.GonzalezAlberquilla@arm.com } else if (completed_inst->isVector()) { 100712110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWakeupAccesses++; 10087897Shestness@cs.utexas.edu } else { 10097897Shestness@cs.utexas.edu intInstQueueWakeupAccesses++; 10107897Shestness@cs.utexas.edu } 10117897Shestness@cs.utexas.edu 10122292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 10132292SN/A 10142292SN/A assert(!completed_inst->isSquashed()); 10151684SN/A 10161684SN/A // Tell the memory dependence unit to wake any dependents on this 10172292SN/A // instruction if it is a memory instruction. Also complete the memory 10182326SN/A // instruction at this point since we know it executed without issues. 10192326SN/A // @todo: Might want to rename "completeMemInst" to something that 10202326SN/A // indicates that it won't need to be replayed, and call this 10212326SN/A // earlier. Might not be a big deal. 10221684SN/A if (completed_inst->isMemRef()) { 10232292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 10242292SN/A completeMemInst(completed_inst); 10252292SN/A } else if (completed_inst->isMemBarrier() || 10262292SN/A completed_inst->isWriteBarrier()) { 10272292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 10281684SN/A } 10291684SN/A 10301684SN/A for (int dest_reg_idx = 0; 10311684SN/A dest_reg_idx < completed_inst->numDestRegs(); 10321684SN/A dest_reg_idx++) 10331684SN/A { 103412105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = 10351684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 10361684SN/A 10371684SN/A // Special case of uniq or control registers. They are not 10381684SN/A // handled by the IQ and thus have no dependency graph entry. 103912105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 104012105Snathanael.premillieu@arm.com DPRINTF(IQ, "Reg %d [%s] is part of a fix mapping, skipping\n", 104112106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className()); 10421684SN/A continue; 10431684SN/A } 10441684SN/A 104512105Snathanael.premillieu@arm.com DPRINTF(IQ, "Waking any dependents on register %i (%s).\n", 104612106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), 104712106SRekai.GonzalezAlberquilla@arm.com dest_reg->className()); 10481684SN/A 10492326SN/A //Go through the dependency chain, marking the registers as 10502326SN/A //ready within the waiting instructions. 105112106SRekai.GonzalezAlberquilla@arm.com DynInstPtr dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10521684SN/A 10532326SN/A while (dep_inst) { 10547599Sminkyu.jeong@arm.com DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 10557720Sgblack@eecs.umich.edu "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 10561684SN/A 10571684SN/A // Might want to give more information to the instruction 10582326SN/A // so that it knows which of its source registers is 10592326SN/A // ready. However that would mean that the dependency 10602326SN/A // graph entries would need to hold the src_reg_idx. 10612326SN/A dep_inst->markSrcRegReady(); 10621684SN/A 10632326SN/A addIfReady(dep_inst); 10641684SN/A 106512106SRekai.GonzalezAlberquilla@arm.com dep_inst = dependGraph.pop(dest_reg->flatIndex()); 10661684SN/A 10672301SN/A ++dependents; 10681684SN/A } 10691684SN/A 10702326SN/A // Reset the head node now that all of its dependents have 10712326SN/A // been woken up. 107212106SRekai.GonzalezAlberquilla@arm.com assert(dependGraph.empty(dest_reg->flatIndex())); 107312106SRekai.GonzalezAlberquilla@arm.com dependGraph.clearInst(dest_reg->flatIndex()); 10741684SN/A 10751684SN/A // Mark the scoreboard as having that register ready. 107612106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = true; 10771684SN/A } 10782301SN/A return dependents; 10792064SN/A} 10802064SN/A 10812064SN/Atemplate <class Impl> 10822064SN/Avoid 108313429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addReadyMemInst(const DynInstPtr &ready_inst) 10842064SN/A{ 10852292SN/A OpClass op_class = ready_inst->opClass(); 10862292SN/A 10872292SN/A readyInsts[op_class].push(ready_inst); 10882292SN/A 10892326SN/A // Will need to reorder the list if either a queue is not on the list, 10902326SN/A // or it has an older instruction than last time. 10912326SN/A if (!queueOnList[op_class]) { 10922326SN/A addToOrderList(op_class); 10932326SN/A } else if (readyInsts[op_class].top()->seqNum < 10942326SN/A (*readyIt[op_class]).oldestInst) { 10952326SN/A listOrder.erase(readyIt[op_class]); 10962326SN/A addToOrderList(op_class); 10972326SN/A } 10982326SN/A 10992292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 11007720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 11017720Sgblack@eecs.umich.edu ready_inst->pcState(), op_class, ready_inst->seqNum); 11022064SN/A} 11032064SN/A 11042064SN/Atemplate <class Impl> 11052064SN/Avoid 110613429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::rescheduleMemInst(const DynInstPtr &resched_inst) 11072064SN/A{ 11084033Sktlim@umich.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 11097944SGiacomo.Gabrielli@arm.com 11107944SGiacomo.Gabrielli@arm.com // Reset DTB translation state 11119046SAli.Saidi@ARM.com resched_inst->translationStarted(false); 11129046SAli.Saidi@ARM.com resched_inst->translationCompleted(false); 11137944SGiacomo.Gabrielli@arm.com 11144033Sktlim@umich.edu resched_inst->clearCanIssue(); 11152292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 11162064SN/A} 11172064SN/A 11182064SN/Atemplate <class Impl> 11192064SN/Avoid 112013429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::replayMemInst(const DynInstPtr &replay_inst) 11212064SN/A{ 112210333Smitch.hayenga@arm.com memDepUnit[replay_inst->threadNumber].replay(); 11232292SN/A} 11242292SN/A 11252292SN/Atemplate <class Impl> 11262292SN/Avoid 112713429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::completeMemInst(const DynInstPtr &completed_inst) 11282292SN/A{ 11296221Snate@binkert.org ThreadID tid = completed_inst->threadNumber; 11302292SN/A 11317720Sgblack@eecs.umich.edu DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 11327720Sgblack@eecs.umich.edu completed_inst->pcState(), completed_inst->seqNum); 11332292SN/A 11342292SN/A ++freeEntries; 11352292SN/A 11369046SAli.Saidi@ARM.com completed_inst->memOpDone(true); 11372292SN/A 11382292SN/A memDepUnit[tid].completed(completed_inst); 11392292SN/A count[tid]--; 11401684SN/A} 11411684SN/A 11421684SN/Atemplate <class Impl> 11431684SN/Avoid 114413429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::deferMemInst(const DynInstPtr &deferred_inst) 11457944SGiacomo.Gabrielli@arm.com{ 11467944SGiacomo.Gabrielli@arm.com deferredMemInsts.push_back(deferred_inst); 11477944SGiacomo.Gabrielli@arm.com} 11487944SGiacomo.Gabrielli@arm.com 11497944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 115010333Smitch.hayenga@arm.comvoid 115113429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::blockMemInst(const DynInstPtr &blocked_inst) 115210333Smitch.hayenga@arm.com{ 115310333Smitch.hayenga@arm.com blocked_inst->translationStarted(false); 115410333Smitch.hayenga@arm.com blocked_inst->translationCompleted(false); 115510333Smitch.hayenga@arm.com 115610333Smitch.hayenga@arm.com blocked_inst->clearIssued(); 115710333Smitch.hayenga@arm.com blocked_inst->clearCanIssue(); 115810333Smitch.hayenga@arm.com blockedMemInsts.push_back(blocked_inst); 115910333Smitch.hayenga@arm.com} 116010333Smitch.hayenga@arm.com 116110333Smitch.hayenga@arm.comtemplate <class Impl> 116210333Smitch.hayenga@arm.comvoid 116310333Smitch.hayenga@arm.comInstructionQueue<Impl>::cacheUnblocked() 116410333Smitch.hayenga@arm.com{ 116510333Smitch.hayenga@arm.com retryMemInsts.splice(retryMemInsts.end(), blockedMemInsts); 116610333Smitch.hayenga@arm.com // Get the CPU ticking again 116710333Smitch.hayenga@arm.com cpu->wakeCPU(); 116810333Smitch.hayenga@arm.com} 116910333Smitch.hayenga@arm.com 117010333Smitch.hayenga@arm.comtemplate <class Impl> 11717944SGiacomo.Gabrielli@arm.comtypename Impl::DynInstPtr 11727944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::getDeferredMemInstToExecute() 11737944SGiacomo.Gabrielli@arm.com{ 11747944SGiacomo.Gabrielli@arm.com for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 11757944SGiacomo.Gabrielli@arm.com ++it) { 11769046SAli.Saidi@ARM.com if ((*it)->translationCompleted() || (*it)->isSquashed()) { 117713429Srekai.gonzalezalberquilla@arm.com DynInstPtr mem_inst = std::move(*it); 11787944SGiacomo.Gabrielli@arm.com deferredMemInsts.erase(it); 117910333Smitch.hayenga@arm.com return mem_inst; 11807944SGiacomo.Gabrielli@arm.com } 11817944SGiacomo.Gabrielli@arm.com } 118210333Smitch.hayenga@arm.com return nullptr; 118310333Smitch.hayenga@arm.com} 118410333Smitch.hayenga@arm.com 118510333Smitch.hayenga@arm.comtemplate <class Impl> 118610333Smitch.hayenga@arm.comtypename Impl::DynInstPtr 118710333Smitch.hayenga@arm.comInstructionQueue<Impl>::getBlockedMemInstToExecute() 118810333Smitch.hayenga@arm.com{ 118910333Smitch.hayenga@arm.com if (retryMemInsts.empty()) { 119010333Smitch.hayenga@arm.com return nullptr; 119110333Smitch.hayenga@arm.com } else { 119213429Srekai.gonzalezalberquilla@arm.com DynInstPtr mem_inst = std::move(retryMemInsts.front()); 119310333Smitch.hayenga@arm.com retryMemInsts.pop_front(); 119410333Smitch.hayenga@arm.com return mem_inst; 119510333Smitch.hayenga@arm.com } 11967944SGiacomo.Gabrielli@arm.com} 11977944SGiacomo.Gabrielli@arm.com 11987944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 11997944SGiacomo.Gabrielli@arm.comvoid 120013429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::violation(const DynInstPtr &store, 120113429Srekai.gonzalezalberquilla@arm.com const DynInstPtr &faulting_load) 12021061SN/A{ 12037897Shestness@cs.utexas.edu intInstQueueWrites++; 12042292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 12051061SN/A} 12061061SN/A 12071061SN/Atemplate <class Impl> 12081060SN/Avoid 12096221Snate@binkert.orgInstructionQueue<Impl>::squash(ThreadID tid) 12101060SN/A{ 12112292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 12122292SN/A "the IQ.\n", tid); 12131060SN/A 12141060SN/A // Read instruction sequence number of last instruction out of the 12151060SN/A // time buffer. 12162292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 12171060SN/A 121810797Sbrandon.potter@amd.com doSquash(tid); 12191061SN/A 12201061SN/A // Also tell the memory dependence unit to squash. 12212292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 12221060SN/A} 12231060SN/A 12241061SN/Atemplate <class Impl> 12251061SN/Avoid 12266221Snate@binkert.orgInstructionQueue<Impl>::doSquash(ThreadID tid) 12271061SN/A{ 12282326SN/A // Start at the tail. 12292326SN/A ListIt squash_it = instList[tid].end(); 12302326SN/A --squash_it; 12311061SN/A 12322292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 12332292SN/A tid, squashedSeqNum[tid]); 12341061SN/A 12351061SN/A // Squash any instructions younger than the squashed sequence number 12361061SN/A // given. 12372326SN/A while (squash_it != instList[tid].end() && 12382326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 12392292SN/A 12402326SN/A DynInstPtr squashed_inst = (*squash_it); 124112110SRekai.GonzalezAlberquilla@arm.com if (squashed_inst->isFloating()) { 124212110SRekai.GonzalezAlberquilla@arm.com fpInstQueueWrites++; 124312110SRekai.GonzalezAlberquilla@arm.com } else if (squashed_inst->isVector()) { 124412110SRekai.GonzalezAlberquilla@arm.com vecInstQueueWrites++; 124512110SRekai.GonzalezAlberquilla@arm.com } else { 124612110SRekai.GonzalezAlberquilla@arm.com intInstQueueWrites++; 124712110SRekai.GonzalezAlberquilla@arm.com } 12481061SN/A 12491061SN/A // Only handle the instruction if it actually is in the IQ and 12501061SN/A // hasn't already been squashed in the IQ. 12512292SN/A if (squashed_inst->threadNumber != tid || 12522292SN/A squashed_inst->isSquashedInIQ()) { 12532326SN/A --squash_it; 12542292SN/A continue; 12552292SN/A } 12562292SN/A 12572292SN/A if (!squashed_inst->isIssued() || 12582292SN/A (squashed_inst->isMemRef() && 12599046SAli.Saidi@ARM.com !squashed_inst->memOpDone())) { 12601062SN/A 12617720Sgblack@eecs.umich.edu DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 12627720Sgblack@eecs.umich.edu tid, squashed_inst->seqNum, squashed_inst->pcState()); 12632367SN/A 126410032SGiacomo.Gabrielli@arm.com bool is_acq_rel = squashed_inst->isMemBarrier() && 126510032SGiacomo.Gabrielli@arm.com (squashed_inst->isLoad() || 126610032SGiacomo.Gabrielli@arm.com (squashed_inst->isStore() && 126710032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional())); 126810032SGiacomo.Gabrielli@arm.com 12691061SN/A // Remove the instruction from the dependency list. 127010032SGiacomo.Gabrielli@arm.com if (is_acq_rel || 127110032SGiacomo.Gabrielli@arm.com (!squashed_inst->isNonSpeculative() && 127210032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional() && 127310032SGiacomo.Gabrielli@arm.com !squashed_inst->isMemBarrier() && 127410032SGiacomo.Gabrielli@arm.com !squashed_inst->isWriteBarrier())) { 12751061SN/A 12761061SN/A for (int src_reg_idx = 0; 12771681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 12781061SN/A src_reg_idx++) 12791061SN/A { 128012105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = 12811061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 12821061SN/A 12832326SN/A // Only remove it from the dependency graph if it 12842326SN/A // was placed there in the first place. 12852326SN/A 12862326SN/A // Instead of doing a linked list traversal, we 12872326SN/A // can just remove these squashed instructions 12882326SN/A // either at issue time, or when the register is 12892326SN/A // overwritten. The only downside to this is it 12902326SN/A // leaves more room for error. 12912292SN/A 12921061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 129312105Snathanael.premillieu@arm.com !src_reg->isFixedMapping()) { 129412106SRekai.GonzalezAlberquilla@arm.com dependGraph.remove(src_reg->flatIndex(), 129512106SRekai.GonzalezAlberquilla@arm.com squashed_inst); 12961061SN/A } 12971062SN/A 12982292SN/A 12991062SN/A ++iqSquashedOperandsExamined; 13001061SN/A } 13014033Sktlim@umich.edu } else if (!squashed_inst->isStoreConditional() || 13024033Sktlim@umich.edu !squashed_inst->isCompleted()) { 13032292SN/A NonSpecMapIt ns_inst_it = 13042292SN/A nonSpecInsts.find(squashed_inst->seqNum); 13058275SAli.Saidi@ARM.com 130610017Sandreas.hansson@arm.com // we remove non-speculative instructions from 130710017Sandreas.hansson@arm.com // nonSpecInsts already when they are ready, and so we 130810017Sandreas.hansson@arm.com // cannot always expect to find them 13094033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 131010017Sandreas.hansson@arm.com // loads that became ready but stalled on a 131110017Sandreas.hansson@arm.com // blocked cache are alreayd removed from 131210017Sandreas.hansson@arm.com // nonSpecInsts, and have not faulted 131310017Sandreas.hansson@arm.com assert(squashed_inst->getFault() != NoFault || 131410017Sandreas.hansson@arm.com squashed_inst->isMemRef()); 13154033Sktlim@umich.edu } else { 13161062SN/A 13174033Sktlim@umich.edu (*ns_inst_it).second = NULL; 13181681SN/A 13194033Sktlim@umich.edu nonSpecInsts.erase(ns_inst_it); 13201062SN/A 13214033Sktlim@umich.edu ++iqSquashedNonSpecRemoved; 13224033Sktlim@umich.edu } 13231061SN/A } 13241061SN/A 13251061SN/A // Might want to also clear out the head of the dependency graph. 13261061SN/A 13271061SN/A // Mark it as squashed within the IQ. 13281061SN/A squashed_inst->setSquashedInIQ(); 13291061SN/A 13302292SN/A // @todo: Remove this hack where several statuses are set so the 13312292SN/A // inst will flow through the rest of the pipeline. 13321681SN/A squashed_inst->setIssued(); 13331681SN/A squashed_inst->setCanCommit(); 13342731Sktlim@umich.edu squashed_inst->clearInIQ(); 13352292SN/A 13362292SN/A //Update Thread IQ Count 13372292SN/A count[squashed_inst->threadNumber]--; 13381681SN/A 13391681SN/A ++freeEntries; 13401061SN/A } 13411061SN/A 134212833Sjang.hanhwi@gmail.com // IQ clears out the heads of the dependency graph only when 134312833Sjang.hanhwi@gmail.com // instructions reach writeback stage. If an instruction is squashed 134412833Sjang.hanhwi@gmail.com // before writeback stage, its head of dependency graph would not be 134512833Sjang.hanhwi@gmail.com // cleared out; it holds the instruction's DynInstPtr. This prevents 134612833Sjang.hanhwi@gmail.com // freeing the squashed instruction's DynInst. 134712833Sjang.hanhwi@gmail.com // Thus, we need to manually clear out the squashed instructions' heads 134812833Sjang.hanhwi@gmail.com // of dependency graph. 134912833Sjang.hanhwi@gmail.com for (int dest_reg_idx = 0; 135012833Sjang.hanhwi@gmail.com dest_reg_idx < squashed_inst->numDestRegs(); 135112833Sjang.hanhwi@gmail.com dest_reg_idx++) 135212833Sjang.hanhwi@gmail.com { 135312833Sjang.hanhwi@gmail.com PhysRegIdPtr dest_reg = 135412833Sjang.hanhwi@gmail.com squashed_inst->renamedDestRegIdx(dest_reg_idx); 135512833Sjang.hanhwi@gmail.com if (dest_reg->isFixedMapping()){ 135612833Sjang.hanhwi@gmail.com continue; 135712833Sjang.hanhwi@gmail.com } 135812833Sjang.hanhwi@gmail.com assert(dependGraph.empty(dest_reg->flatIndex())); 135912833Sjang.hanhwi@gmail.com dependGraph.clearInst(dest_reg->flatIndex()); 136012833Sjang.hanhwi@gmail.com } 13612326SN/A instList[tid].erase(squash_it--); 13621062SN/A ++iqSquashedInstsExamined; 13631061SN/A } 13641060SN/A} 13651060SN/A 13661061SN/Atemplate <class Impl> 13671060SN/Abool 136813429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addToDependents(const DynInstPtr &new_inst) 13691060SN/A{ 13701060SN/A // Loop through the instruction's source registers, adding 13711060SN/A // them to the dependency list if they are not ready. 13721060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 13731060SN/A bool return_val = false; 13741060SN/A 13751060SN/A for (int src_reg_idx = 0; 13761060SN/A src_reg_idx < total_src_regs; 13771060SN/A src_reg_idx++) 13781060SN/A { 13791060SN/A // Only add it to the dependency graph if it's not ready. 13801060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 138112105Snathanael.premillieu@arm.com PhysRegIdPtr src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 13821060SN/A 13831060SN/A // Check the IQ's scoreboard to make sure the register 13841060SN/A // hasn't become ready while the instruction was in flight 13851060SN/A // between stages. Only if it really isn't ready should 13861060SN/A // it be added to the dependency graph. 138712105Snathanael.premillieu@arm.com if (src_reg->isFixedMapping()) { 13881061SN/A continue; 138912106SRekai.GonzalezAlberquilla@arm.com } else if (!regScoreboard[src_reg->flatIndex()]) { 139012105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 13911060SN/A "is being added to the dependency chain.\n", 139212106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 139312106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 13941060SN/A 139512106SRekai.GonzalezAlberquilla@arm.com dependGraph.insert(src_reg->flatIndex(), new_inst); 13961060SN/A 13971060SN/A // Change the return value to indicate that something 13981060SN/A // was added to the dependency graph. 13991060SN/A return_val = true; 14001060SN/A } else { 140112105Snathanael.premillieu@arm.com DPRINTF(IQ, "Instruction PC %s has src reg %i (%s) that " 14021060SN/A "became ready before it reached the IQ.\n", 140312106SRekai.GonzalezAlberquilla@arm.com new_inst->pcState(), src_reg->index(), 140412106SRekai.GonzalezAlberquilla@arm.com src_reg->className()); 14051060SN/A // Mark a register ready within the instruction. 14062326SN/A new_inst->markSrcRegReady(src_reg_idx); 14071060SN/A } 14081060SN/A } 14091060SN/A } 14101060SN/A 14111060SN/A return return_val; 14121060SN/A} 14131060SN/A 14141061SN/Atemplate <class Impl> 14151060SN/Avoid 141613429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addToProducers(const DynInstPtr &new_inst) 14171060SN/A{ 14182326SN/A // Nothing really needs to be marked when an instruction becomes 14192326SN/A // the producer of a register's value, but for convenience a ptr 14202326SN/A // to the producing instruction will be placed in the head node of 14212326SN/A // the dependency links. 14221060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 14231060SN/A 14241060SN/A for (int dest_reg_idx = 0; 14251060SN/A dest_reg_idx < total_dest_regs; 14261060SN/A dest_reg_idx++) 14271060SN/A { 142812105Snathanael.premillieu@arm.com PhysRegIdPtr dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 14291061SN/A 143012105Snathanael.premillieu@arm.com // Some registers have fixed mapping, and there is no need to track 14311061SN/A // dependencies as these instructions must be executed at commit. 143212105Snathanael.premillieu@arm.com if (dest_reg->isFixedMapping()) { 14331061SN/A continue; 14341060SN/A } 14351060SN/A 143612106SRekai.GonzalezAlberquilla@arm.com if (!dependGraph.empty(dest_reg->flatIndex())) { 14372326SN/A dependGraph.dump(); 143812105Snathanael.premillieu@arm.com panic("Dependency graph %i (%s) (flat: %i) not empty!", 143912106SRekai.GonzalezAlberquilla@arm.com dest_reg->index(), dest_reg->className(), 144012106SRekai.GonzalezAlberquilla@arm.com dest_reg->flatIndex()); 14412064SN/A } 14421062SN/A 144312106SRekai.GonzalezAlberquilla@arm.com dependGraph.setInst(dest_reg->flatIndex(), new_inst); 14441062SN/A 14451060SN/A // Mark the scoreboard to say it's not yet ready. 144612106SRekai.GonzalezAlberquilla@arm.com regScoreboard[dest_reg->flatIndex()] = false; 14471060SN/A } 14481060SN/A} 14491060SN/A 14501061SN/Atemplate <class Impl> 14511060SN/Avoid 145213429Srekai.gonzalezalberquilla@arm.comInstructionQueue<Impl>::addIfReady(const DynInstPtr &inst) 14531060SN/A{ 14542326SN/A // If the instruction now has all of its source registers 14551060SN/A // available, then add it to the list of ready instructions. 14561060SN/A if (inst->readyToIssue()) { 14571061SN/A 14581060SN/A //Add the instruction to the proper ready list. 14592292SN/A if (inst->isMemRef()) { 14601061SN/A 14612292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 14621061SN/A 14631062SN/A // Message to the mem dependence unit that this instruction has 14641062SN/A // its registers ready. 14652292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 14661062SN/A 14672292SN/A return; 14682292SN/A } 14691062SN/A 14702292SN/A OpClass op_class = inst->opClass(); 14711061SN/A 14722292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 14737720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 14747720Sgblack@eecs.umich.edu inst->pcState(), op_class, inst->seqNum); 14751061SN/A 14762292SN/A readyInsts[op_class].push(inst); 14771061SN/A 14782326SN/A // Will need to reorder the list if either a queue is not on the list, 14792326SN/A // or it has an older instruction than last time. 14802326SN/A if (!queueOnList[op_class]) { 14812326SN/A addToOrderList(op_class); 14822326SN/A } else if (readyInsts[op_class].top()->seqNum < 14832326SN/A (*readyIt[op_class]).oldestInst) { 14842326SN/A listOrder.erase(readyIt[op_class]); 14852326SN/A addToOrderList(op_class); 14861060SN/A } 14871060SN/A } 14881060SN/A} 14891060SN/A 14901061SN/Atemplate <class Impl> 14911061SN/Aint 14921061SN/AInstructionQueue<Impl>::countInsts() 14931061SN/A{ 14942698Sktlim@umich.edu#if 0 14952292SN/A //ksewell:This works but definitely could use a cleaner write 14962292SN/A //with a more intuitive way of counting. Right now it's 14972292SN/A //just brute force .... 14982698Sktlim@umich.edu // Change the #if if you want to use this method. 14991061SN/A int total_insts = 0; 15001061SN/A 15016221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 15026221Snate@binkert.org ListIt count_it = instList[tid].begin(); 15031681SN/A 15046221Snate@binkert.org while (count_it != instList[tid].end()) { 15052292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 15062292SN/A if (!(*count_it)->isIssued()) { 15072292SN/A ++total_insts; 15082292SN/A } else if ((*count_it)->isMemRef() && 15092292SN/A !(*count_it)->memOpDone) { 15102292SN/A // Loads that have not been marked as executed still count 15112292SN/A // towards the total instructions. 15122292SN/A ++total_insts; 15132292SN/A } 15142292SN/A } 15152292SN/A 15162292SN/A ++count_it; 15171061SN/A } 15181061SN/A } 15191061SN/A 15201061SN/A return total_insts; 15212292SN/A#else 15222292SN/A return numEntries - freeEntries; 15232292SN/A#endif 15241681SN/A} 15251681SN/A 15261681SN/Atemplate <class Impl> 15271681SN/Avoid 15281061SN/AInstructionQueue<Impl>::dumpLists() 15291061SN/A{ 15302292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 15312292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 15321061SN/A 15332292SN/A cprintf("\n"); 15342292SN/A } 15351061SN/A 15361061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 15371061SN/A 15382292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 15392292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 15401061SN/A 15411061SN/A cprintf("Non speculative list: "); 15421061SN/A 15432292SN/A while (non_spec_it != non_spec_end_it) { 15447720Sgblack@eecs.umich.edu cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 15452292SN/A (*non_spec_it).second->seqNum); 15461061SN/A ++non_spec_it; 15471061SN/A } 15481061SN/A 15491061SN/A cprintf("\n"); 15501061SN/A 15512292SN/A ListOrderIt list_order_it = listOrder.begin(); 15522292SN/A ListOrderIt list_order_end_it = listOrder.end(); 15532292SN/A int i = 1; 15542292SN/A 15552292SN/A cprintf("List order: "); 15562292SN/A 15572292SN/A while (list_order_it != list_order_end_it) { 15582292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 15592292SN/A (*list_order_it).oldestInst); 15602292SN/A 15612292SN/A ++list_order_it; 15622292SN/A ++i; 15632292SN/A } 15642292SN/A 15652292SN/A cprintf("\n"); 15661061SN/A} 15672292SN/A 15682292SN/A 15692292SN/Atemplate <class Impl> 15702292SN/Avoid 15712292SN/AInstructionQueue<Impl>::dumpInsts() 15722292SN/A{ 15736221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 15742292SN/A int num = 0; 15752292SN/A int valid_num = 0; 15766221Snate@binkert.org ListIt inst_list_it = instList[tid].begin(); 15772292SN/A 15786221Snate@binkert.org while (inst_list_it != instList[tid].end()) { 15796221Snate@binkert.org cprintf("Instruction:%i\n", num); 15802292SN/A if (!(*inst_list_it)->isSquashed()) { 15812292SN/A if (!(*inst_list_it)->isIssued()) { 15822292SN/A ++valid_num; 15832292SN/A cprintf("Count:%i\n", valid_num); 15842292SN/A } else if ((*inst_list_it)->isMemRef() && 15859046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 15862326SN/A // Loads that have not been marked as executed 15872326SN/A // still count towards the total instructions. 15882292SN/A ++valid_num; 15892292SN/A cprintf("Count:%i\n", valid_num); 15902292SN/A } 15912292SN/A } 15922292SN/A 15937720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 15942292SN/A "Issued:%i\nSquashed:%i\n", 15957720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 15962292SN/A (*inst_list_it)->seqNum, 15972292SN/A (*inst_list_it)->threadNumber, 15982292SN/A (*inst_list_it)->isIssued(), 15992292SN/A (*inst_list_it)->isSquashed()); 16002292SN/A 16012292SN/A if ((*inst_list_it)->isMemRef()) { 16029046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 16032292SN/A } 16042292SN/A 16052292SN/A cprintf("\n"); 16062292SN/A 16072292SN/A inst_list_it++; 16082292SN/A ++num; 16092292SN/A } 16102292SN/A } 16112348SN/A 16122348SN/A cprintf("Insts to Execute list:\n"); 16132348SN/A 16142348SN/A int num = 0; 16152348SN/A int valid_num = 0; 16162348SN/A ListIt inst_list_it = instsToExecute.begin(); 16172348SN/A 16182348SN/A while (inst_list_it != instsToExecute.end()) 16192348SN/A { 16202348SN/A cprintf("Instruction:%i\n", 16212348SN/A num); 16222348SN/A if (!(*inst_list_it)->isSquashed()) { 16232348SN/A if (!(*inst_list_it)->isIssued()) { 16242348SN/A ++valid_num; 16252348SN/A cprintf("Count:%i\n", valid_num); 16262348SN/A } else if ((*inst_list_it)->isMemRef() && 16279046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 16282348SN/A // Loads that have not been marked as executed 16292348SN/A // still count towards the total instructions. 16302348SN/A ++valid_num; 16312348SN/A cprintf("Count:%i\n", valid_num); 16322348SN/A } 16332348SN/A } 16342348SN/A 16357720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 16362348SN/A "Issued:%i\nSquashed:%i\n", 16377720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 16382348SN/A (*inst_list_it)->seqNum, 16392348SN/A (*inst_list_it)->threadNumber, 16402348SN/A (*inst_list_it)->isIssued(), 16412348SN/A (*inst_list_it)->isSquashed()); 16422348SN/A 16432348SN/A if ((*inst_list_it)->isMemRef()) { 16449046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 16452348SN/A } 16462348SN/A 16472348SN/A cprintf("\n"); 16482348SN/A 16492348SN/A inst_list_it++; 16502348SN/A ++num; 16512348SN/A } 16522292SN/A} 16539944Smatt.horsnell@ARM.com 16549944Smatt.horsnell@ARM.com#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1655