inst_queue_impl.hh revision 10032
11689SN/A/* 210032SGiacomo.Gabrielli@arm.com * Copyright (c) 2011-2013 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 422831Sksewell@umich.edu * Korey Sewell 431689SN/A */ 441689SN/A 459944Smatt.horsnell@ARM.com#ifndef __CPU_O3_INST_QUEUE_IMPL_HH__ 469944Smatt.horsnell@ARM.com#define __CPU_O3_INST_QUEUE_IMPL_HH__ 479944Smatt.horsnell@ARM.com 482064SN/A#include <limits> 491060SN/A#include <vector> 501060SN/A 512292SN/A#include "cpu/o3/fu_pool.hh" 521717SN/A#include "cpu/o3/inst_queue.hh" 538232Snate@binkert.org#include "debug/IQ.hh" 544762Snate@binkert.org#include "enums/OpClass.hh" 556221Snate@binkert.org#include "params/DerivO3CPU.hh" 564762Snate@binkert.org#include "sim/core.hh" 571060SN/A 588737Skoansin.tan@gmail.com// clang complains about std::set being overloaded with Packet::set if 598737Skoansin.tan@gmail.com// we open up the entire namespace std 608737Skoansin.tan@gmail.comusing std::list; 615529Snate@binkert.org 621061SN/Atemplate <class Impl> 632292SN/AInstructionQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst, 645606Snate@binkert.org int fu_idx, InstructionQueue<Impl> *iq_ptr) 658581Ssteve.reinhardt@amd.com : Event(Stat_Event_Pri, AutoDelete), 668581Ssteve.reinhardt@amd.com inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr), freeFU(false) 671060SN/A{ 682292SN/A} 692292SN/A 702292SN/Atemplate <class Impl> 712292SN/Avoid 722292SN/AInstructionQueue<Impl>::FUCompletion::process() 732292SN/A{ 742326SN/A iqPtr->processFUCompletion(inst, freeFU ? fuIdx : -1); 752292SN/A inst = NULL; 762292SN/A} 772292SN/A 782292SN/A 792292SN/Atemplate <class Impl> 802292SN/Aconst char * 815336Shines@cs.fsu.eduInstructionQueue<Impl>::FUCompletion::description() const 822292SN/A{ 834873Sstever@eecs.umich.edu return "Functional unit completion"; 842292SN/A} 852292SN/A 862292SN/Atemplate <class Impl> 874329Sktlim@umich.eduInstructionQueue<Impl>::InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, 885529Snate@binkert.org DerivO3CPUParams *params) 894329Sktlim@umich.edu : cpu(cpu_ptr), 904329Sktlim@umich.edu iewStage(iew_ptr), 914329Sktlim@umich.edu fuPool(params->fuPool), 922292SN/A numEntries(params->numIQEntries), 932292SN/A totalWidth(params->issueWidth), 942292SN/A commitToIEWDelay(params->commitToIEWDelay) 952292SN/A{ 962292SN/A assert(fuPool); 972292SN/A 985529Snate@binkert.org numThreads = params->numThreads; 991060SN/A 1009920Syasuko.eckert@amd.com // Set the number of total physical registers 1019920Syasuko.eckert@amd.com numPhysRegs = params->numPhysIntRegs + params->numPhysFloatRegs + 1029920Syasuko.eckert@amd.com params->numPhysCCRegs; 1031060SN/A 1041060SN/A //Create an entry for each physical register within the 1051060SN/A //dependency graph. 1062326SN/A dependGraph.resize(numPhysRegs); 1071060SN/A 1081060SN/A // Resize the register scoreboard. 1091060SN/A regScoreboard.resize(numPhysRegs); 1101060SN/A 1112292SN/A //Initialize Mem Dependence Units 1126221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1136221Snate@binkert.org memDepUnit[tid].init(params, tid); 1146221Snate@binkert.org memDepUnit[tid].setIQ(this); 1151060SN/A } 1161060SN/A 1172307SN/A resetState(); 1182292SN/A 1192980Sgblack@eecs.umich.edu std::string policy = params->smtIQPolicy; 1202292SN/A 1212292SN/A //Convert string to lowercase 1222292SN/A std::transform(policy.begin(), policy.end(), policy.begin(), 1232292SN/A (int(*)(int)) tolower); 1242292SN/A 1252292SN/A //Figure out resource sharing policy 1262292SN/A if (policy == "dynamic") { 1272292SN/A iqPolicy = Dynamic; 1282292SN/A 1292292SN/A //Set Max Entries to Total ROB Capacity 1306221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1316221Snate@binkert.org maxEntries[tid] = numEntries; 1322292SN/A } 1332292SN/A 1342292SN/A } else if (policy == "partitioned") { 1352292SN/A iqPolicy = Partitioned; 1362292SN/A 1372292SN/A //@todo:make work if part_amt doesnt divide evenly. 1382292SN/A int part_amt = numEntries / numThreads; 1392292SN/A 1402292SN/A //Divide ROB up evenly 1416221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1426221Snate@binkert.org maxEntries[tid] = part_amt; 1432292SN/A } 1442292SN/A 1452831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Partitioned:" 1462292SN/A "%i entries per thread.\n",part_amt); 1472292SN/A } else if (policy == "threshold") { 1482292SN/A iqPolicy = Threshold; 1492292SN/A 1502292SN/A double threshold = (double)params->smtIQThreshold / 100; 1512292SN/A 1522292SN/A int thresholdIQ = (int)((double)threshold * numEntries); 1532292SN/A 1542292SN/A //Divide up by threshold amount 1556221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 1566221Snate@binkert.org maxEntries[tid] = thresholdIQ; 1572292SN/A } 1582292SN/A 1592831Sksewell@umich.edu DPRINTF(IQ, "IQ sharing policy set to Threshold:" 1602292SN/A "%i entries per thread.\n",thresholdIQ); 1612292SN/A } else { 1622292SN/A assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic," 1632292SN/A "Partitioned, Threshold}"); 1642292SN/A } 1652292SN/A} 1662292SN/A 1672292SN/Atemplate <class Impl> 1682292SN/AInstructionQueue<Impl>::~InstructionQueue() 1692292SN/A{ 1702326SN/A dependGraph.reset(); 1712348SN/A#ifdef DEBUG 1722326SN/A cprintf("Nodes traversed: %i, removed: %i\n", 1732326SN/A dependGraph.nodesTraversed, dependGraph.nodesRemoved); 1742348SN/A#endif 1752292SN/A} 1762292SN/A 1772292SN/Atemplate <class Impl> 1782292SN/Astd::string 1792292SN/AInstructionQueue<Impl>::name() const 1802292SN/A{ 1812292SN/A return cpu->name() + ".iq"; 1821060SN/A} 1831060SN/A 1841061SN/Atemplate <class Impl> 1851060SN/Avoid 1861062SN/AInstructionQueue<Impl>::regStats() 1871062SN/A{ 1882301SN/A using namespace Stats; 1891062SN/A iqInstsAdded 1901062SN/A .name(name() + ".iqInstsAdded") 1911062SN/A .desc("Number of instructions added to the IQ (excludes non-spec)") 1921062SN/A .prereq(iqInstsAdded); 1931062SN/A 1941062SN/A iqNonSpecInstsAdded 1951062SN/A .name(name() + ".iqNonSpecInstsAdded") 1961062SN/A .desc("Number of non-speculative instructions added to the IQ") 1971062SN/A .prereq(iqNonSpecInstsAdded); 1981062SN/A 1992301SN/A iqInstsIssued 2002301SN/A .name(name() + ".iqInstsIssued") 2012301SN/A .desc("Number of instructions issued") 2022301SN/A .prereq(iqInstsIssued); 2031062SN/A 2041062SN/A iqIntInstsIssued 2051062SN/A .name(name() + ".iqIntInstsIssued") 2061062SN/A .desc("Number of integer instructions issued") 2071062SN/A .prereq(iqIntInstsIssued); 2081062SN/A 2091062SN/A iqFloatInstsIssued 2101062SN/A .name(name() + ".iqFloatInstsIssued") 2111062SN/A .desc("Number of float instructions issued") 2121062SN/A .prereq(iqFloatInstsIssued); 2131062SN/A 2141062SN/A iqBranchInstsIssued 2151062SN/A .name(name() + ".iqBranchInstsIssued") 2161062SN/A .desc("Number of branch instructions issued") 2171062SN/A .prereq(iqBranchInstsIssued); 2181062SN/A 2191062SN/A iqMemInstsIssued 2201062SN/A .name(name() + ".iqMemInstsIssued") 2211062SN/A .desc("Number of memory instructions issued") 2221062SN/A .prereq(iqMemInstsIssued); 2231062SN/A 2241062SN/A iqMiscInstsIssued 2251062SN/A .name(name() + ".iqMiscInstsIssued") 2261062SN/A .desc("Number of miscellaneous instructions issued") 2271062SN/A .prereq(iqMiscInstsIssued); 2281062SN/A 2291062SN/A iqSquashedInstsIssued 2301062SN/A .name(name() + ".iqSquashedInstsIssued") 2311062SN/A .desc("Number of squashed instructions issued") 2321062SN/A .prereq(iqSquashedInstsIssued); 2331062SN/A 2341062SN/A iqSquashedInstsExamined 2351062SN/A .name(name() + ".iqSquashedInstsExamined") 2361062SN/A .desc("Number of squashed instructions iterated over during squash;" 2371062SN/A " mainly for profiling") 2381062SN/A .prereq(iqSquashedInstsExamined); 2391062SN/A 2401062SN/A iqSquashedOperandsExamined 2411062SN/A .name(name() + ".iqSquashedOperandsExamined") 2421062SN/A .desc("Number of squashed operands that are examined and possibly " 2431062SN/A "removed from graph") 2441062SN/A .prereq(iqSquashedOperandsExamined); 2451062SN/A 2461062SN/A iqSquashedNonSpecRemoved 2471062SN/A .name(name() + ".iqSquashedNonSpecRemoved") 2481062SN/A .desc("Number of squashed non-spec instructions that were removed") 2491062SN/A .prereq(iqSquashedNonSpecRemoved); 2502361SN/A/* 2512326SN/A queueResDist 2522301SN/A .init(Num_OpClasses, 0, 99, 2) 2532301SN/A .name(name() + ".IQ:residence:") 2542301SN/A .desc("cycles from dispatch to issue") 2552301SN/A .flags(total | pdf | cdf ) 2562301SN/A ; 2572301SN/A for (int i = 0; i < Num_OpClasses; ++i) { 2582326SN/A queueResDist.subname(i, opClassStrings[i]); 2592301SN/A } 2602361SN/A*/ 2612326SN/A numIssuedDist 2622307SN/A .init(0,totalWidth,1) 2638240Snate@binkert.org .name(name() + ".issued_per_cycle") 2642301SN/A .desc("Number of insts issued each cycle") 2652307SN/A .flags(pdf) 2662301SN/A ; 2672301SN/A/* 2682301SN/A dist_unissued 2692301SN/A .init(Num_OpClasses+2) 2708240Snate@binkert.org .name(name() + ".unissued_cause") 2712301SN/A .desc("Reason ready instruction not issued") 2722301SN/A .flags(pdf | dist) 2732301SN/A ; 2742301SN/A for (int i=0; i < (Num_OpClasses + 2); ++i) { 2752301SN/A dist_unissued.subname(i, unissued_names[i]); 2762301SN/A } 2772301SN/A*/ 2782326SN/A statIssuedInstType 2794762Snate@binkert.org .init(numThreads,Enums::Num_OpClass) 2808240Snate@binkert.org .name(name() + ".FU_type") 2812301SN/A .desc("Type of FU issued") 2822301SN/A .flags(total | pdf | dist) 2832301SN/A ; 2844762Snate@binkert.org statIssuedInstType.ysubnames(Enums::OpClassStrings); 2852301SN/A 2862301SN/A // 2872301SN/A // How long did instructions for a particular FU type wait prior to issue 2882301SN/A // 2892361SN/A/* 2902326SN/A issueDelayDist 2912301SN/A .init(Num_OpClasses,0,99,2) 2928240Snate@binkert.org .name(name() + ".") 2932301SN/A .desc("cycles from operands ready to issue") 2942301SN/A .flags(pdf | cdf) 2952301SN/A ; 2962301SN/A 2972301SN/A for (int i=0; i<Num_OpClasses; ++i) { 2982980Sgblack@eecs.umich.edu std::stringstream subname; 2992301SN/A subname << opClassStrings[i] << "_delay"; 3002326SN/A issueDelayDist.subname(i, subname.str()); 3012301SN/A } 3022361SN/A*/ 3032326SN/A issueRate 3048240Snate@binkert.org .name(name() + ".rate") 3052301SN/A .desc("Inst issue rate") 3062301SN/A .flags(total) 3072301SN/A ; 3082326SN/A issueRate = iqInstsIssued / cpu->numCycles; 3092727Sktlim@umich.edu 3102326SN/A statFuBusy 3112301SN/A .init(Num_OpClasses) 3128240Snate@binkert.org .name(name() + ".fu_full") 3132301SN/A .desc("attempts to use FU when none available") 3142301SN/A .flags(pdf | dist) 3152301SN/A ; 3162301SN/A for (int i=0; i < Num_OpClasses; ++i) { 3174762Snate@binkert.org statFuBusy.subname(i, Enums::OpClassStrings[i]); 3182301SN/A } 3192301SN/A 3202326SN/A fuBusy 3212301SN/A .init(numThreads) 3228240Snate@binkert.org .name(name() + ".fu_busy_cnt") 3232301SN/A .desc("FU busy when requested") 3242301SN/A .flags(total) 3252301SN/A ; 3262301SN/A 3272326SN/A fuBusyRate 3288240Snate@binkert.org .name(name() + ".fu_busy_rate") 3292301SN/A .desc("FU busy rate (busy events/executed inst)") 3302301SN/A .flags(total) 3312301SN/A ; 3322326SN/A fuBusyRate = fuBusy / iqInstsIssued; 3332301SN/A 3346221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 3352292SN/A // Tell mem dependence unit to reg stats as well. 3366221Snate@binkert.org memDepUnit[tid].regStats(); 3372292SN/A } 3387897Shestness@cs.utexas.edu 3397897Shestness@cs.utexas.edu intInstQueueReads 3407897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_reads") 3417897Shestness@cs.utexas.edu .desc("Number of integer instruction queue reads") 3427897Shestness@cs.utexas.edu .flags(total); 3437897Shestness@cs.utexas.edu 3447897Shestness@cs.utexas.edu intInstQueueWrites 3457897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_writes") 3467897Shestness@cs.utexas.edu .desc("Number of integer instruction queue writes") 3477897Shestness@cs.utexas.edu .flags(total); 3487897Shestness@cs.utexas.edu 3497897Shestness@cs.utexas.edu intInstQueueWakeupAccesses 3507897Shestness@cs.utexas.edu .name(name() + ".int_inst_queue_wakeup_accesses") 3517897Shestness@cs.utexas.edu .desc("Number of integer instruction queue wakeup accesses") 3527897Shestness@cs.utexas.edu .flags(total); 3537897Shestness@cs.utexas.edu 3547897Shestness@cs.utexas.edu fpInstQueueReads 3557897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_reads") 3567897Shestness@cs.utexas.edu .desc("Number of floating instruction queue reads") 3577897Shestness@cs.utexas.edu .flags(total); 3587897Shestness@cs.utexas.edu 3597897Shestness@cs.utexas.edu fpInstQueueWrites 3607897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_writes") 3617897Shestness@cs.utexas.edu .desc("Number of floating instruction queue writes") 3627897Shestness@cs.utexas.edu .flags(total); 3637897Shestness@cs.utexas.edu 3647897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses 3657897Shestness@cs.utexas.edu .name(name() + ".fp_inst_queue_wakeup_accesses") 3667897Shestness@cs.utexas.edu .desc("Number of floating instruction queue wakeup accesses") 3677897Shestness@cs.utexas.edu .flags(total); 3687897Shestness@cs.utexas.edu 3697897Shestness@cs.utexas.edu intAluAccesses 3707897Shestness@cs.utexas.edu .name(name() + ".int_alu_accesses") 3717897Shestness@cs.utexas.edu .desc("Number of integer alu accesses") 3727897Shestness@cs.utexas.edu .flags(total); 3737897Shestness@cs.utexas.edu 3747897Shestness@cs.utexas.edu fpAluAccesses 3757897Shestness@cs.utexas.edu .name(name() + ".fp_alu_accesses") 3767897Shestness@cs.utexas.edu .desc("Number of floating point alu accesses") 3777897Shestness@cs.utexas.edu .flags(total); 3787897Shestness@cs.utexas.edu 3791062SN/A} 3801062SN/A 3811062SN/Atemplate <class Impl> 3821062SN/Avoid 3832307SN/AInstructionQueue<Impl>::resetState() 3841060SN/A{ 3852307SN/A //Initialize thread IQ counts 3866221Snate@binkert.org for (ThreadID tid = 0; tid <numThreads; tid++) { 3876221Snate@binkert.org count[tid] = 0; 3886221Snate@binkert.org instList[tid].clear(); 3892307SN/A } 3901060SN/A 3912307SN/A // Initialize the number of free IQ entries. 3922307SN/A freeEntries = numEntries; 3932307SN/A 3942307SN/A // Note that in actuality, the registers corresponding to the logical 3952307SN/A // registers start off as ready. However this doesn't matter for the 3962307SN/A // IQ as the instruction should have been correctly told if those 3972307SN/A // registers are ready in rename. Thus it can all be initialized as 3982307SN/A // unready. 3992307SN/A for (int i = 0; i < numPhysRegs; ++i) { 4002307SN/A regScoreboard[i] = false; 4012307SN/A } 4022307SN/A 4036221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 4046221Snate@binkert.org squashedSeqNum[tid] = 0; 4052307SN/A } 4062307SN/A 4072307SN/A for (int i = 0; i < Num_OpClasses; ++i) { 4082307SN/A while (!readyInsts[i].empty()) 4092307SN/A readyInsts[i].pop(); 4102307SN/A queueOnList[i] = false; 4112307SN/A readyIt[i] = listOrder.end(); 4122307SN/A } 4132307SN/A nonSpecInsts.clear(); 4142307SN/A listOrder.clear(); 4157944SGiacomo.Gabrielli@arm.com deferredMemInsts.clear(); 4161060SN/A} 4171060SN/A 4181061SN/Atemplate <class Impl> 4191060SN/Avoid 4206221Snate@binkert.orgInstructionQueue<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 4211060SN/A{ 4222292SN/A activeThreads = at_ptr; 4232064SN/A} 4242064SN/A 4252064SN/Atemplate <class Impl> 4262064SN/Avoid 4272292SN/AInstructionQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr) 4282064SN/A{ 4294318Sktlim@umich.edu issueToExecuteQueue = i2e_ptr; 4301060SN/A} 4311060SN/A 4321061SN/Atemplate <class Impl> 4331060SN/Avoid 4341060SN/AInstructionQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 4351060SN/A{ 4361060SN/A timeBuffer = tb_ptr; 4371060SN/A 4381060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 4391060SN/A} 4401060SN/A 4411684SN/Atemplate <class Impl> 4422307SN/Avoid 4439444SAndreas.Sandberg@ARM.comInstructionQueue<Impl>::drainSanityCheck() const 4442307SN/A{ 4459444SAndreas.Sandberg@ARM.com assert(dependGraph.empty()); 4469444SAndreas.Sandberg@ARM.com assert(instsToExecute.empty()); 4479444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; ++tid) 4489444SAndreas.Sandberg@ARM.com memDepUnit[tid].drainSanityCheck(); 4492307SN/A} 4502307SN/A 4512307SN/Atemplate <class Impl> 4522307SN/Avoid 4532307SN/AInstructionQueue<Impl>::takeOverFrom() 4542307SN/A{ 4559444SAndreas.Sandberg@ARM.com resetState(); 4562307SN/A} 4572307SN/A 4582307SN/Atemplate <class Impl> 4592292SN/Aint 4606221Snate@binkert.orgInstructionQueue<Impl>::entryAmount(ThreadID num_threads) 4612292SN/A{ 4622292SN/A if (iqPolicy == Partitioned) { 4632292SN/A return numEntries / num_threads; 4642292SN/A } else { 4652292SN/A return 0; 4662292SN/A } 4672292SN/A} 4682292SN/A 4692292SN/A 4702292SN/Atemplate <class Impl> 4712292SN/Avoid 4722292SN/AInstructionQueue<Impl>::resetEntries() 4732292SN/A{ 4742292SN/A if (iqPolicy != Dynamic || numThreads > 1) { 4753867Sbinkertn@umich.edu int active_threads = activeThreads->size(); 4762292SN/A 4776221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 4786221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 4792292SN/A 4803867Sbinkertn@umich.edu while (threads != end) { 4816221Snate@binkert.org ThreadID tid = *threads++; 4823867Sbinkertn@umich.edu 4832292SN/A if (iqPolicy == Partitioned) { 4843867Sbinkertn@umich.edu maxEntries[tid] = numEntries / active_threads; 4852292SN/A } else if(iqPolicy == Threshold && active_threads == 1) { 4863867Sbinkertn@umich.edu maxEntries[tid] = numEntries; 4872292SN/A } 4882292SN/A } 4892292SN/A } 4902292SN/A} 4912292SN/A 4922292SN/Atemplate <class Impl> 4931684SN/Aunsigned 4941684SN/AInstructionQueue<Impl>::numFreeEntries() 4951684SN/A{ 4961684SN/A return freeEntries; 4971684SN/A} 4981684SN/A 4992292SN/Atemplate <class Impl> 5002292SN/Aunsigned 5016221Snate@binkert.orgInstructionQueue<Impl>::numFreeEntries(ThreadID tid) 5022292SN/A{ 5032292SN/A return maxEntries[tid] - count[tid]; 5042292SN/A} 5052292SN/A 5061060SN/A// Might want to do something more complex if it knows how many instructions 5071060SN/A// will be issued this cycle. 5081061SN/Atemplate <class Impl> 5091060SN/Abool 5101060SN/AInstructionQueue<Impl>::isFull() 5111060SN/A{ 5121060SN/A if (freeEntries == 0) { 5131060SN/A return(true); 5141060SN/A } else { 5151060SN/A return(false); 5161060SN/A } 5171060SN/A} 5181060SN/A 5191061SN/Atemplate <class Impl> 5202292SN/Abool 5216221Snate@binkert.orgInstructionQueue<Impl>::isFull(ThreadID tid) 5222292SN/A{ 5232292SN/A if (numFreeEntries(tid) == 0) { 5242292SN/A return(true); 5252292SN/A } else { 5262292SN/A return(false); 5272292SN/A } 5282292SN/A} 5292292SN/A 5302292SN/Atemplate <class Impl> 5312292SN/Abool 5322292SN/AInstructionQueue<Impl>::hasReadyInsts() 5332292SN/A{ 5342292SN/A if (!listOrder.empty()) { 5352292SN/A return true; 5362292SN/A } 5372292SN/A 5382292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 5392292SN/A if (!readyInsts[i].empty()) { 5402292SN/A return true; 5412292SN/A } 5422292SN/A } 5432292SN/A 5442292SN/A return false; 5452292SN/A} 5462292SN/A 5472292SN/Atemplate <class Impl> 5481060SN/Avoid 5491061SN/AInstructionQueue<Impl>::insert(DynInstPtr &new_inst) 5501060SN/A{ 5517897Shestness@cs.utexas.edu new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5521060SN/A // Make sure the instruction is valid 5531060SN/A assert(new_inst); 5541060SN/A 5557720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding instruction [sn:%lli] PC %s to the IQ.\n", 5567720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 5571060SN/A 5581060SN/A assert(freeEntries != 0); 5591060SN/A 5602292SN/A instList[new_inst->threadNumber].push_back(new_inst); 5611060SN/A 5622064SN/A --freeEntries; 5631060SN/A 5642292SN/A new_inst->setInIQ(); 5651060SN/A 5661060SN/A // Look through its source registers (physical regs), and mark any 5671060SN/A // dependencies. 5681060SN/A addToDependents(new_inst); 5691060SN/A 5701060SN/A // Have this instruction set itself as the producer of its destination 5711060SN/A // register(s). 5722326SN/A addToProducers(new_inst); 5731060SN/A 5741061SN/A if (new_inst->isMemRef()) { 5752292SN/A memDepUnit[new_inst->threadNumber].insert(new_inst); 5761062SN/A } else { 5771062SN/A addIfReady(new_inst); 5781061SN/A } 5791061SN/A 5801062SN/A ++iqInstsAdded; 5811060SN/A 5822292SN/A count[new_inst->threadNumber]++; 5832292SN/A 5841060SN/A assert(freeEntries == (numEntries - countInsts())); 5851060SN/A} 5861060SN/A 5871061SN/Atemplate <class Impl> 5881061SN/Avoid 5892292SN/AInstructionQueue<Impl>::insertNonSpec(DynInstPtr &new_inst) 5901061SN/A{ 5911061SN/A // @todo: Clean up this code; can do it by setting inst as unable 5921061SN/A // to issue, then calling normal insert on the inst. 5937897Shestness@cs.utexas.edu new_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 5941061SN/A 5952292SN/A assert(new_inst); 5961061SN/A 5972292SN/A nonSpecInsts[new_inst->seqNum] = new_inst; 5981061SN/A 5997720Sgblack@eecs.umich.edu DPRINTF(IQ, "Adding non-speculative instruction [sn:%lli] PC %s " 6002326SN/A "to the IQ.\n", 6017720Sgblack@eecs.umich.edu new_inst->seqNum, new_inst->pcState()); 6022064SN/A 6031061SN/A assert(freeEntries != 0); 6041061SN/A 6052292SN/A instList[new_inst->threadNumber].push_back(new_inst); 6061061SN/A 6072064SN/A --freeEntries; 6081061SN/A 6092292SN/A new_inst->setInIQ(); 6101061SN/A 6111061SN/A // Have this instruction set itself as the producer of its destination 6121061SN/A // register(s). 6132326SN/A addToProducers(new_inst); 6141061SN/A 6151061SN/A // If it's a memory instruction, add it to the memory dependency 6161061SN/A // unit. 6172292SN/A if (new_inst->isMemRef()) { 6182292SN/A memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst); 6191061SN/A } 6201062SN/A 6211062SN/A ++iqNonSpecInstsAdded; 6222292SN/A 6232292SN/A count[new_inst->threadNumber]++; 6242292SN/A 6252292SN/A assert(freeEntries == (numEntries - countInsts())); 6261061SN/A} 6271061SN/A 6281061SN/Atemplate <class Impl> 6291060SN/Avoid 6302292SN/AInstructionQueue<Impl>::insertBarrier(DynInstPtr &barr_inst) 6311060SN/A{ 6322292SN/A memDepUnit[barr_inst->threadNumber].insertBarrier(barr_inst); 6331060SN/A 6342292SN/A insertNonSpec(barr_inst); 6352292SN/A} 6361060SN/A 6372064SN/Atemplate <class Impl> 6382333SN/Atypename Impl::DynInstPtr 6392333SN/AInstructionQueue<Impl>::getInstToExecute() 6402333SN/A{ 6412333SN/A assert(!instsToExecute.empty()); 6422333SN/A DynInstPtr inst = instsToExecute.front(); 6432333SN/A instsToExecute.pop_front(); 6447897Shestness@cs.utexas.edu if (inst->isFloating()){ 6457897Shestness@cs.utexas.edu fpInstQueueReads++; 6467897Shestness@cs.utexas.edu } else { 6477897Shestness@cs.utexas.edu intInstQueueReads++; 6487897Shestness@cs.utexas.edu } 6492333SN/A return inst; 6502333SN/A} 6511060SN/A 6522333SN/Atemplate <class Impl> 6532064SN/Avoid 6542292SN/AInstructionQueue<Impl>::addToOrderList(OpClass op_class) 6552292SN/A{ 6562292SN/A assert(!readyInsts[op_class].empty()); 6572292SN/A 6582292SN/A ListOrderEntry queue_entry; 6592292SN/A 6602292SN/A queue_entry.queueType = op_class; 6612292SN/A 6622292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6632292SN/A 6642292SN/A ListOrderIt list_it = listOrder.begin(); 6652292SN/A ListOrderIt list_end_it = listOrder.end(); 6662292SN/A 6672292SN/A while (list_it != list_end_it) { 6682292SN/A if ((*list_it).oldestInst > queue_entry.oldestInst) { 6692292SN/A break; 6702292SN/A } 6712292SN/A 6722292SN/A list_it++; 6731060SN/A } 6741060SN/A 6752292SN/A readyIt[op_class] = listOrder.insert(list_it, queue_entry); 6762292SN/A queueOnList[op_class] = true; 6772292SN/A} 6781060SN/A 6792292SN/Atemplate <class Impl> 6802292SN/Avoid 6812292SN/AInstructionQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it) 6822292SN/A{ 6832292SN/A // Get iterator of next item on the list 6842292SN/A // Delete the original iterator 6852292SN/A // Determine if the next item is either the end of the list or younger 6862292SN/A // than the new instruction. If so, then add in a new iterator right here. 6872292SN/A // If not, then move along. 6882292SN/A ListOrderEntry queue_entry; 6892292SN/A OpClass op_class = (*list_order_it).queueType; 6902292SN/A ListOrderIt next_it = list_order_it; 6912292SN/A 6922292SN/A ++next_it; 6932292SN/A 6942292SN/A queue_entry.queueType = op_class; 6952292SN/A queue_entry.oldestInst = readyInsts[op_class].top()->seqNum; 6962292SN/A 6972292SN/A while (next_it != listOrder.end() && 6982292SN/A (*next_it).oldestInst < queue_entry.oldestInst) { 6992292SN/A ++next_it; 7001060SN/A } 7011060SN/A 7022292SN/A readyIt[op_class] = listOrder.insert(next_it, queue_entry); 7031060SN/A} 7041060SN/A 7052292SN/Atemplate <class Impl> 7062292SN/Avoid 7072292SN/AInstructionQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx) 7082292SN/A{ 7092367SN/A DPRINTF(IQ, "Processing FU completion [sn:%lli]\n", inst->seqNum); 7109444SAndreas.Sandberg@ARM.com assert(!cpu->switchedOut()); 7112292SN/A // The CPU could have been sleeping until this op completed (*extremely* 7122292SN/A // long latency op). Wake it if it was. This may be overkill. 7132292SN/A iewStage->wakeCPU(); 7142292SN/A 7152326SN/A if (fu_idx > -1) 7162326SN/A fuPool->freeUnitNextCycle(fu_idx); 7172292SN/A 7182326SN/A // @todo: Ensure that these FU Completions happen at the beginning 7192326SN/A // of a cycle, otherwise they could add too many instructions to 7202326SN/A // the queue. 7215327Smengke97@hotmail.com issueToExecuteQueue->access(-1)->size++; 7222333SN/A instsToExecute.push_back(inst); 7232292SN/A} 7242292SN/A 7251061SN/A// @todo: Figure out a better way to remove the squashed items from the 7261061SN/A// lists. Checking the top item of each list to see if it's squashed 7271061SN/A// wastes time and forces jumps. 7281061SN/Atemplate <class Impl> 7291060SN/Avoid 7301060SN/AInstructionQueue<Impl>::scheduleReadyInsts() 7311060SN/A{ 7322292SN/A DPRINTF(IQ, "Attempting to schedule ready instructions from " 7332292SN/A "the IQ.\n"); 7341060SN/A 7351060SN/A IssueStruct *i2e_info = issueToExecuteQueue->access(0); 7361060SN/A 7377944SGiacomo.Gabrielli@arm.com DynInstPtr deferred_mem_inst; 7387944SGiacomo.Gabrielli@arm.com int total_deferred_mem_issued = 0; 7397944SGiacomo.Gabrielli@arm.com while (total_deferred_mem_issued < totalWidth && 7407962Ssaidi@eecs.umich.edu (deferred_mem_inst = getDeferredMemInstToExecute()) != 0) { 7417944SGiacomo.Gabrielli@arm.com issueToExecuteQueue->access(0)->size++; 7427944SGiacomo.Gabrielli@arm.com instsToExecute.push_back(deferred_mem_inst); 7437944SGiacomo.Gabrielli@arm.com total_deferred_mem_issued++; 7447944SGiacomo.Gabrielli@arm.com } 7457944SGiacomo.Gabrielli@arm.com 7462292SN/A // Have iterator to head of the list 7472292SN/A // While I haven't exceeded bandwidth or reached the end of the list, 7482292SN/A // Try to get a FU that can do what this op needs. 7492292SN/A // If successful, change the oldestInst to the new top of the list, put 7502292SN/A // the queue in the proper place in the list. 7512292SN/A // Increment the iterator. 7522292SN/A // This will avoid trying to schedule a certain op class if there are no 7532292SN/A // FUs that handle it. 7542292SN/A ListOrderIt order_it = listOrder.begin(); 7552292SN/A ListOrderIt order_end_it = listOrder.end(); 7562292SN/A int total_issued = 0; 7571060SN/A 7587944SGiacomo.Gabrielli@arm.com while (total_issued < (totalWidth - total_deferred_mem_issued) && 7592820Sktlim@umich.edu iewStage->canIssue() && 7602326SN/A order_it != order_end_it) { 7612292SN/A OpClass op_class = (*order_it).queueType; 7621060SN/A 7632292SN/A assert(!readyInsts[op_class].empty()); 7641060SN/A 7652292SN/A DynInstPtr issuing_inst = readyInsts[op_class].top(); 7661060SN/A 7677897Shestness@cs.utexas.edu issuing_inst->isFloating() ? fpInstQueueReads++ : intInstQueueReads++; 7687897Shestness@cs.utexas.edu 7692292SN/A assert(issuing_inst->seqNum == (*order_it).oldestInst); 7701060SN/A 7712292SN/A if (issuing_inst->isSquashed()) { 7722292SN/A readyInsts[op_class].pop(); 7731060SN/A 7742292SN/A if (!readyInsts[op_class].empty()) { 7752292SN/A moveToYoungerInst(order_it); 7762292SN/A } else { 7772292SN/A readyIt[op_class] = listOrder.end(); 7782292SN/A queueOnList[op_class] = false; 7791060SN/A } 7801060SN/A 7812292SN/A listOrder.erase(order_it++); 7821060SN/A 7832292SN/A ++iqSquashedInstsIssued; 7842292SN/A 7852292SN/A continue; 7861060SN/A } 7871060SN/A 7882326SN/A int idx = -2; 7899184Sandreas.hansson@arm.com Cycles op_latency = Cycles(1); 7906221Snate@binkert.org ThreadID tid = issuing_inst->threadNumber; 7911060SN/A 7922326SN/A if (op_class != No_OpClass) { 7932326SN/A idx = fuPool->getUnit(op_class); 7947897Shestness@cs.utexas.edu issuing_inst->isFloating() ? fpAluAccesses++ : intAluAccesses++; 7952326SN/A if (idx > -1) { 7962326SN/A op_latency = fuPool->getOpLatency(op_class); 7971060SN/A } 7981060SN/A } 7991060SN/A 8002348SN/A // If we have an instruction that doesn't require a FU, or a 8012348SN/A // valid FU, then schedule for execution. 8022326SN/A if (idx == -2 || idx != -1) { 8039184Sandreas.hansson@arm.com if (op_latency == Cycles(1)) { 8042292SN/A i2e_info->size++; 8052333SN/A instsToExecute.push_back(issuing_inst); 8061060SN/A 8072326SN/A // Add the FU onto the list of FU's to be freed next 8082326SN/A // cycle if we used one. 8092326SN/A if (idx >= 0) 8102326SN/A fuPool->freeUnitNextCycle(idx); 8112292SN/A } else { 8129184Sandreas.hansson@arm.com Cycles issue_latency = fuPool->getIssueLatency(op_class); 8132326SN/A // Generate completion event for the FU 8142326SN/A FUCompletion *execution = new FUCompletion(issuing_inst, 8152326SN/A idx, this); 8161060SN/A 8179180Sandreas.hansson@arm.com cpu->schedule(execution, 8189180Sandreas.hansson@arm.com cpu->clockEdge(Cycles(op_latency - 1))); 8191060SN/A 8202326SN/A // @todo: Enforce that issue_latency == 1 or op_latency 8219184Sandreas.hansson@arm.com if (issue_latency > Cycles(1)) { 8222348SN/A // If FU isn't pipelined, then it must be freed 8232348SN/A // upon the execution completing. 8242326SN/A execution->setFreeFU(); 8252292SN/A } else { 8262292SN/A // Add the FU onto the list of FU's to be freed next cycle. 8272326SN/A fuPool->freeUnitNextCycle(idx); 8282292SN/A } 8291060SN/A } 8301060SN/A 8317720Sgblack@eecs.umich.edu DPRINTF(IQ, "Thread %i: Issuing instruction PC %s " 8322292SN/A "[sn:%lli]\n", 8337720Sgblack@eecs.umich.edu tid, issuing_inst->pcState(), 8342292SN/A issuing_inst->seqNum); 8351060SN/A 8362292SN/A readyInsts[op_class].pop(); 8371061SN/A 8382292SN/A if (!readyInsts[op_class].empty()) { 8392292SN/A moveToYoungerInst(order_it); 8402292SN/A } else { 8412292SN/A readyIt[op_class] = listOrder.end(); 8422292SN/A queueOnList[op_class] = false; 8431060SN/A } 8441060SN/A 8452064SN/A issuing_inst->setIssued(); 8462292SN/A ++total_issued; 8472064SN/A 8488471SGiacomo.Gabrielli@arm.com#if TRACING_ON 8499046SAli.Saidi@ARM.com issuing_inst->issueTick = curTick() - issuing_inst->fetchTick; 8508471SGiacomo.Gabrielli@arm.com#endif 8518471SGiacomo.Gabrielli@arm.com 8522292SN/A if (!issuing_inst->isMemRef()) { 8532292SN/A // Memory instructions can not be freed from the IQ until they 8542292SN/A // complete. 8552292SN/A ++freeEntries; 8562301SN/A count[tid]--; 8572731Sktlim@umich.edu issuing_inst->clearInIQ(); 8582292SN/A } else { 8592301SN/A memDepUnit[tid].issue(issuing_inst); 8602292SN/A } 8612292SN/A 8622292SN/A listOrder.erase(order_it++); 8632326SN/A statIssuedInstType[tid][op_class]++; 8642820Sktlim@umich.edu iewStage->incrWb(issuing_inst->seqNum); 8652292SN/A } else { 8662326SN/A statFuBusy[op_class]++; 8672326SN/A fuBusy[tid]++; 8682292SN/A ++order_it; 8691060SN/A } 8701060SN/A } 8711062SN/A 8722326SN/A numIssuedDist.sample(total_issued); 8732326SN/A iqInstsIssued+= total_issued; 8742307SN/A 8752348SN/A // If we issued any instructions, tell the CPU we had activity. 8768071SAli.Saidi@ARM.com // @todo If the way deferred memory instructions are handeled due to 8778071SAli.Saidi@ARM.com // translation changes then the deferredMemInsts condition should be removed 8788071SAli.Saidi@ARM.com // from the code below. 8798071SAli.Saidi@ARM.com if (total_issued || total_deferred_mem_issued || deferredMemInsts.size()) { 8802292SN/A cpu->activityThisCycle(); 8812292SN/A } else { 8822292SN/A DPRINTF(IQ, "Not able to schedule any instructions.\n"); 8832292SN/A } 8841060SN/A} 8851060SN/A 8861061SN/Atemplate <class Impl> 8871060SN/Avoid 8881061SN/AInstructionQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst) 8891060SN/A{ 8902292SN/A DPRINTF(IQ, "Marking nonspeculative instruction [sn:%lli] as ready " 8912292SN/A "to execute.\n", inst); 8921062SN/A 8932292SN/A NonSpecMapIt inst_it = nonSpecInsts.find(inst); 8941060SN/A 8951061SN/A assert(inst_it != nonSpecInsts.end()); 8961060SN/A 8976221Snate@binkert.org ThreadID tid = (*inst_it).second->threadNumber; 8982292SN/A 8994033Sktlim@umich.edu (*inst_it).second->setAtCommit(); 9004033Sktlim@umich.edu 9011061SN/A (*inst_it).second->setCanIssue(); 9021060SN/A 9031062SN/A if (!(*inst_it).second->isMemRef()) { 9041062SN/A addIfReady((*inst_it).second); 9051062SN/A } else { 9062292SN/A memDepUnit[tid].nonSpecInstReady((*inst_it).second); 9071062SN/A } 9081060SN/A 9092292SN/A (*inst_it).second = NULL; 9102292SN/A 9111061SN/A nonSpecInsts.erase(inst_it); 9121060SN/A} 9131060SN/A 9141061SN/Atemplate <class Impl> 9151061SN/Avoid 9166221Snate@binkert.orgInstructionQueue<Impl>::commit(const InstSeqNum &inst, ThreadID tid) 9172292SN/A{ 9182292SN/A DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n", 9192292SN/A tid,inst); 9202292SN/A 9212292SN/A ListIt iq_it = instList[tid].begin(); 9222292SN/A 9232292SN/A while (iq_it != instList[tid].end() && 9242292SN/A (*iq_it)->seqNum <= inst) { 9252292SN/A ++iq_it; 9262292SN/A instList[tid].pop_front(); 9272292SN/A } 9282292SN/A 9292292SN/A assert(freeEntries == (numEntries - countInsts())); 9302292SN/A} 9312292SN/A 9322292SN/Atemplate <class Impl> 9332301SN/Aint 9341684SN/AInstructionQueue<Impl>::wakeDependents(DynInstPtr &completed_inst) 9351684SN/A{ 9362301SN/A int dependents = 0; 9372301SN/A 9387897Shestness@cs.utexas.edu // The instruction queue here takes care of both floating and int ops 9397897Shestness@cs.utexas.edu if (completed_inst->isFloating()) { 9407897Shestness@cs.utexas.edu fpInstQueueWakeupQccesses++; 9417897Shestness@cs.utexas.edu } else { 9427897Shestness@cs.utexas.edu intInstQueueWakeupAccesses++; 9437897Shestness@cs.utexas.edu } 9447897Shestness@cs.utexas.edu 9452292SN/A DPRINTF(IQ, "Waking dependents of completed instruction.\n"); 9462292SN/A 9472292SN/A assert(!completed_inst->isSquashed()); 9481684SN/A 9491684SN/A // Tell the memory dependence unit to wake any dependents on this 9502292SN/A // instruction if it is a memory instruction. Also complete the memory 9512326SN/A // instruction at this point since we know it executed without issues. 9522326SN/A // @todo: Might want to rename "completeMemInst" to something that 9532326SN/A // indicates that it won't need to be replayed, and call this 9542326SN/A // earlier. Might not be a big deal. 9551684SN/A if (completed_inst->isMemRef()) { 9562292SN/A memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst); 9572292SN/A completeMemInst(completed_inst); 9582292SN/A } else if (completed_inst->isMemBarrier() || 9592292SN/A completed_inst->isWriteBarrier()) { 9602292SN/A memDepUnit[completed_inst->threadNumber].completeBarrier(completed_inst); 9611684SN/A } 9621684SN/A 9631684SN/A for (int dest_reg_idx = 0; 9641684SN/A dest_reg_idx < completed_inst->numDestRegs(); 9651684SN/A dest_reg_idx++) 9661684SN/A { 9671684SN/A PhysRegIndex dest_reg = 9681684SN/A completed_inst->renamedDestRegIdx(dest_reg_idx); 9691684SN/A 9701684SN/A // Special case of uniq or control registers. They are not 9711684SN/A // handled by the IQ and thus have no dependency graph entry. 9721684SN/A // @todo Figure out a cleaner way to handle this. 9731684SN/A if (dest_reg >= numPhysRegs) { 9747599Sminkyu.jeong@arm.com DPRINTF(IQ, "dest_reg :%d, numPhysRegs: %d\n", dest_reg, 9757599Sminkyu.jeong@arm.com numPhysRegs); 9761684SN/A continue; 9771684SN/A } 9781684SN/A 9792292SN/A DPRINTF(IQ, "Waking any dependents on register %i.\n", 9801684SN/A (int) dest_reg); 9811684SN/A 9822326SN/A //Go through the dependency chain, marking the registers as 9832326SN/A //ready within the waiting instructions. 9842326SN/A DynInstPtr dep_inst = dependGraph.pop(dest_reg); 9851684SN/A 9862326SN/A while (dep_inst) { 9877599Sminkyu.jeong@arm.com DPRINTF(IQ, "Waking up a dependent instruction, [sn:%lli] " 9887720Sgblack@eecs.umich.edu "PC %s.\n", dep_inst->seqNum, dep_inst->pcState()); 9891684SN/A 9901684SN/A // Might want to give more information to the instruction 9912326SN/A // so that it knows which of its source registers is 9922326SN/A // ready. However that would mean that the dependency 9932326SN/A // graph entries would need to hold the src_reg_idx. 9942326SN/A dep_inst->markSrcRegReady(); 9951684SN/A 9962326SN/A addIfReady(dep_inst); 9971684SN/A 9982326SN/A dep_inst = dependGraph.pop(dest_reg); 9991684SN/A 10002301SN/A ++dependents; 10011684SN/A } 10021684SN/A 10032326SN/A // Reset the head node now that all of its dependents have 10042326SN/A // been woken up. 10052326SN/A assert(dependGraph.empty(dest_reg)); 10062326SN/A dependGraph.clearInst(dest_reg); 10071684SN/A 10081684SN/A // Mark the scoreboard as having that register ready. 10091684SN/A regScoreboard[dest_reg] = true; 10101684SN/A } 10112301SN/A return dependents; 10122064SN/A} 10132064SN/A 10142064SN/Atemplate <class Impl> 10152064SN/Avoid 10162292SN/AInstructionQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst) 10172064SN/A{ 10182292SN/A OpClass op_class = ready_inst->opClass(); 10192292SN/A 10202292SN/A readyInsts[op_class].push(ready_inst); 10212292SN/A 10222326SN/A // Will need to reorder the list if either a queue is not on the list, 10232326SN/A // or it has an older instruction than last time. 10242326SN/A if (!queueOnList[op_class]) { 10252326SN/A addToOrderList(op_class); 10262326SN/A } else if (readyInsts[op_class].top()->seqNum < 10272326SN/A (*readyIt[op_class]).oldestInst) { 10282326SN/A listOrder.erase(readyIt[op_class]); 10292326SN/A addToOrderList(op_class); 10302326SN/A } 10312326SN/A 10322292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 10337720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 10347720Sgblack@eecs.umich.edu ready_inst->pcState(), op_class, ready_inst->seqNum); 10352064SN/A} 10362064SN/A 10372064SN/Atemplate <class Impl> 10382064SN/Avoid 10392292SN/AInstructionQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst) 10402064SN/A{ 10414033Sktlim@umich.edu DPRINTF(IQ, "Rescheduling mem inst [sn:%lli]\n", resched_inst->seqNum); 10427944SGiacomo.Gabrielli@arm.com 10437944SGiacomo.Gabrielli@arm.com // Reset DTB translation state 10449046SAli.Saidi@ARM.com resched_inst->translationStarted(false); 10459046SAli.Saidi@ARM.com resched_inst->translationCompleted(false); 10467944SGiacomo.Gabrielli@arm.com 10474033Sktlim@umich.edu resched_inst->clearCanIssue(); 10482292SN/A memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); 10492064SN/A} 10502064SN/A 10512064SN/Atemplate <class Impl> 10522064SN/Avoid 10532292SN/AInstructionQueue<Impl>::replayMemInst(DynInstPtr &replay_inst) 10542064SN/A{ 10552292SN/A memDepUnit[replay_inst->threadNumber].replay(replay_inst); 10562292SN/A} 10572292SN/A 10582292SN/Atemplate <class Impl> 10592292SN/Avoid 10602292SN/AInstructionQueue<Impl>::completeMemInst(DynInstPtr &completed_inst) 10612292SN/A{ 10626221Snate@binkert.org ThreadID tid = completed_inst->threadNumber; 10632292SN/A 10647720Sgblack@eecs.umich.edu DPRINTF(IQ, "Completing mem instruction PC: %s [sn:%lli]\n", 10657720Sgblack@eecs.umich.edu completed_inst->pcState(), completed_inst->seqNum); 10662292SN/A 10672292SN/A ++freeEntries; 10682292SN/A 10699046SAli.Saidi@ARM.com completed_inst->memOpDone(true); 10702292SN/A 10712292SN/A memDepUnit[tid].completed(completed_inst); 10722292SN/A count[tid]--; 10731684SN/A} 10741684SN/A 10751684SN/Atemplate <class Impl> 10761684SN/Avoid 10777944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::deferMemInst(DynInstPtr &deferred_inst) 10787944SGiacomo.Gabrielli@arm.com{ 10797944SGiacomo.Gabrielli@arm.com deferredMemInsts.push_back(deferred_inst); 10807944SGiacomo.Gabrielli@arm.com} 10817944SGiacomo.Gabrielli@arm.com 10827944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 10837944SGiacomo.Gabrielli@arm.comtypename Impl::DynInstPtr 10847944SGiacomo.Gabrielli@arm.comInstructionQueue<Impl>::getDeferredMemInstToExecute() 10857944SGiacomo.Gabrielli@arm.com{ 10867944SGiacomo.Gabrielli@arm.com for (ListIt it = deferredMemInsts.begin(); it != deferredMemInsts.end(); 10877944SGiacomo.Gabrielli@arm.com ++it) { 10889046SAli.Saidi@ARM.com if ((*it)->translationCompleted() || (*it)->isSquashed()) { 10897944SGiacomo.Gabrielli@arm.com DynInstPtr ret = *it; 10907944SGiacomo.Gabrielli@arm.com deferredMemInsts.erase(it); 10917944SGiacomo.Gabrielli@arm.com return ret; 10927944SGiacomo.Gabrielli@arm.com } 10937944SGiacomo.Gabrielli@arm.com } 10947944SGiacomo.Gabrielli@arm.com return NULL; 10957944SGiacomo.Gabrielli@arm.com} 10967944SGiacomo.Gabrielli@arm.com 10977944SGiacomo.Gabrielli@arm.comtemplate <class Impl> 10987944SGiacomo.Gabrielli@arm.comvoid 10991061SN/AInstructionQueue<Impl>::violation(DynInstPtr &store, 11001061SN/A DynInstPtr &faulting_load) 11011061SN/A{ 11027897Shestness@cs.utexas.edu intInstQueueWrites++; 11032292SN/A memDepUnit[store->threadNumber].violation(store, faulting_load); 11041061SN/A} 11051061SN/A 11061061SN/Atemplate <class Impl> 11071060SN/Avoid 11086221Snate@binkert.orgInstructionQueue<Impl>::squash(ThreadID tid) 11091060SN/A{ 11102292SN/A DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in " 11112292SN/A "the IQ.\n", tid); 11121060SN/A 11131060SN/A // Read instruction sequence number of last instruction out of the 11141060SN/A // time buffer. 11152292SN/A squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum; 11161060SN/A 11171681SN/A // Call doSquash if there are insts in the IQ 11182292SN/A if (count[tid] > 0) { 11192292SN/A doSquash(tid); 11201681SN/A } 11211061SN/A 11221061SN/A // Also tell the memory dependence unit to squash. 11232292SN/A memDepUnit[tid].squash(squashedSeqNum[tid], tid); 11241060SN/A} 11251060SN/A 11261061SN/Atemplate <class Impl> 11271061SN/Avoid 11286221Snate@binkert.orgInstructionQueue<Impl>::doSquash(ThreadID tid) 11291061SN/A{ 11302326SN/A // Start at the tail. 11312326SN/A ListIt squash_it = instList[tid].end(); 11322326SN/A --squash_it; 11331061SN/A 11342292SN/A DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n", 11352292SN/A tid, squashedSeqNum[tid]); 11361061SN/A 11371061SN/A // Squash any instructions younger than the squashed sequence number 11381061SN/A // given. 11392326SN/A while (squash_it != instList[tid].end() && 11402326SN/A (*squash_it)->seqNum > squashedSeqNum[tid]) { 11412292SN/A 11422326SN/A DynInstPtr squashed_inst = (*squash_it); 11437897Shestness@cs.utexas.edu squashed_inst->isFloating() ? fpInstQueueWrites++ : intInstQueueWrites++; 11441061SN/A 11451061SN/A // Only handle the instruction if it actually is in the IQ and 11461061SN/A // hasn't already been squashed in the IQ. 11472292SN/A if (squashed_inst->threadNumber != tid || 11482292SN/A squashed_inst->isSquashedInIQ()) { 11492326SN/A --squash_it; 11502292SN/A continue; 11512292SN/A } 11522292SN/A 11532292SN/A if (!squashed_inst->isIssued() || 11542292SN/A (squashed_inst->isMemRef() && 11559046SAli.Saidi@ARM.com !squashed_inst->memOpDone())) { 11561062SN/A 11577720Sgblack@eecs.umich.edu DPRINTF(IQ, "[tid:%i]: Instruction [sn:%lli] PC %s squashed.\n", 11587720Sgblack@eecs.umich.edu tid, squashed_inst->seqNum, squashed_inst->pcState()); 11592367SN/A 116010032SGiacomo.Gabrielli@arm.com bool is_acq_rel = squashed_inst->isMemBarrier() && 116110032SGiacomo.Gabrielli@arm.com (squashed_inst->isLoad() || 116210032SGiacomo.Gabrielli@arm.com (squashed_inst->isStore() && 116310032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional())); 116410032SGiacomo.Gabrielli@arm.com 11651061SN/A // Remove the instruction from the dependency list. 116610032SGiacomo.Gabrielli@arm.com if (is_acq_rel || 116710032SGiacomo.Gabrielli@arm.com (!squashed_inst->isNonSpeculative() && 116810032SGiacomo.Gabrielli@arm.com !squashed_inst->isStoreConditional() && 116910032SGiacomo.Gabrielli@arm.com !squashed_inst->isMemBarrier() && 117010032SGiacomo.Gabrielli@arm.com !squashed_inst->isWriteBarrier())) { 11711061SN/A 11721061SN/A for (int src_reg_idx = 0; 11731681SN/A src_reg_idx < squashed_inst->numSrcRegs(); 11741061SN/A src_reg_idx++) 11751061SN/A { 11761061SN/A PhysRegIndex src_reg = 11771061SN/A squashed_inst->renamedSrcRegIdx(src_reg_idx); 11781061SN/A 11792326SN/A // Only remove it from the dependency graph if it 11802326SN/A // was placed there in the first place. 11812326SN/A 11822326SN/A // Instead of doing a linked list traversal, we 11832326SN/A // can just remove these squashed instructions 11842326SN/A // either at issue time, or when the register is 11852326SN/A // overwritten. The only downside to this is it 11862326SN/A // leaves more room for error. 11872292SN/A 11881061SN/A if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) && 11891061SN/A src_reg < numPhysRegs) { 11902326SN/A dependGraph.remove(src_reg, squashed_inst); 11911061SN/A } 11921062SN/A 11932292SN/A 11941062SN/A ++iqSquashedOperandsExamined; 11951061SN/A } 11964033Sktlim@umich.edu } else if (!squashed_inst->isStoreConditional() || 11974033Sktlim@umich.edu !squashed_inst->isCompleted()) { 11982292SN/A NonSpecMapIt ns_inst_it = 11992292SN/A nonSpecInsts.find(squashed_inst->seqNum); 12008275SAli.Saidi@ARM.com 120110017Sandreas.hansson@arm.com // we remove non-speculative instructions from 120210017Sandreas.hansson@arm.com // nonSpecInsts already when they are ready, and so we 120310017Sandreas.hansson@arm.com // cannot always expect to find them 12044033Sktlim@umich.edu if (ns_inst_it == nonSpecInsts.end()) { 120510017Sandreas.hansson@arm.com // loads that became ready but stalled on a 120610017Sandreas.hansson@arm.com // blocked cache are alreayd removed from 120710017Sandreas.hansson@arm.com // nonSpecInsts, and have not faulted 120810017Sandreas.hansson@arm.com assert(squashed_inst->getFault() != NoFault || 120910017Sandreas.hansson@arm.com squashed_inst->isMemRef()); 12104033Sktlim@umich.edu } else { 12111062SN/A 12124033Sktlim@umich.edu (*ns_inst_it).second = NULL; 12131681SN/A 12144033Sktlim@umich.edu nonSpecInsts.erase(ns_inst_it); 12151062SN/A 12164033Sktlim@umich.edu ++iqSquashedNonSpecRemoved; 12174033Sktlim@umich.edu } 12181061SN/A } 12191061SN/A 12201061SN/A // Might want to also clear out the head of the dependency graph. 12211061SN/A 12221061SN/A // Mark it as squashed within the IQ. 12231061SN/A squashed_inst->setSquashedInIQ(); 12241061SN/A 12252292SN/A // @todo: Remove this hack where several statuses are set so the 12262292SN/A // inst will flow through the rest of the pipeline. 12271681SN/A squashed_inst->setIssued(); 12281681SN/A squashed_inst->setCanCommit(); 12292731Sktlim@umich.edu squashed_inst->clearInIQ(); 12302292SN/A 12312292SN/A //Update Thread IQ Count 12322292SN/A count[squashed_inst->threadNumber]--; 12331681SN/A 12341681SN/A ++freeEntries; 12351061SN/A } 12361061SN/A 12372326SN/A instList[tid].erase(squash_it--); 12381062SN/A ++iqSquashedInstsExamined; 12391061SN/A } 12401060SN/A} 12411060SN/A 12421061SN/Atemplate <class Impl> 12431060SN/Abool 12441061SN/AInstructionQueue<Impl>::addToDependents(DynInstPtr &new_inst) 12451060SN/A{ 12461060SN/A // Loop through the instruction's source registers, adding 12471060SN/A // them to the dependency list if they are not ready. 12481060SN/A int8_t total_src_regs = new_inst->numSrcRegs(); 12491060SN/A bool return_val = false; 12501060SN/A 12511060SN/A for (int src_reg_idx = 0; 12521060SN/A src_reg_idx < total_src_regs; 12531060SN/A src_reg_idx++) 12541060SN/A { 12551060SN/A // Only add it to the dependency graph if it's not ready. 12561060SN/A if (!new_inst->isReadySrcRegIdx(src_reg_idx)) { 12571060SN/A PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx); 12581060SN/A 12591060SN/A // Check the IQ's scoreboard to make sure the register 12601060SN/A // hasn't become ready while the instruction was in flight 12611060SN/A // between stages. Only if it really isn't ready should 12621060SN/A // it be added to the dependency graph. 12631061SN/A if (src_reg >= numPhysRegs) { 12641061SN/A continue; 12651061SN/A } else if (regScoreboard[src_reg] == false) { 12667720Sgblack@eecs.umich.edu DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12671060SN/A "is being added to the dependency chain.\n", 12687720Sgblack@eecs.umich.edu new_inst->pcState(), src_reg); 12691060SN/A 12702326SN/A dependGraph.insert(src_reg, new_inst); 12711060SN/A 12721060SN/A // Change the return value to indicate that something 12731060SN/A // was added to the dependency graph. 12741060SN/A return_val = true; 12751060SN/A } else { 12767720Sgblack@eecs.umich.edu DPRINTF(IQ, "Instruction PC %s has src reg %i that " 12771060SN/A "became ready before it reached the IQ.\n", 12787720Sgblack@eecs.umich.edu new_inst->pcState(), src_reg); 12791060SN/A // Mark a register ready within the instruction. 12802326SN/A new_inst->markSrcRegReady(src_reg_idx); 12811060SN/A } 12821060SN/A } 12831060SN/A } 12841060SN/A 12851060SN/A return return_val; 12861060SN/A} 12871060SN/A 12881061SN/Atemplate <class Impl> 12891060SN/Avoid 12902326SN/AInstructionQueue<Impl>::addToProducers(DynInstPtr &new_inst) 12911060SN/A{ 12922326SN/A // Nothing really needs to be marked when an instruction becomes 12932326SN/A // the producer of a register's value, but for convenience a ptr 12942326SN/A // to the producing instruction will be placed in the head node of 12952326SN/A // the dependency links. 12961060SN/A int8_t total_dest_regs = new_inst->numDestRegs(); 12971060SN/A 12981060SN/A for (int dest_reg_idx = 0; 12991060SN/A dest_reg_idx < total_dest_regs; 13001060SN/A dest_reg_idx++) 13011060SN/A { 13021061SN/A PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx); 13031061SN/A 13041061SN/A // Instructions that use the misc regs will have a reg number 13051061SN/A // higher than the normal physical registers. In this case these 13061061SN/A // registers are not renamed, and there is no need to track 13071061SN/A // dependencies as these instructions must be executed at commit. 13081061SN/A if (dest_reg >= numPhysRegs) { 13091061SN/A continue; 13101060SN/A } 13111060SN/A 13122326SN/A if (!dependGraph.empty(dest_reg)) { 13132326SN/A dependGraph.dump(); 13142292SN/A panic("Dependency graph %i not empty!", dest_reg); 13152064SN/A } 13161062SN/A 13172326SN/A dependGraph.setInst(dest_reg, new_inst); 13181062SN/A 13191060SN/A // Mark the scoreboard to say it's not yet ready. 13201060SN/A regScoreboard[dest_reg] = false; 13211060SN/A } 13221060SN/A} 13231060SN/A 13241061SN/Atemplate <class Impl> 13251060SN/Avoid 13261061SN/AInstructionQueue<Impl>::addIfReady(DynInstPtr &inst) 13271060SN/A{ 13282326SN/A // If the instruction now has all of its source registers 13291060SN/A // available, then add it to the list of ready instructions. 13301060SN/A if (inst->readyToIssue()) { 13311061SN/A 13321060SN/A //Add the instruction to the proper ready list. 13332292SN/A if (inst->isMemRef()) { 13341061SN/A 13352292SN/A DPRINTF(IQ, "Checking if memory instruction can issue.\n"); 13361061SN/A 13371062SN/A // Message to the mem dependence unit that this instruction has 13381062SN/A // its registers ready. 13392292SN/A memDepUnit[inst->threadNumber].regsReady(inst); 13401062SN/A 13412292SN/A return; 13422292SN/A } 13431062SN/A 13442292SN/A OpClass op_class = inst->opClass(); 13451061SN/A 13462292SN/A DPRINTF(IQ, "Instruction is ready to issue, putting it onto " 13477720Sgblack@eecs.umich.edu "the ready list, PC %s opclass:%i [sn:%lli].\n", 13487720Sgblack@eecs.umich.edu inst->pcState(), op_class, inst->seqNum); 13491061SN/A 13502292SN/A readyInsts[op_class].push(inst); 13511061SN/A 13522326SN/A // Will need to reorder the list if either a queue is not on the list, 13532326SN/A // or it has an older instruction than last time. 13542326SN/A if (!queueOnList[op_class]) { 13552326SN/A addToOrderList(op_class); 13562326SN/A } else if (readyInsts[op_class].top()->seqNum < 13572326SN/A (*readyIt[op_class]).oldestInst) { 13582326SN/A listOrder.erase(readyIt[op_class]); 13592326SN/A addToOrderList(op_class); 13601060SN/A } 13611060SN/A } 13621060SN/A} 13631060SN/A 13641061SN/Atemplate <class Impl> 13651061SN/Aint 13661061SN/AInstructionQueue<Impl>::countInsts() 13671061SN/A{ 13682698Sktlim@umich.edu#if 0 13692292SN/A //ksewell:This works but definitely could use a cleaner write 13702292SN/A //with a more intuitive way of counting. Right now it's 13712292SN/A //just brute force .... 13722698Sktlim@umich.edu // Change the #if if you want to use this method. 13731061SN/A int total_insts = 0; 13741061SN/A 13756221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 13766221Snate@binkert.org ListIt count_it = instList[tid].begin(); 13771681SN/A 13786221Snate@binkert.org while (count_it != instList[tid].end()) { 13792292SN/A if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) { 13802292SN/A if (!(*count_it)->isIssued()) { 13812292SN/A ++total_insts; 13822292SN/A } else if ((*count_it)->isMemRef() && 13832292SN/A !(*count_it)->memOpDone) { 13842292SN/A // Loads that have not been marked as executed still count 13852292SN/A // towards the total instructions. 13862292SN/A ++total_insts; 13872292SN/A } 13882292SN/A } 13892292SN/A 13902292SN/A ++count_it; 13911061SN/A } 13921061SN/A } 13931061SN/A 13941061SN/A return total_insts; 13952292SN/A#else 13962292SN/A return numEntries - freeEntries; 13972292SN/A#endif 13981681SN/A} 13991681SN/A 14001681SN/Atemplate <class Impl> 14011681SN/Avoid 14021061SN/AInstructionQueue<Impl>::dumpLists() 14031061SN/A{ 14042292SN/A for (int i = 0; i < Num_OpClasses; ++i) { 14052292SN/A cprintf("Ready list %i size: %i\n", i, readyInsts[i].size()); 14061061SN/A 14072292SN/A cprintf("\n"); 14082292SN/A } 14091061SN/A 14101061SN/A cprintf("Non speculative list size: %i\n", nonSpecInsts.size()); 14111061SN/A 14122292SN/A NonSpecMapIt non_spec_it = nonSpecInsts.begin(); 14132292SN/A NonSpecMapIt non_spec_end_it = nonSpecInsts.end(); 14141061SN/A 14151061SN/A cprintf("Non speculative list: "); 14161061SN/A 14172292SN/A while (non_spec_it != non_spec_end_it) { 14187720Sgblack@eecs.umich.edu cprintf("%s [sn:%lli]", (*non_spec_it).second->pcState(), 14192292SN/A (*non_spec_it).second->seqNum); 14201061SN/A ++non_spec_it; 14211061SN/A } 14221061SN/A 14231061SN/A cprintf("\n"); 14241061SN/A 14252292SN/A ListOrderIt list_order_it = listOrder.begin(); 14262292SN/A ListOrderIt list_order_end_it = listOrder.end(); 14272292SN/A int i = 1; 14282292SN/A 14292292SN/A cprintf("List order: "); 14302292SN/A 14312292SN/A while (list_order_it != list_order_end_it) { 14322292SN/A cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType, 14332292SN/A (*list_order_it).oldestInst); 14342292SN/A 14352292SN/A ++list_order_it; 14362292SN/A ++i; 14372292SN/A } 14382292SN/A 14392292SN/A cprintf("\n"); 14401061SN/A} 14412292SN/A 14422292SN/A 14432292SN/Atemplate <class Impl> 14442292SN/Avoid 14452292SN/AInstructionQueue<Impl>::dumpInsts() 14462292SN/A{ 14476221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; ++tid) { 14482292SN/A int num = 0; 14492292SN/A int valid_num = 0; 14506221Snate@binkert.org ListIt inst_list_it = instList[tid].begin(); 14512292SN/A 14526221Snate@binkert.org while (inst_list_it != instList[tid].end()) { 14536221Snate@binkert.org cprintf("Instruction:%i\n", num); 14542292SN/A if (!(*inst_list_it)->isSquashed()) { 14552292SN/A if (!(*inst_list_it)->isIssued()) { 14562292SN/A ++valid_num; 14572292SN/A cprintf("Count:%i\n", valid_num); 14582292SN/A } else if ((*inst_list_it)->isMemRef() && 14599046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 14602326SN/A // Loads that have not been marked as executed 14612326SN/A // still count towards the total instructions. 14622292SN/A ++valid_num; 14632292SN/A cprintf("Count:%i\n", valid_num); 14642292SN/A } 14652292SN/A } 14662292SN/A 14677720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 14682292SN/A "Issued:%i\nSquashed:%i\n", 14697720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 14702292SN/A (*inst_list_it)->seqNum, 14712292SN/A (*inst_list_it)->threadNumber, 14722292SN/A (*inst_list_it)->isIssued(), 14732292SN/A (*inst_list_it)->isSquashed()); 14742292SN/A 14752292SN/A if ((*inst_list_it)->isMemRef()) { 14769046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 14772292SN/A } 14782292SN/A 14792292SN/A cprintf("\n"); 14802292SN/A 14812292SN/A inst_list_it++; 14822292SN/A ++num; 14832292SN/A } 14842292SN/A } 14852348SN/A 14862348SN/A cprintf("Insts to Execute list:\n"); 14872348SN/A 14882348SN/A int num = 0; 14892348SN/A int valid_num = 0; 14902348SN/A ListIt inst_list_it = instsToExecute.begin(); 14912348SN/A 14922348SN/A while (inst_list_it != instsToExecute.end()) 14932348SN/A { 14942348SN/A cprintf("Instruction:%i\n", 14952348SN/A num); 14962348SN/A if (!(*inst_list_it)->isSquashed()) { 14972348SN/A if (!(*inst_list_it)->isIssued()) { 14982348SN/A ++valid_num; 14992348SN/A cprintf("Count:%i\n", valid_num); 15002348SN/A } else if ((*inst_list_it)->isMemRef() && 15019046SAli.Saidi@ARM.com !(*inst_list_it)->memOpDone()) { 15022348SN/A // Loads that have not been marked as executed 15032348SN/A // still count towards the total instructions. 15042348SN/A ++valid_num; 15052348SN/A cprintf("Count:%i\n", valid_num); 15062348SN/A } 15072348SN/A } 15082348SN/A 15097720Sgblack@eecs.umich.edu cprintf("PC: %s\n[sn:%lli]\n[tid:%i]\n" 15102348SN/A "Issued:%i\nSquashed:%i\n", 15117720Sgblack@eecs.umich.edu (*inst_list_it)->pcState(), 15122348SN/A (*inst_list_it)->seqNum, 15132348SN/A (*inst_list_it)->threadNumber, 15142348SN/A (*inst_list_it)->isIssued(), 15152348SN/A (*inst_list_it)->isSquashed()); 15162348SN/A 15172348SN/A if ((*inst_list_it)->isMemRef()) { 15189046SAli.Saidi@ARM.com cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone()); 15192348SN/A } 15202348SN/A 15212348SN/A cprintf("\n"); 15222348SN/A 15232348SN/A inst_list_it++; 15242348SN/A ++num; 15252348SN/A } 15262292SN/A} 15279944Smatt.horsnell@ARM.com 15289944Smatt.horsnell@ARM.com#endif//__CPU_O3_INST_QUEUE_IMPL_HH__ 1529