inst_queue.hh revision 9184
11689SN/A/* 27944SGiacomo.Gabrielli@arm.com * Copyright (c) 2011 ARM Limited 37944SGiacomo.Gabrielli@arm.com * All rights reserved. 47944SGiacomo.Gabrielli@arm.com * 57944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 67944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 77944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 87944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 97944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 107944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 117944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 127944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 137944SGiacomo.Gabrielli@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 432292SN/A#ifndef __CPU_O3_INST_QUEUE_HH__ 442292SN/A#define __CPU_O3_INST_QUEUE_HH__ 451060SN/A 461060SN/A#include <list> 471061SN/A#include <map> 481060SN/A#include <queue> 491061SN/A#include <vector> 501060SN/A 511062SN/A#include "base/statistics.hh" 528229Snate@binkert.org#include "base/types.hh" 538229Snate@binkert.org#include "cpu/o3/dep_graph.hh" 548229Snate@binkert.org#include "cpu/inst_seq.hh" 558229Snate@binkert.org#include "cpu/op_class.hh" 567813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 575529Snate@binkert.org#include "sim/eventq.hh" 581060SN/A 598737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 602292SN/Aclass FUPool; 612292SN/Aclass MemInterface; 622292SN/A 631060SN/A/** 641689SN/A * A standard instruction queue class. It holds ready instructions, in 651689SN/A * order, in seperate priority queues to facilitate the scheduling of 661689SN/A * instructions. The IQ uses a separate linked list to track dependencies. 671689SN/A * Similar to the rename map and the free list, it expects that 681060SN/A * floating point registers have their indices start after the integer 691060SN/A * registers (ie with 96 int and 96 fp registers, regs 0-95 are integer 701060SN/A * and 96-191 are fp). This remains true even for both logical and 712292SN/A * physical register indices. The IQ depends on the memory dependence unit to 722292SN/A * track when memory operations are ready in terms of ordering; register 732292SN/A * dependencies are tracked normally. Right now the IQ also handles the 742292SN/A * execution timing; this is mainly to allow back-to-back scheduling without 752292SN/A * requiring IEW to be able to peek into the IQ. At the end of the execution 762292SN/A * latency, the instruction is put into the queue to execute, where it will 772292SN/A * have the execute() function called on it. 782292SN/A * @todo: Make IQ able to handle multiple FU pools. 791060SN/A */ 801061SN/Atemplate <class Impl> 811060SN/Aclass InstructionQueue 821060SN/A{ 831060SN/A public: 841060SN/A //Typedefs from the Impl. 852733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 861061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 871060SN/A 882292SN/A typedef typename Impl::CPUPol::IEW IEW; 891061SN/A typedef typename Impl::CPUPol::MemDepUnit MemDepUnit; 901061SN/A typedef typename Impl::CPUPol::IssueStruct IssueStruct; 911061SN/A typedef typename Impl::CPUPol::TimeStruct TimeStruct; 921060SN/A 932292SN/A // Typedef of iterator through the list of instructions. 941061SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 951060SN/A 962292SN/A /** FU completion event class. */ 972292SN/A class FUCompletion : public Event { 982292SN/A private: 992292SN/A /** Executing instruction. */ 1002292SN/A DynInstPtr inst; 1012292SN/A 1022292SN/A /** Index of the FU used for executing. */ 1032292SN/A int fuIdx; 1042292SN/A 1052292SN/A /** Pointer back to the instruction queue. */ 1062292SN/A InstructionQueue<Impl> *iqPtr; 1072292SN/A 1082348SN/A /** Should the FU be added to the list to be freed upon 1092348SN/A * completing this event. 1102348SN/A */ 1112326SN/A bool freeFU; 1122326SN/A 1132292SN/A public: 1142292SN/A /** Construct a FU completion event. */ 1152292SN/A FUCompletion(DynInstPtr &_inst, int fu_idx, 1162292SN/A InstructionQueue<Impl> *iq_ptr); 1172292SN/A 1182292SN/A virtual void process(); 1195336Shines@cs.fsu.edu virtual const char *description() const; 1202326SN/A void setFreeFU() { freeFU = true; } 1211060SN/A }; 1221060SN/A 1232292SN/A /** Constructs an IQ. */ 1245529Snate@binkert.org InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 1251061SN/A 1262292SN/A /** Destructs the IQ. */ 1272292SN/A ~InstructionQueue(); 1281061SN/A 1292292SN/A /** Returns the name of the IQ. */ 1302292SN/A std::string name() const; 1311060SN/A 1322292SN/A /** Registers statistics. */ 1331062SN/A void regStats(); 1341062SN/A 1352348SN/A /** Resets all instruction queue state. */ 1362307SN/A void resetState(); 1371060SN/A 1382292SN/A /** Sets active threads list. */ 1396221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1402292SN/A 1412292SN/A /** Sets the timer buffer between issue and execute. */ 1421060SN/A void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue); 1431060SN/A 1442292SN/A /** Sets the global time buffer. */ 1451060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1461060SN/A 1472348SN/A /** Switches out the instruction queue. */ 1482307SN/A void switchOut(); 1492307SN/A 1502348SN/A /** Takes over execution from another CPU's thread. */ 1512307SN/A void takeOverFrom(); 1522307SN/A 1532348SN/A /** Returns if the IQ is switched out. */ 1542307SN/A bool isSwitchedOut() { return switchedOut; } 1552307SN/A 1562292SN/A /** Number of entries needed for given amount of threads. */ 1576221Snate@binkert.org int entryAmount(ThreadID num_threads); 1582292SN/A 1592292SN/A /** Resets max entries for all threads. */ 1602292SN/A void resetEntries(); 1612292SN/A 1622292SN/A /** Returns total number of free entries. */ 1631060SN/A unsigned numFreeEntries(); 1641060SN/A 1652292SN/A /** Returns number of free entries for a thread. */ 1666221Snate@binkert.org unsigned numFreeEntries(ThreadID tid); 1672292SN/A 1682292SN/A /** Returns whether or not the IQ is full. */ 1691060SN/A bool isFull(); 1701060SN/A 1712292SN/A /** Returns whether or not the IQ is full for a specific thread. */ 1726221Snate@binkert.org bool isFull(ThreadID tid); 1732292SN/A 1742292SN/A /** Returns if there are any ready instructions in the IQ. */ 1752292SN/A bool hasReadyInsts(); 1762292SN/A 1772292SN/A /** Inserts a new instruction into the IQ. */ 1781061SN/A void insert(DynInstPtr &new_inst); 1791060SN/A 1802292SN/A /** Inserts a new, non-speculative instruction into the IQ. */ 1811061SN/A void insertNonSpec(DynInstPtr &new_inst); 1821061SN/A 1832292SN/A /** Inserts a memory or write barrier into the IQ to make sure 1842292SN/A * loads and stores are ordered properly. 1852292SN/A */ 1862292SN/A void insertBarrier(DynInstPtr &barr_inst); 1871060SN/A 1882348SN/A /** Returns the oldest scheduled instruction, and removes it from 1892348SN/A * the list of instructions waiting to execute. 1902348SN/A */ 1912333SN/A DynInstPtr getInstToExecute(); 1922333SN/A 1937944SGiacomo.Gabrielli@arm.com /** Returns a memory instruction that was referred due to a delayed DTB 1947944SGiacomo.Gabrielli@arm.com * translation if it is now ready to execute. 1957944SGiacomo.Gabrielli@arm.com */ 1967944SGiacomo.Gabrielli@arm.com DynInstPtr getDeferredMemInstToExecute(); 1977944SGiacomo.Gabrielli@arm.com 1982292SN/A /** 1992326SN/A * Records the instruction as the producer of a register without 2002326SN/A * adding it to the rest of the IQ. 2012292SN/A */ 2022326SN/A void recordProducer(DynInstPtr &inst) 2032326SN/A { addToProducers(inst); } 2041755SN/A 2052292SN/A /** Process FU completion event. */ 2062292SN/A void processFUCompletion(DynInstPtr &inst, int fu_idx); 2072292SN/A 2082292SN/A /** 2092292SN/A * Schedules ready instructions, adding the ready ones (oldest first) to 2102292SN/A * the queue to execute. 2112292SN/A */ 2121060SN/A void scheduleReadyInsts(); 2131060SN/A 2142292SN/A /** Schedules a single specific non-speculative instruction. */ 2151061SN/A void scheduleNonSpec(const InstSeqNum &inst); 2161061SN/A 2172292SN/A /** 2182292SN/A * Commits all instructions up to and including the given sequence number, 2192292SN/A * for a specific thread. 2202292SN/A */ 2216221Snate@binkert.org void commit(const InstSeqNum &inst, ThreadID tid = 0); 2221061SN/A 2232292SN/A /** Wakes all dependents of a completed instruction. */ 2242301SN/A int wakeDependents(DynInstPtr &completed_inst); 2251755SN/A 2262292SN/A /** Adds a ready memory instruction to the ready list. */ 2272292SN/A void addReadyMemInst(DynInstPtr &ready_inst); 2282292SN/A 2292292SN/A /** 2302292SN/A * Reschedules a memory instruction. It will be ready to issue once 2312292SN/A * replayMemInst() is called. 2322292SN/A */ 2332292SN/A void rescheduleMemInst(DynInstPtr &resched_inst); 2342292SN/A 2352292SN/A /** Replays a memory instruction. It must be rescheduled first. */ 2362292SN/A void replayMemInst(DynInstPtr &replay_inst); 2372292SN/A 2382292SN/A /** Completes a memory operation. */ 2392292SN/A void completeMemInst(DynInstPtr &completed_inst); 2402292SN/A 2417944SGiacomo.Gabrielli@arm.com /** 2427944SGiacomo.Gabrielli@arm.com * Defers a memory instruction when its DTB translation incurs a hw 2437944SGiacomo.Gabrielli@arm.com * page table walk. 2447944SGiacomo.Gabrielli@arm.com */ 2457944SGiacomo.Gabrielli@arm.com void deferMemInst(DynInstPtr &deferred_inst); 2467944SGiacomo.Gabrielli@arm.com 2472292SN/A /** Indicates an ordering violation between a store and a load. */ 2481061SN/A void violation(DynInstPtr &store, DynInstPtr &faulting_load); 2491061SN/A 2502292SN/A /** 2512292SN/A * Squashes instructions for a thread. Squashing information is obtained 2522292SN/A * from the time buffer. 2532292SN/A */ 2546221Snate@binkert.org void squash(ThreadID tid); 2551060SN/A 2562292SN/A /** Returns the number of used entries for a thread. */ 2576221Snate@binkert.org unsigned getCount(ThreadID tid) { return count[tid]; }; 2581060SN/A 2592292SN/A /** Debug function to print all instructions. */ 2602292SN/A void printInsts(); 2611060SN/A 2621060SN/A private: 2632292SN/A /** Does the actual squashing. */ 2646221Snate@binkert.org void doSquash(ThreadID tid); 2652292SN/A 2662292SN/A ///////////////////////// 2672292SN/A // Various pointers 2682292SN/A ///////////////////////// 2692292SN/A 2701060SN/A /** Pointer to the CPU. */ 2712733Sktlim@umich.edu O3CPU *cpu; 2721060SN/A 2732292SN/A /** Cache interface. */ 2742292SN/A MemInterface *dcacheInterface; 2752292SN/A 2762292SN/A /** Pointer to IEW stage. */ 2772292SN/A IEW *iewStage; 2782292SN/A 2791061SN/A /** The memory dependence unit, which tracks/predicts memory dependences 2801061SN/A * between instructions. 2811061SN/A */ 2822292SN/A MemDepUnit memDepUnit[Impl::MaxThreads]; 2831061SN/A 2841060SN/A /** The queue to the execute stage. Issued instructions will be written 2851060SN/A * into it. 2861060SN/A */ 2871060SN/A TimeBuffer<IssueStruct> *issueToExecuteQueue; 2881060SN/A 2891060SN/A /** The backwards time buffer. */ 2901060SN/A TimeBuffer<TimeStruct> *timeBuffer; 2911060SN/A 2921060SN/A /** Wire to read information from timebuffer. */ 2931060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 2941060SN/A 2952292SN/A /** Function unit pool. */ 2962292SN/A FUPool *fuPool; 2972292SN/A 2982292SN/A ////////////////////////////////////// 2992292SN/A // Instruction lists, ready queues, and ordering 3002292SN/A ////////////////////////////////////// 3012292SN/A 3022292SN/A /** List of all the instructions in the IQ (some of which may be issued). */ 3032292SN/A std::list<DynInstPtr> instList[Impl::MaxThreads]; 3042292SN/A 3052348SN/A /** List of instructions that are ready to be executed. */ 3062333SN/A std::list<DynInstPtr> instsToExecute; 3072333SN/A 3087944SGiacomo.Gabrielli@arm.com /** List of instructions waiting for their DTB translation to 3097944SGiacomo.Gabrielli@arm.com * complete (hw page table walk in progress). 3107944SGiacomo.Gabrielli@arm.com */ 3117944SGiacomo.Gabrielli@arm.com std::list<DynInstPtr> deferredMemInsts; 3127944SGiacomo.Gabrielli@arm.com 3132292SN/A /** 3142348SN/A * Struct for comparing entries to be added to the priority queue. 3152348SN/A * This gives reverse ordering to the instructions in terms of 3162348SN/A * sequence numbers: the instructions with smaller sequence 3172348SN/A * numbers (and hence are older) will be at the top of the 3182348SN/A * priority queue. 3192292SN/A */ 3202292SN/A struct pqCompare { 3212292SN/A bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const 3222292SN/A { 3232292SN/A return lhs->seqNum > rhs->seqNum; 3242292SN/A } 3251060SN/A }; 3261060SN/A 3272292SN/A typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> 3282292SN/A ReadyInstQueue; 3291755SN/A 3302292SN/A /** List of ready instructions, per op class. They are separated by op 3312292SN/A * class to allow for easy mapping to FUs. 3321061SN/A */ 3332292SN/A ReadyInstQueue readyInsts[Num_OpClasses]; 3341061SN/A 3351061SN/A /** List of non-speculative instructions that will be scheduled 3361061SN/A * once the IQ gets a signal from commit. While it's redundant to 3371061SN/A * have the key be a part of the value (the sequence number is stored 3381061SN/A * inside of DynInst), when these instructions are woken up only 3391681SN/A * the sequence number will be available. Thus it is most efficient to be 3401061SN/A * able to search by the sequence number alone. 3411061SN/A */ 3421061SN/A std::map<InstSeqNum, DynInstPtr> nonSpecInsts; 3431061SN/A 3442292SN/A typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt; 3452292SN/A 3462292SN/A /** Entry for the list age ordering by op class. */ 3472292SN/A struct ListOrderEntry { 3482292SN/A OpClass queueType; 3492292SN/A InstSeqNum oldestInst; 3502292SN/A }; 3512292SN/A 3522292SN/A /** List that contains the age order of the oldest instruction of each 3532292SN/A * ready queue. Used to select the oldest instruction available 3542292SN/A * among op classes. 3552326SN/A * @todo: Might be better to just move these entries around instead 3562326SN/A * of creating new ones every time the position changes due to an 3572326SN/A * instruction issuing. Not sure std::list supports this. 3582292SN/A */ 3592292SN/A std::list<ListOrderEntry> listOrder; 3602292SN/A 3612292SN/A typedef typename std::list<ListOrderEntry>::iterator ListOrderIt; 3622292SN/A 3632292SN/A /** Tracks if each ready queue is on the age order list. */ 3642292SN/A bool queueOnList[Num_OpClasses]; 3652292SN/A 3662292SN/A /** Iterators of each ready queue. Points to their spot in the age order 3672292SN/A * list. 3682292SN/A */ 3692292SN/A ListOrderIt readyIt[Num_OpClasses]; 3702292SN/A 3712292SN/A /** Add an op class to the age order list. */ 3722292SN/A void addToOrderList(OpClass op_class); 3732292SN/A 3742292SN/A /** 3752292SN/A * Called when the oldest instruction has been removed from a ready queue; 3762292SN/A * this places that ready queue into the proper spot in the age order list. 3772292SN/A */ 3782292SN/A void moveToYoungerInst(ListOrderIt age_order_it); 3792292SN/A 3802326SN/A DependencyGraph<DynInstPtr> dependGraph; 3812326SN/A 3822292SN/A ////////////////////////////////////// 3832292SN/A // Various parameters 3842292SN/A ////////////////////////////////////// 3852292SN/A 3862292SN/A /** IQ Resource Sharing Policy */ 3872292SN/A enum IQPolicy { 3882292SN/A Dynamic, 3892292SN/A Partitioned, 3902292SN/A Threshold 3912292SN/A }; 3922292SN/A 3932292SN/A /** IQ sharing policy for SMT. */ 3942292SN/A IQPolicy iqPolicy; 3952292SN/A 3962292SN/A /** Number of Total Threads*/ 3976221Snate@binkert.org ThreadID numThreads; 3982292SN/A 3992292SN/A /** Pointer to list of active threads. */ 4006221Snate@binkert.org std::list<ThreadID> *activeThreads; 4012292SN/A 4022292SN/A /** Per Thread IQ count */ 4032292SN/A unsigned count[Impl::MaxThreads]; 4042292SN/A 4052292SN/A /** Max IQ Entries Per Thread */ 4062292SN/A unsigned maxEntries[Impl::MaxThreads]; 4071060SN/A 4081060SN/A /** Number of free IQ entries left. */ 4091060SN/A unsigned freeEntries; 4101060SN/A 4111060SN/A /** The number of entries in the instruction queue. */ 4121060SN/A unsigned numEntries; 4131060SN/A 4141060SN/A /** The total number of instructions that can be issued in one cycle. */ 4151060SN/A unsigned totalWidth; 4161060SN/A 4172292SN/A /** The number of physical registers in the CPU. */ 4181060SN/A unsigned numPhysRegs; 4191060SN/A 4201060SN/A /** The number of physical integer registers in the CPU. */ 4211060SN/A unsigned numPhysIntRegs; 4221060SN/A 4231060SN/A /** The number of floating point registers in the CPU. */ 4241060SN/A unsigned numPhysFloatRegs; 4251060SN/A 4261060SN/A /** Delay between commit stage and the IQ. 4271060SN/A * @todo: Make there be a distinction between the delays within IEW. 4281060SN/A */ 4299184Sandreas.hansson@arm.com Cycles commitToIEWDelay; 4301060SN/A 4312348SN/A /** Is the IQ switched out. */ 4322307SN/A bool switchedOut; 4331060SN/A 4341060SN/A /** The sequence number of the squashed instruction. */ 4352292SN/A InstSeqNum squashedSeqNum[Impl::MaxThreads]; 4361060SN/A 4371060SN/A /** A cache of the recently woken registers. It is 1 if the register 4381060SN/A * has been woken up recently, and 0 if the register has been added 4391060SN/A * to the dependency graph and has not yet received its value. It 4401060SN/A * is basically a secondary scoreboard, and should pretty much mirror 4411060SN/A * the scoreboard that exists in the rename map. 4421060SN/A */ 4432292SN/A std::vector<bool> regScoreboard; 4441060SN/A 4452326SN/A /** Adds an instruction to the dependency graph, as a consumer. */ 4461061SN/A bool addToDependents(DynInstPtr &new_inst); 4471684SN/A 4482326SN/A /** Adds an instruction to the dependency graph, as a producer. */ 4492326SN/A void addToProducers(DynInstPtr &new_inst); 4501755SN/A 4512292SN/A /** Moves an instruction to the ready queue if it is ready. */ 4521684SN/A void addIfReady(DynInstPtr &inst); 4531684SN/A 4541684SN/A /** Debugging function to count how many entries are in the IQ. It does 4551684SN/A * a linear walk through the instructions, so do not call this function 4561684SN/A * during normal execution. 4571684SN/A */ 4581684SN/A int countInsts(); 4591684SN/A 4601684SN/A /** Debugging function to dump all the list sizes, as well as print 4611684SN/A * out the list of nonspeculative instructions. Should not be used 4621684SN/A * in any other capacity, but it has no harmful sideaffects. 4631684SN/A */ 4641684SN/A void dumpLists(); 4651062SN/A 4662292SN/A /** Debugging function to dump out all instructions that are in the 4672292SN/A * IQ. 4682292SN/A */ 4692292SN/A void dumpInsts(); 4702292SN/A 4712292SN/A /** Stat for number of instructions added. */ 4725999Snate@binkert.org Stats::Scalar iqInstsAdded; 4732292SN/A /** Stat for number of non-speculative instructions added. */ 4745999Snate@binkert.org Stats::Scalar iqNonSpecInstsAdded; 4752326SN/A 4765999Snate@binkert.org Stats::Scalar iqInstsIssued; 4772292SN/A /** Stat for number of integer instructions issued. */ 4785999Snate@binkert.org Stats::Scalar iqIntInstsIssued; 4792292SN/A /** Stat for number of floating point instructions issued. */ 4805999Snate@binkert.org Stats::Scalar iqFloatInstsIssued; 4812292SN/A /** Stat for number of branch instructions issued. */ 4825999Snate@binkert.org Stats::Scalar iqBranchInstsIssued; 4832292SN/A /** Stat for number of memory instructions issued. */ 4845999Snate@binkert.org Stats::Scalar iqMemInstsIssued; 4852292SN/A /** Stat for number of miscellaneous instructions issued. */ 4865999Snate@binkert.org Stats::Scalar iqMiscInstsIssued; 4872292SN/A /** Stat for number of squashed instructions that were ready to issue. */ 4885999Snate@binkert.org Stats::Scalar iqSquashedInstsIssued; 4892292SN/A /** Stat for number of squashed instructions examined when squashing. */ 4905999Snate@binkert.org Stats::Scalar iqSquashedInstsExamined; 4912292SN/A /** Stat for number of squashed instruction operands examined when 4922292SN/A * squashing. 4932292SN/A */ 4945999Snate@binkert.org Stats::Scalar iqSquashedOperandsExamined; 4952292SN/A /** Stat for number of non-speculative instructions removed due to a squash. 4962292SN/A */ 4975999Snate@binkert.org Stats::Scalar iqSquashedNonSpecRemoved; 4982727Sktlim@umich.edu // Also include number of instructions rescheduled and replayed. 4991062SN/A 5002727Sktlim@umich.edu /** Distribution of number of instructions in the queue. 5012727Sktlim@umich.edu * @todo: Need to create struct to track the entry time for each 5022727Sktlim@umich.edu * instruction. */ 5035999Snate@binkert.org// Stats::VectorDistribution queueResDist; 5042348SN/A /** Distribution of the number of instructions issued. */ 5055999Snate@binkert.org Stats::Distribution numIssuedDist; 5062727Sktlim@umich.edu /** Distribution of the cycles it takes to issue an instruction. 5072727Sktlim@umich.edu * @todo: Need to create struct to track the ready time for each 5082727Sktlim@umich.edu * instruction. */ 5095999Snate@binkert.org// Stats::VectorDistribution issueDelayDist; 5102301SN/A 5112348SN/A /** Number of times an instruction could not be issued because a 5122348SN/A * FU was busy. 5132348SN/A */ 5145999Snate@binkert.org Stats::Vector statFuBusy; 5155999Snate@binkert.org// Stats::Vector dist_unissued; 5162348SN/A /** Stat for total number issued for each instruction type. */ 5175999Snate@binkert.org Stats::Vector2d statIssuedInstType; 5182301SN/A 5192348SN/A /** Number of instructions issued per cycle. */ 5202326SN/A Stats::Formula issueRate; 5212727Sktlim@umich.edu 5222348SN/A /** Number of times the FU was busy. */ 5235999Snate@binkert.org Stats::Vector fuBusy; 5242348SN/A /** Number of times the FU was busy per instruction issued. */ 5252326SN/A Stats::Formula fuBusyRate; 5267897Shestness@cs.utexas.edu public: 5277897Shestness@cs.utexas.edu Stats::Scalar intInstQueueReads; 5287897Shestness@cs.utexas.edu Stats::Scalar intInstQueueWrites; 5297897Shestness@cs.utexas.edu Stats::Scalar intInstQueueWakeupAccesses; 5307897Shestness@cs.utexas.edu Stats::Scalar fpInstQueueReads; 5317897Shestness@cs.utexas.edu Stats::Scalar fpInstQueueWrites; 5327897Shestness@cs.utexas.edu Stats::Scalar fpInstQueueWakeupQccesses; 5337897Shestness@cs.utexas.edu 5347897Shestness@cs.utexas.edu Stats::Scalar intAluAccesses; 5357897Shestness@cs.utexas.edu Stats::Scalar fpAluAccesses; 5361060SN/A}; 5371060SN/A 5382292SN/A#endif //__CPU_O3_INST_QUEUE_HH__ 539