inst_queue.hh revision 7944
110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2011 ARM Limited 310259SAndrew.Bardsley@arm.com * All rights reserved. 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 1510259SAndrew.Bardsley@arm.com * All rights reserved. 1610259SAndrew.Bardsley@arm.com * 1710259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1810259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1910259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 2010259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 2110259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 2210259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2310259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2410259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2510259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2610259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2710259SAndrew.Bardsley@arm.com * 2810259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2910259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3010259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3110259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3210259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3310259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3410259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3510259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3610259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3710259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3810259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3910259SAndrew.Bardsley@arm.com * 4010259SAndrew.Bardsley@arm.com * Authors: Kevin Lim 4110259SAndrew.Bardsley@arm.com */ 4210259SAndrew.Bardsley@arm.com 4310259SAndrew.Bardsley@arm.com#ifndef __CPU_O3_INST_QUEUE_HH__ 4410259SAndrew.Bardsley@arm.com#define __CPU_O3_INST_QUEUE_HH__ 4510259SAndrew.Bardsley@arm.com 4610259SAndrew.Bardsley@arm.com#include <list> 4710259SAndrew.Bardsley@arm.com#include <map> 4810259SAndrew.Bardsley@arm.com#include <queue> 4910259SAndrew.Bardsley@arm.com#include <vector> 5010259SAndrew.Bardsley@arm.com 5110259SAndrew.Bardsley@arm.com#include "base/statistics.hh" 5210259SAndrew.Bardsley@arm.com#include "cpu/timebuf.hh" 5310259SAndrew.Bardsley@arm.com#include "base/types.hh" 5410259SAndrew.Bardsley@arm.com#include "cpu/inst_seq.hh" 5510259SAndrew.Bardsley@arm.com#include "cpu/o3/dep_graph.hh" 5610259SAndrew.Bardsley@arm.com#include "cpu/op_class.hh" 5710259SAndrew.Bardsley@arm.com#include "sim/eventq.hh" 5810259SAndrew.Bardsley@arm.com 5910259SAndrew.Bardsley@arm.comclass DerivO3CPUParams; 6010259SAndrew.Bardsley@arm.comclass FUPool; 6110259SAndrew.Bardsley@arm.comclass MemInterface; 6210259SAndrew.Bardsley@arm.com 6310259SAndrew.Bardsley@arm.com/** 6410259SAndrew.Bardsley@arm.com * A standard instruction queue class. It holds ready instructions, in 6510259SAndrew.Bardsley@arm.com * order, in seperate priority queues to facilitate the scheduling of 6610259SAndrew.Bardsley@arm.com * instructions. The IQ uses a separate linked list to track dependencies. 6710259SAndrew.Bardsley@arm.com * Similar to the rename map and the free list, it expects that 6810259SAndrew.Bardsley@arm.com * floating point registers have their indices start after the integer 6910259SAndrew.Bardsley@arm.com * registers (ie with 96 int and 96 fp registers, regs 0-95 are integer 7010259SAndrew.Bardsley@arm.com * and 96-191 are fp). This remains true even for both logical and 7110259SAndrew.Bardsley@arm.com * physical register indices. The IQ depends on the memory dependence unit to 7210259SAndrew.Bardsley@arm.com * track when memory operations are ready in terms of ordering; register 7310259SAndrew.Bardsley@arm.com * dependencies are tracked normally. Right now the IQ also handles the 7410259SAndrew.Bardsley@arm.com * execution timing; this is mainly to allow back-to-back scheduling without 7510259SAndrew.Bardsley@arm.com * requiring IEW to be able to peek into the IQ. At the end of the execution 7610259SAndrew.Bardsley@arm.com * latency, the instruction is put into the queue to execute, where it will 7710259SAndrew.Bardsley@arm.com * have the execute() function called on it. 7810259SAndrew.Bardsley@arm.com * @todo: Make IQ able to handle multiple FU pools. 7910259SAndrew.Bardsley@arm.com */ 8010259SAndrew.Bardsley@arm.comtemplate <class Impl> 8110259SAndrew.Bardsley@arm.comclass InstructionQueue 8210259SAndrew.Bardsley@arm.com{ 8310259SAndrew.Bardsley@arm.com public: 8410259SAndrew.Bardsley@arm.com //Typedefs from the Impl. 8510259SAndrew.Bardsley@arm.com typedef typename Impl::O3CPU O3CPU; 8610259SAndrew.Bardsley@arm.com typedef typename Impl::DynInstPtr DynInstPtr; 8710259SAndrew.Bardsley@arm.com 8810259SAndrew.Bardsley@arm.com typedef typename Impl::CPUPol::IEW IEW; 8910259SAndrew.Bardsley@arm.com typedef typename Impl::CPUPol::MemDepUnit MemDepUnit; 9010259SAndrew.Bardsley@arm.com typedef typename Impl::CPUPol::IssueStruct IssueStruct; 9110259SAndrew.Bardsley@arm.com typedef typename Impl::CPUPol::TimeStruct TimeStruct; 9210259SAndrew.Bardsley@arm.com 9310259SAndrew.Bardsley@arm.com // Typedef of iterator through the list of instructions. 9410259SAndrew.Bardsley@arm.com typedef typename std::list<DynInstPtr>::iterator ListIt; 9510259SAndrew.Bardsley@arm.com 9610259SAndrew.Bardsley@arm.com friend class Impl::O3CPU; 9710259SAndrew.Bardsley@arm.com 9810259SAndrew.Bardsley@arm.com /** FU completion event class. */ 9910259SAndrew.Bardsley@arm.com class FUCompletion : public Event { 10010259SAndrew.Bardsley@arm.com private: 10110259SAndrew.Bardsley@arm.com /** Executing instruction. */ 10210259SAndrew.Bardsley@arm.com DynInstPtr inst; 10310259SAndrew.Bardsley@arm.com 10410259SAndrew.Bardsley@arm.com /** Index of the FU used for executing. */ 10510259SAndrew.Bardsley@arm.com int fuIdx; 10610259SAndrew.Bardsley@arm.com 10710259SAndrew.Bardsley@arm.com /** Pointer back to the instruction queue. */ 10810259SAndrew.Bardsley@arm.com InstructionQueue<Impl> *iqPtr; 10910259SAndrew.Bardsley@arm.com 11010259SAndrew.Bardsley@arm.com /** Should the FU be added to the list to be freed upon 11110259SAndrew.Bardsley@arm.com * completing this event. 11210259SAndrew.Bardsley@arm.com */ 11310259SAndrew.Bardsley@arm.com bool freeFU; 11410259SAndrew.Bardsley@arm.com 11510259SAndrew.Bardsley@arm.com public: 11610259SAndrew.Bardsley@arm.com /** Construct a FU completion event. */ 11710259SAndrew.Bardsley@arm.com FUCompletion(DynInstPtr &_inst, int fu_idx, 11810259SAndrew.Bardsley@arm.com InstructionQueue<Impl> *iq_ptr); 11910259SAndrew.Bardsley@arm.com 12010259SAndrew.Bardsley@arm.com virtual void process(); 12110259SAndrew.Bardsley@arm.com virtual const char *description() const; 12210259SAndrew.Bardsley@arm.com void setFreeFU() { freeFU = true; } 12310259SAndrew.Bardsley@arm.com }; 12410259SAndrew.Bardsley@arm.com 12510259SAndrew.Bardsley@arm.com /** Constructs an IQ. */ 12610259SAndrew.Bardsley@arm.com InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 12710259SAndrew.Bardsley@arm.com 12810259SAndrew.Bardsley@arm.com /** Destructs the IQ. */ 12910259SAndrew.Bardsley@arm.com ~InstructionQueue(); 13010259SAndrew.Bardsley@arm.com 13110259SAndrew.Bardsley@arm.com /** Returns the name of the IQ. */ 13210259SAndrew.Bardsley@arm.com std::string name() const; 13310259SAndrew.Bardsley@arm.com 13410259SAndrew.Bardsley@arm.com /** Registers statistics. */ 13510259SAndrew.Bardsley@arm.com void regStats(); 13610259SAndrew.Bardsley@arm.com 13710259SAndrew.Bardsley@arm.com /** Resets all instruction queue state. */ 13810259SAndrew.Bardsley@arm.com void resetState(); 13910259SAndrew.Bardsley@arm.com 14010259SAndrew.Bardsley@arm.com /** Sets active threads list. */ 14110259SAndrew.Bardsley@arm.com void setActiveThreads(std::list<ThreadID> *at_ptr); 14210259SAndrew.Bardsley@arm.com 14310259SAndrew.Bardsley@arm.com /** Sets the timer buffer between issue and execute. */ 14410259SAndrew.Bardsley@arm.com void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue); 14510259SAndrew.Bardsley@arm.com 14610259SAndrew.Bardsley@arm.com /** Sets the global time buffer. */ 14710259SAndrew.Bardsley@arm.com void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 14810259SAndrew.Bardsley@arm.com 14910259SAndrew.Bardsley@arm.com /** Switches out the instruction queue. */ 15010259SAndrew.Bardsley@arm.com void switchOut(); 15110259SAndrew.Bardsley@arm.com 15210259SAndrew.Bardsley@arm.com /** Takes over execution from another CPU's thread. */ 15310259SAndrew.Bardsley@arm.com void takeOverFrom(); 15410259SAndrew.Bardsley@arm.com 15510259SAndrew.Bardsley@arm.com /** Returns if the IQ is switched out. */ 15610259SAndrew.Bardsley@arm.com bool isSwitchedOut() { return switchedOut; } 15710259SAndrew.Bardsley@arm.com 15810259SAndrew.Bardsley@arm.com /** Number of entries needed for given amount of threads. */ 15910259SAndrew.Bardsley@arm.com int entryAmount(ThreadID num_threads); 16010259SAndrew.Bardsley@arm.com 16110259SAndrew.Bardsley@arm.com /** Resets max entries for all threads. */ 16210259SAndrew.Bardsley@arm.com void resetEntries(); 16310259SAndrew.Bardsley@arm.com 16410259SAndrew.Bardsley@arm.com /** Returns total number of free entries. */ 16510259SAndrew.Bardsley@arm.com unsigned numFreeEntries(); 16610259SAndrew.Bardsley@arm.com 16710259SAndrew.Bardsley@arm.com /** Returns number of free entries for a thread. */ 16810259SAndrew.Bardsley@arm.com unsigned numFreeEntries(ThreadID tid); 16910259SAndrew.Bardsley@arm.com 17010259SAndrew.Bardsley@arm.com /** Returns whether or not the IQ is full. */ 17110259SAndrew.Bardsley@arm.com bool isFull(); 17210259SAndrew.Bardsley@arm.com 17310259SAndrew.Bardsley@arm.com /** Returns whether or not the IQ is full for a specific thread. */ 17410259SAndrew.Bardsley@arm.com bool isFull(ThreadID tid); 17510259SAndrew.Bardsley@arm.com 17610259SAndrew.Bardsley@arm.com /** Returns if there are any ready instructions in the IQ. */ 17710259SAndrew.Bardsley@arm.com bool hasReadyInsts(); 17810259SAndrew.Bardsley@arm.com 17910259SAndrew.Bardsley@arm.com /** Inserts a new instruction into the IQ. */ 18010259SAndrew.Bardsley@arm.com void insert(DynInstPtr &new_inst); 18110259SAndrew.Bardsley@arm.com 18210259SAndrew.Bardsley@arm.com /** Inserts a new, non-speculative instruction into the IQ. */ 18310259SAndrew.Bardsley@arm.com void insertNonSpec(DynInstPtr &new_inst); 18410259SAndrew.Bardsley@arm.com 18510259SAndrew.Bardsley@arm.com /** Inserts a memory or write barrier into the IQ to make sure 18610259SAndrew.Bardsley@arm.com * loads and stores are ordered properly. 18710259SAndrew.Bardsley@arm.com */ 18810259SAndrew.Bardsley@arm.com void insertBarrier(DynInstPtr &barr_inst); 18910259SAndrew.Bardsley@arm.com 19010259SAndrew.Bardsley@arm.com /** Returns the oldest scheduled instruction, and removes it from 19110259SAndrew.Bardsley@arm.com * the list of instructions waiting to execute. 19210259SAndrew.Bardsley@arm.com */ 19310259SAndrew.Bardsley@arm.com DynInstPtr getInstToExecute(); 19410259SAndrew.Bardsley@arm.com 19510259SAndrew.Bardsley@arm.com /** Returns a memory instruction that was referred due to a delayed DTB 19610259SAndrew.Bardsley@arm.com * translation if it is now ready to execute. 19710259SAndrew.Bardsley@arm.com */ 19810259SAndrew.Bardsley@arm.com DynInstPtr getDeferredMemInstToExecute(); 19910259SAndrew.Bardsley@arm.com 20010259SAndrew.Bardsley@arm.com /** 20110259SAndrew.Bardsley@arm.com * Records the instruction as the producer of a register without 20210259SAndrew.Bardsley@arm.com * adding it to the rest of the IQ. 20310259SAndrew.Bardsley@arm.com */ 20410259SAndrew.Bardsley@arm.com void recordProducer(DynInstPtr &inst) 20513954Sgiacomo.gabrielli@arm.com { addToProducers(inst); } 20613954Sgiacomo.gabrielli@arm.com 20713954Sgiacomo.gabrielli@arm.com /** Process FU completion event. */ 20813954Sgiacomo.gabrielli@arm.com void processFUCompletion(DynInstPtr &inst, int fu_idx); 20913954Sgiacomo.gabrielli@arm.com 21013954Sgiacomo.gabrielli@arm.com /** 21113954Sgiacomo.gabrielli@arm.com * Schedules ready instructions, adding the ready ones (oldest first) to 21210259SAndrew.Bardsley@arm.com * the queue to execute. 21310259SAndrew.Bardsley@arm.com */ 21410259SAndrew.Bardsley@arm.com void scheduleReadyInsts(); 21510259SAndrew.Bardsley@arm.com 21610259SAndrew.Bardsley@arm.com /** Schedules a single specific non-speculative instruction. */ 21710259SAndrew.Bardsley@arm.com void scheduleNonSpec(const InstSeqNum &inst); 21810259SAndrew.Bardsley@arm.com 21910259SAndrew.Bardsley@arm.com /** 22010259SAndrew.Bardsley@arm.com * Commits all instructions up to and including the given sequence number, 22110259SAndrew.Bardsley@arm.com * for a specific thread. 22210259SAndrew.Bardsley@arm.com */ 22310259SAndrew.Bardsley@arm.com void commit(const InstSeqNum &inst, ThreadID tid = 0); 22410259SAndrew.Bardsley@arm.com 22510259SAndrew.Bardsley@arm.com /** Wakes all dependents of a completed instruction. */ 22610259SAndrew.Bardsley@arm.com int wakeDependents(DynInstPtr &completed_inst); 22710259SAndrew.Bardsley@arm.com 22810259SAndrew.Bardsley@arm.com /** Adds a ready memory instruction to the ready list. */ 22912104Snathanael.premillieu@arm.com void addReadyMemInst(DynInstPtr &ready_inst); 23010259SAndrew.Bardsley@arm.com 23110259SAndrew.Bardsley@arm.com /** 23210259SAndrew.Bardsley@arm.com * Reschedules a memory instruction. It will be ready to issue once 23310259SAndrew.Bardsley@arm.com * replayMemInst() is called. 23410259SAndrew.Bardsley@arm.com */ 23510259SAndrew.Bardsley@arm.com void rescheduleMemInst(DynInstPtr &resched_inst); 23610259SAndrew.Bardsley@arm.com 23713954Sgiacomo.gabrielli@arm.com /** Replays a memory instruction. It must be rescheduled first. */ 23810259SAndrew.Bardsley@arm.com void replayMemInst(DynInstPtr &replay_inst); 23912420Sgabeblack@google.com 24010259SAndrew.Bardsley@arm.com /** Completes a memory operation. */ 24110259SAndrew.Bardsley@arm.com void completeMemInst(DynInstPtr &completed_inst); 24210259SAndrew.Bardsley@arm.com 24310259SAndrew.Bardsley@arm.com /** 24410259SAndrew.Bardsley@arm.com * Defers a memory instruction when its DTB translation incurs a hw 24510259SAndrew.Bardsley@arm.com * page table walk. 24610259SAndrew.Bardsley@arm.com */ 24710259SAndrew.Bardsley@arm.com void deferMemInst(DynInstPtr &deferred_inst); 24810259SAndrew.Bardsley@arm.com 24910259SAndrew.Bardsley@arm.com /** Indicates an ordering violation between a store and a load. */ 25010259SAndrew.Bardsley@arm.com void violation(DynInstPtr &store, DynInstPtr &faulting_load); 25110259SAndrew.Bardsley@arm.com 25210259SAndrew.Bardsley@arm.com /** 25310259SAndrew.Bardsley@arm.com * Squashes instructions for a thread. Squashing information is obtained 25410259SAndrew.Bardsley@arm.com * from the time buffer. 25510259SAndrew.Bardsley@arm.com */ 25610259SAndrew.Bardsley@arm.com void squash(ThreadID tid); 25710259SAndrew.Bardsley@arm.com 25810259SAndrew.Bardsley@arm.com /** Returns the number of used entries for a thread. */ 25910259SAndrew.Bardsley@arm.com unsigned getCount(ThreadID tid) { return count[tid]; }; 26010259SAndrew.Bardsley@arm.com 26110259SAndrew.Bardsley@arm.com /** Debug function to print all instructions. */ 26210259SAndrew.Bardsley@arm.com void printInsts(); 26310259SAndrew.Bardsley@arm.com 26410259SAndrew.Bardsley@arm.com private: 26510259SAndrew.Bardsley@arm.com /** Does the actual squashing. */ 26610259SAndrew.Bardsley@arm.com void doSquash(ThreadID tid); 26710259SAndrew.Bardsley@arm.com 26810259SAndrew.Bardsley@arm.com ///////////////////////// 26910259SAndrew.Bardsley@arm.com // Various pointers 27010259SAndrew.Bardsley@arm.com ///////////////////////// 27110259SAndrew.Bardsley@arm.com 27210259SAndrew.Bardsley@arm.com /** Pointer to the CPU. */ 27310259SAndrew.Bardsley@arm.com O3CPU *cpu; 27410259SAndrew.Bardsley@arm.com 27510259SAndrew.Bardsley@arm.com /** Cache interface. */ 27613954Sgiacomo.gabrielli@arm.com MemInterface *dcacheInterface; 27713954Sgiacomo.gabrielli@arm.com 27813954Sgiacomo.gabrielli@arm.com /** Pointer to IEW stage. */ 27913954Sgiacomo.gabrielli@arm.com IEW *iewStage; 28013954Sgiacomo.gabrielli@arm.com 28113954Sgiacomo.gabrielli@arm.com /** The memory dependence unit, which tracks/predicts memory dependences 28213954Sgiacomo.gabrielli@arm.com * between instructions. 28313954Sgiacomo.gabrielli@arm.com */ 28410259SAndrew.Bardsley@arm.com MemDepUnit memDepUnit[Impl::MaxThreads]; 28510259SAndrew.Bardsley@arm.com 28610259SAndrew.Bardsley@arm.com /** The queue to the execute stage. Issued instructions will be written 28710259SAndrew.Bardsley@arm.com * into it. 28810259SAndrew.Bardsley@arm.com */ 28910259SAndrew.Bardsley@arm.com TimeBuffer<IssueStruct> *issueToExecuteQueue; 29010259SAndrew.Bardsley@arm.com 29110259SAndrew.Bardsley@arm.com /** The backwards time buffer. */ 29210259SAndrew.Bardsley@arm.com TimeBuffer<TimeStruct> *timeBuffer; 293 294 /** Wire to read information from timebuffer. */ 295 typename TimeBuffer<TimeStruct>::wire fromCommit; 296 297 /** Function unit pool. */ 298 FUPool *fuPool; 299 300 ////////////////////////////////////// 301 // Instruction lists, ready queues, and ordering 302 ////////////////////////////////////// 303 304 /** List of all the instructions in the IQ (some of which may be issued). */ 305 std::list<DynInstPtr> instList[Impl::MaxThreads]; 306 307 /** List of instructions that are ready to be executed. */ 308 std::list<DynInstPtr> instsToExecute; 309 310 /** List of instructions waiting for their DTB translation to 311 * complete (hw page table walk in progress). 312 */ 313 std::list<DynInstPtr> deferredMemInsts; 314 315 /** 316 * Struct for comparing entries to be added to the priority queue. 317 * This gives reverse ordering to the instructions in terms of 318 * sequence numbers: the instructions with smaller sequence 319 * numbers (and hence are older) will be at the top of the 320 * priority queue. 321 */ 322 struct pqCompare { 323 bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const 324 { 325 return lhs->seqNum > rhs->seqNum; 326 } 327 }; 328 329 typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> 330 ReadyInstQueue; 331 332 /** List of ready instructions, per op class. They are separated by op 333 * class to allow for easy mapping to FUs. 334 */ 335 ReadyInstQueue readyInsts[Num_OpClasses]; 336 337 /** List of non-speculative instructions that will be scheduled 338 * once the IQ gets a signal from commit. While it's redundant to 339 * have the key be a part of the value (the sequence number is stored 340 * inside of DynInst), when these instructions are woken up only 341 * the sequence number will be available. Thus it is most efficient to be 342 * able to search by the sequence number alone. 343 */ 344 std::map<InstSeqNum, DynInstPtr> nonSpecInsts; 345 346 typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt; 347 348 /** Entry for the list age ordering by op class. */ 349 struct ListOrderEntry { 350 OpClass queueType; 351 InstSeqNum oldestInst; 352 }; 353 354 /** List that contains the age order of the oldest instruction of each 355 * ready queue. Used to select the oldest instruction available 356 * among op classes. 357 * @todo: Might be better to just move these entries around instead 358 * of creating new ones every time the position changes due to an 359 * instruction issuing. Not sure std::list supports this. 360 */ 361 std::list<ListOrderEntry> listOrder; 362 363 typedef typename std::list<ListOrderEntry>::iterator ListOrderIt; 364 365 /** Tracks if each ready queue is on the age order list. */ 366 bool queueOnList[Num_OpClasses]; 367 368 /** Iterators of each ready queue. Points to their spot in the age order 369 * list. 370 */ 371 ListOrderIt readyIt[Num_OpClasses]; 372 373 /** Add an op class to the age order list. */ 374 void addToOrderList(OpClass op_class); 375 376 /** 377 * Called when the oldest instruction has been removed from a ready queue; 378 * this places that ready queue into the proper spot in the age order list. 379 */ 380 void moveToYoungerInst(ListOrderIt age_order_it); 381 382 DependencyGraph<DynInstPtr> dependGraph; 383 384 ////////////////////////////////////// 385 // Various parameters 386 ////////////////////////////////////// 387 388 /** IQ Resource Sharing Policy */ 389 enum IQPolicy { 390 Dynamic, 391 Partitioned, 392 Threshold 393 }; 394 395 /** IQ sharing policy for SMT. */ 396 IQPolicy iqPolicy; 397 398 /** Number of Total Threads*/ 399 ThreadID numThreads; 400 401 /** Pointer to list of active threads. */ 402 std::list<ThreadID> *activeThreads; 403 404 /** Per Thread IQ count */ 405 unsigned count[Impl::MaxThreads]; 406 407 /** Max IQ Entries Per Thread */ 408 unsigned maxEntries[Impl::MaxThreads]; 409 410 /** Number of free IQ entries left. */ 411 unsigned freeEntries; 412 413 /** The number of entries in the instruction queue. */ 414 unsigned numEntries; 415 416 /** The total number of instructions that can be issued in one cycle. */ 417 unsigned totalWidth; 418 419 /** The number of physical registers in the CPU. */ 420 unsigned numPhysRegs; 421 422 /** The number of physical integer registers in the CPU. */ 423 unsigned numPhysIntRegs; 424 425 /** The number of floating point registers in the CPU. */ 426 unsigned numPhysFloatRegs; 427 428 /** Delay between commit stage and the IQ. 429 * @todo: Make there be a distinction between the delays within IEW. 430 */ 431 unsigned commitToIEWDelay; 432 433 /** Is the IQ switched out. */ 434 bool switchedOut; 435 436 /** The sequence number of the squashed instruction. */ 437 InstSeqNum squashedSeqNum[Impl::MaxThreads]; 438 439 /** A cache of the recently woken registers. It is 1 if the register 440 * has been woken up recently, and 0 if the register has been added 441 * to the dependency graph and has not yet received its value. It 442 * is basically a secondary scoreboard, and should pretty much mirror 443 * the scoreboard that exists in the rename map. 444 */ 445 std::vector<bool> regScoreboard; 446 447 /** Adds an instruction to the dependency graph, as a consumer. */ 448 bool addToDependents(DynInstPtr &new_inst); 449 450 /** Adds an instruction to the dependency graph, as a producer. */ 451 void addToProducers(DynInstPtr &new_inst); 452 453 /** Moves an instruction to the ready queue if it is ready. */ 454 void addIfReady(DynInstPtr &inst); 455 456 /** Debugging function to count how many entries are in the IQ. It does 457 * a linear walk through the instructions, so do not call this function 458 * during normal execution. 459 */ 460 int countInsts(); 461 462 /** Debugging function to dump all the list sizes, as well as print 463 * out the list of nonspeculative instructions. Should not be used 464 * in any other capacity, but it has no harmful sideaffects. 465 */ 466 void dumpLists(); 467 468 /** Debugging function to dump out all instructions that are in the 469 * IQ. 470 */ 471 void dumpInsts(); 472 473 /** Stat for number of instructions added. */ 474 Stats::Scalar iqInstsAdded; 475 /** Stat for number of non-speculative instructions added. */ 476 Stats::Scalar iqNonSpecInstsAdded; 477 478 Stats::Scalar iqInstsIssued; 479 /** Stat for number of integer instructions issued. */ 480 Stats::Scalar iqIntInstsIssued; 481 /** Stat for number of floating point instructions issued. */ 482 Stats::Scalar iqFloatInstsIssued; 483 /** Stat for number of branch instructions issued. */ 484 Stats::Scalar iqBranchInstsIssued; 485 /** Stat for number of memory instructions issued. */ 486 Stats::Scalar iqMemInstsIssued; 487 /** Stat for number of miscellaneous instructions issued. */ 488 Stats::Scalar iqMiscInstsIssued; 489 /** Stat for number of squashed instructions that were ready to issue. */ 490 Stats::Scalar iqSquashedInstsIssued; 491 /** Stat for number of squashed instructions examined when squashing. */ 492 Stats::Scalar iqSquashedInstsExamined; 493 /** Stat for number of squashed instruction operands examined when 494 * squashing. 495 */ 496 Stats::Scalar iqSquashedOperandsExamined; 497 /** Stat for number of non-speculative instructions removed due to a squash. 498 */ 499 Stats::Scalar iqSquashedNonSpecRemoved; 500 // Also include number of instructions rescheduled and replayed. 501 502 /** Distribution of number of instructions in the queue. 503 * @todo: Need to create struct to track the entry time for each 504 * instruction. */ 505// Stats::VectorDistribution queueResDist; 506 /** Distribution of the number of instructions issued. */ 507 Stats::Distribution numIssuedDist; 508 /** Distribution of the cycles it takes to issue an instruction. 509 * @todo: Need to create struct to track the ready time for each 510 * instruction. */ 511// Stats::VectorDistribution issueDelayDist; 512 513 /** Number of times an instruction could not be issued because a 514 * FU was busy. 515 */ 516 Stats::Vector statFuBusy; 517// Stats::Vector dist_unissued; 518 /** Stat for total number issued for each instruction type. */ 519 Stats::Vector2d statIssuedInstType; 520 521 /** Number of instructions issued per cycle. */ 522 Stats::Formula issueRate; 523 524 /** Number of times the FU was busy. */ 525 Stats::Vector fuBusy; 526 /** Number of times the FU was busy per instruction issued. */ 527 Stats::Formula fuBusyRate; 528 public: 529 Stats::Scalar intInstQueueReads; 530 Stats::Scalar intInstQueueWrites; 531 Stats::Scalar intInstQueueWakeupAccesses; 532 Stats::Scalar fpInstQueueReads; 533 Stats::Scalar fpInstQueueWrites; 534 Stats::Scalar fpInstQueueWakeupQccesses; 535 536 Stats::Scalar intAluAccesses; 537 Stats::Scalar fpAluAccesses; 538}; 539 540#endif //__CPU_O3_INST_QUEUE_HH__ 541