inst_queue.hh revision 6216
11689SN/A/*
22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
31689SN/A * All rights reserved.
41689SN/A *
51689SN/A * Redistribution and use in source and binary forms, with or without
61689SN/A * modification, are permitted provided that the following conditions are
71689SN/A * met: redistributions of source code must retain the above copyright
81689SN/A * notice, this list of conditions and the following disclaimer;
91689SN/A * redistributions in binary form must reproduce the above copyright
101689SN/A * notice, this list of conditions and the following disclaimer in the
111689SN/A * documentation and/or other materials provided with the distribution;
121689SN/A * neither the name of the copyright holders nor the names of its
131689SN/A * contributors may be used to endorse or promote products derived from
141689SN/A * this software without specific prior written permission.
151689SN/A *
161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
291689SN/A */
301689SN/A
312292SN/A#ifndef __CPU_O3_INST_QUEUE_HH__
322292SN/A#define __CPU_O3_INST_QUEUE_HH__
331060SN/A
341060SN/A#include <list>
351061SN/A#include <map>
361060SN/A#include <queue>
371061SN/A#include <vector>
381060SN/A
391062SN/A#include "base/statistics.hh"
401060SN/A#include "base/timebuf.hh"
416216Snate@binkert.org#include "base/types.hh"
421061SN/A#include "cpu/inst_seq.hh"
432326SN/A#include "cpu/o3/dep_graph.hh"
442669Sktlim@umich.edu#include "cpu/op_class.hh"
455529Snate@binkert.org#include "sim/eventq.hh"
461060SN/A
475529Snate@binkert.orgclass DerivO3CPUParams;
482292SN/Aclass FUPool;
492292SN/Aclass MemInterface;
502292SN/A
511060SN/A/**
521689SN/A * A standard instruction queue class.  It holds ready instructions, in
531689SN/A * order, in seperate priority queues to facilitate the scheduling of
541689SN/A * instructions.  The IQ uses a separate linked list to track dependencies.
551689SN/A * Similar to the rename map and the free list, it expects that
561060SN/A * floating point registers have their indices start after the integer
571060SN/A * registers (ie with 96 int and 96 fp registers, regs 0-95 are integer
581060SN/A * and 96-191 are fp).  This remains true even for both logical and
592292SN/A * physical register indices. The IQ depends on the memory dependence unit to
602292SN/A * track when memory operations are ready in terms of ordering; register
612292SN/A * dependencies are tracked normally. Right now the IQ also handles the
622292SN/A * execution timing; this is mainly to allow back-to-back scheduling without
632292SN/A * requiring IEW to be able to peek into the IQ. At the end of the execution
642292SN/A * latency, the instruction is put into the queue to execute, where it will
652292SN/A * have the execute() function called on it.
662292SN/A * @todo: Make IQ able to handle multiple FU pools.
671060SN/A */
681061SN/Atemplate <class Impl>
691060SN/Aclass InstructionQueue
701060SN/A{
711060SN/A  public:
721060SN/A    //Typedefs from the Impl.
732733Sktlim@umich.edu    typedef typename Impl::O3CPU O3CPU;
741061SN/A    typedef typename Impl::DynInstPtr DynInstPtr;
751060SN/A
762292SN/A    typedef typename Impl::CPUPol::IEW IEW;
771061SN/A    typedef typename Impl::CPUPol::MemDepUnit MemDepUnit;
781061SN/A    typedef typename Impl::CPUPol::IssueStruct IssueStruct;
791061SN/A    typedef typename Impl::CPUPol::TimeStruct TimeStruct;
801060SN/A
812292SN/A    // Typedef of iterator through the list of instructions.
821061SN/A    typedef typename std::list<DynInstPtr>::iterator ListIt;
831060SN/A
842733Sktlim@umich.edu    friend class Impl::O3CPU;
852292SN/A
862292SN/A    /** FU completion event class. */
872292SN/A    class FUCompletion : public Event {
882292SN/A      private:
892292SN/A        /** Executing instruction. */
902292SN/A        DynInstPtr inst;
912292SN/A
922292SN/A        /** Index of the FU used for executing. */
932292SN/A        int fuIdx;
942292SN/A
952292SN/A        /** Pointer back to the instruction queue. */
962292SN/A        InstructionQueue<Impl> *iqPtr;
972292SN/A
982348SN/A        /** Should the FU be added to the list to be freed upon
992348SN/A         * completing this event.
1002348SN/A         */
1012326SN/A        bool freeFU;
1022326SN/A
1032292SN/A      public:
1042292SN/A        /** Construct a FU completion event. */
1052292SN/A        FUCompletion(DynInstPtr &_inst, int fu_idx,
1062292SN/A                     InstructionQueue<Impl> *iq_ptr);
1072292SN/A
1082292SN/A        virtual void process();
1095336Shines@cs.fsu.edu        virtual const char *description() const;
1102326SN/A        void setFreeFU() { freeFU = true; }
1111060SN/A    };
1121060SN/A
1132292SN/A    /** Constructs an IQ. */
1145529Snate@binkert.org    InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params);
1151061SN/A
1162292SN/A    /** Destructs the IQ. */
1172292SN/A    ~InstructionQueue();
1181061SN/A
1192292SN/A    /** Returns the name of the IQ. */
1202292SN/A    std::string name() const;
1211060SN/A
1222292SN/A    /** Registers statistics. */
1231062SN/A    void regStats();
1241062SN/A
1252348SN/A    /** Resets all instruction queue state. */
1262307SN/A    void resetState();
1271060SN/A
1282292SN/A    /** Sets active threads list. */
1292292SN/A    void setActiveThreads(std::list<unsigned> *at_ptr);
1302292SN/A
1312292SN/A    /** Sets the timer buffer between issue and execute. */
1321060SN/A    void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue);
1331060SN/A
1342292SN/A    /** Sets the global time buffer. */
1351060SN/A    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
1361060SN/A
1372348SN/A    /** Switches out the instruction queue. */
1382307SN/A    void switchOut();
1392307SN/A
1402348SN/A    /** Takes over execution from another CPU's thread. */
1412307SN/A    void takeOverFrom();
1422307SN/A
1432348SN/A    /** Returns if the IQ is switched out. */
1442307SN/A    bool isSwitchedOut() { return switchedOut; }
1452307SN/A
1462292SN/A    /** Number of entries needed for given amount of threads. */
1472292SN/A    int entryAmount(int num_threads);
1482292SN/A
1492292SN/A    /** Resets max entries for all threads. */
1502292SN/A    void resetEntries();
1512292SN/A
1522292SN/A    /** Returns total number of free entries. */
1531060SN/A    unsigned numFreeEntries();
1541060SN/A
1552292SN/A    /** Returns number of free entries for a thread. */
1562292SN/A    unsigned numFreeEntries(unsigned tid);
1572292SN/A
1582292SN/A    /** Returns whether or not the IQ is full. */
1591060SN/A    bool isFull();
1601060SN/A
1612292SN/A    /** Returns whether or not the IQ is full for a specific thread. */
1622292SN/A    bool isFull(unsigned tid);
1632292SN/A
1642292SN/A    /** Returns if there are any ready instructions in the IQ. */
1652292SN/A    bool hasReadyInsts();
1662292SN/A
1672292SN/A    /** Inserts a new instruction into the IQ. */
1681061SN/A    void insert(DynInstPtr &new_inst);
1691060SN/A
1702292SN/A    /** Inserts a new, non-speculative instruction into the IQ. */
1711061SN/A    void insertNonSpec(DynInstPtr &new_inst);
1721061SN/A
1732292SN/A    /** Inserts a memory or write barrier into the IQ to make sure
1742292SN/A     *  loads and stores are ordered properly.
1752292SN/A     */
1762292SN/A    void insertBarrier(DynInstPtr &barr_inst);
1771060SN/A
1782348SN/A    /** Returns the oldest scheduled instruction, and removes it from
1792348SN/A     * the list of instructions waiting to execute.
1802348SN/A     */
1812333SN/A    DynInstPtr getInstToExecute();
1822333SN/A
1832292SN/A    /**
1842326SN/A     * Records the instruction as the producer of a register without
1852326SN/A     * adding it to the rest of the IQ.
1862292SN/A     */
1872326SN/A    void recordProducer(DynInstPtr &inst)
1882326SN/A    { addToProducers(inst); }
1891755SN/A
1902292SN/A    /** Process FU completion event. */
1912292SN/A    void processFUCompletion(DynInstPtr &inst, int fu_idx);
1922292SN/A
1932292SN/A    /**
1942292SN/A     * Schedules ready instructions, adding the ready ones (oldest first) to
1952292SN/A     * the queue to execute.
1962292SN/A     */
1971060SN/A    void scheduleReadyInsts();
1981060SN/A
1992292SN/A    /** Schedules a single specific non-speculative instruction. */
2001061SN/A    void scheduleNonSpec(const InstSeqNum &inst);
2011061SN/A
2022292SN/A    /**
2032292SN/A     * Commits all instructions up to and including the given sequence number,
2042292SN/A     * for a specific thread.
2052292SN/A     */
2062292SN/A    void commit(const InstSeqNum &inst, unsigned tid = 0);
2071061SN/A
2082292SN/A    /** Wakes all dependents of a completed instruction. */
2092301SN/A    int wakeDependents(DynInstPtr &completed_inst);
2101755SN/A
2112292SN/A    /** Adds a ready memory instruction to the ready list. */
2122292SN/A    void addReadyMemInst(DynInstPtr &ready_inst);
2132292SN/A
2142292SN/A    /**
2152292SN/A     * Reschedules a memory instruction. It will be ready to issue once
2162292SN/A     * replayMemInst() is called.
2172292SN/A     */
2182292SN/A    void rescheduleMemInst(DynInstPtr &resched_inst);
2192292SN/A
2202292SN/A    /** Replays a memory instruction. It must be rescheduled first. */
2212292SN/A    void replayMemInst(DynInstPtr &replay_inst);
2222292SN/A
2232292SN/A    /** Completes a memory operation. */
2242292SN/A    void completeMemInst(DynInstPtr &completed_inst);
2252292SN/A
2262292SN/A    /** Indicates an ordering violation between a store and a load. */
2271061SN/A    void violation(DynInstPtr &store, DynInstPtr &faulting_load);
2281061SN/A
2292292SN/A    /**
2302292SN/A     * Squashes instructions for a thread. Squashing information is obtained
2312292SN/A     * from the time buffer.
2322292SN/A     */
2332292SN/A    void squash(unsigned tid);
2341060SN/A
2352292SN/A    /** Returns the number of used entries for a thread. */
2362292SN/A    unsigned getCount(unsigned tid) { return count[tid]; };
2371060SN/A
2382292SN/A    /** Debug function to print all instructions. */
2392292SN/A    void printInsts();
2401060SN/A
2411060SN/A  private:
2422292SN/A    /** Does the actual squashing. */
2432292SN/A    void doSquash(unsigned tid);
2442292SN/A
2452292SN/A    /////////////////////////
2462292SN/A    // Various pointers
2472292SN/A    /////////////////////////
2482292SN/A
2491060SN/A    /** Pointer to the CPU. */
2502733Sktlim@umich.edu    O3CPU *cpu;
2511060SN/A
2522292SN/A    /** Cache interface. */
2532292SN/A    MemInterface *dcacheInterface;
2542292SN/A
2552292SN/A    /** Pointer to IEW stage. */
2562292SN/A    IEW *iewStage;
2572292SN/A
2581061SN/A    /** The memory dependence unit, which tracks/predicts memory dependences
2591061SN/A     *  between instructions.
2601061SN/A     */
2612292SN/A    MemDepUnit memDepUnit[Impl::MaxThreads];
2621061SN/A
2631060SN/A    /** The queue to the execute stage.  Issued instructions will be written
2641060SN/A     *  into it.
2651060SN/A     */
2661060SN/A    TimeBuffer<IssueStruct> *issueToExecuteQueue;
2671060SN/A
2681060SN/A    /** The backwards time buffer. */
2691060SN/A    TimeBuffer<TimeStruct> *timeBuffer;
2701060SN/A
2711060SN/A    /** Wire to read information from timebuffer. */
2721060SN/A    typename TimeBuffer<TimeStruct>::wire fromCommit;
2731060SN/A
2742292SN/A    /** Function unit pool. */
2752292SN/A    FUPool *fuPool;
2762292SN/A
2772292SN/A    //////////////////////////////////////
2782292SN/A    // Instruction lists, ready queues, and ordering
2792292SN/A    //////////////////////////////////////
2802292SN/A
2812292SN/A    /** List of all the instructions in the IQ (some of which may be issued). */
2822292SN/A    std::list<DynInstPtr> instList[Impl::MaxThreads];
2832292SN/A
2842348SN/A    /** List of instructions that are ready to be executed. */
2852333SN/A    std::list<DynInstPtr> instsToExecute;
2862333SN/A
2872292SN/A    /**
2882348SN/A     * Struct for comparing entries to be added to the priority queue.
2892348SN/A     * This gives reverse ordering to the instructions in terms of
2902348SN/A     * sequence numbers: the instructions with smaller sequence
2912348SN/A     * numbers (and hence are older) will be at the top of the
2922348SN/A     * priority queue.
2932292SN/A     */
2942292SN/A    struct pqCompare {
2952292SN/A        bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
2962292SN/A        {
2972292SN/A            return lhs->seqNum > rhs->seqNum;
2982292SN/A        }
2991060SN/A    };
3001060SN/A
3012292SN/A    typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare>
3022292SN/A    ReadyInstQueue;
3031755SN/A
3042292SN/A    /** List of ready instructions, per op class.  They are separated by op
3052292SN/A     *  class to allow for easy mapping to FUs.
3061061SN/A     */
3072292SN/A    ReadyInstQueue readyInsts[Num_OpClasses];
3081061SN/A
3091061SN/A    /** List of non-speculative instructions that will be scheduled
3101061SN/A     *  once the IQ gets a signal from commit.  While it's redundant to
3111061SN/A     *  have the key be a part of the value (the sequence number is stored
3121061SN/A     *  inside of DynInst), when these instructions are woken up only
3131681SN/A     *  the sequence number will be available.  Thus it is most efficient to be
3141061SN/A     *  able to search by the sequence number alone.
3151061SN/A     */
3161061SN/A    std::map<InstSeqNum, DynInstPtr> nonSpecInsts;
3171061SN/A
3182292SN/A    typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt;
3192292SN/A
3202292SN/A    /** Entry for the list age ordering by op class. */
3212292SN/A    struct ListOrderEntry {
3222292SN/A        OpClass queueType;
3232292SN/A        InstSeqNum oldestInst;
3242292SN/A    };
3252292SN/A
3262292SN/A    /** List that contains the age order of the oldest instruction of each
3272292SN/A     *  ready queue.  Used to select the oldest instruction available
3282292SN/A     *  among op classes.
3292326SN/A     *  @todo: Might be better to just move these entries around instead
3302326SN/A     *  of creating new ones every time the position changes due to an
3312326SN/A     *  instruction issuing.  Not sure std::list supports this.
3322292SN/A     */
3332292SN/A    std::list<ListOrderEntry> listOrder;
3342292SN/A
3352292SN/A    typedef typename std::list<ListOrderEntry>::iterator ListOrderIt;
3362292SN/A
3372292SN/A    /** Tracks if each ready queue is on the age order list. */
3382292SN/A    bool queueOnList[Num_OpClasses];
3392292SN/A
3402292SN/A    /** Iterators of each ready queue.  Points to their spot in the age order
3412292SN/A     *  list.
3422292SN/A     */
3432292SN/A    ListOrderIt readyIt[Num_OpClasses];
3442292SN/A
3452292SN/A    /** Add an op class to the age order list. */
3462292SN/A    void addToOrderList(OpClass op_class);
3472292SN/A
3482292SN/A    /**
3492292SN/A     * Called when the oldest instruction has been removed from a ready queue;
3502292SN/A     * this places that ready queue into the proper spot in the age order list.
3512292SN/A     */
3522292SN/A    void moveToYoungerInst(ListOrderIt age_order_it);
3532292SN/A
3542326SN/A    DependencyGraph<DynInstPtr> dependGraph;
3552326SN/A
3562292SN/A    //////////////////////////////////////
3572292SN/A    // Various parameters
3582292SN/A    //////////////////////////////////////
3592292SN/A
3602292SN/A    /** IQ Resource Sharing Policy */
3612292SN/A    enum IQPolicy {
3622292SN/A        Dynamic,
3632292SN/A        Partitioned,
3642292SN/A        Threshold
3652292SN/A    };
3662292SN/A
3672292SN/A    /** IQ sharing policy for SMT. */
3682292SN/A    IQPolicy iqPolicy;
3692292SN/A
3702292SN/A    /** Number of Total Threads*/
3712292SN/A    unsigned numThreads;
3722292SN/A
3732292SN/A    /** Pointer to list of active threads. */
3742292SN/A    std::list<unsigned> *activeThreads;
3752292SN/A
3762292SN/A    /** Per Thread IQ count */
3772292SN/A    unsigned count[Impl::MaxThreads];
3782292SN/A
3792292SN/A    /** Max IQ Entries Per Thread */
3802292SN/A    unsigned maxEntries[Impl::MaxThreads];
3811060SN/A
3821060SN/A    /** Number of free IQ entries left. */
3831060SN/A    unsigned freeEntries;
3841060SN/A
3851060SN/A    /** The number of entries in the instruction queue. */
3861060SN/A    unsigned numEntries;
3871060SN/A
3881060SN/A    /** The total number of instructions that can be issued in one cycle. */
3891060SN/A    unsigned totalWidth;
3901060SN/A
3912292SN/A    /** The number of physical registers in the CPU. */
3921060SN/A    unsigned numPhysRegs;
3931060SN/A
3941060SN/A    /** The number of physical integer registers in the CPU. */
3951060SN/A    unsigned numPhysIntRegs;
3961060SN/A
3971060SN/A    /** The number of floating point registers in the CPU. */
3981060SN/A    unsigned numPhysFloatRegs;
3991060SN/A
4001060SN/A    /** Delay between commit stage and the IQ.
4011060SN/A     *  @todo: Make there be a distinction between the delays within IEW.
4021060SN/A     */
4031060SN/A    unsigned commitToIEWDelay;
4041060SN/A
4052348SN/A    /** Is the IQ switched out. */
4062307SN/A    bool switchedOut;
4071060SN/A
4081060SN/A    /** The sequence number of the squashed instruction. */
4092292SN/A    InstSeqNum squashedSeqNum[Impl::MaxThreads];
4101060SN/A
4111060SN/A    /** A cache of the recently woken registers.  It is 1 if the register
4121060SN/A     *  has been woken up recently, and 0 if the register has been added
4131060SN/A     *  to the dependency graph and has not yet received its value.  It
4141060SN/A     *  is basically a secondary scoreboard, and should pretty much mirror
4151060SN/A     *  the scoreboard that exists in the rename map.
4161060SN/A     */
4172292SN/A    std::vector<bool> regScoreboard;
4181060SN/A
4192326SN/A    /** Adds an instruction to the dependency graph, as a consumer. */
4201061SN/A    bool addToDependents(DynInstPtr &new_inst);
4211684SN/A
4222326SN/A    /** Adds an instruction to the dependency graph, as a producer. */
4232326SN/A    void addToProducers(DynInstPtr &new_inst);
4241755SN/A
4252292SN/A    /** Moves an instruction to the ready queue if it is ready. */
4261684SN/A    void addIfReady(DynInstPtr &inst);
4271684SN/A
4281684SN/A    /** Debugging function to count how many entries are in the IQ.  It does
4291684SN/A     *  a linear walk through the instructions, so do not call this function
4301684SN/A     *  during normal execution.
4311684SN/A     */
4321684SN/A    int countInsts();
4331684SN/A
4341684SN/A    /** Debugging function to dump all the list sizes, as well as print
4351684SN/A     *  out the list of nonspeculative instructions.  Should not be used
4361684SN/A     *  in any other capacity, but it has no harmful sideaffects.
4371684SN/A     */
4381684SN/A    void dumpLists();
4391062SN/A
4402292SN/A    /** Debugging function to dump out all instructions that are in the
4412292SN/A     *  IQ.
4422292SN/A     */
4432292SN/A    void dumpInsts();
4442292SN/A
4452292SN/A    /** Stat for number of instructions added. */
4465999Snate@binkert.org    Stats::Scalar iqInstsAdded;
4472292SN/A    /** Stat for number of non-speculative instructions added. */
4485999Snate@binkert.org    Stats::Scalar iqNonSpecInstsAdded;
4492326SN/A
4505999Snate@binkert.org    Stats::Scalar iqInstsIssued;
4512292SN/A    /** Stat for number of integer instructions issued. */
4525999Snate@binkert.org    Stats::Scalar iqIntInstsIssued;
4532292SN/A    /** Stat for number of floating point instructions issued. */
4545999Snate@binkert.org    Stats::Scalar iqFloatInstsIssued;
4552292SN/A    /** Stat for number of branch instructions issued. */
4565999Snate@binkert.org    Stats::Scalar iqBranchInstsIssued;
4572292SN/A    /** Stat for number of memory instructions issued. */
4585999Snate@binkert.org    Stats::Scalar iqMemInstsIssued;
4592292SN/A    /** Stat for number of miscellaneous instructions issued. */
4605999Snate@binkert.org    Stats::Scalar iqMiscInstsIssued;
4612292SN/A    /** Stat for number of squashed instructions that were ready to issue. */
4625999Snate@binkert.org    Stats::Scalar iqSquashedInstsIssued;
4632292SN/A    /** Stat for number of squashed instructions examined when squashing. */
4645999Snate@binkert.org    Stats::Scalar iqSquashedInstsExamined;
4652292SN/A    /** Stat for number of squashed instruction operands examined when
4662292SN/A     * squashing.
4672292SN/A     */
4685999Snate@binkert.org    Stats::Scalar iqSquashedOperandsExamined;
4692292SN/A    /** Stat for number of non-speculative instructions removed due to a squash.
4702292SN/A     */
4715999Snate@binkert.org    Stats::Scalar iqSquashedNonSpecRemoved;
4722727Sktlim@umich.edu    // Also include number of instructions rescheduled and replayed.
4731062SN/A
4742727Sktlim@umich.edu    /** Distribution of number of instructions in the queue.
4752727Sktlim@umich.edu     * @todo: Need to create struct to track the entry time for each
4762727Sktlim@umich.edu     * instruction. */
4775999Snate@binkert.org//    Stats::VectorDistribution queueResDist;
4782348SN/A    /** Distribution of the number of instructions issued. */
4795999Snate@binkert.org    Stats::Distribution numIssuedDist;
4802727Sktlim@umich.edu    /** Distribution of the cycles it takes to issue an instruction.
4812727Sktlim@umich.edu     * @todo: Need to create struct to track the ready time for each
4822727Sktlim@umich.edu     * instruction. */
4835999Snate@binkert.org//    Stats::VectorDistribution issueDelayDist;
4842301SN/A
4852348SN/A    /** Number of times an instruction could not be issued because a
4862348SN/A     * FU was busy.
4872348SN/A     */
4885999Snate@binkert.org    Stats::Vector statFuBusy;
4895999Snate@binkert.org//    Stats::Vector dist_unissued;
4902348SN/A    /** Stat for total number issued for each instruction type. */
4915999Snate@binkert.org    Stats::Vector2d statIssuedInstType;
4922301SN/A
4932348SN/A    /** Number of instructions issued per cycle. */
4942326SN/A    Stats::Formula issueRate;
4952727Sktlim@umich.edu
4962348SN/A    /** Number of times the FU was busy. */
4975999Snate@binkert.org    Stats::Vector fuBusy;
4982348SN/A    /** Number of times the FU was busy per instruction issued. */
4992326SN/A    Stats::Formula fuBusyRate;
5001060SN/A};
5011060SN/A
5022292SN/A#endif //__CPU_O3_INST_QUEUE_HH__
503