inst_queue.hh revision 2333
112137Sar4jc@virginia.edu/* 212137Sar4jc@virginia.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 312137Sar4jc@virginia.edu * All rights reserved. 412137Sar4jc@virginia.edu * 512137Sar4jc@virginia.edu * Redistribution and use in source and binary forms, with or without 612137Sar4jc@virginia.edu * modification, are permitted provided that the following conditions are 712137Sar4jc@virginia.edu * met: redistributions of source code must retain the above copyright 812137Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer; 912137Sar4jc@virginia.edu * redistributions in binary form must reproduce the above copyright 1012137Sar4jc@virginia.edu * notice, this list of conditions and the following disclaimer in the 1112137Sar4jc@virginia.edu * documentation and/or other materials provided with the distribution; 1212137Sar4jc@virginia.edu * neither the name of the copyright holders nor the names of its 1312137Sar4jc@virginia.edu * contributors may be used to endorse or promote products derived from 1412137Sar4jc@virginia.edu * this software without specific prior written permission. 1512137Sar4jc@virginia.edu * 1612137Sar4jc@virginia.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712137Sar4jc@virginia.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812137Sar4jc@virginia.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912137Sar4jc@virginia.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012137Sar4jc@virginia.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112137Sar4jc@virginia.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212137Sar4jc@virginia.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312137Sar4jc@virginia.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412137Sar4jc@virginia.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512137Sar4jc@virginia.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612137Sar4jc@virginia.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712137Sar4jc@virginia.edu */ 2812137Sar4jc@virginia.edu 2912137Sar4jc@virginia.edu#ifndef __CPU_O3_INST_QUEUE_HH__ 3012137Sar4jc@virginia.edu#define __CPU_O3_INST_QUEUE_HH__ 3112137Sar4jc@virginia.edu 3212137Sar4jc@virginia.edu#include <list> 3312137Sar4jc@virginia.edu#include <map> 3412137Sar4jc@virginia.edu#include <queue> 3512137Sar4jc@virginia.edu#include <vector> 3612137Sar4jc@virginia.edu 3712137Sar4jc@virginia.edu#include "base/statistics.hh" 3812137Sar4jc@virginia.edu#include "base/timebuf.hh" 3912137Sar4jc@virginia.edu#include "cpu/inst_seq.hh" 4012137Sar4jc@virginia.edu#include "cpu/o3/dep_graph.hh" 4112137Sar4jc@virginia.edu#include "encumbered/cpu/full/op_class.hh" 4212137Sar4jc@virginia.edu#include "sim/host.hh" 4312137Sar4jc@virginia.edu 4412137Sar4jc@virginia.educlass FUPool; 4512137Sar4jc@virginia.educlass MemInterface; 4612137Sar4jc@virginia.edu 4712137Sar4jc@virginia.edu/** 4812137Sar4jc@virginia.edu * A standard instruction queue class. It holds ready instructions, in 4912137Sar4jc@virginia.edu * order, in seperate priority queues to facilitate the scheduling of 5012137Sar4jc@virginia.edu * instructions. The IQ uses a separate linked list to track dependencies. 5112137Sar4jc@virginia.edu * Similar to the rename map and the free list, it expects that 5212137Sar4jc@virginia.edu * floating point registers have their indices start after the integer 5312137Sar4jc@virginia.edu * registers (ie with 96 int and 96 fp registers, regs 0-95 are integer 5412137Sar4jc@virginia.edu * and 96-191 are fp). This remains true even for both logical and 5512137Sar4jc@virginia.edu * physical register indices. The IQ depends on the memory dependence unit to 5612137Sar4jc@virginia.edu * track when memory operations are ready in terms of ordering; register 5712137Sar4jc@virginia.edu * dependencies are tracked normally. Right now the IQ also handles the 5812137Sar4jc@virginia.edu * execution timing; this is mainly to allow back-to-back scheduling without 5912137Sar4jc@virginia.edu * requiring IEW to be able to peek into the IQ. At the end of the execution 6012137Sar4jc@virginia.edu * latency, the instruction is put into the queue to execute, where it will 6112137Sar4jc@virginia.edu * have the execute() function called on it. 6212137Sar4jc@virginia.edu * @todo: Make IQ able to handle multiple FU pools. 6312137Sar4jc@virginia.edu */ 6412137Sar4jc@virginia.edutemplate <class Impl> 6512137Sar4jc@virginia.educlass InstructionQueue 6612137Sar4jc@virginia.edu{ 6712137Sar4jc@virginia.edu public: 6812137Sar4jc@virginia.edu //Typedefs from the Impl. 6912137Sar4jc@virginia.edu typedef typename Impl::FullCPU FullCPU; 7012137Sar4jc@virginia.edu typedef typename Impl::DynInstPtr DynInstPtr; 7112137Sar4jc@virginia.edu typedef typename Impl::Params Params; 7212137Sar4jc@virginia.edu 7312137Sar4jc@virginia.edu typedef typename Impl::CPUPol::IEW IEW; 7412137Sar4jc@virginia.edu typedef typename Impl::CPUPol::MemDepUnit MemDepUnit; 7512137Sar4jc@virginia.edu typedef typename Impl::CPUPol::IssueStruct IssueStruct; 7612137Sar4jc@virginia.edu typedef typename Impl::CPUPol::TimeStruct TimeStruct; 7712137Sar4jc@virginia.edu 7812137Sar4jc@virginia.edu // Typedef of iterator through the list of instructions. 7912137Sar4jc@virginia.edu typedef typename std::list<DynInstPtr>::iterator ListIt; 8012137Sar4jc@virginia.edu 8112137Sar4jc@virginia.edu friend class Impl::FullCPU; 8212137Sar4jc@virginia.edu 8312137Sar4jc@virginia.edu /** FU completion event class. */ 8412137Sar4jc@virginia.edu class FUCompletion : public Event { 8512137Sar4jc@virginia.edu private: 8612137Sar4jc@virginia.edu /** Executing instruction. */ 8712137Sar4jc@virginia.edu DynInstPtr inst; 8812137Sar4jc@virginia.edu 8912137Sar4jc@virginia.edu /** Index of the FU used for executing. */ 9012137Sar4jc@virginia.edu int fuIdx; 9112137Sar4jc@virginia.edu 9212137Sar4jc@virginia.edu /** Pointer back to the instruction queue. */ 9312137Sar4jc@virginia.edu InstructionQueue<Impl> *iqPtr; 9412137Sar4jc@virginia.edu 9512137Sar4jc@virginia.edu bool freeFU; 9612137Sar4jc@virginia.edu 9712137Sar4jc@virginia.edu public: 9812137Sar4jc@virginia.edu /** Construct a FU completion event. */ 9912137Sar4jc@virginia.edu FUCompletion(DynInstPtr &_inst, int fu_idx, 10012137Sar4jc@virginia.edu InstructionQueue<Impl> *iq_ptr); 10112137Sar4jc@virginia.edu 10212137Sar4jc@virginia.edu virtual void process(); 10312137Sar4jc@virginia.edu virtual const char *description(); 10412137Sar4jc@virginia.edu void setFreeFU() { freeFU = true; } 10512137Sar4jc@virginia.edu }; 10612137Sar4jc@virginia.edu 10712137Sar4jc@virginia.edu /** Constructs an IQ. */ 10812137Sar4jc@virginia.edu InstructionQueue(Params *params); 10912137Sar4jc@virginia.edu 11012137Sar4jc@virginia.edu /** Destructs the IQ. */ 11112137Sar4jc@virginia.edu ~InstructionQueue(); 11212137Sar4jc@virginia.edu 11312137Sar4jc@virginia.edu /** Returns the name of the IQ. */ 11412137Sar4jc@virginia.edu std::string name() const; 11512137Sar4jc@virginia.edu 11612137Sar4jc@virginia.edu /** Registers statistics. */ 11712137Sar4jc@virginia.edu void regStats(); 11812137Sar4jc@virginia.edu 11912137Sar4jc@virginia.edu void resetState(); 12012137Sar4jc@virginia.edu 12112137Sar4jc@virginia.edu /** Sets CPU pointer. */ 12212137Sar4jc@virginia.edu void setCPU(FullCPU *_cpu) { cpu = _cpu; } 12312137Sar4jc@virginia.edu 12412137Sar4jc@virginia.edu /** Sets active threads list. */ 12512137Sar4jc@virginia.edu void setActiveThreads(std::list<unsigned> *at_ptr); 12612137Sar4jc@virginia.edu 12712137Sar4jc@virginia.edu /** Sets the IEW pointer. */ 12812137Sar4jc@virginia.edu void setIEW(IEW *iew_ptr) { iewStage = iew_ptr; } 12912137Sar4jc@virginia.edu 13012137Sar4jc@virginia.edu /** Sets the timer buffer between issue and execute. */ 13112137Sar4jc@virginia.edu void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue); 13212137Sar4jc@virginia.edu 13312137Sar4jc@virginia.edu /** Sets the global time buffer. */ 13412137Sar4jc@virginia.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 13512137Sar4jc@virginia.edu 13612137Sar4jc@virginia.edu void switchOut(); 13712137Sar4jc@virginia.edu 13812137Sar4jc@virginia.edu void takeOverFrom(); 13912137Sar4jc@virginia.edu 14012137Sar4jc@virginia.edu bool isSwitchedOut() { return switchedOut; } 14112137Sar4jc@virginia.edu 14212137Sar4jc@virginia.edu /** Number of entries needed for given amount of threads. */ 14312137Sar4jc@virginia.edu int entryAmount(int num_threads); 14412137Sar4jc@virginia.edu 14512137Sar4jc@virginia.edu /** Resets max entries for all threads. */ 14612137Sar4jc@virginia.edu void resetEntries(); 14712137Sar4jc@virginia.edu 14812137Sar4jc@virginia.edu /** Returns total number of free entries. */ 14912137Sar4jc@virginia.edu unsigned numFreeEntries(); 15012137Sar4jc@virginia.edu 15112137Sar4jc@virginia.edu /** Returns number of free entries for a thread. */ 15212137Sar4jc@virginia.edu unsigned numFreeEntries(unsigned tid); 15312137Sar4jc@virginia.edu 15412137Sar4jc@virginia.edu /** Returns whether or not the IQ is full. */ 15512137Sar4jc@virginia.edu bool isFull(); 15612137Sar4jc@virginia.edu 15712137Sar4jc@virginia.edu /** Returns whether or not the IQ is full for a specific thread. */ 15812137Sar4jc@virginia.edu bool isFull(unsigned tid); 15912137Sar4jc@virginia.edu 16012137Sar4jc@virginia.edu /** Returns if there are any ready instructions in the IQ. */ 16112137Sar4jc@virginia.edu bool hasReadyInsts(); 16212137Sar4jc@virginia.edu 16312137Sar4jc@virginia.edu /** Inserts a new instruction into the IQ. */ 16412137Sar4jc@virginia.edu void insert(DynInstPtr &new_inst); 16512137Sar4jc@virginia.edu 16612137Sar4jc@virginia.edu /** Inserts a new, non-speculative instruction into the IQ. */ 16712137Sar4jc@virginia.edu void insertNonSpec(DynInstPtr &new_inst); 16812137Sar4jc@virginia.edu 16912137Sar4jc@virginia.edu /** Inserts a memory or write barrier into the IQ to make sure 17012137Sar4jc@virginia.edu * loads and stores are ordered properly. 17112137Sar4jc@virginia.edu */ 17212137Sar4jc@virginia.edu void insertBarrier(DynInstPtr &barr_inst); 17312137Sar4jc@virginia.edu 17412137Sar4jc@virginia.edu DynInstPtr getInstToExecute(); 17512137Sar4jc@virginia.edu 17612137Sar4jc@virginia.edu /** 17712137Sar4jc@virginia.edu * Records the instruction as the producer of a register without 17812137Sar4jc@virginia.edu * adding it to the rest of the IQ. 17912137Sar4jc@virginia.edu */ 18012137Sar4jc@virginia.edu void recordProducer(DynInstPtr &inst) 18112137Sar4jc@virginia.edu { addToProducers(inst); } 18212137Sar4jc@virginia.edu 18312137Sar4jc@virginia.edu /** Process FU completion event. */ 18412137Sar4jc@virginia.edu void processFUCompletion(DynInstPtr &inst, int fu_idx); 18512137Sar4jc@virginia.edu 18612137Sar4jc@virginia.edu /** 18712137Sar4jc@virginia.edu * Schedules ready instructions, adding the ready ones (oldest first) to 18812137Sar4jc@virginia.edu * the queue to execute. 18912137Sar4jc@virginia.edu */ 19012137Sar4jc@virginia.edu void scheduleReadyInsts(); 19112137Sar4jc@virginia.edu 19212137Sar4jc@virginia.edu /** Schedules a single specific non-speculative instruction. */ 19312137Sar4jc@virginia.edu void scheduleNonSpec(const InstSeqNum &inst); 19412137Sar4jc@virginia.edu 19512137Sar4jc@virginia.edu /** 19612137Sar4jc@virginia.edu * Commits all instructions up to and including the given sequence number, 19712137Sar4jc@virginia.edu * for a specific thread. 19812137Sar4jc@virginia.edu */ 19912137Sar4jc@virginia.edu void commit(const InstSeqNum &inst, unsigned tid = 0); 20012137Sar4jc@virginia.edu 20112137Sar4jc@virginia.edu /** Wakes all dependents of a completed instruction. */ 20212137Sar4jc@virginia.edu int wakeDependents(DynInstPtr &completed_inst); 20312137Sar4jc@virginia.edu 20412137Sar4jc@virginia.edu /** Adds a ready memory instruction to the ready list. */ 20512137Sar4jc@virginia.edu void addReadyMemInst(DynInstPtr &ready_inst); 20612137Sar4jc@virginia.edu 20712137Sar4jc@virginia.edu /** 20812137Sar4jc@virginia.edu * Reschedules a memory instruction. It will be ready to issue once 20912137Sar4jc@virginia.edu * replayMemInst() is called. 21012137Sar4jc@virginia.edu */ 21112137Sar4jc@virginia.edu void rescheduleMemInst(DynInstPtr &resched_inst); 21212137Sar4jc@virginia.edu 21312137Sar4jc@virginia.edu /** Replays a memory instruction. It must be rescheduled first. */ 21412137Sar4jc@virginia.edu void replayMemInst(DynInstPtr &replay_inst); 21512137Sar4jc@virginia.edu 21612137Sar4jc@virginia.edu /** Completes a memory operation. */ 21712137Sar4jc@virginia.edu void completeMemInst(DynInstPtr &completed_inst); 21812137Sar4jc@virginia.edu 21912137Sar4jc@virginia.edu /** Indicates an ordering violation between a store and a load. */ 22012137Sar4jc@virginia.edu void violation(DynInstPtr &store, DynInstPtr &faulting_load); 22112137Sar4jc@virginia.edu 22212137Sar4jc@virginia.edu /** 22312137Sar4jc@virginia.edu * Squashes instructions for a thread. Squashing information is obtained 22412137Sar4jc@virginia.edu * from the time buffer. 22512137Sar4jc@virginia.edu */ 22612137Sar4jc@virginia.edu void squash(unsigned tid); 22712137Sar4jc@virginia.edu 22812137Sar4jc@virginia.edu /** Returns the number of used entries for a thread. */ 22912137Sar4jc@virginia.edu unsigned getCount(unsigned tid) { return count[tid]; }; 23012137Sar4jc@virginia.edu 23112137Sar4jc@virginia.edu /** Debug function to print all instructions. */ 23212137Sar4jc@virginia.edu void printInsts(); 23312137Sar4jc@virginia.edu 23412137Sar4jc@virginia.edu private: 23512137Sar4jc@virginia.edu /** Does the actual squashing. */ 23612137Sar4jc@virginia.edu void doSquash(unsigned tid); 23712137Sar4jc@virginia.edu 23812137Sar4jc@virginia.edu ///////////////////////// 23912137Sar4jc@virginia.edu // Various pointers 24012137Sar4jc@virginia.edu ///////////////////////// 24112137Sar4jc@virginia.edu 24212137Sar4jc@virginia.edu /** Pointer to the CPU. */ 24312137Sar4jc@virginia.edu FullCPU *cpu; 24412137Sar4jc@virginia.edu 24512137Sar4jc@virginia.edu /** Cache interface. */ 24612137Sar4jc@virginia.edu MemInterface *dcacheInterface; 24712137Sar4jc@virginia.edu 24812137Sar4jc@virginia.edu /** Pointer to IEW stage. */ 24912137Sar4jc@virginia.edu IEW *iewStage; 25012137Sar4jc@virginia.edu 25112137Sar4jc@virginia.edu /** The memory dependence unit, which tracks/predicts memory dependences 25212137Sar4jc@virginia.edu * between instructions. 25312137Sar4jc@virginia.edu */ 25412137Sar4jc@virginia.edu MemDepUnit memDepUnit[Impl::MaxThreads]; 25512137Sar4jc@virginia.edu 25612137Sar4jc@virginia.edu /** The queue to the execute stage. Issued instructions will be written 25712137Sar4jc@virginia.edu * into it. 25812137Sar4jc@virginia.edu */ 25912137Sar4jc@virginia.edu TimeBuffer<IssueStruct> *issueToExecuteQueue; 26012137Sar4jc@virginia.edu 26112137Sar4jc@virginia.edu /** The backwards time buffer. */ 26212137Sar4jc@virginia.edu TimeBuffer<TimeStruct> *timeBuffer; 26312137Sar4jc@virginia.edu 26412137Sar4jc@virginia.edu /** Wire to read information from timebuffer. */ 26512137Sar4jc@virginia.edu typename TimeBuffer<TimeStruct>::wire fromCommit; 26612137Sar4jc@virginia.edu 26712137Sar4jc@virginia.edu /** Function unit pool. */ 26812137Sar4jc@virginia.edu FUPool *fuPool; 26912137Sar4jc@virginia.edu 27012137Sar4jc@virginia.edu ////////////////////////////////////// 27112137Sar4jc@virginia.edu // Instruction lists, ready queues, and ordering 27212137Sar4jc@virginia.edu ////////////////////////////////////// 27312137Sar4jc@virginia.edu 27412137Sar4jc@virginia.edu /** List of all the instructions in the IQ (some of which may be issued). */ 27512137Sar4jc@virginia.edu std::list<DynInstPtr> instList[Impl::MaxThreads]; 27612137Sar4jc@virginia.edu 27712137Sar4jc@virginia.edu std::list<DynInstPtr> instsToExecute; 27812137Sar4jc@virginia.edu 27912137Sar4jc@virginia.edu /** 28012137Sar4jc@virginia.edu * Struct for comparing entries to be added to the priority queue. This 28112137Sar4jc@virginia.edu * gives reverse ordering to the instructions in terms of sequence 28212137Sar4jc@virginia.edu * numbers: the instructions with smaller sequence numbers (and hence 28312137Sar4jc@virginia.edu * are older) will be at the top of the priority queue. 28412137Sar4jc@virginia.edu */ 28512137Sar4jc@virginia.edu struct pqCompare { 28612137Sar4jc@virginia.edu bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const 28712137Sar4jc@virginia.edu { 28812137Sar4jc@virginia.edu return lhs->seqNum > rhs->seqNum; 28912137Sar4jc@virginia.edu } 29012137Sar4jc@virginia.edu }; 29112137Sar4jc@virginia.edu 29212137Sar4jc@virginia.edu typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> 29312137Sar4jc@virginia.edu ReadyInstQueue; 29412137Sar4jc@virginia.edu 29512137Sar4jc@virginia.edu /** List of ready instructions, per op class. They are separated by op 29612137Sar4jc@virginia.edu * class to allow for easy mapping to FUs. 29712137Sar4jc@virginia.edu */ 29812137Sar4jc@virginia.edu ReadyInstQueue readyInsts[Num_OpClasses]; 29912137Sar4jc@virginia.edu 30012137Sar4jc@virginia.edu /** List of non-speculative instructions that will be scheduled 30112137Sar4jc@virginia.edu * once the IQ gets a signal from commit. While it's redundant to 30212137Sar4jc@virginia.edu * have the key be a part of the value (the sequence number is stored 30312137Sar4jc@virginia.edu * inside of DynInst), when these instructions are woken up only 30412137Sar4jc@virginia.edu * the sequence number will be available. Thus it is most efficient to be 30512137Sar4jc@virginia.edu * able to search by the sequence number alone. 30612137Sar4jc@virginia.edu */ 30712137Sar4jc@virginia.edu std::map<InstSeqNum, DynInstPtr> nonSpecInsts; 30812137Sar4jc@virginia.edu 30912137Sar4jc@virginia.edu typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt; 31012137Sar4jc@virginia.edu 31112137Sar4jc@virginia.edu /** Entry for the list age ordering by op class. */ 31212137Sar4jc@virginia.edu struct ListOrderEntry { 31312137Sar4jc@virginia.edu OpClass queueType; 31412137Sar4jc@virginia.edu InstSeqNum oldestInst; 31512137Sar4jc@virginia.edu }; 31612137Sar4jc@virginia.edu 31712137Sar4jc@virginia.edu /** List that contains the age order of the oldest instruction of each 31812137Sar4jc@virginia.edu * ready queue. Used to select the oldest instruction available 31912137Sar4jc@virginia.edu * among op classes. 32012137Sar4jc@virginia.edu * @todo: Might be better to just move these entries around instead 32112137Sar4jc@virginia.edu * of creating new ones every time the position changes due to an 32212137Sar4jc@virginia.edu * instruction issuing. Not sure std::list supports this. 32312137Sar4jc@virginia.edu */ 32412137Sar4jc@virginia.edu std::list<ListOrderEntry> listOrder; 32512137Sar4jc@virginia.edu 32612137Sar4jc@virginia.edu typedef typename std::list<ListOrderEntry>::iterator ListOrderIt; 32712137Sar4jc@virginia.edu 32812137Sar4jc@virginia.edu /** Tracks if each ready queue is on the age order list. */ 32912137Sar4jc@virginia.edu bool queueOnList[Num_OpClasses]; 33012137Sar4jc@virginia.edu 33112137Sar4jc@virginia.edu /** Iterators of each ready queue. Points to their spot in the age order 33212137Sar4jc@virginia.edu * list. 33312137Sar4jc@virginia.edu */ 33412137Sar4jc@virginia.edu ListOrderIt readyIt[Num_OpClasses]; 33512137Sar4jc@virginia.edu 33612137Sar4jc@virginia.edu /** Add an op class to the age order list. */ 33712137Sar4jc@virginia.edu void addToOrderList(OpClass op_class); 33812137Sar4jc@virginia.edu 33912137Sar4jc@virginia.edu /** 34012137Sar4jc@virginia.edu * Called when the oldest instruction has been removed from a ready queue; 34112137Sar4jc@virginia.edu * this places that ready queue into the proper spot in the age order list. 34212137Sar4jc@virginia.edu */ 34312137Sar4jc@virginia.edu void moveToYoungerInst(ListOrderIt age_order_it); 34412137Sar4jc@virginia.edu 34512137Sar4jc@virginia.edu DependencyGraph<DynInstPtr> dependGraph; 34612137Sar4jc@virginia.edu 34712137Sar4jc@virginia.edu ////////////////////////////////////// 34812137Sar4jc@virginia.edu // Various parameters 34912137Sar4jc@virginia.edu ////////////////////////////////////// 35012137Sar4jc@virginia.edu 35112137Sar4jc@virginia.edu /** IQ Resource Sharing Policy */ 35212137Sar4jc@virginia.edu enum IQPolicy { 35312137Sar4jc@virginia.edu Dynamic, 35412137Sar4jc@virginia.edu Partitioned, 35512137Sar4jc@virginia.edu Threshold 35612137Sar4jc@virginia.edu }; 35712137Sar4jc@virginia.edu 35812137Sar4jc@virginia.edu /** IQ sharing policy for SMT. */ 35912137Sar4jc@virginia.edu IQPolicy iqPolicy; 36012137Sar4jc@virginia.edu 36112137Sar4jc@virginia.edu /** Number of Total Threads*/ 36212137Sar4jc@virginia.edu unsigned numThreads; 36312137Sar4jc@virginia.edu 36412137Sar4jc@virginia.edu /** Pointer to list of active threads. */ 36512137Sar4jc@virginia.edu std::list<unsigned> *activeThreads; 36612137Sar4jc@virginia.edu 36712137Sar4jc@virginia.edu /** Per Thread IQ count */ 36812137Sar4jc@virginia.edu unsigned count[Impl::MaxThreads]; 36912137Sar4jc@virginia.edu 37012137Sar4jc@virginia.edu /** Max IQ Entries Per Thread */ 37112137Sar4jc@virginia.edu unsigned maxEntries[Impl::MaxThreads]; 37212137Sar4jc@virginia.edu 37312137Sar4jc@virginia.edu /** Number of free IQ entries left. */ 37412137Sar4jc@virginia.edu unsigned freeEntries; 37512137Sar4jc@virginia.edu 37612137Sar4jc@virginia.edu /** The number of entries in the instruction queue. */ 37712137Sar4jc@virginia.edu unsigned numEntries; 37812137Sar4jc@virginia.edu 37912137Sar4jc@virginia.edu /** The total number of instructions that can be issued in one cycle. */ 38012137Sar4jc@virginia.edu unsigned totalWidth; 38112137Sar4jc@virginia.edu 38212137Sar4jc@virginia.edu /** The number of physical registers in the CPU. */ 38312137Sar4jc@virginia.edu unsigned numPhysRegs; 38412137Sar4jc@virginia.edu 38512137Sar4jc@virginia.edu /** The number of physical integer registers in the CPU. */ 38612137Sar4jc@virginia.edu unsigned numPhysIntRegs; 38712137Sar4jc@virginia.edu 38812137Sar4jc@virginia.edu /** The number of floating point registers in the CPU. */ 38912137Sar4jc@virginia.edu unsigned numPhysFloatRegs; 39012137Sar4jc@virginia.edu 39112137Sar4jc@virginia.edu /** Delay between commit stage and the IQ. 39212137Sar4jc@virginia.edu * @todo: Make there be a distinction between the delays within IEW. 39312137Sar4jc@virginia.edu */ 39412137Sar4jc@virginia.edu unsigned commitToIEWDelay; 39512137Sar4jc@virginia.edu 39612137Sar4jc@virginia.edu bool switchedOut; 39712137Sar4jc@virginia.edu 39812137Sar4jc@virginia.edu /** The sequence number of the squashed instruction. */ 39912137Sar4jc@virginia.edu InstSeqNum squashedSeqNum[Impl::MaxThreads]; 40012137Sar4jc@virginia.edu 40112137Sar4jc@virginia.edu /** A cache of the recently woken registers. It is 1 if the register 40212137Sar4jc@virginia.edu * has been woken up recently, and 0 if the register has been added 40312137Sar4jc@virginia.edu * to the dependency graph and has not yet received its value. It 40412137Sar4jc@virginia.edu * is basically a secondary scoreboard, and should pretty much mirror 40512137Sar4jc@virginia.edu * the scoreboard that exists in the rename map. 40612137Sar4jc@virginia.edu */ 40712137Sar4jc@virginia.edu std::vector<bool> regScoreboard; 40812137Sar4jc@virginia.edu 40912137Sar4jc@virginia.edu /** Adds an instruction to the dependency graph, as a consumer. */ 41012137Sar4jc@virginia.edu bool addToDependents(DynInstPtr &new_inst); 41112137Sar4jc@virginia.edu 41212137Sar4jc@virginia.edu /** Adds an instruction to the dependency graph, as a producer. */ 41312137Sar4jc@virginia.edu void addToProducers(DynInstPtr &new_inst); 41412137Sar4jc@virginia.edu 41512137Sar4jc@virginia.edu /** Moves an instruction to the ready queue if it is ready. */ 41612137Sar4jc@virginia.edu void addIfReady(DynInstPtr &inst); 41712137Sar4jc@virginia.edu 41812137Sar4jc@virginia.edu /** Debugging function to count how many entries are in the IQ. It does 41912137Sar4jc@virginia.edu * a linear walk through the instructions, so do not call this function 42012137Sar4jc@virginia.edu * during normal execution. 42112137Sar4jc@virginia.edu */ 42212137Sar4jc@virginia.edu int countInsts(); 42312137Sar4jc@virginia.edu 42412137Sar4jc@virginia.edu /** Debugging function to dump all the list sizes, as well as print 42512137Sar4jc@virginia.edu * out the list of nonspeculative instructions. Should not be used 42612137Sar4jc@virginia.edu * in any other capacity, but it has no harmful sideaffects. 42712137Sar4jc@virginia.edu */ 42812137Sar4jc@virginia.edu void dumpLists(); 42912137Sar4jc@virginia.edu 43012137Sar4jc@virginia.edu /** Debugging function to dump out all instructions that are in the 43112137Sar4jc@virginia.edu * IQ. 43212137Sar4jc@virginia.edu */ 43312137Sar4jc@virginia.edu void dumpInsts(); 43412137Sar4jc@virginia.edu 43512137Sar4jc@virginia.edu /** Stat for number of instructions added. */ 43612137Sar4jc@virginia.edu Stats::Scalar<> iqInstsAdded; 43712137Sar4jc@virginia.edu /** Stat for number of non-speculative instructions added. */ 43812137Sar4jc@virginia.edu Stats::Scalar<> iqNonSpecInstsAdded; 43912137Sar4jc@virginia.edu 44012137Sar4jc@virginia.edu Stats::Scalar<> iqInstsIssued; 44112137Sar4jc@virginia.edu /** Stat for number of integer instructions issued. */ 44212137Sar4jc@virginia.edu Stats::Scalar<> iqIntInstsIssued; 44312137Sar4jc@virginia.edu /** Stat for number of floating point instructions issued. */ 44412137Sar4jc@virginia.edu Stats::Scalar<> iqFloatInstsIssued; 44512137Sar4jc@virginia.edu /** Stat for number of branch instructions issued. */ 44612137Sar4jc@virginia.edu Stats::Scalar<> iqBranchInstsIssued; 44712137Sar4jc@virginia.edu /** Stat for number of memory instructions issued. */ 44812137Sar4jc@virginia.edu Stats::Scalar<> iqMemInstsIssued; 44912137Sar4jc@virginia.edu /** Stat for number of miscellaneous instructions issued. */ 45012137Sar4jc@virginia.edu Stats::Scalar<> iqMiscInstsIssued; 45112137Sar4jc@virginia.edu /** Stat for number of squashed instructions that were ready to issue. */ 45212137Sar4jc@virginia.edu Stats::Scalar<> iqSquashedInstsIssued; 45312137Sar4jc@virginia.edu /** Stat for number of squashed instructions examined when squashing. */ 45412137Sar4jc@virginia.edu Stats::Scalar<> iqSquashedInstsExamined; 45512137Sar4jc@virginia.edu /** Stat for number of squashed instruction operands examined when 45612137Sar4jc@virginia.edu * squashing. 45712137Sar4jc@virginia.edu */ 45812137Sar4jc@virginia.edu Stats::Scalar<> iqSquashedOperandsExamined; 45912137Sar4jc@virginia.edu /** Stat for number of non-speculative instructions removed due to a squash. 46012137Sar4jc@virginia.edu */ 46112137Sar4jc@virginia.edu Stats::Scalar<> iqSquashedNonSpecRemoved; 46212137Sar4jc@virginia.edu 46312137Sar4jc@virginia.edu Stats::VectorDistribution<> queueResDist; 46412137Sar4jc@virginia.edu Stats::Distribution<> numIssuedDist; 46512137Sar4jc@virginia.edu Stats::VectorDistribution<> issueDelayDist; 46612137Sar4jc@virginia.edu 46712137Sar4jc@virginia.edu Stats::Vector<> statFuBusy; 46812137Sar4jc@virginia.edu// Stats::Vector<> dist_unissued; 46912137Sar4jc@virginia.edu Stats::Vector2d<> statIssuedInstType; 47012137Sar4jc@virginia.edu 47112137Sar4jc@virginia.edu Stats::Formula issueRate; 47212137Sar4jc@virginia.edu// Stats::Formula issue_stores; 47312137Sar4jc@virginia.edu// Stats::Formula issue_op_rate; 47412137Sar4jc@virginia.edu Stats::Vector<> fuBusy; //cumulative fu busy 47512137Sar4jc@virginia.edu 47612137Sar4jc@virginia.edu Stats::Formula fuBusyRate; 47712137Sar4jc@virginia.edu}; 47812137Sar4jc@virginia.edu 47912137Sar4jc@virginia.edu#endif //__CPU_O3_INST_QUEUE_HH__ 48012137Sar4jc@virginia.edu