iew_impl.hh revision 8513
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43// @todo: Fix the instantaneous communication among all the stages within
44// iew.  There's a clear delay between issue and execute, yet backwards
45// communication happens simultaneously.
46
47#include <queue>
48
49#include "arch/utility.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/fu_pool.hh"
52#include "cpu/o3/iew.hh"
53#include "cpu/timebuf.hh"
54#include "debug/Activity.hh"
55#include "debug/Decode.hh"
56#include "debug/IEW.hh"
57#include "params/DerivO3CPU.hh"
58
59using namespace std;
60
61template<class Impl>
62DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
63    : issueToExecQueue(params->backComSize, params->forwardComSize),
64      cpu(_cpu),
65      instQueue(_cpu, this, params),
66      ldstQueue(_cpu, this, params),
67      fuPool(params->fuPool),
68      commitToIEWDelay(params->commitToIEWDelay),
69      renameToIEWDelay(params->renameToIEWDelay),
70      issueToExecuteDelay(params->issueToExecuteDelay),
71      dispatchWidth(params->dispatchWidth),
72      issueWidth(params->issueWidth),
73      wbOutstanding(0),
74      wbWidth(params->wbWidth),
75      numThreads(params->numThreads),
76      switchedOut(false)
77{
78    _status = Active;
79    exeStatus = Running;
80    wbStatus = Idle;
81
82    // Setup wire to read instructions coming from issue.
83    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
84
85    // Instruction queue needs the queue between issue and execute.
86    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
87
88    for (ThreadID tid = 0; tid < numThreads; tid++) {
89        dispatchStatus[tid] = Running;
90        stalls[tid].commit = false;
91        fetchRedirect[tid] = false;
92    }
93
94    wbMax = wbWidth * params->wbDepth;
95
96    updateLSQNextCycle = false;
97
98    ableToIssue = true;
99
100    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
101}
102
103template <class Impl>
104std::string
105DefaultIEW<Impl>::name() const
106{
107    return cpu->name() + ".iew";
108}
109
110template <class Impl>
111void
112DefaultIEW<Impl>::regStats()
113{
114    using namespace Stats;
115
116    instQueue.regStats();
117    ldstQueue.regStats();
118
119    iewIdleCycles
120        .name(name() + ".iewIdleCycles")
121        .desc("Number of cycles IEW is idle");
122
123    iewSquashCycles
124        .name(name() + ".iewSquashCycles")
125        .desc("Number of cycles IEW is squashing");
126
127    iewBlockCycles
128        .name(name() + ".iewBlockCycles")
129        .desc("Number of cycles IEW is blocking");
130
131    iewUnblockCycles
132        .name(name() + ".iewUnblockCycles")
133        .desc("Number of cycles IEW is unblocking");
134
135    iewDispatchedInsts
136        .name(name() + ".iewDispatchedInsts")
137        .desc("Number of instructions dispatched to IQ");
138
139    iewDispSquashedInsts
140        .name(name() + ".iewDispSquashedInsts")
141        .desc("Number of squashed instructions skipped by dispatch");
142
143    iewDispLoadInsts
144        .name(name() + ".iewDispLoadInsts")
145        .desc("Number of dispatched load instructions");
146
147    iewDispStoreInsts
148        .name(name() + ".iewDispStoreInsts")
149        .desc("Number of dispatched store instructions");
150
151    iewDispNonSpecInsts
152        .name(name() + ".iewDispNonSpecInsts")
153        .desc("Number of dispatched non-speculative instructions");
154
155    iewIQFullEvents
156        .name(name() + ".iewIQFullEvents")
157        .desc("Number of times the IQ has become full, causing a stall");
158
159    iewLSQFullEvents
160        .name(name() + ".iewLSQFullEvents")
161        .desc("Number of times the LSQ has become full, causing a stall");
162
163    memOrderViolationEvents
164        .name(name() + ".memOrderViolationEvents")
165        .desc("Number of memory order violations");
166
167    predictedTakenIncorrect
168        .name(name() + ".predictedTakenIncorrect")
169        .desc("Number of branches that were predicted taken incorrectly");
170
171    predictedNotTakenIncorrect
172        .name(name() + ".predictedNotTakenIncorrect")
173        .desc("Number of branches that were predicted not taken incorrectly");
174
175    branchMispredicts
176        .name(name() + ".branchMispredicts")
177        .desc("Number of branch mispredicts detected at execute");
178
179    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
180
181    iewExecutedInsts
182        .name(name() + ".iewExecutedInsts")
183        .desc("Number of executed instructions");
184
185    iewExecLoadInsts
186        .init(cpu->numThreads)
187        .name(name() + ".iewExecLoadInsts")
188        .desc("Number of load instructions executed")
189        .flags(total);
190
191    iewExecSquashedInsts
192        .name(name() + ".iewExecSquashedInsts")
193        .desc("Number of squashed instructions skipped in execute");
194
195    iewExecutedSwp
196        .init(cpu->numThreads)
197        .name(name() + ".exec_swp")
198        .desc("number of swp insts executed")
199        .flags(total);
200
201    iewExecutedNop
202        .init(cpu->numThreads)
203        .name(name() + ".exec_nop")
204        .desc("number of nop insts executed")
205        .flags(total);
206
207    iewExecutedRefs
208        .init(cpu->numThreads)
209        .name(name() + ".exec_refs")
210        .desc("number of memory reference insts executed")
211        .flags(total);
212
213    iewExecutedBranches
214        .init(cpu->numThreads)
215        .name(name() + ".exec_branches")
216        .desc("Number of branches executed")
217        .flags(total);
218
219    iewExecStoreInsts
220        .name(name() + ".exec_stores")
221        .desc("Number of stores executed")
222        .flags(total);
223    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
224
225    iewExecRate
226        .name(name() + ".exec_rate")
227        .desc("Inst execution rate")
228        .flags(total);
229
230    iewExecRate = iewExecutedInsts / cpu->numCycles;
231
232    iewInstsToCommit
233        .init(cpu->numThreads)
234        .name(name() + ".wb_sent")
235        .desc("cumulative count of insts sent to commit")
236        .flags(total);
237
238    writebackCount
239        .init(cpu->numThreads)
240        .name(name() + ".wb_count")
241        .desc("cumulative count of insts written-back")
242        .flags(total);
243
244    producerInst
245        .init(cpu->numThreads)
246        .name(name() + ".wb_producers")
247        .desc("num instructions producing a value")
248        .flags(total);
249
250    consumerInst
251        .init(cpu->numThreads)
252        .name(name() + ".wb_consumers")
253        .desc("num instructions consuming a value")
254        .flags(total);
255
256    wbPenalized
257        .init(cpu->numThreads)
258        .name(name() + ".wb_penalized")
259        .desc("number of instrctions required to write to 'other' IQ")
260        .flags(total);
261
262    wbPenalizedRate
263        .name(name() + ".wb_penalized_rate")
264        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
265        .flags(total);
266
267    wbPenalizedRate = wbPenalized / writebackCount;
268
269    wbFanout
270        .name(name() + ".wb_fanout")
271        .desc("average fanout of values written-back")
272        .flags(total);
273
274    wbFanout = producerInst / consumerInst;
275
276    wbRate
277        .name(name() + ".wb_rate")
278        .desc("insts written-back per cycle")
279        .flags(total);
280    wbRate = writebackCount / cpu->numCycles;
281}
282
283template<class Impl>
284void
285DefaultIEW<Impl>::initStage()
286{
287    for (ThreadID tid = 0; tid < numThreads; tid++) {
288        toRename->iewInfo[tid].usedIQ = true;
289        toRename->iewInfo[tid].freeIQEntries =
290            instQueue.numFreeEntries(tid);
291
292        toRename->iewInfo[tid].usedLSQ = true;
293        toRename->iewInfo[tid].freeLSQEntries =
294            ldstQueue.numFreeEntries(tid);
295    }
296
297    cpu->activateStage(O3CPU::IEWIdx);
298}
299
300template<class Impl>
301void
302DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
303{
304    timeBuffer = tb_ptr;
305
306    // Setup wire to read information from time buffer, from commit.
307    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
308
309    // Setup wire to write information back to previous stages.
310    toRename = timeBuffer->getWire(0);
311
312    toFetch = timeBuffer->getWire(0);
313
314    // Instruction queue also needs main time buffer.
315    instQueue.setTimeBuffer(tb_ptr);
316}
317
318template<class Impl>
319void
320DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
321{
322    renameQueue = rq_ptr;
323
324    // Setup wire to read information from rename queue.
325    fromRename = renameQueue->getWire(-renameToIEWDelay);
326}
327
328template<class Impl>
329void
330DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
331{
332    iewQueue = iq_ptr;
333
334    // Setup wire to write instructions to commit.
335    toCommit = iewQueue->getWire(0);
336}
337
338template<class Impl>
339void
340DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
341{
342    activeThreads = at_ptr;
343
344    ldstQueue.setActiveThreads(at_ptr);
345    instQueue.setActiveThreads(at_ptr);
346}
347
348template<class Impl>
349void
350DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
351{
352    scoreboard = sb_ptr;
353}
354
355template <class Impl>
356bool
357DefaultIEW<Impl>::drain()
358{
359    // IEW is ready to drain at any time.
360    cpu->signalDrained();
361    return true;
362}
363
364template <class Impl>
365void
366DefaultIEW<Impl>::resume()
367{
368}
369
370template <class Impl>
371void
372DefaultIEW<Impl>::switchOut()
373{
374    // Clear any state.
375    switchedOut = true;
376    assert(insts[0].empty());
377    assert(skidBuffer[0].empty());
378
379    instQueue.switchOut();
380    ldstQueue.switchOut();
381    fuPool->switchOut();
382
383    for (ThreadID tid = 0; tid < numThreads; tid++) {
384        while (!insts[tid].empty())
385            insts[tid].pop();
386        while (!skidBuffer[tid].empty())
387            skidBuffer[tid].pop();
388    }
389}
390
391template <class Impl>
392void
393DefaultIEW<Impl>::takeOverFrom()
394{
395    // Reset all state.
396    _status = Active;
397    exeStatus = Running;
398    wbStatus = Idle;
399    switchedOut = false;
400
401    instQueue.takeOverFrom();
402    ldstQueue.takeOverFrom();
403    fuPool->takeOverFrom();
404
405    initStage();
406    cpu->activityThisCycle();
407
408    for (ThreadID tid = 0; tid < numThreads; tid++) {
409        dispatchStatus[tid] = Running;
410        stalls[tid].commit = false;
411        fetchRedirect[tid] = false;
412    }
413
414    updateLSQNextCycle = false;
415
416    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
417        issueToExecQueue.advance();
418    }
419}
420
421template<class Impl>
422void
423DefaultIEW<Impl>::squash(ThreadID tid)
424{
425    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
426
427    // Tell the IQ to start squashing.
428    instQueue.squash(tid);
429
430    // Tell the LDSTQ to start squashing.
431    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
432    updatedQueues = true;
433
434    // Clear the skid buffer in case it has any data in it.
435    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
436            tid, fromCommit->commitInfo[tid].doneSeqNum);
437
438    while (!skidBuffer[tid].empty()) {
439        if (skidBuffer[tid].front()->isLoad() ||
440            skidBuffer[tid].front()->isStore() ) {
441            toRename->iewInfo[tid].dispatchedToLSQ++;
442        }
443
444        toRename->iewInfo[tid].dispatched++;
445
446        skidBuffer[tid].pop();
447    }
448
449    emptyRenameInsts(tid);
450}
451
452template<class Impl>
453void
454DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
455{
456    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
457            "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
458
459    if (toCommit->squash[tid] == false ||
460            inst->seqNum < toCommit->squashedSeqNum[tid]) {
461        toCommit->squash[tid] = true;
462        toCommit->squashedSeqNum[tid] = inst->seqNum;
463        toCommit->branchTaken[tid] = inst->pcState().branching();
464
465        TheISA::PCState pc = inst->pcState();
466        TheISA::advancePC(pc, inst->staticInst);
467
468        toCommit->pc[tid] = pc;
469        toCommit->mispredictInst[tid] = inst;
470        toCommit->includeSquashInst[tid] = false;
471
472        wroteToTimeBuffer = true;
473    }
474
475}
476
477template<class Impl>
478void
479DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
480{
481    DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
482            "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
483    // Need to include inst->seqNum in the following comparison to cover the
484    // corner case when a branch misprediction and a memory violation for the
485    // same instruction (e.g. load PC) are detected in the same cycle.  In this
486    // case the memory violator should take precedence over the branch
487    // misprediction because it requires the violator itself to be included in
488    // the squash.
489    if (toCommit->squash[tid] == false ||
490            inst->seqNum <= toCommit->squashedSeqNum[tid]) {
491        toCommit->squash[tid] = true;
492
493        toCommit->squashedSeqNum[tid] = inst->seqNum;
494        toCommit->pc[tid] = inst->pcState();
495        toCommit->mispredictInst[tid] = NULL;
496
497        // Must include the memory violator in the squash.
498        toCommit->includeSquashInst[tid] = true;
499
500        wroteToTimeBuffer = true;
501    }
502}
503
504template<class Impl>
505void
506DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
507{
508    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
509            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
510    if (toCommit->squash[tid] == false ||
511            inst->seqNum < toCommit->squashedSeqNum[tid]) {
512        toCommit->squash[tid] = true;
513
514        toCommit->squashedSeqNum[tid] = inst->seqNum;
515        toCommit->pc[tid] = inst->pcState();
516        toCommit->mispredictInst[tid] = NULL;
517
518        // Must include the broadcasted SN in the squash.
519        toCommit->includeSquashInst[tid] = true;
520
521        ldstQueue.setLoadBlockedHandled(tid);
522
523        wroteToTimeBuffer = true;
524    }
525}
526
527template<class Impl>
528void
529DefaultIEW<Impl>::block(ThreadID tid)
530{
531    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
532
533    if (dispatchStatus[tid] != Blocked &&
534        dispatchStatus[tid] != Unblocking) {
535        toRename->iewBlock[tid] = true;
536        wroteToTimeBuffer = true;
537    }
538
539    // Add the current inputs to the skid buffer so they can be
540    // reprocessed when this stage unblocks.
541    skidInsert(tid);
542
543    dispatchStatus[tid] = Blocked;
544}
545
546template<class Impl>
547void
548DefaultIEW<Impl>::unblock(ThreadID tid)
549{
550    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
551            "buffer %u.\n",tid, tid);
552
553    // If the skid bufffer is empty, signal back to previous stages to unblock.
554    // Also switch status to running.
555    if (skidBuffer[tid].empty()) {
556        toRename->iewUnblock[tid] = true;
557        wroteToTimeBuffer = true;
558        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
559        dispatchStatus[tid] = Running;
560    }
561}
562
563template<class Impl>
564void
565DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
566{
567    instQueue.wakeDependents(inst);
568}
569
570template<class Impl>
571void
572DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
573{
574    instQueue.rescheduleMemInst(inst);
575}
576
577template<class Impl>
578void
579DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
580{
581    instQueue.replayMemInst(inst);
582}
583
584template<class Impl>
585void
586DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
587{
588    // This function should not be called after writebackInsts in a
589    // single cycle.  That will cause problems with an instruction
590    // being added to the queue to commit without being processed by
591    // writebackInsts prior to being sent to commit.
592
593    // First check the time slot that this instruction will write
594    // to.  If there are free write ports at the time, then go ahead
595    // and write the instruction to that time.  If there are not,
596    // keep looking back to see where's the first time there's a
597    // free slot.
598    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
599        ++wbNumInst;
600        if (wbNumInst == wbWidth) {
601            ++wbCycle;
602            wbNumInst = 0;
603        }
604
605        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
606    }
607
608    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
609            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
610    // Add finished instruction to queue to commit.
611    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
612    (*iewQueue)[wbCycle].size++;
613}
614
615template <class Impl>
616unsigned
617DefaultIEW<Impl>::validInstsFromRename()
618{
619    unsigned inst_count = 0;
620
621    for (int i=0; i<fromRename->size; i++) {
622        if (!fromRename->insts[i]->isSquashed())
623            inst_count++;
624    }
625
626    return inst_count;
627}
628
629template<class Impl>
630void
631DefaultIEW<Impl>::skidInsert(ThreadID tid)
632{
633    DynInstPtr inst = NULL;
634
635    while (!insts[tid].empty()) {
636        inst = insts[tid].front();
637
638        insts[tid].pop();
639
640        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
641                "dispatch skidBuffer %i\n",tid, inst->seqNum,
642                inst->pcState(),tid);
643
644        skidBuffer[tid].push(inst);
645    }
646
647    assert(skidBuffer[tid].size() <= skidBufferMax &&
648           "Skidbuffer Exceeded Max Size");
649}
650
651template<class Impl>
652int
653DefaultIEW<Impl>::skidCount()
654{
655    int max=0;
656
657    list<ThreadID>::iterator threads = activeThreads->begin();
658    list<ThreadID>::iterator end = activeThreads->end();
659
660    while (threads != end) {
661        ThreadID tid = *threads++;
662        unsigned thread_count = skidBuffer[tid].size();
663        if (max < thread_count)
664            max = thread_count;
665    }
666
667    return max;
668}
669
670template<class Impl>
671bool
672DefaultIEW<Impl>::skidsEmpty()
673{
674    list<ThreadID>::iterator threads = activeThreads->begin();
675    list<ThreadID>::iterator end = activeThreads->end();
676
677    while (threads != end) {
678        ThreadID tid = *threads++;
679
680        if (!skidBuffer[tid].empty())
681            return false;
682    }
683
684    return true;
685}
686
687template <class Impl>
688void
689DefaultIEW<Impl>::updateStatus()
690{
691    bool any_unblocking = false;
692
693    list<ThreadID>::iterator threads = activeThreads->begin();
694    list<ThreadID>::iterator end = activeThreads->end();
695
696    while (threads != end) {
697        ThreadID tid = *threads++;
698
699        if (dispatchStatus[tid] == Unblocking) {
700            any_unblocking = true;
701            break;
702        }
703    }
704
705    // If there are no ready instructions waiting to be scheduled by the IQ,
706    // and there's no stores waiting to write back, and dispatch is not
707    // unblocking, then there is no internal activity for the IEW stage.
708    instQueue.intInstQueueReads++;
709    if (_status == Active && !instQueue.hasReadyInsts() &&
710        !ldstQueue.willWB() && !any_unblocking) {
711        DPRINTF(IEW, "IEW switching to idle\n");
712
713        deactivateStage();
714
715        _status = Inactive;
716    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
717                                       ldstQueue.willWB() ||
718                                       any_unblocking)) {
719        // Otherwise there is internal activity.  Set to active.
720        DPRINTF(IEW, "IEW switching to active\n");
721
722        activateStage();
723
724        _status = Active;
725    }
726}
727
728template <class Impl>
729void
730DefaultIEW<Impl>::resetEntries()
731{
732    instQueue.resetEntries();
733    ldstQueue.resetEntries();
734}
735
736template <class Impl>
737void
738DefaultIEW<Impl>::readStallSignals(ThreadID tid)
739{
740    if (fromCommit->commitBlock[tid]) {
741        stalls[tid].commit = true;
742    }
743
744    if (fromCommit->commitUnblock[tid]) {
745        assert(stalls[tid].commit);
746        stalls[tid].commit = false;
747    }
748}
749
750template <class Impl>
751bool
752DefaultIEW<Impl>::checkStall(ThreadID tid)
753{
754    bool ret_val(false);
755
756    if (stalls[tid].commit) {
757        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
758        ret_val = true;
759    } else if (instQueue.isFull(tid)) {
760        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
761        ret_val = true;
762    } else if (ldstQueue.isFull(tid)) {
763        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
764
765        if (ldstQueue.numLoads(tid) > 0 ) {
766
767            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
768                    tid,ldstQueue.getLoadHeadSeqNum(tid));
769        }
770
771        if (ldstQueue.numStores(tid) > 0) {
772
773            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
774                    tid,ldstQueue.getStoreHeadSeqNum(tid));
775        }
776
777        ret_val = true;
778    } else if (ldstQueue.isStalled(tid)) {
779        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
780        ret_val = true;
781    }
782
783    return ret_val;
784}
785
786template <class Impl>
787void
788DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
789{
790    // Check if there's a squash signal, squash if there is
791    // Check stall signals, block if there is.
792    // If status was Blocked
793    //     if so then go to unblocking
794    // If status was Squashing
795    //     check if squashing is not high.  Switch to running this cycle.
796
797    readStallSignals(tid);
798
799    if (fromCommit->commitInfo[tid].squash) {
800        squash(tid);
801
802        if (dispatchStatus[tid] == Blocked ||
803            dispatchStatus[tid] == Unblocking) {
804            toRename->iewUnblock[tid] = true;
805            wroteToTimeBuffer = true;
806        }
807
808        dispatchStatus[tid] = Squashing;
809        fetchRedirect[tid] = false;
810        return;
811    }
812
813    if (fromCommit->commitInfo[tid].robSquashing) {
814        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
815
816        dispatchStatus[tid] = Squashing;
817        emptyRenameInsts(tid);
818        wroteToTimeBuffer = true;
819        return;
820    }
821
822    if (checkStall(tid)) {
823        block(tid);
824        dispatchStatus[tid] = Blocked;
825        return;
826    }
827
828    if (dispatchStatus[tid] == Blocked) {
829        // Status from previous cycle was blocked, but there are no more stall
830        // conditions.  Switch over to unblocking.
831        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
832                tid);
833
834        dispatchStatus[tid] = Unblocking;
835
836        unblock(tid);
837
838        return;
839    }
840
841    if (dispatchStatus[tid] == Squashing) {
842        // Switch status to running if rename isn't being told to block or
843        // squash this cycle.
844        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
845                tid);
846
847        dispatchStatus[tid] = Running;
848
849        return;
850    }
851}
852
853template <class Impl>
854void
855DefaultIEW<Impl>::sortInsts()
856{
857    int insts_from_rename = fromRename->size;
858#ifdef DEBUG
859    for (ThreadID tid = 0; tid < numThreads; tid++)
860        assert(insts[tid].empty());
861#endif
862    for (int i = 0; i < insts_from_rename; ++i) {
863        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
864    }
865}
866
867template <class Impl>
868void
869DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
870{
871    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
872
873    while (!insts[tid].empty()) {
874
875        if (insts[tid].front()->isLoad() ||
876            insts[tid].front()->isStore() ) {
877            toRename->iewInfo[tid].dispatchedToLSQ++;
878        }
879
880        toRename->iewInfo[tid].dispatched++;
881
882        insts[tid].pop();
883    }
884}
885
886template <class Impl>
887void
888DefaultIEW<Impl>::wakeCPU()
889{
890    cpu->wakeCPU();
891}
892
893template <class Impl>
894void
895DefaultIEW<Impl>::activityThisCycle()
896{
897    DPRINTF(Activity, "Activity this cycle.\n");
898    cpu->activityThisCycle();
899}
900
901template <class Impl>
902inline void
903DefaultIEW<Impl>::activateStage()
904{
905    DPRINTF(Activity, "Activating stage.\n");
906    cpu->activateStage(O3CPU::IEWIdx);
907}
908
909template <class Impl>
910inline void
911DefaultIEW<Impl>::deactivateStage()
912{
913    DPRINTF(Activity, "Deactivating stage.\n");
914    cpu->deactivateStage(O3CPU::IEWIdx);
915}
916
917template<class Impl>
918void
919DefaultIEW<Impl>::dispatch(ThreadID tid)
920{
921    // If status is Running or idle,
922    //     call dispatchInsts()
923    // If status is Unblocking,
924    //     buffer any instructions coming from rename
925    //     continue trying to empty skid buffer
926    //     check if stall conditions have passed
927
928    if (dispatchStatus[tid] == Blocked) {
929        ++iewBlockCycles;
930
931    } else if (dispatchStatus[tid] == Squashing) {
932        ++iewSquashCycles;
933    }
934
935    // Dispatch should try to dispatch as many instructions as its bandwidth
936    // will allow, as long as it is not currently blocked.
937    if (dispatchStatus[tid] == Running ||
938        dispatchStatus[tid] == Idle) {
939        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
940                "dispatch.\n", tid);
941
942        dispatchInsts(tid);
943    } else if (dispatchStatus[tid] == Unblocking) {
944        // Make sure that the skid buffer has something in it if the
945        // status is unblocking.
946        assert(!skidsEmpty());
947
948        // If the status was unblocking, then instructions from the skid
949        // buffer were used.  Remove those instructions and handle
950        // the rest of unblocking.
951        dispatchInsts(tid);
952
953        ++iewUnblockCycles;
954
955        if (validInstsFromRename()) {
956            // Add the current inputs to the skid buffer so they can be
957            // reprocessed when this stage unblocks.
958            skidInsert(tid);
959        }
960
961        unblock(tid);
962    }
963}
964
965template <class Impl>
966void
967DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
968{
969    // Obtain instructions from skid buffer if unblocking, or queue from rename
970    // otherwise.
971    std::queue<DynInstPtr> &insts_to_dispatch =
972        dispatchStatus[tid] == Unblocking ?
973        skidBuffer[tid] : insts[tid];
974
975    int insts_to_add = insts_to_dispatch.size();
976
977    DynInstPtr inst;
978    bool add_to_iq = false;
979    int dis_num_inst = 0;
980
981    // Loop through the instructions, putting them in the instruction
982    // queue.
983    for ( ; dis_num_inst < insts_to_add &&
984              dis_num_inst < dispatchWidth;
985          ++dis_num_inst)
986    {
987        inst = insts_to_dispatch.front();
988
989        if (dispatchStatus[tid] == Unblocking) {
990            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
991                    "buffer\n", tid);
992        }
993
994        // Make sure there's a valid instruction there.
995        assert(inst);
996
997        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
998                "IQ.\n",
999                tid, inst->pcState(), inst->seqNum, inst->threadNumber);
1000
1001        // Be sure to mark these instructions as ready so that the
1002        // commit stage can go ahead and execute them, and mark
1003        // them as issued so the IQ doesn't reprocess them.
1004
1005        // Check for squashed instructions.
1006        if (inst->isSquashed()) {
1007            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
1008                    "not adding to IQ.\n", tid);
1009
1010            ++iewDispSquashedInsts;
1011
1012            insts_to_dispatch.pop();
1013
1014            //Tell Rename That An Instruction has been processed
1015            if (inst->isLoad() || inst->isStore()) {
1016                toRename->iewInfo[tid].dispatchedToLSQ++;
1017            }
1018            toRename->iewInfo[tid].dispatched++;
1019
1020            continue;
1021        }
1022
1023        // Check for full conditions.
1024        if (instQueue.isFull(tid)) {
1025            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1026
1027            // Call function to start blocking.
1028            block(tid);
1029
1030            // Set unblock to false. Special case where we are using
1031            // skidbuffer (unblocking) instructions but then we still
1032            // get full in the IQ.
1033            toRename->iewUnblock[tid] = false;
1034
1035            ++iewIQFullEvents;
1036            break;
1037        } else if (ldstQueue.isFull(tid)) {
1038            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1039
1040            // Call function to start blocking.
1041            block(tid);
1042
1043            // Set unblock to false. Special case where we are using
1044            // skidbuffer (unblocking) instructions but then we still
1045            // get full in the IQ.
1046            toRename->iewUnblock[tid] = false;
1047
1048            ++iewLSQFullEvents;
1049            break;
1050        }
1051
1052        // Otherwise issue the instruction just fine.
1053        if (inst->isLoad()) {
1054            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1055                    "encountered, adding to LSQ.\n", tid);
1056
1057            // Reserve a spot in the load store queue for this
1058            // memory access.
1059            ldstQueue.insertLoad(inst);
1060
1061            ++iewDispLoadInsts;
1062
1063            add_to_iq = true;
1064
1065            toRename->iewInfo[tid].dispatchedToLSQ++;
1066        } else if (inst->isStore()) {
1067            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1068                    "encountered, adding to LSQ.\n", tid);
1069
1070            ldstQueue.insertStore(inst);
1071
1072            ++iewDispStoreInsts;
1073
1074            if (inst->isStoreConditional()) {
1075                // Store conditionals need to be set as "canCommit()"
1076                // so that commit can process them when they reach the
1077                // head of commit.
1078                // @todo: This is somewhat specific to Alpha.
1079                inst->setCanCommit();
1080                instQueue.insertNonSpec(inst);
1081                add_to_iq = false;
1082
1083                ++iewDispNonSpecInsts;
1084            } else {
1085                add_to_iq = true;
1086            }
1087
1088            toRename->iewInfo[tid].dispatchedToLSQ++;
1089        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1090            // Same as non-speculative stores.
1091            inst->setCanCommit();
1092            instQueue.insertBarrier(inst);
1093            add_to_iq = false;
1094        } else if (inst->isNop()) {
1095            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1096                    "skipping.\n", tid);
1097
1098            inst->setIssued();
1099            inst->setExecuted();
1100            inst->setCanCommit();
1101
1102            instQueue.recordProducer(inst);
1103
1104            iewExecutedNop[tid]++;
1105
1106            add_to_iq = false;
1107        } else if (inst->isExecuted()) {
1108            assert(0 && "Instruction shouldn't be executed.\n");
1109            DPRINTF(IEW, "Issue: Executed branch encountered, "
1110                    "skipping.\n");
1111
1112            inst->setIssued();
1113            inst->setCanCommit();
1114
1115            instQueue.recordProducer(inst);
1116
1117            add_to_iq = false;
1118        } else {
1119            add_to_iq = true;
1120        }
1121        if (inst->isNonSpeculative()) {
1122            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1123                    "encountered, skipping.\n", tid);
1124
1125            // Same as non-speculative stores.
1126            inst->setCanCommit();
1127
1128            // Specifically insert it as nonspeculative.
1129            instQueue.insertNonSpec(inst);
1130
1131            ++iewDispNonSpecInsts;
1132
1133            add_to_iq = false;
1134        }
1135
1136        // If the instruction queue is not full, then add the
1137        // instruction.
1138        if (add_to_iq) {
1139            instQueue.insert(inst);
1140        }
1141
1142        insts_to_dispatch.pop();
1143
1144        toRename->iewInfo[tid].dispatched++;
1145
1146        ++iewDispatchedInsts;
1147
1148#if TRACING_ON
1149        inst->dispatchTick = curTick();
1150#endif
1151    }
1152
1153    if (!insts_to_dispatch.empty()) {
1154        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1155        block(tid);
1156        toRename->iewUnblock[tid] = false;
1157    }
1158
1159    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1160        dispatchStatus[tid] = Running;
1161
1162        updatedQueues = true;
1163    }
1164
1165    dis_num_inst = 0;
1166}
1167
1168template <class Impl>
1169void
1170DefaultIEW<Impl>::printAvailableInsts()
1171{
1172    int inst = 0;
1173
1174    std::cout << "Available Instructions: ";
1175
1176    while (fromIssue->insts[inst]) {
1177
1178        if (inst%3==0) std::cout << "\n\t";
1179
1180        std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1181             << " TN: " << fromIssue->insts[inst]->threadNumber
1182             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1183
1184        inst++;
1185
1186    }
1187
1188    std::cout << "\n";
1189}
1190
1191template <class Impl>
1192void
1193DefaultIEW<Impl>::executeInsts()
1194{
1195    wbNumInst = 0;
1196    wbCycle = 0;
1197
1198    list<ThreadID>::iterator threads = activeThreads->begin();
1199    list<ThreadID>::iterator end = activeThreads->end();
1200
1201    while (threads != end) {
1202        ThreadID tid = *threads++;
1203        fetchRedirect[tid] = false;
1204    }
1205
1206    // Uncomment this if you want to see all available instructions.
1207    // @todo This doesn't actually work anymore, we should fix it.
1208//    printAvailableInsts();
1209
1210    // Execute/writeback any instructions that are available.
1211    int insts_to_execute = fromIssue->size;
1212    int inst_num = 0;
1213    for (; inst_num < insts_to_execute;
1214          ++inst_num) {
1215
1216        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1217
1218        DynInstPtr inst = instQueue.getInstToExecute();
1219
1220        DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1221                inst->pcState(), inst->threadNumber,inst->seqNum);
1222
1223        // Check if the instruction is squashed; if so then skip it
1224        if (inst->isSquashed()) {
1225            DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
1226                         " [sn:%i]\n", inst->pcState(), inst->threadNumber,
1227                         inst->seqNum);
1228
1229            // Consider this instruction executed so that commit can go
1230            // ahead and retire the instruction.
1231            inst->setExecuted();
1232
1233            // Not sure if I should set this here or just let commit try to
1234            // commit any squashed instructions.  I like the latter a bit more.
1235            inst->setCanCommit();
1236
1237            ++iewExecSquashedInsts;
1238
1239            decrWb(inst->seqNum);
1240            continue;
1241        }
1242
1243        Fault fault = NoFault;
1244
1245        // Execute instruction.
1246        // Note that if the instruction faults, it will be handled
1247        // at the commit stage.
1248        if (inst->isMemRef()) {
1249            DPRINTF(IEW, "Execute: Calculating address for memory "
1250                    "reference.\n");
1251
1252            // Tell the LDSTQ to execute this instruction (if it is a load).
1253            if (inst->isLoad()) {
1254                // Loads will mark themselves as executed, and their writeback
1255                // event adds the instruction to the queue to commit
1256                fault = ldstQueue.executeLoad(inst);
1257
1258                if (inst->isTranslationDelayed() &&
1259                    fault == NoFault) {
1260                    // A hw page table walk is currently going on; the
1261                    // instruction must be deferred.
1262                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1263                            "load.\n");
1264                    instQueue.deferMemInst(inst);
1265                    continue;
1266                }
1267
1268                if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1269                    inst->fault = NoFault;
1270                }
1271            } else if (inst->isStore()) {
1272                fault = ldstQueue.executeStore(inst);
1273
1274                if (inst->isTranslationDelayed() &&
1275                    fault == NoFault) {
1276                    // A hw page table walk is currently going on; the
1277                    // instruction must be deferred.
1278                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1279                            "store.\n");
1280                    instQueue.deferMemInst(inst);
1281                    continue;
1282                }
1283
1284                // If the store had a fault then it may not have a mem req
1285                if (fault != NoFault || inst->readPredicate() == false ||
1286                        !inst->isStoreConditional()) {
1287                    // If the instruction faulted, then we need to send it along
1288                    // to commit without the instruction completing.
1289                    // Send this instruction to commit, also make sure iew stage
1290                    // realizes there is activity.
1291                    inst->setExecuted();
1292                    instToCommit(inst);
1293                    activityThisCycle();
1294                }
1295
1296                // Store conditionals will mark themselves as
1297                // executed, and their writeback event will add the
1298                // instruction to the queue to commit.
1299            } else {
1300                panic("Unexpected memory type!\n");
1301            }
1302
1303        } else {
1304            // If the instruction has already faulted, then skip executing it.
1305            // Such case can happen when it faulted during ITLB translation.
1306            // If we execute the instruction (even if it's a nop) the fault
1307            // will be replaced and we will lose it.
1308            if (inst->getFault() == NoFault) {
1309                inst->execute();
1310                if (inst->readPredicate() == false)
1311                    inst->forwardOldRegs();
1312            }
1313
1314            inst->setExecuted();
1315
1316            instToCommit(inst);
1317        }
1318
1319        updateExeInstStats(inst);
1320
1321        // Check if branch prediction was correct, if not then we need
1322        // to tell commit to squash in flight instructions.  Only
1323        // handle this if there hasn't already been something that
1324        // redirects fetch in this group of instructions.
1325
1326        // This probably needs to prioritize the redirects if a different
1327        // scheduler is used.  Currently the scheduler schedules the oldest
1328        // instruction first, so the branch resolution order will be correct.
1329        ThreadID tid = inst->threadNumber;
1330
1331        if (!fetchRedirect[tid] ||
1332            !toCommit->squash[tid] ||
1333            toCommit->squashedSeqNum[tid] > inst->seqNum) {
1334
1335            // Prevent testing for misprediction on load instructions,
1336            // that have not been executed.
1337            bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1338
1339            if (inst->mispredicted() && !loadNotExecuted) {
1340                fetchRedirect[tid] = true;
1341
1342                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1343                DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1344                        inst->predInstAddr(), inst->predNextInstAddr());
1345                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1346                        inst->pcState(), inst->nextInstAddr());
1347                // If incorrect, then signal the ROB that it must be squashed.
1348                squashDueToBranch(inst, tid);
1349
1350                if (inst->readPredTaken()) {
1351                    predictedTakenIncorrect++;
1352                } else {
1353                    predictedNotTakenIncorrect++;
1354                }
1355            } else if (ldstQueue.violation(tid)) {
1356                assert(inst->isMemRef());
1357                // If there was an ordering violation, then get the
1358                // DynInst that caused the violation.  Note that this
1359                // clears the violation signal.
1360                DynInstPtr violator;
1361                violator = ldstQueue.getMemDepViolator(tid);
1362
1363                DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1364                        "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1365                        violator->pcState(), violator->seqNum,
1366                        inst->pcState(), inst->seqNum, inst->physEffAddr);
1367
1368                fetchRedirect[tid] = true;
1369
1370                // Tell the instruction queue that a violation has occured.
1371                instQueue.violation(inst, violator);
1372
1373                // Squash.
1374                squashDueToMemOrder(violator, tid);
1375
1376                ++memOrderViolationEvents;
1377            } else if (ldstQueue.loadBlocked(tid) &&
1378                       !ldstQueue.isLoadBlockedHandled(tid)) {
1379                fetchRedirect[tid] = true;
1380
1381                DPRINTF(IEW, "Load operation couldn't execute because the "
1382                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1383                        inst->pcState(), inst->seqNum);
1384
1385                squashDueToMemBlocked(inst, tid);
1386            }
1387        } else {
1388            // Reset any state associated with redirects that will not
1389            // be used.
1390            if (ldstQueue.violation(tid)) {
1391                assert(inst->isMemRef());
1392
1393                DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1394
1395                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1396                        "%s, inst PC: %s.  Addr is: %#x.\n",
1397                        violator->pcState(), inst->pcState(),
1398                        inst->physEffAddr);
1399                DPRINTF(IEW, "Violation will not be handled because "
1400                        "already squashing\n");
1401
1402                ++memOrderViolationEvents;
1403            }
1404            if (ldstQueue.loadBlocked(tid) &&
1405                !ldstQueue.isLoadBlockedHandled(tid)) {
1406                DPRINTF(IEW, "Load operation couldn't execute because the "
1407                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1408                        inst->pcState(), inst->seqNum);
1409                DPRINTF(IEW, "Blocked load will not be handled because "
1410                        "already squashing\n");
1411
1412                ldstQueue.setLoadBlockedHandled(tid);
1413            }
1414
1415        }
1416    }
1417
1418    // Update and record activity if we processed any instructions.
1419    if (inst_num) {
1420        if (exeStatus == Idle) {
1421            exeStatus = Running;
1422        }
1423
1424        updatedQueues = true;
1425
1426        cpu->activityThisCycle();
1427    }
1428
1429    // Need to reset this in case a writeback event needs to write into the
1430    // iew queue.  That way the writeback event will write into the correct
1431    // spot in the queue.
1432    wbNumInst = 0;
1433
1434}
1435
1436template <class Impl>
1437void
1438DefaultIEW<Impl>::writebackInsts()
1439{
1440    // Loop through the head of the time buffer and wake any
1441    // dependents.  These instructions are about to write back.  Also
1442    // mark scoreboard that this instruction is finally complete.
1443    // Either have IEW have direct access to scoreboard, or have this
1444    // as part of backwards communication.
1445    for (int inst_num = 0; inst_num < wbWidth &&
1446             toCommit->insts[inst_num]; inst_num++) {
1447        DynInstPtr inst = toCommit->insts[inst_num];
1448        ThreadID tid = inst->threadNumber;
1449
1450        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1451                inst->seqNum, inst->pcState());
1452
1453        iewInstsToCommit[tid]++;
1454
1455        // Some instructions will be sent to commit without having
1456        // executed because they need commit to handle them.
1457        // E.g. Uncached loads have not actually executed when they
1458        // are first sent to commit.  Instead commit must tell the LSQ
1459        // when it's ready to execute the uncached load.
1460        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1461            int dependents = instQueue.wakeDependents(inst);
1462
1463            for (int i = 0; i < inst->numDestRegs(); i++) {
1464                //mark as Ready
1465                DPRINTF(IEW,"Setting Destination Register %i\n",
1466                        inst->renamedDestRegIdx(i));
1467                scoreboard->setReg(inst->renamedDestRegIdx(i));
1468            }
1469
1470            if (dependents) {
1471                producerInst[tid]++;
1472                consumerInst[tid]+= dependents;
1473            }
1474            writebackCount[tid]++;
1475        }
1476
1477        decrWb(inst->seqNum);
1478    }
1479}
1480
1481template<class Impl>
1482void
1483DefaultIEW<Impl>::tick()
1484{
1485    wbNumInst = 0;
1486    wbCycle = 0;
1487
1488    wroteToTimeBuffer = false;
1489    updatedQueues = false;
1490
1491    sortInsts();
1492
1493    // Free function units marked as being freed this cycle.
1494    fuPool->processFreeUnits();
1495
1496    list<ThreadID>::iterator threads = activeThreads->begin();
1497    list<ThreadID>::iterator end = activeThreads->end();
1498
1499    // Check stall and squash signals, dispatch any instructions.
1500    while (threads != end) {
1501        ThreadID tid = *threads++;
1502
1503        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1504
1505        checkSignalsAndUpdate(tid);
1506        dispatch(tid);
1507    }
1508
1509    if (exeStatus != Squashing) {
1510        executeInsts();
1511
1512        writebackInsts();
1513
1514        // Have the instruction queue try to schedule any ready instructions.
1515        // (In actuality, this scheduling is for instructions that will
1516        // be executed next cycle.)
1517        instQueue.scheduleReadyInsts();
1518
1519        // Also should advance its own time buffers if the stage ran.
1520        // Not the best place for it, but this works (hopefully).
1521        issueToExecQueue.advance();
1522    }
1523
1524    bool broadcast_free_entries = false;
1525
1526    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1527        exeStatus = Idle;
1528        updateLSQNextCycle = false;
1529
1530        broadcast_free_entries = true;
1531    }
1532
1533    // Writeback any stores using any leftover bandwidth.
1534    ldstQueue.writebackStores();
1535
1536    // Check the committed load/store signals to see if there's a load
1537    // or store to commit.  Also check if it's being told to execute a
1538    // nonspeculative instruction.
1539    // This is pretty inefficient...
1540
1541    threads = activeThreads->begin();
1542    while (threads != end) {
1543        ThreadID tid = (*threads++);
1544
1545        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1546
1547        // Update structures based on instructions committed.
1548        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1549            !fromCommit->commitInfo[tid].squash &&
1550            !fromCommit->commitInfo[tid].robSquashing) {
1551
1552            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1553
1554            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1555
1556            updateLSQNextCycle = true;
1557            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1558        }
1559
1560        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1561
1562            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1563            if (fromCommit->commitInfo[tid].uncached) {
1564                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1565                fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1566            } else {
1567                instQueue.scheduleNonSpec(
1568                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1569            }
1570        }
1571
1572        if (broadcast_free_entries) {
1573            toFetch->iewInfo[tid].iqCount =
1574                instQueue.getCount(tid);
1575            toFetch->iewInfo[tid].ldstqCount =
1576                ldstQueue.getCount(tid);
1577
1578            toRename->iewInfo[tid].usedIQ = true;
1579            toRename->iewInfo[tid].freeIQEntries =
1580                instQueue.numFreeEntries();
1581            toRename->iewInfo[tid].usedLSQ = true;
1582            toRename->iewInfo[tid].freeLSQEntries =
1583                ldstQueue.numFreeEntries(tid);
1584
1585            wroteToTimeBuffer = true;
1586        }
1587
1588        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1589                tid, toRename->iewInfo[tid].dispatched);
1590    }
1591
1592    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1593            "LSQ has %i free entries.\n",
1594            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1595            ldstQueue.numFreeEntries());
1596
1597    updateStatus();
1598
1599    if (wroteToTimeBuffer) {
1600        DPRINTF(Activity, "Activity this cycle.\n");
1601        cpu->activityThisCycle();
1602    }
1603}
1604
1605template <class Impl>
1606void
1607DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1608{
1609    ThreadID tid = inst->threadNumber;
1610
1611    //
1612    //  Pick off the software prefetches
1613    //
1614#ifdef TARGET_ALPHA
1615    if (inst->isDataPrefetch())
1616        iewExecutedSwp[tid]++;
1617    else
1618        iewIewExecutedcutedInsts++;
1619#else
1620    iewExecutedInsts++;
1621#endif
1622
1623#if TRACING_ON
1624    inst->completeTick = curTick();
1625#endif
1626
1627    //
1628    //  Control operations
1629    //
1630    if (inst->isControl())
1631        iewExecutedBranches[tid]++;
1632
1633    //
1634    //  Memory operations
1635    //
1636    if (inst->isMemRef()) {
1637        iewExecutedRefs[tid]++;
1638
1639        if (inst->isLoad()) {
1640            iewExecLoadInsts[tid]++;
1641        }
1642    }
1643}
1644
1645template <class Impl>
1646void
1647DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1648{
1649    ThreadID tid = inst->threadNumber;
1650
1651    if (!fetchRedirect[tid] ||
1652        !toCommit->squash[tid] ||
1653        toCommit->squashedSeqNum[tid] > inst->seqNum) {
1654
1655        if (inst->mispredicted()) {
1656            fetchRedirect[tid] = true;
1657
1658            DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1659            DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1660                    inst->predInstAddr(), inst->predNextInstAddr());
1661            DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1662                    " NPC: %#x.\n", inst->nextInstAddr(),
1663                    inst->nextInstAddr());
1664            // If incorrect, then signal the ROB that it must be squashed.
1665            squashDueToBranch(inst, tid);
1666
1667            if (inst->readPredTaken()) {
1668                predictedTakenIncorrect++;
1669            } else {
1670                predictedNotTakenIncorrect++;
1671            }
1672        }
1673    }
1674}
1675