iew_impl.hh revision 8137
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 */
42
43// @todo: Fix the instantaneous communication among all the stages within
44// iew.  There's a clear delay between issue and execute, yet backwards
45// communication happens simultaneously.
46
47#include <queue>
48
49#include "cpu/timebuf.hh"
50#include "config/the_isa.hh"
51#include "cpu/o3/fu_pool.hh"
52#include "cpu/o3/iew.hh"
53#include "params/DerivO3CPU.hh"
54
55using namespace std;
56
57template<class Impl>
58DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
59    : issueToExecQueue(params->backComSize, params->forwardComSize),
60      cpu(_cpu),
61      instQueue(_cpu, this, params),
62      ldstQueue(_cpu, this, params),
63      fuPool(params->fuPool),
64      commitToIEWDelay(params->commitToIEWDelay),
65      renameToIEWDelay(params->renameToIEWDelay),
66      issueToExecuteDelay(params->issueToExecuteDelay),
67      dispatchWidth(params->dispatchWidth),
68      issueWidth(params->issueWidth),
69      wbOutstanding(0),
70      wbWidth(params->wbWidth),
71      numThreads(params->numThreads),
72      switchedOut(false)
73{
74    _status = Active;
75    exeStatus = Running;
76    wbStatus = Idle;
77
78    // Setup wire to read instructions coming from issue.
79    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
80
81    // Instruction queue needs the queue between issue and execute.
82    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
83
84    for (ThreadID tid = 0; tid < numThreads; tid++) {
85        dispatchStatus[tid] = Running;
86        stalls[tid].commit = false;
87        fetchRedirect[tid] = false;
88    }
89
90    wbMax = wbWidth * params->wbDepth;
91
92    updateLSQNextCycle = false;
93
94    ableToIssue = true;
95
96    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
97}
98
99template <class Impl>
100std::string
101DefaultIEW<Impl>::name() const
102{
103    return cpu->name() + ".iew";
104}
105
106template <class Impl>
107void
108DefaultIEW<Impl>::regStats()
109{
110    using namespace Stats;
111
112    instQueue.regStats();
113    ldstQueue.regStats();
114
115    iewIdleCycles
116        .name(name() + ".iewIdleCycles")
117        .desc("Number of cycles IEW is idle");
118
119    iewSquashCycles
120        .name(name() + ".iewSquashCycles")
121        .desc("Number of cycles IEW is squashing");
122
123    iewBlockCycles
124        .name(name() + ".iewBlockCycles")
125        .desc("Number of cycles IEW is blocking");
126
127    iewUnblockCycles
128        .name(name() + ".iewUnblockCycles")
129        .desc("Number of cycles IEW is unblocking");
130
131    iewDispatchedInsts
132        .name(name() + ".iewDispatchedInsts")
133        .desc("Number of instructions dispatched to IQ");
134
135    iewDispSquashedInsts
136        .name(name() + ".iewDispSquashedInsts")
137        .desc("Number of squashed instructions skipped by dispatch");
138
139    iewDispLoadInsts
140        .name(name() + ".iewDispLoadInsts")
141        .desc("Number of dispatched load instructions");
142
143    iewDispStoreInsts
144        .name(name() + ".iewDispStoreInsts")
145        .desc("Number of dispatched store instructions");
146
147    iewDispNonSpecInsts
148        .name(name() + ".iewDispNonSpecInsts")
149        .desc("Number of dispatched non-speculative instructions");
150
151    iewIQFullEvents
152        .name(name() + ".iewIQFullEvents")
153        .desc("Number of times the IQ has become full, causing a stall");
154
155    iewLSQFullEvents
156        .name(name() + ".iewLSQFullEvents")
157        .desc("Number of times the LSQ has become full, causing a stall");
158
159    memOrderViolationEvents
160        .name(name() + ".memOrderViolationEvents")
161        .desc("Number of memory order violations");
162
163    predictedTakenIncorrect
164        .name(name() + ".predictedTakenIncorrect")
165        .desc("Number of branches that were predicted taken incorrectly");
166
167    predictedNotTakenIncorrect
168        .name(name() + ".predictedNotTakenIncorrect")
169        .desc("Number of branches that were predicted not taken incorrectly");
170
171    branchMispredicts
172        .name(name() + ".branchMispredicts")
173        .desc("Number of branch mispredicts detected at execute");
174
175    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
176
177    iewExecutedInsts
178        .name(name() + ".iewExecutedInsts")
179        .desc("Number of executed instructions");
180
181    iewExecLoadInsts
182        .init(cpu->numThreads)
183        .name(name() + ".iewExecLoadInsts")
184        .desc("Number of load instructions executed")
185        .flags(total);
186
187    iewExecSquashedInsts
188        .name(name() + ".iewExecSquashedInsts")
189        .desc("Number of squashed instructions skipped in execute");
190
191    iewExecutedSwp
192        .init(cpu->numThreads)
193        .name(name() + ".EXEC:swp")
194        .desc("number of swp insts executed")
195        .flags(total);
196
197    iewExecutedNop
198        .init(cpu->numThreads)
199        .name(name() + ".EXEC:nop")
200        .desc("number of nop insts executed")
201        .flags(total);
202
203    iewExecutedRefs
204        .init(cpu->numThreads)
205        .name(name() + ".EXEC:refs")
206        .desc("number of memory reference insts executed")
207        .flags(total);
208
209    iewExecutedBranches
210        .init(cpu->numThreads)
211        .name(name() + ".EXEC:branches")
212        .desc("Number of branches executed")
213        .flags(total);
214
215    iewExecStoreInsts
216        .name(name() + ".EXEC:stores")
217        .desc("Number of stores executed")
218        .flags(total);
219    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
220
221    iewExecRate
222        .name(name() + ".EXEC:rate")
223        .desc("Inst execution rate")
224        .flags(total);
225
226    iewExecRate = iewExecutedInsts / cpu->numCycles;
227
228    iewInstsToCommit
229        .init(cpu->numThreads)
230        .name(name() + ".WB:sent")
231        .desc("cumulative count of insts sent to commit")
232        .flags(total);
233
234    writebackCount
235        .init(cpu->numThreads)
236        .name(name() + ".WB:count")
237        .desc("cumulative count of insts written-back")
238        .flags(total);
239
240    producerInst
241        .init(cpu->numThreads)
242        .name(name() + ".WB:producers")
243        .desc("num instructions producing a value")
244        .flags(total);
245
246    consumerInst
247        .init(cpu->numThreads)
248        .name(name() + ".WB:consumers")
249        .desc("num instructions consuming a value")
250        .flags(total);
251
252    wbPenalized
253        .init(cpu->numThreads)
254        .name(name() + ".WB:penalized")
255        .desc("number of instrctions required to write to 'other' IQ")
256        .flags(total);
257
258    wbPenalizedRate
259        .name(name() + ".WB:penalized_rate")
260        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
261        .flags(total);
262
263    wbPenalizedRate = wbPenalized / writebackCount;
264
265    wbFanout
266        .name(name() + ".WB:fanout")
267        .desc("average fanout of values written-back")
268        .flags(total);
269
270    wbFanout = producerInst / consumerInst;
271
272    wbRate
273        .name(name() + ".WB:rate")
274        .desc("insts written-back per cycle")
275        .flags(total);
276    wbRate = writebackCount / cpu->numCycles;
277}
278
279template<class Impl>
280void
281DefaultIEW<Impl>::initStage()
282{
283    for (ThreadID tid = 0; tid < numThreads; tid++) {
284        toRename->iewInfo[tid].usedIQ = true;
285        toRename->iewInfo[tid].freeIQEntries =
286            instQueue.numFreeEntries(tid);
287
288        toRename->iewInfo[tid].usedLSQ = true;
289        toRename->iewInfo[tid].freeLSQEntries =
290            ldstQueue.numFreeEntries(tid);
291    }
292
293    cpu->activateStage(O3CPU::IEWIdx);
294}
295
296template<class Impl>
297void
298DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
299{
300    timeBuffer = tb_ptr;
301
302    // Setup wire to read information from time buffer, from commit.
303    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
304
305    // Setup wire to write information back to previous stages.
306    toRename = timeBuffer->getWire(0);
307
308    toFetch = timeBuffer->getWire(0);
309
310    // Instruction queue also needs main time buffer.
311    instQueue.setTimeBuffer(tb_ptr);
312}
313
314template<class Impl>
315void
316DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
317{
318    renameQueue = rq_ptr;
319
320    // Setup wire to read information from rename queue.
321    fromRename = renameQueue->getWire(-renameToIEWDelay);
322}
323
324template<class Impl>
325void
326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
327{
328    iewQueue = iq_ptr;
329
330    // Setup wire to write instructions to commit.
331    toCommit = iewQueue->getWire(0);
332}
333
334template<class Impl>
335void
336DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
337{
338    activeThreads = at_ptr;
339
340    ldstQueue.setActiveThreads(at_ptr);
341    instQueue.setActiveThreads(at_ptr);
342}
343
344template<class Impl>
345void
346DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
347{
348    scoreboard = sb_ptr;
349}
350
351template <class Impl>
352bool
353DefaultIEW<Impl>::drain()
354{
355    // IEW is ready to drain at any time.
356    cpu->signalDrained();
357    return true;
358}
359
360template <class Impl>
361void
362DefaultIEW<Impl>::resume()
363{
364}
365
366template <class Impl>
367void
368DefaultIEW<Impl>::switchOut()
369{
370    // Clear any state.
371    switchedOut = true;
372    assert(insts[0].empty());
373    assert(skidBuffer[0].empty());
374
375    instQueue.switchOut();
376    ldstQueue.switchOut();
377    fuPool->switchOut();
378
379    for (ThreadID tid = 0; tid < numThreads; tid++) {
380        while (!insts[tid].empty())
381            insts[tid].pop();
382        while (!skidBuffer[tid].empty())
383            skidBuffer[tid].pop();
384    }
385}
386
387template <class Impl>
388void
389DefaultIEW<Impl>::takeOverFrom()
390{
391    // Reset all state.
392    _status = Active;
393    exeStatus = Running;
394    wbStatus = Idle;
395    switchedOut = false;
396
397    instQueue.takeOverFrom();
398    ldstQueue.takeOverFrom();
399    fuPool->takeOverFrom();
400
401    initStage();
402    cpu->activityThisCycle();
403
404    for (ThreadID tid = 0; tid < numThreads; tid++) {
405        dispatchStatus[tid] = Running;
406        stalls[tid].commit = false;
407        fetchRedirect[tid] = false;
408    }
409
410    updateLSQNextCycle = false;
411
412    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
413        issueToExecQueue.advance();
414    }
415}
416
417template<class Impl>
418void
419DefaultIEW<Impl>::squash(ThreadID tid)
420{
421    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
422
423    // Tell the IQ to start squashing.
424    instQueue.squash(tid);
425
426    // Tell the LDSTQ to start squashing.
427    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
428    updatedQueues = true;
429
430    // Clear the skid buffer in case it has any data in it.
431    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
432            tid, fromCommit->commitInfo[tid].doneSeqNum);
433
434    while (!skidBuffer[tid].empty()) {
435        if (skidBuffer[tid].front()->isLoad() ||
436            skidBuffer[tid].front()->isStore() ) {
437            toRename->iewInfo[tid].dispatchedToLSQ++;
438        }
439
440        toRename->iewInfo[tid].dispatched++;
441
442        skidBuffer[tid].pop();
443    }
444
445    emptyRenameInsts(tid);
446}
447
448template<class Impl>
449void
450DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
451{
452    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
453            "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
454
455    if (toCommit->squash[tid] == false ||
456            inst->seqNum < toCommit->squashedSeqNum[tid]) {
457        toCommit->squash[tid] = true;
458        toCommit->squashedSeqNum[tid] = inst->seqNum;
459        toCommit->branchTaken[tid] = inst->pcState().branching();
460
461        TheISA::PCState pc = inst->pcState();
462        TheISA::advancePC(pc, inst->staticInst);
463
464        toCommit->pc[tid] = pc;
465        toCommit->mispredictInst[tid] = inst;
466        toCommit->includeSquashInst[tid] = false;
467
468        wroteToTimeBuffer = true;
469    }
470
471}
472
473template<class Impl>
474void
475DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
476{
477    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
478            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
479
480    if (toCommit->squash[tid] == false ||
481            inst->seqNum < toCommit->squashedSeqNum[tid]) {
482        toCommit->squash[tid] = true;
483        toCommit->squashedSeqNum[tid] = inst->seqNum;
484        TheISA::PCState pc = inst->pcState();
485        TheISA::advancePC(pc, inst->staticInst);
486        toCommit->pc[tid] = pc;
487        toCommit->mispredictInst[tid] = NULL;
488
489        toCommit->includeSquashInst[tid] = false;
490
491        wroteToTimeBuffer = true;
492    }
493}
494
495template<class Impl>
496void
497DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
498{
499    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
500            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
501    if (toCommit->squash[tid] == false ||
502            inst->seqNum < toCommit->squashedSeqNum[tid]) {
503        toCommit->squash[tid] = true;
504
505        toCommit->squashedSeqNum[tid] = inst->seqNum;
506        toCommit->pc[tid] = inst->pcState();
507        toCommit->mispredictInst[tid] = NULL;
508
509        // Must include the broadcasted SN in the squash.
510        toCommit->includeSquashInst[tid] = true;
511
512        ldstQueue.setLoadBlockedHandled(tid);
513
514        wroteToTimeBuffer = true;
515    }
516}
517
518template<class Impl>
519void
520DefaultIEW<Impl>::block(ThreadID tid)
521{
522    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
523
524    if (dispatchStatus[tid] != Blocked &&
525        dispatchStatus[tid] != Unblocking) {
526        toRename->iewBlock[tid] = true;
527        wroteToTimeBuffer = true;
528    }
529
530    // Add the current inputs to the skid buffer so they can be
531    // reprocessed when this stage unblocks.
532    skidInsert(tid);
533
534    dispatchStatus[tid] = Blocked;
535}
536
537template<class Impl>
538void
539DefaultIEW<Impl>::unblock(ThreadID tid)
540{
541    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
542            "buffer %u.\n",tid, tid);
543
544    // If the skid bufffer is empty, signal back to previous stages to unblock.
545    // Also switch status to running.
546    if (skidBuffer[tid].empty()) {
547        toRename->iewUnblock[tid] = true;
548        wroteToTimeBuffer = true;
549        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
550        dispatchStatus[tid] = Running;
551    }
552}
553
554template<class Impl>
555void
556DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
557{
558    instQueue.wakeDependents(inst);
559}
560
561template<class Impl>
562void
563DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
564{
565    instQueue.rescheduleMemInst(inst);
566}
567
568template<class Impl>
569void
570DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
571{
572    instQueue.replayMemInst(inst);
573}
574
575template<class Impl>
576void
577DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
578{
579    // This function should not be called after writebackInsts in a
580    // single cycle.  That will cause problems with an instruction
581    // being added to the queue to commit without being processed by
582    // writebackInsts prior to being sent to commit.
583
584    // First check the time slot that this instruction will write
585    // to.  If there are free write ports at the time, then go ahead
586    // and write the instruction to that time.  If there are not,
587    // keep looking back to see where's the first time there's a
588    // free slot.
589    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
590        ++wbNumInst;
591        if (wbNumInst == wbWidth) {
592            ++wbCycle;
593            wbNumInst = 0;
594        }
595
596        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
597    }
598
599    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
600            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
601    // Add finished instruction to queue to commit.
602    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
603    (*iewQueue)[wbCycle].size++;
604}
605
606template <class Impl>
607unsigned
608DefaultIEW<Impl>::validInstsFromRename()
609{
610    unsigned inst_count = 0;
611
612    for (int i=0; i<fromRename->size; i++) {
613        if (!fromRename->insts[i]->isSquashed())
614            inst_count++;
615    }
616
617    return inst_count;
618}
619
620template<class Impl>
621void
622DefaultIEW<Impl>::skidInsert(ThreadID tid)
623{
624    DynInstPtr inst = NULL;
625
626    while (!insts[tid].empty()) {
627        inst = insts[tid].front();
628
629        insts[tid].pop();
630
631        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
632                "dispatch skidBuffer %i\n",tid, inst->seqNum,
633                inst->pcState(),tid);
634
635        skidBuffer[tid].push(inst);
636    }
637
638    assert(skidBuffer[tid].size() <= skidBufferMax &&
639           "Skidbuffer Exceeded Max Size");
640}
641
642template<class Impl>
643int
644DefaultIEW<Impl>::skidCount()
645{
646    int max=0;
647
648    list<ThreadID>::iterator threads = activeThreads->begin();
649    list<ThreadID>::iterator end = activeThreads->end();
650
651    while (threads != end) {
652        ThreadID tid = *threads++;
653        unsigned thread_count = skidBuffer[tid].size();
654        if (max < thread_count)
655            max = thread_count;
656    }
657
658    return max;
659}
660
661template<class Impl>
662bool
663DefaultIEW<Impl>::skidsEmpty()
664{
665    list<ThreadID>::iterator threads = activeThreads->begin();
666    list<ThreadID>::iterator end = activeThreads->end();
667
668    while (threads != end) {
669        ThreadID tid = *threads++;
670
671        if (!skidBuffer[tid].empty())
672            return false;
673    }
674
675    return true;
676}
677
678template <class Impl>
679void
680DefaultIEW<Impl>::updateStatus()
681{
682    bool any_unblocking = false;
683
684    list<ThreadID>::iterator threads = activeThreads->begin();
685    list<ThreadID>::iterator end = activeThreads->end();
686
687    while (threads != end) {
688        ThreadID tid = *threads++;
689
690        if (dispatchStatus[tid] == Unblocking) {
691            any_unblocking = true;
692            break;
693        }
694    }
695
696    // If there are no ready instructions waiting to be scheduled by the IQ,
697    // and there's no stores waiting to write back, and dispatch is not
698    // unblocking, then there is no internal activity for the IEW stage.
699    instQueue.intInstQueueReads++;
700    if (_status == Active && !instQueue.hasReadyInsts() &&
701        !ldstQueue.willWB() && !any_unblocking) {
702        DPRINTF(IEW, "IEW switching to idle\n");
703
704        deactivateStage();
705
706        _status = Inactive;
707    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
708                                       ldstQueue.willWB() ||
709                                       any_unblocking)) {
710        // Otherwise there is internal activity.  Set to active.
711        DPRINTF(IEW, "IEW switching to active\n");
712
713        activateStage();
714
715        _status = Active;
716    }
717}
718
719template <class Impl>
720void
721DefaultIEW<Impl>::resetEntries()
722{
723    instQueue.resetEntries();
724    ldstQueue.resetEntries();
725}
726
727template <class Impl>
728void
729DefaultIEW<Impl>::readStallSignals(ThreadID tid)
730{
731    if (fromCommit->commitBlock[tid]) {
732        stalls[tid].commit = true;
733    }
734
735    if (fromCommit->commitUnblock[tid]) {
736        assert(stalls[tid].commit);
737        stalls[tid].commit = false;
738    }
739}
740
741template <class Impl>
742bool
743DefaultIEW<Impl>::checkStall(ThreadID tid)
744{
745    bool ret_val(false);
746
747    if (stalls[tid].commit) {
748        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
749        ret_val = true;
750    } else if (instQueue.isFull(tid)) {
751        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
752        ret_val = true;
753    } else if (ldstQueue.isFull(tid)) {
754        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
755
756        if (ldstQueue.numLoads(tid) > 0 ) {
757
758            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
759                    tid,ldstQueue.getLoadHeadSeqNum(tid));
760        }
761
762        if (ldstQueue.numStores(tid) > 0) {
763
764            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
765                    tid,ldstQueue.getStoreHeadSeqNum(tid));
766        }
767
768        ret_val = true;
769    } else if (ldstQueue.isStalled(tid)) {
770        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
771        ret_val = true;
772    }
773
774    return ret_val;
775}
776
777template <class Impl>
778void
779DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
780{
781    // Check if there's a squash signal, squash if there is
782    // Check stall signals, block if there is.
783    // If status was Blocked
784    //     if so then go to unblocking
785    // If status was Squashing
786    //     check if squashing is not high.  Switch to running this cycle.
787
788    readStallSignals(tid);
789
790    if (fromCommit->commitInfo[tid].squash) {
791        squash(tid);
792
793        if (dispatchStatus[tid] == Blocked ||
794            dispatchStatus[tid] == Unblocking) {
795            toRename->iewUnblock[tid] = true;
796            wroteToTimeBuffer = true;
797        }
798
799        dispatchStatus[tid] = Squashing;
800        fetchRedirect[tid] = false;
801        return;
802    }
803
804    if (fromCommit->commitInfo[tid].robSquashing) {
805        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
806
807        dispatchStatus[tid] = Squashing;
808        emptyRenameInsts(tid);
809        wroteToTimeBuffer = true;
810        return;
811    }
812
813    if (checkStall(tid)) {
814        block(tid);
815        dispatchStatus[tid] = Blocked;
816        return;
817    }
818
819    if (dispatchStatus[tid] == Blocked) {
820        // Status from previous cycle was blocked, but there are no more stall
821        // conditions.  Switch over to unblocking.
822        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
823                tid);
824
825        dispatchStatus[tid] = Unblocking;
826
827        unblock(tid);
828
829        return;
830    }
831
832    if (dispatchStatus[tid] == Squashing) {
833        // Switch status to running if rename isn't being told to block or
834        // squash this cycle.
835        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
836                tid);
837
838        dispatchStatus[tid] = Running;
839
840        return;
841    }
842}
843
844template <class Impl>
845void
846DefaultIEW<Impl>::sortInsts()
847{
848    int insts_from_rename = fromRename->size;
849#ifdef DEBUG
850    for (ThreadID tid = 0; tid < numThreads; tid++)
851        assert(insts[tid].empty());
852#endif
853    for (int i = 0; i < insts_from_rename; ++i) {
854        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
855    }
856}
857
858template <class Impl>
859void
860DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
861{
862    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
863
864    while (!insts[tid].empty()) {
865
866        if (insts[tid].front()->isLoad() ||
867            insts[tid].front()->isStore() ) {
868            toRename->iewInfo[tid].dispatchedToLSQ++;
869        }
870
871        toRename->iewInfo[tid].dispatched++;
872
873        insts[tid].pop();
874    }
875}
876
877template <class Impl>
878void
879DefaultIEW<Impl>::wakeCPU()
880{
881    cpu->wakeCPU();
882}
883
884template <class Impl>
885void
886DefaultIEW<Impl>::activityThisCycle()
887{
888    DPRINTF(Activity, "Activity this cycle.\n");
889    cpu->activityThisCycle();
890}
891
892template <class Impl>
893inline void
894DefaultIEW<Impl>::activateStage()
895{
896    DPRINTF(Activity, "Activating stage.\n");
897    cpu->activateStage(O3CPU::IEWIdx);
898}
899
900template <class Impl>
901inline void
902DefaultIEW<Impl>::deactivateStage()
903{
904    DPRINTF(Activity, "Deactivating stage.\n");
905    cpu->deactivateStage(O3CPU::IEWIdx);
906}
907
908template<class Impl>
909void
910DefaultIEW<Impl>::dispatch(ThreadID tid)
911{
912    // If status is Running or idle,
913    //     call dispatchInsts()
914    // If status is Unblocking,
915    //     buffer any instructions coming from rename
916    //     continue trying to empty skid buffer
917    //     check if stall conditions have passed
918
919    if (dispatchStatus[tid] == Blocked) {
920        ++iewBlockCycles;
921
922    } else if (dispatchStatus[tid] == Squashing) {
923        ++iewSquashCycles;
924    }
925
926    // Dispatch should try to dispatch as many instructions as its bandwidth
927    // will allow, as long as it is not currently blocked.
928    if (dispatchStatus[tid] == Running ||
929        dispatchStatus[tid] == Idle) {
930        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
931                "dispatch.\n", tid);
932
933        dispatchInsts(tid);
934    } else if (dispatchStatus[tid] == Unblocking) {
935        // Make sure that the skid buffer has something in it if the
936        // status is unblocking.
937        assert(!skidsEmpty());
938
939        // If the status was unblocking, then instructions from the skid
940        // buffer were used.  Remove those instructions and handle
941        // the rest of unblocking.
942        dispatchInsts(tid);
943
944        ++iewUnblockCycles;
945
946        if (validInstsFromRename()) {
947            // Add the current inputs to the skid buffer so they can be
948            // reprocessed when this stage unblocks.
949            skidInsert(tid);
950        }
951
952        unblock(tid);
953    }
954}
955
956template <class Impl>
957void
958DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
959{
960    // Obtain instructions from skid buffer if unblocking, or queue from rename
961    // otherwise.
962    std::queue<DynInstPtr> &insts_to_dispatch =
963        dispatchStatus[tid] == Unblocking ?
964        skidBuffer[tid] : insts[tid];
965
966    int insts_to_add = insts_to_dispatch.size();
967
968    DynInstPtr inst;
969    bool add_to_iq = false;
970    int dis_num_inst = 0;
971
972    // Loop through the instructions, putting them in the instruction
973    // queue.
974    for ( ; dis_num_inst < insts_to_add &&
975              dis_num_inst < dispatchWidth;
976          ++dis_num_inst)
977    {
978        inst = insts_to_dispatch.front();
979
980        if (dispatchStatus[tid] == Unblocking) {
981            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
982                    "buffer\n", tid);
983        }
984
985        // Make sure there's a valid instruction there.
986        assert(inst);
987
988        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
989                "IQ.\n",
990                tid, inst->pcState(), inst->seqNum, inst->threadNumber);
991
992        // Be sure to mark these instructions as ready so that the
993        // commit stage can go ahead and execute them, and mark
994        // them as issued so the IQ doesn't reprocess them.
995
996        // Check for squashed instructions.
997        if (inst->isSquashed()) {
998            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
999                    "not adding to IQ.\n", tid);
1000
1001            ++iewDispSquashedInsts;
1002
1003            insts_to_dispatch.pop();
1004
1005            //Tell Rename That An Instruction has been processed
1006            if (inst->isLoad() || inst->isStore()) {
1007                toRename->iewInfo[tid].dispatchedToLSQ++;
1008            }
1009            toRename->iewInfo[tid].dispatched++;
1010
1011            continue;
1012        }
1013
1014        // Check for full conditions.
1015        if (instQueue.isFull(tid)) {
1016            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1017
1018            // Call function to start blocking.
1019            block(tid);
1020
1021            // Set unblock to false. Special case where we are using
1022            // skidbuffer (unblocking) instructions but then we still
1023            // get full in the IQ.
1024            toRename->iewUnblock[tid] = false;
1025
1026            ++iewIQFullEvents;
1027            break;
1028        } else if (ldstQueue.isFull(tid)) {
1029            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1030
1031            // Call function to start blocking.
1032            block(tid);
1033
1034            // Set unblock to false. Special case where we are using
1035            // skidbuffer (unblocking) instructions but then we still
1036            // get full in the IQ.
1037            toRename->iewUnblock[tid] = false;
1038
1039            ++iewLSQFullEvents;
1040            break;
1041        }
1042
1043        // Otherwise issue the instruction just fine.
1044        if (inst->isLoad()) {
1045            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1046                    "encountered, adding to LSQ.\n", tid);
1047
1048            // Reserve a spot in the load store queue for this
1049            // memory access.
1050            ldstQueue.insertLoad(inst);
1051
1052            ++iewDispLoadInsts;
1053
1054            add_to_iq = true;
1055
1056            toRename->iewInfo[tid].dispatchedToLSQ++;
1057        } else if (inst->isStore()) {
1058            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1059                    "encountered, adding to LSQ.\n", tid);
1060
1061            ldstQueue.insertStore(inst);
1062
1063            ++iewDispStoreInsts;
1064
1065            if (inst->isStoreConditional()) {
1066                // Store conditionals need to be set as "canCommit()"
1067                // so that commit can process them when they reach the
1068                // head of commit.
1069                // @todo: This is somewhat specific to Alpha.
1070                inst->setCanCommit();
1071                instQueue.insertNonSpec(inst);
1072                add_to_iq = false;
1073
1074                ++iewDispNonSpecInsts;
1075            } else {
1076                add_to_iq = true;
1077            }
1078
1079            toRename->iewInfo[tid].dispatchedToLSQ++;
1080        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1081            // Same as non-speculative stores.
1082            inst->setCanCommit();
1083            instQueue.insertBarrier(inst);
1084            add_to_iq = false;
1085        } else if (inst->isNop()) {
1086            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1087                    "skipping.\n", tid);
1088
1089            inst->setIssued();
1090            inst->setExecuted();
1091            inst->setCanCommit();
1092
1093            instQueue.recordProducer(inst);
1094
1095            iewExecutedNop[tid]++;
1096
1097            add_to_iq = false;
1098        } else if (inst->isExecuted()) {
1099            assert(0 && "Instruction shouldn't be executed.\n");
1100            DPRINTF(IEW, "Issue: Executed branch encountered, "
1101                    "skipping.\n");
1102
1103            inst->setIssued();
1104            inst->setCanCommit();
1105
1106            instQueue.recordProducer(inst);
1107
1108            add_to_iq = false;
1109        } else {
1110            add_to_iq = true;
1111        }
1112        if (inst->isNonSpeculative()) {
1113            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1114                    "encountered, skipping.\n", tid);
1115
1116            // Same as non-speculative stores.
1117            inst->setCanCommit();
1118
1119            // Specifically insert it as nonspeculative.
1120            instQueue.insertNonSpec(inst);
1121
1122            ++iewDispNonSpecInsts;
1123
1124            add_to_iq = false;
1125        }
1126
1127        // If the instruction queue is not full, then add the
1128        // instruction.
1129        if (add_to_iq) {
1130            instQueue.insert(inst);
1131        }
1132
1133        insts_to_dispatch.pop();
1134
1135        toRename->iewInfo[tid].dispatched++;
1136
1137        ++iewDispatchedInsts;
1138    }
1139
1140    if (!insts_to_dispatch.empty()) {
1141        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1142        block(tid);
1143        toRename->iewUnblock[tid] = false;
1144    }
1145
1146    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1147        dispatchStatus[tid] = Running;
1148
1149        updatedQueues = true;
1150    }
1151
1152    dis_num_inst = 0;
1153}
1154
1155template <class Impl>
1156void
1157DefaultIEW<Impl>::printAvailableInsts()
1158{
1159    int inst = 0;
1160
1161    std::cout << "Available Instructions: ";
1162
1163    while (fromIssue->insts[inst]) {
1164
1165        if (inst%3==0) std::cout << "\n\t";
1166
1167        std::cout << "PC: " << fromIssue->insts[inst]->pcState()
1168             << " TN: " << fromIssue->insts[inst]->threadNumber
1169             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1170
1171        inst++;
1172
1173    }
1174
1175    std::cout << "\n";
1176}
1177
1178template <class Impl>
1179void
1180DefaultIEW<Impl>::executeInsts()
1181{
1182    wbNumInst = 0;
1183    wbCycle = 0;
1184
1185    list<ThreadID>::iterator threads = activeThreads->begin();
1186    list<ThreadID>::iterator end = activeThreads->end();
1187
1188    while (threads != end) {
1189        ThreadID tid = *threads++;
1190        fetchRedirect[tid] = false;
1191    }
1192
1193    // Uncomment this if you want to see all available instructions.
1194    // @todo This doesn't actually work anymore, we should fix it.
1195//    printAvailableInsts();
1196
1197    // Execute/writeback any instructions that are available.
1198    int insts_to_execute = fromIssue->size;
1199    int inst_num = 0;
1200    for (; inst_num < insts_to_execute;
1201          ++inst_num) {
1202
1203        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1204
1205        DynInstPtr inst = instQueue.getInstToExecute();
1206
1207        DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
1208                inst->pcState(), inst->threadNumber,inst->seqNum);
1209
1210        // Check if the instruction is squashed; if so then skip it
1211        if (inst->isSquashed()) {
1212            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1213
1214            // Consider this instruction executed so that commit can go
1215            // ahead and retire the instruction.
1216            inst->setExecuted();
1217
1218            // Not sure if I should set this here or just let commit try to
1219            // commit any squashed instructions.  I like the latter a bit more.
1220            inst->setCanCommit();
1221
1222            ++iewExecSquashedInsts;
1223
1224            decrWb(inst->seqNum);
1225            continue;
1226        }
1227
1228        Fault fault = NoFault;
1229
1230        // Execute instruction.
1231        // Note that if the instruction faults, it will be handled
1232        // at the commit stage.
1233        if (inst->isMemRef()) {
1234            DPRINTF(IEW, "Execute: Calculating address for memory "
1235                    "reference.\n");
1236
1237            // Tell the LDSTQ to execute this instruction (if it is a load).
1238            if (inst->isLoad()) {
1239                // Loads will mark themselves as executed, and their writeback
1240                // event adds the instruction to the queue to commit
1241                fault = ldstQueue.executeLoad(inst);
1242
1243                if (inst->isTranslationDelayed() &&
1244                    fault == NoFault) {
1245                    // A hw page table walk is currently going on; the
1246                    // instruction must be deferred.
1247                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1248                            "load.\n");
1249                    instQueue.deferMemInst(inst);
1250                    continue;
1251                }
1252
1253                if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
1254                    inst->fault = NoFault;
1255                }
1256            } else if (inst->isStore()) {
1257                fault = ldstQueue.executeStore(inst);
1258
1259                if (inst->isTranslationDelayed() &&
1260                    fault == NoFault) {
1261                    // A hw page table walk is currently going on; the
1262                    // instruction must be deferred.
1263                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
1264                            "store.\n");
1265                    instQueue.deferMemInst(inst);
1266                    continue;
1267                }
1268
1269                // If the store had a fault then it may not have a mem req
1270                if (fault != NoFault || inst->readPredicate() == false ||
1271                        !inst->isStoreConditional()) {
1272                    // If the instruction faulted, then we need to send it along
1273                    // to commit without the instruction completing.
1274                    // Send this instruction to commit, also make sure iew stage
1275                    // realizes there is activity.
1276                    inst->setExecuted();
1277                    instToCommit(inst);
1278                    activityThisCycle();
1279                }
1280
1281                // Store conditionals will mark themselves as
1282                // executed, and their writeback event will add the
1283                // instruction to the queue to commit.
1284            } else {
1285                panic("Unexpected memory type!\n");
1286            }
1287
1288        } else {
1289            // If the instruction has already faulted, then skip executing it.
1290            // Such case can happen when it faulted during ITLB translation.
1291            // If we execute the instruction (even if it's a nop) the fault
1292            // will be replaced and we will lose it.
1293            if (inst->getFault() == NoFault) {
1294                inst->execute();
1295                if (inst->readPredicate() == false)
1296                    inst->forwardOldRegs();
1297            }
1298
1299            inst->setExecuted();
1300
1301            instToCommit(inst);
1302        }
1303
1304        updateExeInstStats(inst);
1305
1306        // Check if branch prediction was correct, if not then we need
1307        // to tell commit to squash in flight instructions.  Only
1308        // handle this if there hasn't already been something that
1309        // redirects fetch in this group of instructions.
1310
1311        // This probably needs to prioritize the redirects if a different
1312        // scheduler is used.  Currently the scheduler schedules the oldest
1313        // instruction first, so the branch resolution order will be correct.
1314        ThreadID tid = inst->threadNumber;
1315
1316        if (!fetchRedirect[tid] ||
1317            !toCommit->squash[tid] ||
1318            toCommit->squashedSeqNum[tid] > inst->seqNum) {
1319
1320            // Prevent testing for misprediction on load instructions,
1321            // that have not been executed.
1322            bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
1323
1324            if (inst->mispredicted() && !loadNotExecuted) {
1325                fetchRedirect[tid] = true;
1326
1327                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1328                DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1329                        inst->predInstAddr(), inst->predNextInstAddr());
1330                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
1331                        inst->pcState(), inst->nextInstAddr());
1332                // If incorrect, then signal the ROB that it must be squashed.
1333                squashDueToBranch(inst, tid);
1334
1335                if (inst->readPredTaken()) {
1336                    predictedTakenIncorrect++;
1337                } else {
1338                    predictedNotTakenIncorrect++;
1339                }
1340            } else if (ldstQueue.violation(tid)) {
1341                assert(inst->isMemRef());
1342                // If there was an ordering violation, then get the
1343                // DynInst that caused the violation.  Note that this
1344                // clears the violation signal.
1345                DynInstPtr violator;
1346                violator = ldstQueue.getMemDepViolator(tid);
1347
1348                DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
1349                        "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
1350                        violator->pcState(), violator->seqNum,
1351                        inst->pcState(), inst->seqNum, inst->physEffAddr);
1352
1353                fetchRedirect[tid] = true;
1354
1355                // Tell the instruction queue that a violation has occured.
1356                instQueue.violation(inst, violator);
1357
1358                // Squash.
1359                squashDueToMemOrder(inst,tid);
1360
1361                ++memOrderViolationEvents;
1362            } else if (ldstQueue.loadBlocked(tid) &&
1363                       !ldstQueue.isLoadBlockedHandled(tid)) {
1364                fetchRedirect[tid] = true;
1365
1366                DPRINTF(IEW, "Load operation couldn't execute because the "
1367                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1368                        inst->pcState(), inst->seqNum);
1369
1370                squashDueToMemBlocked(inst, tid);
1371            }
1372        } else {
1373            // Reset any state associated with redirects that will not
1374            // be used.
1375            if (ldstQueue.violation(tid)) {
1376                assert(inst->isMemRef());
1377
1378                DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1379
1380                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1381                        "%s, inst PC: %s.  Addr is: %#x.\n",
1382                        violator->pcState(), inst->pcState(),
1383                        inst->physEffAddr);
1384                DPRINTF(IEW, "Violation will not be handled because "
1385                        "already squashing\n");
1386
1387                ++memOrderViolationEvents;
1388            }
1389            if (ldstQueue.loadBlocked(tid) &&
1390                !ldstQueue.isLoadBlockedHandled(tid)) {
1391                DPRINTF(IEW, "Load operation couldn't execute because the "
1392                        "memory system is blocked.  PC: %s [sn:%lli]\n",
1393                        inst->pcState(), inst->seqNum);
1394                DPRINTF(IEW, "Blocked load will not be handled because "
1395                        "already squashing\n");
1396
1397                ldstQueue.setLoadBlockedHandled(tid);
1398            }
1399
1400        }
1401    }
1402
1403    // Update and record activity if we processed any instructions.
1404    if (inst_num) {
1405        if (exeStatus == Idle) {
1406            exeStatus = Running;
1407        }
1408
1409        updatedQueues = true;
1410
1411        cpu->activityThisCycle();
1412    }
1413
1414    // Need to reset this in case a writeback event needs to write into the
1415    // iew queue.  That way the writeback event will write into the correct
1416    // spot in the queue.
1417    wbNumInst = 0;
1418
1419}
1420
1421template <class Impl>
1422void
1423DefaultIEW<Impl>::writebackInsts()
1424{
1425    // Loop through the head of the time buffer and wake any
1426    // dependents.  These instructions are about to write back.  Also
1427    // mark scoreboard that this instruction is finally complete.
1428    // Either have IEW have direct access to scoreboard, or have this
1429    // as part of backwards communication.
1430    for (int inst_num = 0; inst_num < wbWidth &&
1431             toCommit->insts[inst_num]; inst_num++) {
1432        DynInstPtr inst = toCommit->insts[inst_num];
1433        ThreadID tid = inst->threadNumber;
1434
1435        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
1436                inst->seqNum, inst->pcState());
1437
1438        iewInstsToCommit[tid]++;
1439
1440        // Some instructions will be sent to commit without having
1441        // executed because they need commit to handle them.
1442        // E.g. Uncached loads have not actually executed when they
1443        // are first sent to commit.  Instead commit must tell the LSQ
1444        // when it's ready to execute the uncached load.
1445        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1446            int dependents = instQueue.wakeDependents(inst);
1447
1448            for (int i = 0; i < inst->numDestRegs(); i++) {
1449                //mark as Ready
1450                DPRINTF(IEW,"Setting Destination Register %i\n",
1451                        inst->renamedDestRegIdx(i));
1452                scoreboard->setReg(inst->renamedDestRegIdx(i));
1453            }
1454
1455            if (dependents) {
1456                producerInst[tid]++;
1457                consumerInst[tid]+= dependents;
1458            }
1459            writebackCount[tid]++;
1460        }
1461
1462        decrWb(inst->seqNum);
1463    }
1464}
1465
1466template<class Impl>
1467void
1468DefaultIEW<Impl>::tick()
1469{
1470    wbNumInst = 0;
1471    wbCycle = 0;
1472
1473    wroteToTimeBuffer = false;
1474    updatedQueues = false;
1475
1476    sortInsts();
1477
1478    // Free function units marked as being freed this cycle.
1479    fuPool->processFreeUnits();
1480
1481    list<ThreadID>::iterator threads = activeThreads->begin();
1482    list<ThreadID>::iterator end = activeThreads->end();
1483
1484    // Check stall and squash signals, dispatch any instructions.
1485    while (threads != end) {
1486        ThreadID tid = *threads++;
1487
1488        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1489
1490        checkSignalsAndUpdate(tid);
1491        dispatch(tid);
1492    }
1493
1494    if (exeStatus != Squashing) {
1495        executeInsts();
1496
1497        writebackInsts();
1498
1499        // Have the instruction queue try to schedule any ready instructions.
1500        // (In actuality, this scheduling is for instructions that will
1501        // be executed next cycle.)
1502        instQueue.scheduleReadyInsts();
1503
1504        // Also should advance its own time buffers if the stage ran.
1505        // Not the best place for it, but this works (hopefully).
1506        issueToExecQueue.advance();
1507    }
1508
1509    bool broadcast_free_entries = false;
1510
1511    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1512        exeStatus = Idle;
1513        updateLSQNextCycle = false;
1514
1515        broadcast_free_entries = true;
1516    }
1517
1518    // Writeback any stores using any leftover bandwidth.
1519    ldstQueue.writebackStores();
1520
1521    // Check the committed load/store signals to see if there's a load
1522    // or store to commit.  Also check if it's being told to execute a
1523    // nonspeculative instruction.
1524    // This is pretty inefficient...
1525
1526    threads = activeThreads->begin();
1527    while (threads != end) {
1528        ThreadID tid = (*threads++);
1529
1530        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1531
1532        // Update structures based on instructions committed.
1533        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1534            !fromCommit->commitInfo[tid].squash &&
1535            !fromCommit->commitInfo[tid].robSquashing) {
1536
1537            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1538
1539            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1540
1541            updateLSQNextCycle = true;
1542            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1543        }
1544
1545        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1546
1547            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1548            if (fromCommit->commitInfo[tid].uncached) {
1549                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1550                fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1551            } else {
1552                instQueue.scheduleNonSpec(
1553                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1554            }
1555        }
1556
1557        if (broadcast_free_entries) {
1558            toFetch->iewInfo[tid].iqCount =
1559                instQueue.getCount(tid);
1560            toFetch->iewInfo[tid].ldstqCount =
1561                ldstQueue.getCount(tid);
1562
1563            toRename->iewInfo[tid].usedIQ = true;
1564            toRename->iewInfo[tid].freeIQEntries =
1565                instQueue.numFreeEntries();
1566            toRename->iewInfo[tid].usedLSQ = true;
1567            toRename->iewInfo[tid].freeLSQEntries =
1568                ldstQueue.numFreeEntries(tid);
1569
1570            wroteToTimeBuffer = true;
1571        }
1572
1573        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1574                tid, toRename->iewInfo[tid].dispatched);
1575    }
1576
1577    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1578            "LSQ has %i free entries.\n",
1579            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1580            ldstQueue.numFreeEntries());
1581
1582    updateStatus();
1583
1584    if (wroteToTimeBuffer) {
1585        DPRINTF(Activity, "Activity this cycle.\n");
1586        cpu->activityThisCycle();
1587    }
1588}
1589
1590template <class Impl>
1591void
1592DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1593{
1594    ThreadID tid = inst->threadNumber;
1595
1596    //
1597    //  Pick off the software prefetches
1598    //
1599#ifdef TARGET_ALPHA
1600    if (inst->isDataPrefetch())
1601        iewExecutedSwp[tid]++;
1602    else
1603        iewIewExecutedcutedInsts++;
1604#else
1605    iewExecutedInsts++;
1606#endif
1607
1608    //
1609    //  Control operations
1610    //
1611    if (inst->isControl())
1612        iewExecutedBranches[tid]++;
1613
1614    //
1615    //  Memory operations
1616    //
1617    if (inst->isMemRef()) {
1618        iewExecutedRefs[tid]++;
1619
1620        if (inst->isLoad()) {
1621            iewExecLoadInsts[tid]++;
1622        }
1623    }
1624}
1625
1626template <class Impl>
1627void
1628DefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
1629{
1630    ThreadID tid = inst->threadNumber;
1631
1632    if (!fetchRedirect[tid] ||
1633        !toCommit->squash[tid] ||
1634        toCommit->squashedSeqNum[tid] > inst->seqNum) {
1635
1636        if (inst->mispredicted()) {
1637            fetchRedirect[tid] = true;
1638
1639            DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1640            DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1641                    inst->predInstAddr(), inst->predNextInstAddr());
1642            DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1643                    " NPC: %#x.\n", inst->nextInstAddr(),
1644                    inst->nextInstAddr());
1645            // If incorrect, then signal the ROB that it must be squashed.
1646            squashDueToBranch(inst, tid);
1647
1648            if (inst->readPredTaken()) {
1649                predictedTakenIncorrect++;
1650            } else {
1651                predictedNotTakenIncorrect++;
1652            }
1653        }
1654    }
1655}
1656