iew_impl.hh revision 6221 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31// @todo: Fix the instantaneous communication among all the stages within
32// iew.  There's a clear delay between issue and execute, yet backwards
33// communication happens simultaneously.
34
35#include <queue>
36
37#include "base/timebuf.hh"
38#include "cpu/o3/fu_pool.hh"
39#include "cpu/o3/iew.hh"
40#include "params/DerivO3CPU.hh"
41
42using namespace std;
43
44template<class Impl>
45DefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
46    : issueToExecQueue(params->backComSize, params->forwardComSize),
47      cpu(_cpu),
48      instQueue(_cpu, this, params),
49      ldstQueue(_cpu, this, params),
50      fuPool(params->fuPool),
51      commitToIEWDelay(params->commitToIEWDelay),
52      renameToIEWDelay(params->renameToIEWDelay),
53      issueToExecuteDelay(params->issueToExecuteDelay),
54      dispatchWidth(params->dispatchWidth),
55      issueWidth(params->issueWidth),
56      wbOutstanding(0),
57      wbWidth(params->wbWidth),
58      numThreads(params->numThreads),
59      switchedOut(false)
60{
61    _status = Active;
62    exeStatus = Running;
63    wbStatus = Idle;
64
65    // Setup wire to read instructions coming from issue.
66    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
67
68    // Instruction queue needs the queue between issue and execute.
69    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
70
71    for (ThreadID tid = 0; tid < numThreads; tid++) {
72        dispatchStatus[tid] = Running;
73        stalls[tid].commit = false;
74        fetchRedirect[tid] = false;
75    }
76
77    wbMax = wbWidth * params->wbDepth;
78
79    updateLSQNextCycle = false;
80
81    ableToIssue = true;
82
83    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
84}
85
86template <class Impl>
87std::string
88DefaultIEW<Impl>::name() const
89{
90    return cpu->name() + ".iew";
91}
92
93template <class Impl>
94void
95DefaultIEW<Impl>::regStats()
96{
97    using namespace Stats;
98
99    instQueue.regStats();
100    ldstQueue.regStats();
101
102    iewIdleCycles
103        .name(name() + ".iewIdleCycles")
104        .desc("Number of cycles IEW is idle");
105
106    iewSquashCycles
107        .name(name() + ".iewSquashCycles")
108        .desc("Number of cycles IEW is squashing");
109
110    iewBlockCycles
111        .name(name() + ".iewBlockCycles")
112        .desc("Number of cycles IEW is blocking");
113
114    iewUnblockCycles
115        .name(name() + ".iewUnblockCycles")
116        .desc("Number of cycles IEW is unblocking");
117
118    iewDispatchedInsts
119        .name(name() + ".iewDispatchedInsts")
120        .desc("Number of instructions dispatched to IQ");
121
122    iewDispSquashedInsts
123        .name(name() + ".iewDispSquashedInsts")
124        .desc("Number of squashed instructions skipped by dispatch");
125
126    iewDispLoadInsts
127        .name(name() + ".iewDispLoadInsts")
128        .desc("Number of dispatched load instructions");
129
130    iewDispStoreInsts
131        .name(name() + ".iewDispStoreInsts")
132        .desc("Number of dispatched store instructions");
133
134    iewDispNonSpecInsts
135        .name(name() + ".iewDispNonSpecInsts")
136        .desc("Number of dispatched non-speculative instructions");
137
138    iewIQFullEvents
139        .name(name() + ".iewIQFullEvents")
140        .desc("Number of times the IQ has become full, causing a stall");
141
142    iewLSQFullEvents
143        .name(name() + ".iewLSQFullEvents")
144        .desc("Number of times the LSQ has become full, causing a stall");
145
146    memOrderViolationEvents
147        .name(name() + ".memOrderViolationEvents")
148        .desc("Number of memory order violations");
149
150    predictedTakenIncorrect
151        .name(name() + ".predictedTakenIncorrect")
152        .desc("Number of branches that were predicted taken incorrectly");
153
154    predictedNotTakenIncorrect
155        .name(name() + ".predictedNotTakenIncorrect")
156        .desc("Number of branches that were predicted not taken incorrectly");
157
158    branchMispredicts
159        .name(name() + ".branchMispredicts")
160        .desc("Number of branch mispredicts detected at execute");
161
162    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
163
164    iewExecutedInsts
165        .name(name() + ".iewExecutedInsts")
166        .desc("Number of executed instructions");
167
168    iewExecLoadInsts
169        .init(cpu->numThreads)
170        .name(name() + ".iewExecLoadInsts")
171        .desc("Number of load instructions executed")
172        .flags(total);
173
174    iewExecSquashedInsts
175        .name(name() + ".iewExecSquashedInsts")
176        .desc("Number of squashed instructions skipped in execute");
177
178    iewExecutedSwp
179        .init(cpu->numThreads)
180        .name(name() + ".EXEC:swp")
181        .desc("number of swp insts executed")
182        .flags(total);
183
184    iewExecutedNop
185        .init(cpu->numThreads)
186        .name(name() + ".EXEC:nop")
187        .desc("number of nop insts executed")
188        .flags(total);
189
190    iewExecutedRefs
191        .init(cpu->numThreads)
192        .name(name() + ".EXEC:refs")
193        .desc("number of memory reference insts executed")
194        .flags(total);
195
196    iewExecutedBranches
197        .init(cpu->numThreads)
198        .name(name() + ".EXEC:branches")
199        .desc("Number of branches executed")
200        .flags(total);
201
202    iewExecStoreInsts
203        .name(name() + ".EXEC:stores")
204        .desc("Number of stores executed")
205        .flags(total);
206    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
207
208    iewExecRate
209        .name(name() + ".EXEC:rate")
210        .desc("Inst execution rate")
211        .flags(total);
212
213    iewExecRate = iewExecutedInsts / cpu->numCycles;
214
215    iewInstsToCommit
216        .init(cpu->numThreads)
217        .name(name() + ".WB:sent")
218        .desc("cumulative count of insts sent to commit")
219        .flags(total);
220
221    writebackCount
222        .init(cpu->numThreads)
223        .name(name() + ".WB:count")
224        .desc("cumulative count of insts written-back")
225        .flags(total);
226
227    producerInst
228        .init(cpu->numThreads)
229        .name(name() + ".WB:producers")
230        .desc("num instructions producing a value")
231        .flags(total);
232
233    consumerInst
234        .init(cpu->numThreads)
235        .name(name() + ".WB:consumers")
236        .desc("num instructions consuming a value")
237        .flags(total);
238
239    wbPenalized
240        .init(cpu->numThreads)
241        .name(name() + ".WB:penalized")
242        .desc("number of instrctions required to write to 'other' IQ")
243        .flags(total);
244
245    wbPenalizedRate
246        .name(name() + ".WB:penalized_rate")
247        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
248        .flags(total);
249
250    wbPenalizedRate = wbPenalized / writebackCount;
251
252    wbFanout
253        .name(name() + ".WB:fanout")
254        .desc("average fanout of values written-back")
255        .flags(total);
256
257    wbFanout = producerInst / consumerInst;
258
259    wbRate
260        .name(name() + ".WB:rate")
261        .desc("insts written-back per cycle")
262        .flags(total);
263    wbRate = writebackCount / cpu->numCycles;
264}
265
266template<class Impl>
267void
268DefaultIEW<Impl>::initStage()
269{
270    for (ThreadID tid = 0; tid < numThreads; tid++) {
271        toRename->iewInfo[tid].usedIQ = true;
272        toRename->iewInfo[tid].freeIQEntries =
273            instQueue.numFreeEntries(tid);
274
275        toRename->iewInfo[tid].usedLSQ = true;
276        toRename->iewInfo[tid].freeLSQEntries =
277            ldstQueue.numFreeEntries(tid);
278    }
279
280    cpu->activateStage(O3CPU::IEWIdx);
281}
282
283template<class Impl>
284void
285DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
286{
287    timeBuffer = tb_ptr;
288
289    // Setup wire to read information from time buffer, from commit.
290    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
291
292    // Setup wire to write information back to previous stages.
293    toRename = timeBuffer->getWire(0);
294
295    toFetch = timeBuffer->getWire(0);
296
297    // Instruction queue also needs main time buffer.
298    instQueue.setTimeBuffer(tb_ptr);
299}
300
301template<class Impl>
302void
303DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
304{
305    renameQueue = rq_ptr;
306
307    // Setup wire to read information from rename queue.
308    fromRename = renameQueue->getWire(-renameToIEWDelay);
309}
310
311template<class Impl>
312void
313DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
314{
315    iewQueue = iq_ptr;
316
317    // Setup wire to write instructions to commit.
318    toCommit = iewQueue->getWire(0);
319}
320
321template<class Impl>
322void
323DefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
324{
325    activeThreads = at_ptr;
326
327    ldstQueue.setActiveThreads(at_ptr);
328    instQueue.setActiveThreads(at_ptr);
329}
330
331template<class Impl>
332void
333DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
334{
335    scoreboard = sb_ptr;
336}
337
338template <class Impl>
339bool
340DefaultIEW<Impl>::drain()
341{
342    // IEW is ready to drain at any time.
343    cpu->signalDrained();
344    return true;
345}
346
347template <class Impl>
348void
349DefaultIEW<Impl>::resume()
350{
351}
352
353template <class Impl>
354void
355DefaultIEW<Impl>::switchOut()
356{
357    // Clear any state.
358    switchedOut = true;
359    assert(insts[0].empty());
360    assert(skidBuffer[0].empty());
361
362    instQueue.switchOut();
363    ldstQueue.switchOut();
364    fuPool->switchOut();
365
366    for (ThreadID tid = 0; tid < numThreads; tid++) {
367        while (!insts[tid].empty())
368            insts[tid].pop();
369        while (!skidBuffer[tid].empty())
370            skidBuffer[tid].pop();
371    }
372}
373
374template <class Impl>
375void
376DefaultIEW<Impl>::takeOverFrom()
377{
378    // Reset all state.
379    _status = Active;
380    exeStatus = Running;
381    wbStatus = Idle;
382    switchedOut = false;
383
384    instQueue.takeOverFrom();
385    ldstQueue.takeOverFrom();
386    fuPool->takeOverFrom();
387
388    initStage();
389    cpu->activityThisCycle();
390
391    for (ThreadID tid = 0; tid < numThreads; tid++) {
392        dispatchStatus[tid] = Running;
393        stalls[tid].commit = false;
394        fetchRedirect[tid] = false;
395    }
396
397    updateLSQNextCycle = false;
398
399    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
400        issueToExecQueue.advance();
401    }
402}
403
404template<class Impl>
405void
406DefaultIEW<Impl>::squash(ThreadID tid)
407{
408    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
409
410    // Tell the IQ to start squashing.
411    instQueue.squash(tid);
412
413    // Tell the LDSTQ to start squashing.
414    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
415    updatedQueues = true;
416
417    // Clear the skid buffer in case it has any data in it.
418    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
419            tid, fromCommit->commitInfo[tid].doneSeqNum);
420
421    while (!skidBuffer[tid].empty()) {
422        if (skidBuffer[tid].front()->isLoad() ||
423            skidBuffer[tid].front()->isStore() ) {
424            toRename->iewInfo[tid].dispatchedToLSQ++;
425        }
426
427        toRename->iewInfo[tid].dispatched++;
428
429        skidBuffer[tid].pop();
430    }
431
432    emptyRenameInsts(tid);
433}
434
435template<class Impl>
436void
437DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
438{
439    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x "
440            "[sn:%i].\n", tid, inst->readPC(), inst->seqNum);
441
442    toCommit->squash[tid] = true;
443    toCommit->squashedSeqNum[tid] = inst->seqNum;
444    toCommit->mispredPC[tid] = inst->readPC();
445    toCommit->branchMispredict[tid] = true;
446
447#if ISA_HAS_DELAY_SLOT
448    int instSize = sizeof(TheISA::MachInst);
449    toCommit->branchTaken[tid] =
450        !(inst->readNextPC() + instSize == inst->readNextNPC() &&
451          (inst->readNextPC() == inst->readPC() + instSize ||
452           inst->readNextPC() == inst->readPC() + 2 * instSize));
453#else
454    toCommit->branchTaken[tid] = inst->readNextPC() !=
455        (inst->readPC() + sizeof(TheISA::MachInst));
456#endif
457    toCommit->nextPC[tid] = inst->readNextPC();
458    toCommit->nextNPC[tid] = inst->readNextNPC();
459    toCommit->nextMicroPC[tid] = inst->readNextMicroPC();
460
461    toCommit->includeSquashInst[tid] = false;
462
463    wroteToTimeBuffer = true;
464}
465
466template<class Impl>
467void
468DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
469{
470    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, "
471            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
472
473    toCommit->squash[tid] = true;
474    toCommit->squashedSeqNum[tid] = inst->seqNum;
475    toCommit->nextPC[tid] = inst->readNextPC();
476    toCommit->nextNPC[tid] = inst->readNextNPC();
477    toCommit->branchMispredict[tid] = false;
478
479    toCommit->includeSquashInst[tid] = false;
480
481    wroteToTimeBuffer = true;
482}
483
484template<class Impl>
485void
486DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
487{
488    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
489            "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum);
490
491    toCommit->squash[tid] = true;
492    toCommit->squashedSeqNum[tid] = inst->seqNum;
493    toCommit->nextPC[tid] = inst->readPC();
494    toCommit->nextNPC[tid] = inst->readNextPC();
495    toCommit->branchMispredict[tid] = false;
496
497    // Must include the broadcasted SN in the squash.
498    toCommit->includeSquashInst[tid] = true;
499
500    ldstQueue.setLoadBlockedHandled(tid);
501
502    wroteToTimeBuffer = true;
503}
504
505template<class Impl>
506void
507DefaultIEW<Impl>::block(ThreadID tid)
508{
509    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
510
511    if (dispatchStatus[tid] != Blocked &&
512        dispatchStatus[tid] != Unblocking) {
513        toRename->iewBlock[tid] = true;
514        wroteToTimeBuffer = true;
515    }
516
517    // Add the current inputs to the skid buffer so they can be
518    // reprocessed when this stage unblocks.
519    skidInsert(tid);
520
521    dispatchStatus[tid] = Blocked;
522}
523
524template<class Impl>
525void
526DefaultIEW<Impl>::unblock(ThreadID tid)
527{
528    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
529            "buffer %u.\n",tid, tid);
530
531    // If the skid bufffer is empty, signal back to previous stages to unblock.
532    // Also switch status to running.
533    if (skidBuffer[tid].empty()) {
534        toRename->iewUnblock[tid] = true;
535        wroteToTimeBuffer = true;
536        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
537        dispatchStatus[tid] = Running;
538    }
539}
540
541template<class Impl>
542void
543DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
544{
545    instQueue.wakeDependents(inst);
546}
547
548template<class Impl>
549void
550DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
551{
552    instQueue.rescheduleMemInst(inst);
553}
554
555template<class Impl>
556void
557DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
558{
559    instQueue.replayMemInst(inst);
560}
561
562template<class Impl>
563void
564DefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
565{
566    // This function should not be called after writebackInsts in a
567    // single cycle.  That will cause problems with an instruction
568    // being added to the queue to commit without being processed by
569    // writebackInsts prior to being sent to commit.
570
571    // First check the time slot that this instruction will write
572    // to.  If there are free write ports at the time, then go ahead
573    // and write the instruction to that time.  If there are not,
574    // keep looking back to see where's the first time there's a
575    // free slot.
576    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
577        ++wbNumInst;
578        if (wbNumInst == wbWidth) {
579            ++wbCycle;
580            wbNumInst = 0;
581        }
582
583        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
584    }
585
586    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
587            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
588    // Add finished instruction to queue to commit.
589    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
590    (*iewQueue)[wbCycle].size++;
591}
592
593template <class Impl>
594unsigned
595DefaultIEW<Impl>::validInstsFromRename()
596{
597    unsigned inst_count = 0;
598
599    for (int i=0; i<fromRename->size; i++) {
600        if (!fromRename->insts[i]->isSquashed())
601            inst_count++;
602    }
603
604    return inst_count;
605}
606
607template<class Impl>
608void
609DefaultIEW<Impl>::skidInsert(ThreadID tid)
610{
611    DynInstPtr inst = NULL;
612
613    while (!insts[tid].empty()) {
614        inst = insts[tid].front();
615
616        insts[tid].pop();
617
618        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into "
619                "dispatch skidBuffer %i\n",tid, inst->seqNum,
620                inst->readPC(),tid);
621
622        skidBuffer[tid].push(inst);
623    }
624
625    assert(skidBuffer[tid].size() <= skidBufferMax &&
626           "Skidbuffer Exceeded Max Size");
627}
628
629template<class Impl>
630int
631DefaultIEW<Impl>::skidCount()
632{
633    int max=0;
634
635    list<ThreadID>::iterator threads = activeThreads->begin();
636    list<ThreadID>::iterator end = activeThreads->end();
637
638    while (threads != end) {
639        ThreadID tid = *threads++;
640        unsigned thread_count = skidBuffer[tid].size();
641        if (max < thread_count)
642            max = thread_count;
643    }
644
645    return max;
646}
647
648template<class Impl>
649bool
650DefaultIEW<Impl>::skidsEmpty()
651{
652    list<ThreadID>::iterator threads = activeThreads->begin();
653    list<ThreadID>::iterator end = activeThreads->end();
654
655    while (threads != end) {
656        ThreadID tid = *threads++;
657
658        if (!skidBuffer[tid].empty())
659            return false;
660    }
661
662    return true;
663}
664
665template <class Impl>
666void
667DefaultIEW<Impl>::updateStatus()
668{
669    bool any_unblocking = false;
670
671    list<ThreadID>::iterator threads = activeThreads->begin();
672    list<ThreadID>::iterator end = activeThreads->end();
673
674    while (threads != end) {
675        ThreadID tid = *threads++;
676
677        if (dispatchStatus[tid] == Unblocking) {
678            any_unblocking = true;
679            break;
680        }
681    }
682
683    // If there are no ready instructions waiting to be scheduled by the IQ,
684    // and there's no stores waiting to write back, and dispatch is not
685    // unblocking, then there is no internal activity for the IEW stage.
686    if (_status == Active && !instQueue.hasReadyInsts() &&
687        !ldstQueue.willWB() && !any_unblocking) {
688        DPRINTF(IEW, "IEW switching to idle\n");
689
690        deactivateStage();
691
692        _status = Inactive;
693    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
694                                       ldstQueue.willWB() ||
695                                       any_unblocking)) {
696        // Otherwise there is internal activity.  Set to active.
697        DPRINTF(IEW, "IEW switching to active\n");
698
699        activateStage();
700
701        _status = Active;
702    }
703}
704
705template <class Impl>
706void
707DefaultIEW<Impl>::resetEntries()
708{
709    instQueue.resetEntries();
710    ldstQueue.resetEntries();
711}
712
713template <class Impl>
714void
715DefaultIEW<Impl>::readStallSignals(ThreadID tid)
716{
717    if (fromCommit->commitBlock[tid]) {
718        stalls[tid].commit = true;
719    }
720
721    if (fromCommit->commitUnblock[tid]) {
722        assert(stalls[tid].commit);
723        stalls[tid].commit = false;
724    }
725}
726
727template <class Impl>
728bool
729DefaultIEW<Impl>::checkStall(ThreadID tid)
730{
731    bool ret_val(false);
732
733    if (stalls[tid].commit) {
734        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
735        ret_val = true;
736    } else if (instQueue.isFull(tid)) {
737        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
738        ret_val = true;
739    } else if (ldstQueue.isFull(tid)) {
740        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
741
742        if (ldstQueue.numLoads(tid) > 0 ) {
743
744            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
745                    tid,ldstQueue.getLoadHeadSeqNum(tid));
746        }
747
748        if (ldstQueue.numStores(tid) > 0) {
749
750            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
751                    tid,ldstQueue.getStoreHeadSeqNum(tid));
752        }
753
754        ret_val = true;
755    } else if (ldstQueue.isStalled(tid)) {
756        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
757        ret_val = true;
758    }
759
760    return ret_val;
761}
762
763template <class Impl>
764void
765DefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
766{
767    // Check if there's a squash signal, squash if there is
768    // Check stall signals, block if there is.
769    // If status was Blocked
770    //     if so then go to unblocking
771    // If status was Squashing
772    //     check if squashing is not high.  Switch to running this cycle.
773
774    readStallSignals(tid);
775
776    if (fromCommit->commitInfo[tid].squash) {
777        squash(tid);
778
779        if (dispatchStatus[tid] == Blocked ||
780            dispatchStatus[tid] == Unblocking) {
781            toRename->iewUnblock[tid] = true;
782            wroteToTimeBuffer = true;
783        }
784
785        dispatchStatus[tid] = Squashing;
786
787        fetchRedirect[tid] = false;
788        return;
789    }
790
791    if (fromCommit->commitInfo[tid].robSquashing) {
792        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
793
794        dispatchStatus[tid] = Squashing;
795
796        emptyRenameInsts(tid);
797        wroteToTimeBuffer = true;
798        return;
799    }
800
801    if (checkStall(tid)) {
802        block(tid);
803        dispatchStatus[tid] = Blocked;
804        return;
805    }
806
807    if (dispatchStatus[tid] == Blocked) {
808        // Status from previous cycle was blocked, but there are no more stall
809        // conditions.  Switch over to unblocking.
810        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
811                tid);
812
813        dispatchStatus[tid] = Unblocking;
814
815        unblock(tid);
816
817        return;
818    }
819
820    if (dispatchStatus[tid] == Squashing) {
821        // Switch status to running if rename isn't being told to block or
822        // squash this cycle.
823        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
824                tid);
825
826        dispatchStatus[tid] = Running;
827
828        return;
829    }
830}
831
832template <class Impl>
833void
834DefaultIEW<Impl>::sortInsts()
835{
836    int insts_from_rename = fromRename->size;
837#ifdef DEBUG
838    for (ThreadID tid = 0; tid < numThreads; tid++)
839        assert(insts[tid].empty());
840#endif
841    for (int i = 0; i < insts_from_rename; ++i) {
842        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
843    }
844}
845
846template <class Impl>
847void
848DefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
849{
850    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
851
852    while (!insts[tid].empty()) {
853
854        if (insts[tid].front()->isLoad() ||
855            insts[tid].front()->isStore() ) {
856            toRename->iewInfo[tid].dispatchedToLSQ++;
857        }
858
859        toRename->iewInfo[tid].dispatched++;
860
861        insts[tid].pop();
862    }
863}
864
865template <class Impl>
866void
867DefaultIEW<Impl>::wakeCPU()
868{
869    cpu->wakeCPU();
870}
871
872template <class Impl>
873void
874DefaultIEW<Impl>::activityThisCycle()
875{
876    DPRINTF(Activity, "Activity this cycle.\n");
877    cpu->activityThisCycle();
878}
879
880template <class Impl>
881inline void
882DefaultIEW<Impl>::activateStage()
883{
884    DPRINTF(Activity, "Activating stage.\n");
885    cpu->activateStage(O3CPU::IEWIdx);
886}
887
888template <class Impl>
889inline void
890DefaultIEW<Impl>::deactivateStage()
891{
892    DPRINTF(Activity, "Deactivating stage.\n");
893    cpu->deactivateStage(O3CPU::IEWIdx);
894}
895
896template<class Impl>
897void
898DefaultIEW<Impl>::dispatch(ThreadID tid)
899{
900    // If status is Running or idle,
901    //     call dispatchInsts()
902    // If status is Unblocking,
903    //     buffer any instructions coming from rename
904    //     continue trying to empty skid buffer
905    //     check if stall conditions have passed
906
907    if (dispatchStatus[tid] == Blocked) {
908        ++iewBlockCycles;
909
910    } else if (dispatchStatus[tid] == Squashing) {
911        ++iewSquashCycles;
912    }
913
914    // Dispatch should try to dispatch as many instructions as its bandwidth
915    // will allow, as long as it is not currently blocked.
916    if (dispatchStatus[tid] == Running ||
917        dispatchStatus[tid] == Idle) {
918        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
919                "dispatch.\n", tid);
920
921        dispatchInsts(tid);
922    } else if (dispatchStatus[tid] == Unblocking) {
923        // Make sure that the skid buffer has something in it if the
924        // status is unblocking.
925        assert(!skidsEmpty());
926
927        // If the status was unblocking, then instructions from the skid
928        // buffer were used.  Remove those instructions and handle
929        // the rest of unblocking.
930        dispatchInsts(tid);
931
932        ++iewUnblockCycles;
933
934        if (validInstsFromRename()) {
935            // Add the current inputs to the skid buffer so they can be
936            // reprocessed when this stage unblocks.
937            skidInsert(tid);
938        }
939
940        unblock(tid);
941    }
942}
943
944template <class Impl>
945void
946DefaultIEW<Impl>::dispatchInsts(ThreadID tid)
947{
948    // Obtain instructions from skid buffer if unblocking, or queue from rename
949    // otherwise.
950    std::queue<DynInstPtr> &insts_to_dispatch =
951        dispatchStatus[tid] == Unblocking ?
952        skidBuffer[tid] : insts[tid];
953
954    int insts_to_add = insts_to_dispatch.size();
955
956    DynInstPtr inst;
957    bool add_to_iq = false;
958    int dis_num_inst = 0;
959
960    // Loop through the instructions, putting them in the instruction
961    // queue.
962    for ( ; dis_num_inst < insts_to_add &&
963              dis_num_inst < dispatchWidth;
964          ++dis_num_inst)
965    {
966        inst = insts_to_dispatch.front();
967
968        if (dispatchStatus[tid] == Unblocking) {
969            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
970                    "buffer\n", tid);
971        }
972
973        // Make sure there's a valid instruction there.
974        assert(inst);
975
976        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to "
977                "IQ.\n",
978                tid, inst->readPC(), inst->seqNum, inst->threadNumber);
979
980        // Be sure to mark these instructions as ready so that the
981        // commit stage can go ahead and execute them, and mark
982        // them as issued so the IQ doesn't reprocess them.
983
984        // Check for squashed instructions.
985        if (inst->isSquashed()) {
986            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
987                    "not adding to IQ.\n", tid);
988
989            ++iewDispSquashedInsts;
990
991            insts_to_dispatch.pop();
992
993            //Tell Rename That An Instruction has been processed
994            if (inst->isLoad() || inst->isStore()) {
995                toRename->iewInfo[tid].dispatchedToLSQ++;
996            }
997            toRename->iewInfo[tid].dispatched++;
998
999            continue;
1000        }
1001
1002        // Check for full conditions.
1003        if (instQueue.isFull(tid)) {
1004            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
1005
1006            // Call function to start blocking.
1007            block(tid);
1008
1009            // Set unblock to false. Special case where we are using
1010            // skidbuffer (unblocking) instructions but then we still
1011            // get full in the IQ.
1012            toRename->iewUnblock[tid] = false;
1013
1014            ++iewIQFullEvents;
1015            break;
1016        } else if (ldstQueue.isFull(tid)) {
1017            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
1018
1019            // Call function to start blocking.
1020            block(tid);
1021
1022            // Set unblock to false. Special case where we are using
1023            // skidbuffer (unblocking) instructions but then we still
1024            // get full in the IQ.
1025            toRename->iewUnblock[tid] = false;
1026
1027            ++iewLSQFullEvents;
1028            break;
1029        }
1030
1031        // Otherwise issue the instruction just fine.
1032        if (inst->isLoad()) {
1033            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1034                    "encountered, adding to LSQ.\n", tid);
1035
1036            // Reserve a spot in the load store queue for this
1037            // memory access.
1038            ldstQueue.insertLoad(inst);
1039
1040            ++iewDispLoadInsts;
1041
1042            add_to_iq = true;
1043
1044            toRename->iewInfo[tid].dispatchedToLSQ++;
1045        } else if (inst->isStore()) {
1046            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
1047                    "encountered, adding to LSQ.\n", tid);
1048
1049            ldstQueue.insertStore(inst);
1050
1051            ++iewDispStoreInsts;
1052
1053            if (inst->isStoreConditional()) {
1054                // Store conditionals need to be set as "canCommit()"
1055                // so that commit can process them when they reach the
1056                // head of commit.
1057                // @todo: This is somewhat specific to Alpha.
1058                inst->setCanCommit();
1059                instQueue.insertNonSpec(inst);
1060                add_to_iq = false;
1061
1062                ++iewDispNonSpecInsts;
1063            } else {
1064                add_to_iq = true;
1065            }
1066
1067            toRename->iewInfo[tid].dispatchedToLSQ++;
1068        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1069            // Same as non-speculative stores.
1070            inst->setCanCommit();
1071            instQueue.insertBarrier(inst);
1072            add_to_iq = false;
1073        } else if (inst->isNop()) {
1074            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
1075                    "skipping.\n", tid);
1076
1077            inst->setIssued();
1078            inst->setExecuted();
1079            inst->setCanCommit();
1080
1081            instQueue.recordProducer(inst);
1082
1083            iewExecutedNop[tid]++;
1084
1085            add_to_iq = false;
1086        } else if (inst->isExecuted()) {
1087            assert(0 && "Instruction shouldn't be executed.\n");
1088            DPRINTF(IEW, "Issue: Executed branch encountered, "
1089                    "skipping.\n");
1090
1091            inst->setIssued();
1092            inst->setCanCommit();
1093
1094            instQueue.recordProducer(inst);
1095
1096            add_to_iq = false;
1097        } else {
1098            add_to_iq = true;
1099        }
1100        if (inst->isNonSpeculative()) {
1101            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
1102                    "encountered, skipping.\n", tid);
1103
1104            // Same as non-speculative stores.
1105            inst->setCanCommit();
1106
1107            // Specifically insert it as nonspeculative.
1108            instQueue.insertNonSpec(inst);
1109
1110            ++iewDispNonSpecInsts;
1111
1112            add_to_iq = false;
1113        }
1114
1115        // If the instruction queue is not full, then add the
1116        // instruction.
1117        if (add_to_iq) {
1118            instQueue.insert(inst);
1119        }
1120
1121        insts_to_dispatch.pop();
1122
1123        toRename->iewInfo[tid].dispatched++;
1124
1125        ++iewDispatchedInsts;
1126    }
1127
1128    if (!insts_to_dispatch.empty()) {
1129        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
1130        block(tid);
1131        toRename->iewUnblock[tid] = false;
1132    }
1133
1134    if (dispatchStatus[tid] == Idle && dis_num_inst) {
1135        dispatchStatus[tid] = Running;
1136
1137        updatedQueues = true;
1138    }
1139
1140    dis_num_inst = 0;
1141}
1142
1143template <class Impl>
1144void
1145DefaultIEW<Impl>::printAvailableInsts()
1146{
1147    int inst = 0;
1148
1149    std::cout << "Available Instructions: ";
1150
1151    while (fromIssue->insts[inst]) {
1152
1153        if (inst%3==0) std::cout << "\n\t";
1154
1155        std::cout << "PC: " << fromIssue->insts[inst]->readPC()
1156             << " TN: " << fromIssue->insts[inst]->threadNumber
1157             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
1158
1159        inst++;
1160
1161    }
1162
1163    std::cout << "\n";
1164}
1165
1166template <class Impl>
1167void
1168DefaultIEW<Impl>::executeInsts()
1169{
1170    wbNumInst = 0;
1171    wbCycle = 0;
1172
1173    list<ThreadID>::iterator threads = activeThreads->begin();
1174    list<ThreadID>::iterator end = activeThreads->end();
1175
1176    while (threads != end) {
1177        ThreadID tid = *threads++;
1178        fetchRedirect[tid] = false;
1179    }
1180
1181    // Uncomment this if you want to see all available instructions.
1182//    printAvailableInsts();
1183
1184    // Execute/writeback any instructions that are available.
1185    int insts_to_execute = fromIssue->size;
1186    int inst_num = 0;
1187    for (; inst_num < insts_to_execute;
1188          ++inst_num) {
1189
1190        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
1191
1192        DynInstPtr inst = instQueue.getInstToExecute();
1193
1194        DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n",
1195                inst->readPC(), inst->threadNumber,inst->seqNum);
1196
1197        // Check if the instruction is squashed; if so then skip it
1198        if (inst->isSquashed()) {
1199            DPRINTF(IEW, "Execute: Instruction was squashed.\n");
1200
1201            // Consider this instruction executed so that commit can go
1202            // ahead and retire the instruction.
1203            inst->setExecuted();
1204
1205            // Not sure if I should set this here or just let commit try to
1206            // commit any squashed instructions.  I like the latter a bit more.
1207            inst->setCanCommit();
1208
1209            ++iewExecSquashedInsts;
1210
1211            decrWb(inst->seqNum);
1212            continue;
1213        }
1214
1215        Fault fault = NoFault;
1216
1217        // Execute instruction.
1218        // Note that if the instruction faults, it will be handled
1219        // at the commit stage.
1220        if (inst->isMemRef() &&
1221            (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
1222            DPRINTF(IEW, "Execute: Calculating address for memory "
1223                    "reference.\n");
1224
1225            // Tell the LDSTQ to execute this instruction (if it is a load).
1226            if (inst->isLoad()) {
1227                // Loads will mark themselves as executed, and their writeback
1228                // event adds the instruction to the queue to commit
1229                fault = ldstQueue.executeLoad(inst);
1230            } else if (inst->isStore()) {
1231                fault = ldstQueue.executeStore(inst);
1232
1233                // If the store had a fault then it may not have a mem req
1234                if (!inst->isStoreConditional() && fault == NoFault) {
1235                    inst->setExecuted();
1236
1237                    instToCommit(inst);
1238                } else if (fault != NoFault) {
1239                    // If the instruction faulted, then we need to send it along to commit
1240                    // without the instruction completing.
1241                    DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n",
1242                            fault->name(), inst->seqNum);
1243
1244                    // Send this instruction to commit, also make sure iew stage
1245                    // realizes there is activity.
1246                    inst->setExecuted();
1247
1248                    instToCommit(inst);
1249                    activityThisCycle();
1250                }
1251
1252                // Store conditionals will mark themselves as
1253                // executed, and their writeback event will add the
1254                // instruction to the queue to commit.
1255            } else {
1256                panic("Unexpected memory type!\n");
1257            }
1258
1259        } else {
1260            inst->execute();
1261
1262            inst->setExecuted();
1263
1264            instToCommit(inst);
1265        }
1266
1267        updateExeInstStats(inst);
1268
1269        // Check if branch prediction was correct, if not then we need
1270        // to tell commit to squash in flight instructions.  Only
1271        // handle this if there hasn't already been something that
1272        // redirects fetch in this group of instructions.
1273
1274        // This probably needs to prioritize the redirects if a different
1275        // scheduler is used.  Currently the scheduler schedules the oldest
1276        // instruction first, so the branch resolution order will be correct.
1277        ThreadID tid = inst->threadNumber;
1278
1279        if (!fetchRedirect[tid] ||
1280            toCommit->squashedSeqNum[tid] > inst->seqNum) {
1281
1282            if (inst->mispredicted()) {
1283                fetchRedirect[tid] = true;
1284
1285                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
1286                DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
1287                        inst->readPredPC(), inst->readPredNPC());
1288                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
1289                        " NPC: %#x.\n", inst->readNextPC(),
1290                        inst->readNextNPC());
1291                // If incorrect, then signal the ROB that it must be squashed.
1292                squashDueToBranch(inst, tid);
1293
1294                if (inst->readPredTaken()) {
1295                    predictedTakenIncorrect++;
1296                } else {
1297                    predictedNotTakenIncorrect++;
1298                }
1299            } else if (ldstQueue.violation(tid)) {
1300                assert(inst->isMemRef());
1301                // If there was an ordering violation, then get the
1302                // DynInst that caused the violation.  Note that this
1303                // clears the violation signal.
1304                DynInstPtr violator;
1305                violator = ldstQueue.getMemDepViolator(tid);
1306
1307                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1308                        "%#x, inst PC: %#x.  Addr is: %#x.\n",
1309                        violator->readPC(), inst->readPC(), inst->physEffAddr);
1310
1311                // Ensure the violating instruction is older than
1312                // current squash
1313/*                if (fetchRedirect[tid] &&
1314                    violator->seqNum >= toCommit->squashedSeqNum[tid] + 1)
1315                    continue;
1316*/
1317                fetchRedirect[tid] = true;
1318
1319                // Tell the instruction queue that a violation has occured.
1320                instQueue.violation(inst, violator);
1321
1322                // Squash.
1323                squashDueToMemOrder(inst,tid);
1324
1325                ++memOrderViolationEvents;
1326            } else if (ldstQueue.loadBlocked(tid) &&
1327                       !ldstQueue.isLoadBlockedHandled(tid)) {
1328                fetchRedirect[tid] = true;
1329
1330                DPRINTF(IEW, "Load operation couldn't execute because the "
1331                        "memory system is blocked.  PC: %#x [sn:%lli]\n",
1332                        inst->readPC(), inst->seqNum);
1333
1334                squashDueToMemBlocked(inst, tid);
1335            }
1336        } else {
1337            // Reset any state associated with redirects that will not
1338            // be used.
1339            if (ldstQueue.violation(tid)) {
1340                assert(inst->isMemRef());
1341
1342                DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
1343
1344                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
1345                        "%#x, inst PC: %#x.  Addr is: %#x.\n",
1346                        violator->readPC(), inst->readPC(), inst->physEffAddr);
1347                DPRINTF(IEW, "Violation will not be handled because "
1348                        "already squashing\n");
1349
1350                ++memOrderViolationEvents;
1351            }
1352            if (ldstQueue.loadBlocked(tid) &&
1353                !ldstQueue.isLoadBlockedHandled(tid)) {
1354                DPRINTF(IEW, "Load operation couldn't execute because the "
1355                        "memory system is blocked.  PC: %#x [sn:%lli]\n",
1356                        inst->readPC(), inst->seqNum);
1357                DPRINTF(IEW, "Blocked load will not be handled because "
1358                        "already squashing\n");
1359
1360                ldstQueue.setLoadBlockedHandled(tid);
1361            }
1362
1363        }
1364    }
1365
1366    // Update and record activity if we processed any instructions.
1367    if (inst_num) {
1368        if (exeStatus == Idle) {
1369            exeStatus = Running;
1370        }
1371
1372        updatedQueues = true;
1373
1374        cpu->activityThisCycle();
1375    }
1376
1377    // Need to reset this in case a writeback event needs to write into the
1378    // iew queue.  That way the writeback event will write into the correct
1379    // spot in the queue.
1380    wbNumInst = 0;
1381}
1382
1383template <class Impl>
1384void
1385DefaultIEW<Impl>::writebackInsts()
1386{
1387    // Loop through the head of the time buffer and wake any
1388    // dependents.  These instructions are about to write back.  Also
1389    // mark scoreboard that this instruction is finally complete.
1390    // Either have IEW have direct access to scoreboard, or have this
1391    // as part of backwards communication.
1392    for (int inst_num = 0; inst_num < wbWidth &&
1393             toCommit->insts[inst_num]; inst_num++) {
1394        DynInstPtr inst = toCommit->insts[inst_num];
1395        ThreadID tid = inst->threadNumber;
1396
1397        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n",
1398                inst->seqNum, inst->readPC());
1399
1400        iewInstsToCommit[tid]++;
1401
1402        // Some instructions will be sent to commit without having
1403        // executed because they need commit to handle them.
1404        // E.g. Uncached loads have not actually executed when they
1405        // are first sent to commit.  Instead commit must tell the LSQ
1406        // when it's ready to execute the uncached load.
1407        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
1408            int dependents = instQueue.wakeDependents(inst);
1409
1410            for (int i = 0; i < inst->numDestRegs(); i++) {
1411                //mark as Ready
1412                DPRINTF(IEW,"Setting Destination Register %i\n",
1413                        inst->renamedDestRegIdx(i));
1414                scoreboard->setReg(inst->renamedDestRegIdx(i));
1415            }
1416
1417            if (dependents) {
1418                producerInst[tid]++;
1419                consumerInst[tid]+= dependents;
1420            }
1421            writebackCount[tid]++;
1422        }
1423
1424        decrWb(inst->seqNum);
1425    }
1426}
1427
1428template<class Impl>
1429void
1430DefaultIEW<Impl>::tick()
1431{
1432    wbNumInst = 0;
1433    wbCycle = 0;
1434
1435    wroteToTimeBuffer = false;
1436    updatedQueues = false;
1437
1438    sortInsts();
1439
1440    // Free function units marked as being freed this cycle.
1441    fuPool->processFreeUnits();
1442
1443    list<ThreadID>::iterator threads = activeThreads->begin();
1444    list<ThreadID>::iterator end = activeThreads->end();
1445
1446    // Check stall and squash signals, dispatch any instructions.
1447    while (threads != end) {
1448        ThreadID tid = *threads++;
1449
1450        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
1451
1452        checkSignalsAndUpdate(tid);
1453        dispatch(tid);
1454    }
1455
1456    if (exeStatus != Squashing) {
1457        executeInsts();
1458
1459        writebackInsts();
1460
1461        // Have the instruction queue try to schedule any ready instructions.
1462        // (In actuality, this scheduling is for instructions that will
1463        // be executed next cycle.)
1464        instQueue.scheduleReadyInsts();
1465
1466        // Also should advance its own time buffers if the stage ran.
1467        // Not the best place for it, but this works (hopefully).
1468        issueToExecQueue.advance();
1469    }
1470
1471    bool broadcast_free_entries = false;
1472
1473    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
1474        exeStatus = Idle;
1475        updateLSQNextCycle = false;
1476
1477        broadcast_free_entries = true;
1478    }
1479
1480    // Writeback any stores using any leftover bandwidth.
1481    ldstQueue.writebackStores();
1482
1483    // Check the committed load/store signals to see if there's a load
1484    // or store to commit.  Also check if it's being told to execute a
1485    // nonspeculative instruction.
1486    // This is pretty inefficient...
1487
1488    threads = activeThreads->begin();
1489    while (threads != end) {
1490        ThreadID tid = (*threads++);
1491
1492        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
1493
1494        // Update structures based on instructions committed.
1495        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
1496            !fromCommit->commitInfo[tid].squash &&
1497            !fromCommit->commitInfo[tid].robSquashing) {
1498
1499            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
1500
1501            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
1502
1503            updateLSQNextCycle = true;
1504            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
1505        }
1506
1507        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
1508
1509            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
1510            if (fromCommit->commitInfo[tid].uncached) {
1511                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
1512                fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
1513            } else {
1514                instQueue.scheduleNonSpec(
1515                    fromCommit->commitInfo[tid].nonSpecSeqNum);
1516            }
1517        }
1518
1519        if (broadcast_free_entries) {
1520            toFetch->iewInfo[tid].iqCount =
1521                instQueue.getCount(tid);
1522            toFetch->iewInfo[tid].ldstqCount =
1523                ldstQueue.getCount(tid);
1524
1525            toRename->iewInfo[tid].usedIQ = true;
1526            toRename->iewInfo[tid].freeIQEntries =
1527                instQueue.numFreeEntries();
1528            toRename->iewInfo[tid].usedLSQ = true;
1529            toRename->iewInfo[tid].freeLSQEntries =
1530                ldstQueue.numFreeEntries(tid);
1531
1532            wroteToTimeBuffer = true;
1533        }
1534
1535        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
1536                tid, toRename->iewInfo[tid].dispatched);
1537    }
1538
1539    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
1540            "LSQ has %i free entries.\n",
1541            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
1542            ldstQueue.numFreeEntries());
1543
1544    updateStatus();
1545
1546    if (wroteToTimeBuffer) {
1547        DPRINTF(Activity, "Activity this cycle.\n");
1548        cpu->activityThisCycle();
1549    }
1550}
1551
1552template <class Impl>
1553void
1554DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
1555{
1556    ThreadID tid = inst->threadNumber;
1557
1558    //
1559    //  Pick off the software prefetches
1560    //
1561#ifdef TARGET_ALPHA
1562    if (inst->isDataPrefetch())
1563        iewExecutedSwp[tid]++;
1564    else
1565        iewIewExecutedcutedInsts++;
1566#else
1567    iewExecutedInsts++;
1568#endif
1569
1570    //
1571    //  Control operations
1572    //
1573    if (inst->isControl())
1574        iewExecutedBranches[tid]++;
1575
1576    //
1577    //  Memory operations
1578    //
1579    if (inst->isMemRef()) {
1580        iewExecutedRefs[tid]++;
1581
1582        if (inst->isLoad()) {
1583            iewExecLoadInsts[tid]++;
1584        }
1585    }
1586}
1587