iew_impl.hh revision 3795
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31// @todo: Fix the instantaneous communication among all the stages within 32// iew. There's a clear delay between issue and execute, yet backwards 33// communication happens simultaneously. 34 35#include <queue> 36 37#include "base/timebuf.hh" 38#include "cpu/o3/fu_pool.hh" 39#include "cpu/o3/iew.hh" 40 41template<class Impl> 42DefaultIEW<Impl>::DefaultIEW(Params *params) 43 : issueToExecQueue(params->backComSize, params->forwardComSize), 44 instQueue(params), 45 ldstQueue(params), 46 fuPool(params->fuPool), 47 commitToIEWDelay(params->commitToIEWDelay), 48 renameToIEWDelay(params->renameToIEWDelay), 49 issueToExecuteDelay(params->issueToExecuteDelay), 50 dispatchWidth(params->dispatchWidth), 51 issueWidth(params->issueWidth), 52 wbOutstanding(0), 53 wbWidth(params->wbWidth), 54 numThreads(params->numberOfThreads), 55 switchedOut(false) 56{ 57 _status = Active; 58 exeStatus = Running; 59 wbStatus = Idle; 60 61 // Setup wire to read instructions coming from issue. 62 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 63 64 // Instruction queue needs the queue between issue and execute. 65 instQueue.setIssueToExecuteQueue(&issueToExecQueue); 66 67 instQueue.setIEW(this); 68 ldstQueue.setIEW(this); 69 70 for (int i=0; i < numThreads; i++) { 71 dispatchStatus[i] = Running; 72 stalls[i].commit = false; 73 fetchRedirect[i] = false; 74 bdelayDoneSeqNum[i] = 0; 75 } 76 77 wbMax = wbWidth * params->wbDepth; 78 79 updateLSQNextCycle = false; 80 81 ableToIssue = true; 82 83 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 84} 85 86template <class Impl> 87std::string 88DefaultIEW<Impl>::name() const 89{ 90 return cpu->name() + ".iew"; 91} 92 93template <class Impl> 94void 95DefaultIEW<Impl>::regStats() 96{ 97 using namespace Stats; 98 99 instQueue.regStats(); 100 ldstQueue.regStats(); 101 102 iewIdleCycles 103 .name(name() + ".iewIdleCycles") 104 .desc("Number of cycles IEW is idle"); 105 106 iewSquashCycles 107 .name(name() + ".iewSquashCycles") 108 .desc("Number of cycles IEW is squashing"); 109 110 iewBlockCycles 111 .name(name() + ".iewBlockCycles") 112 .desc("Number of cycles IEW is blocking"); 113 114 iewUnblockCycles 115 .name(name() + ".iewUnblockCycles") 116 .desc("Number of cycles IEW is unblocking"); 117 118 iewDispatchedInsts 119 .name(name() + ".iewDispatchedInsts") 120 .desc("Number of instructions dispatched to IQ"); 121 122 iewDispSquashedInsts 123 .name(name() + ".iewDispSquashedInsts") 124 .desc("Number of squashed instructions skipped by dispatch"); 125 126 iewDispLoadInsts 127 .name(name() + ".iewDispLoadInsts") 128 .desc("Number of dispatched load instructions"); 129 130 iewDispStoreInsts 131 .name(name() + ".iewDispStoreInsts") 132 .desc("Number of dispatched store instructions"); 133 134 iewDispNonSpecInsts 135 .name(name() + ".iewDispNonSpecInsts") 136 .desc("Number of dispatched non-speculative instructions"); 137 138 iewIQFullEvents 139 .name(name() + ".iewIQFullEvents") 140 .desc("Number of times the IQ has become full, causing a stall"); 141 142 iewLSQFullEvents 143 .name(name() + ".iewLSQFullEvents") 144 .desc("Number of times the LSQ has become full, causing a stall"); 145 146 memOrderViolationEvents 147 .name(name() + ".memOrderViolationEvents") 148 .desc("Number of memory order violations"); 149 150 predictedTakenIncorrect 151 .name(name() + ".predictedTakenIncorrect") 152 .desc("Number of branches that were predicted taken incorrectly"); 153 154 predictedNotTakenIncorrect 155 .name(name() + ".predictedNotTakenIncorrect") 156 .desc("Number of branches that were predicted not taken incorrectly"); 157 158 branchMispredicts 159 .name(name() + ".branchMispredicts") 160 .desc("Number of branch mispredicts detected at execute"); 161 162 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 163 164 iewExecutedInsts 165 .name(name() + ".iewExecutedInsts") 166 .desc("Number of executed instructions"); 167 168 iewExecLoadInsts 169 .init(cpu->number_of_threads) 170 .name(name() + ".iewExecLoadInsts") 171 .desc("Number of load instructions executed") 172 .flags(total); 173 174 iewExecSquashedInsts 175 .name(name() + ".iewExecSquashedInsts") 176 .desc("Number of squashed instructions skipped in execute"); 177 178 iewExecutedSwp 179 .init(cpu->number_of_threads) 180 .name(name() + ".EXEC:swp") 181 .desc("number of swp insts executed") 182 .flags(total); 183 184 iewExecutedNop 185 .init(cpu->number_of_threads) 186 .name(name() + ".EXEC:nop") 187 .desc("number of nop insts executed") 188 .flags(total); 189 190 iewExecutedRefs 191 .init(cpu->number_of_threads) 192 .name(name() + ".EXEC:refs") 193 .desc("number of memory reference insts executed") 194 .flags(total); 195 196 iewExecutedBranches 197 .init(cpu->number_of_threads) 198 .name(name() + ".EXEC:branches") 199 .desc("Number of branches executed") 200 .flags(total); 201 202 iewExecStoreInsts 203 .name(name() + ".EXEC:stores") 204 .desc("Number of stores executed") 205 .flags(total); 206 iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 207 208 iewExecRate 209 .name(name() + ".EXEC:rate") 210 .desc("Inst execution rate") 211 .flags(total); 212 213 iewExecRate = iewExecutedInsts / cpu->numCycles; 214 215 iewInstsToCommit 216 .init(cpu->number_of_threads) 217 .name(name() + ".WB:sent") 218 .desc("cumulative count of insts sent to commit") 219 .flags(total); 220 221 writebackCount 222 .init(cpu->number_of_threads) 223 .name(name() + ".WB:count") 224 .desc("cumulative count of insts written-back") 225 .flags(total); 226 227 producerInst 228 .init(cpu->number_of_threads) 229 .name(name() + ".WB:producers") 230 .desc("num instructions producing a value") 231 .flags(total); 232 233 consumerInst 234 .init(cpu->number_of_threads) 235 .name(name() + ".WB:consumers") 236 .desc("num instructions consuming a value") 237 .flags(total); 238 239 wbPenalized 240 .init(cpu->number_of_threads) 241 .name(name() + ".WB:penalized") 242 .desc("number of instrctions required to write to 'other' IQ") 243 .flags(total); 244 245 wbPenalizedRate 246 .name(name() + ".WB:penalized_rate") 247 .desc ("fraction of instructions written-back that wrote to 'other' IQ") 248 .flags(total); 249 250 wbPenalizedRate = wbPenalized / writebackCount; 251 252 wbFanout 253 .name(name() + ".WB:fanout") 254 .desc("average fanout of values written-back") 255 .flags(total); 256 257 wbFanout = producerInst / consumerInst; 258 259 wbRate 260 .name(name() + ".WB:rate") 261 .desc("insts written-back per cycle") 262 .flags(total); 263 wbRate = writebackCount / cpu->numCycles; 264} 265 266template<class Impl> 267void 268DefaultIEW<Impl>::initStage() 269{ 270 for (int tid=0; tid < numThreads; tid++) { 271 toRename->iewInfo[tid].usedIQ = true; 272 toRename->iewInfo[tid].freeIQEntries = 273 instQueue.numFreeEntries(tid); 274 275 toRename->iewInfo[tid].usedLSQ = true; 276 toRename->iewInfo[tid].freeLSQEntries = 277 ldstQueue.numFreeEntries(tid); 278 } 279} 280 281template<class Impl> 282void 283DefaultIEW<Impl>::setCPU(O3CPU *cpu_ptr) 284{ 285 DPRINTF(IEW, "Setting CPU pointer.\n"); 286 cpu = cpu_ptr; 287 288 instQueue.setCPU(cpu_ptr); 289 ldstQueue.setCPU(cpu_ptr); 290 291 cpu->activateStage(O3CPU::IEWIdx); 292} 293 294template<class Impl> 295void 296DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 297{ 298 DPRINTF(IEW, "Setting time buffer pointer.\n"); 299 timeBuffer = tb_ptr; 300 301 // Setup wire to read information from time buffer, from commit. 302 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 303 304 // Setup wire to write information back to previous stages. 305 toRename = timeBuffer->getWire(0); 306 307 toFetch = timeBuffer->getWire(0); 308 309 // Instruction queue also needs main time buffer. 310 instQueue.setTimeBuffer(tb_ptr); 311} 312 313template<class Impl> 314void 315DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 316{ 317 DPRINTF(IEW, "Setting rename queue pointer.\n"); 318 renameQueue = rq_ptr; 319 320 // Setup wire to read information from rename queue. 321 fromRename = renameQueue->getWire(-renameToIEWDelay); 322} 323 324template<class Impl> 325void 326DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 327{ 328 DPRINTF(IEW, "Setting IEW queue pointer.\n"); 329 iewQueue = iq_ptr; 330 331 // Setup wire to write instructions to commit. 332 toCommit = iewQueue->getWire(0); 333} 334 335template<class Impl> 336void 337DefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 338{ 339 DPRINTF(IEW, "Setting active threads list pointer.\n"); 340 activeThreads = at_ptr; 341 342 ldstQueue.setActiveThreads(at_ptr); 343 instQueue.setActiveThreads(at_ptr); 344} 345 346template<class Impl> 347void 348DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 349{ 350 DPRINTF(IEW, "Setting scoreboard pointer.\n"); 351 scoreboard = sb_ptr; 352} 353 354template <class Impl> 355bool 356DefaultIEW<Impl>::drain() 357{ 358 // IEW is ready to drain at any time. 359 cpu->signalDrained(); 360 return true; 361} 362 363template <class Impl> 364void 365DefaultIEW<Impl>::resume() 366{ 367} 368 369template <class Impl> 370void 371DefaultIEW<Impl>::switchOut() 372{ 373 // Clear any state. 374 switchedOut = true; 375 assert(insts[0].empty()); 376 assert(skidBuffer[0].empty()); 377 378 instQueue.switchOut(); 379 ldstQueue.switchOut(); 380 fuPool->switchOut(); 381 382 for (int i = 0; i < numThreads; i++) { 383 while (!insts[i].empty()) 384 insts[i].pop(); 385 while (!skidBuffer[i].empty()) 386 skidBuffer[i].pop(); 387 } 388} 389 390template <class Impl> 391void 392DefaultIEW<Impl>::takeOverFrom() 393{ 394 // Reset all state. 395 _status = Active; 396 exeStatus = Running; 397 wbStatus = Idle; 398 switchedOut = false; 399 400 instQueue.takeOverFrom(); 401 ldstQueue.takeOverFrom(); 402 fuPool->takeOverFrom(); 403 404 initStage(); 405 cpu->activityThisCycle(); 406 407 for (int i=0; i < numThreads; i++) { 408 dispatchStatus[i] = Running; 409 stalls[i].commit = false; 410 fetchRedirect[i] = false; 411 } 412 413 updateLSQNextCycle = false; 414 415 for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 416 issueToExecQueue.advance(); 417 } 418} 419 420template<class Impl> 421void 422DefaultIEW<Impl>::squash(unsigned tid) 423{ 424 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 425 tid); 426 427 // Tell the IQ to start squashing. 428 instQueue.squash(tid); 429 430 // Tell the LDSTQ to start squashing. 431#if ISA_HAS_DELAY_SLOT 432 ldstQueue.squash(fromCommit->commitInfo[tid].bdelayDoneSeqNum, tid); 433#else 434 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 435#endif 436 updatedQueues = true; 437 438 // Clear the skid buffer in case it has any data in it. 439 DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 440 tid, fromCommit->commitInfo[tid].bdelayDoneSeqNum); 441 442 while (!skidBuffer[tid].empty()) { 443#if ISA_HAS_DELAY_SLOT 444 if (skidBuffer[tid].front()->seqNum <= 445 fromCommit->commitInfo[tid].bdelayDoneSeqNum) { 446 DPRINTF(IEW, "[tid:%i]: Cannot remove skidbuffer instructions " 447 "that occur before delay slot [sn:%i].\n", 448 fromCommit->commitInfo[tid].bdelayDoneSeqNum, 449 tid); 450 break; 451 } else { 452 DPRINTF(IEW, "[tid:%i]: Removing instruction [sn:%i] from " 453 "skidBuffer.\n", tid, skidBuffer[tid].front()->seqNum); 454 } 455#endif 456 if (skidBuffer[tid].front()->isLoad() || 457 skidBuffer[tid].front()->isStore() ) { 458 toRename->iewInfo[tid].dispatchedToLSQ++; 459 } 460 461 toRename->iewInfo[tid].dispatched++; 462 463 skidBuffer[tid].pop(); 464 } 465 466 bdelayDoneSeqNum[tid] = fromCommit->commitInfo[tid].bdelayDoneSeqNum; 467 468 emptyRenameInsts(tid); 469} 470 471template<class Impl> 472void 473DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 474{ 475 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 476 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 477 478 toCommit->squash[tid] = true; 479 toCommit->squashedSeqNum[tid] = inst->seqNum; 480 toCommit->mispredPC[tid] = inst->readPC(); 481 toCommit->branchMispredict[tid] = true; 482 483#if ISA_HAS_DELAY_SLOT 484 int instSize = sizeof(TheISA::MachInst); 485 bool branch_taken = 486 !(inst->readNextPC() + instSize == inst->readNextNPC() && 487 (inst->readNextPC() == inst->readPC() + instSize || 488 inst->readNextPC() == inst->readPC() + 2 * instSize)); 489 DPRINTF(Sparc, "Branch taken = %s [sn:%i]\n", 490 branch_taken ? "true": "false", inst->seqNum); 491 492 toCommit->branchTaken[tid] = branch_taken; 493 494 bool squashDelaySlot = true; 495// (inst->readNextPC() != inst->readPC() + sizeof(TheISA::MachInst)); 496 DPRINTF(Sparc, "Squash delay slot = %s [sn:%i]\n", 497 squashDelaySlot ? "true": "false", inst->seqNum); 498 toCommit->squashDelaySlot[tid] = squashDelaySlot; 499 //If we're squashing the delay slot, we need to pick back up at NextPC. 500 //Otherwise, NextPC isn't being squashed, so we should pick back up at 501 //NextNPC. 502 if (squashDelaySlot) { 503 toCommit->nextPC[tid] = inst->readNextPC(); 504 toCommit->nextNPC[tid] = inst->readNextNPC(); 505 } else 506 toCommit->nextPC[tid] = inst->readNextNPC(); 507#else 508 toCommit->branchTaken[tid] = inst->readNextPC() != 509 (inst->readPC() + sizeof(TheISA::MachInst)); 510 toCommit->nextPC[tid] = inst->readNextPC(); 511#endif 512 513 toCommit->includeSquashInst[tid] = false; 514 515 wroteToTimeBuffer = true; 516} 517 518template<class Impl> 519void 520DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 521{ 522 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 523 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 524 525 toCommit->squash[tid] = true; 526 toCommit->squashedSeqNum[tid] = inst->seqNum; 527 toCommit->nextPC[tid] = inst->readNextPC(); 528#if ISA_HAS_DELAY_SLOT 529 toCommit->nextNPC[tid] = inst->readNextNPC(); 530#endif 531 532 toCommit->includeSquashInst[tid] = false; 533 534 wroteToTimeBuffer = true; 535} 536 537template<class Impl> 538void 539DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 540{ 541 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 542 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 543 544 toCommit->squash[tid] = true; 545 toCommit->squashedSeqNum[tid] = inst->seqNum; 546 toCommit->nextPC[tid] = inst->readPC(); 547#if ISA_HAS_DELAY_SLOT 548 toCommit->nextNPC[tid] = inst->readNextNPC(); 549#endif 550 551 // Must include the broadcasted SN in the squash. 552 toCommit->includeSquashInst[tid] = true; 553 554 ldstQueue.setLoadBlockedHandled(tid); 555 556 wroteToTimeBuffer = true; 557} 558 559template<class Impl> 560void 561DefaultIEW<Impl>::block(unsigned tid) 562{ 563 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 564 565 if (dispatchStatus[tid] != Blocked && 566 dispatchStatus[tid] != Unblocking) { 567 toRename->iewBlock[tid] = true; 568 wroteToTimeBuffer = true; 569 } 570 571 // Add the current inputs to the skid buffer so they can be 572 // reprocessed when this stage unblocks. 573 skidInsert(tid); 574 575 dispatchStatus[tid] = Blocked; 576} 577 578template<class Impl> 579void 580DefaultIEW<Impl>::unblock(unsigned tid) 581{ 582 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 583 "buffer %u.\n",tid, tid); 584 585 // If the skid bufffer is empty, signal back to previous stages to unblock. 586 // Also switch status to running. 587 if (skidBuffer[tid].empty()) { 588 toRename->iewUnblock[tid] = true; 589 wroteToTimeBuffer = true; 590 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 591 dispatchStatus[tid] = Running; 592 } 593} 594 595template<class Impl> 596void 597DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 598{ 599 instQueue.wakeDependents(inst); 600} 601 602template<class Impl> 603void 604DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 605{ 606 instQueue.rescheduleMemInst(inst); 607} 608 609template<class Impl> 610void 611DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 612{ 613 instQueue.replayMemInst(inst); 614} 615 616template<class Impl> 617void 618DefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 619{ 620 // This function should not be called after writebackInsts in a 621 // single cycle. That will cause problems with an instruction 622 // being added to the queue to commit without being processed by 623 // writebackInsts prior to being sent to commit. 624 625 // First check the time slot that this instruction will write 626 // to. If there are free write ports at the time, then go ahead 627 // and write the instruction to that time. If there are not, 628 // keep looking back to see where's the first time there's a 629 // free slot. 630 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 631 ++wbNumInst; 632 if (wbNumInst == wbWidth) { 633 ++wbCycle; 634 wbNumInst = 0; 635 } 636 637 assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 638 } 639 640 DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 641 wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 642 // Add finished instruction to queue to commit. 643 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 644 (*iewQueue)[wbCycle].size++; 645} 646 647template <class Impl> 648unsigned 649DefaultIEW<Impl>::validInstsFromRename() 650{ 651 unsigned inst_count = 0; 652 653 for (int i=0; i<fromRename->size; i++) { 654 if (!fromRename->insts[i]->isSquashed()) 655 inst_count++; 656 } 657 658 return inst_count; 659} 660 661template<class Impl> 662void 663DefaultIEW<Impl>::skidInsert(unsigned tid) 664{ 665 DynInstPtr inst = NULL; 666 667 while (!insts[tid].empty()) { 668 inst = insts[tid].front(); 669 670 insts[tid].pop(); 671 672 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 673 "dispatch skidBuffer %i\n",tid, inst->seqNum, 674 inst->readPC(),tid); 675 676 skidBuffer[tid].push(inst); 677 } 678 679 assert(skidBuffer[tid].size() <= skidBufferMax && 680 "Skidbuffer Exceeded Max Size"); 681} 682 683template<class Impl> 684int 685DefaultIEW<Impl>::skidCount() 686{ 687 int max=0; 688 689 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 690 691 while (threads != (*activeThreads).end()) { 692 unsigned thread_count = skidBuffer[*threads++].size(); 693 if (max < thread_count) 694 max = thread_count; 695 } 696 697 return max; 698} 699 700template<class Impl> 701bool 702DefaultIEW<Impl>::skidsEmpty() 703{ 704 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 705 706 while (threads != (*activeThreads).end()) { 707 if (!skidBuffer[*threads++].empty()) 708 return false; 709 } 710 711 return true; 712} 713 714template <class Impl> 715void 716DefaultIEW<Impl>::updateStatus() 717{ 718 bool any_unblocking = false; 719 720 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 721 722 threads = (*activeThreads).begin(); 723 724 while (threads != (*activeThreads).end()) { 725 unsigned tid = *threads++; 726 727 if (dispatchStatus[tid] == Unblocking) { 728 any_unblocking = true; 729 break; 730 } 731 } 732 733 // If there are no ready instructions waiting to be scheduled by the IQ, 734 // and there's no stores waiting to write back, and dispatch is not 735 // unblocking, then there is no internal activity for the IEW stage. 736 if (_status == Active && !instQueue.hasReadyInsts() && 737 !ldstQueue.willWB() && !any_unblocking) { 738 DPRINTF(IEW, "IEW switching to idle\n"); 739 740 deactivateStage(); 741 742 _status = Inactive; 743 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 744 ldstQueue.willWB() || 745 any_unblocking)) { 746 // Otherwise there is internal activity. Set to active. 747 DPRINTF(IEW, "IEW switching to active\n"); 748 749 activateStage(); 750 751 _status = Active; 752 } 753} 754 755template <class Impl> 756void 757DefaultIEW<Impl>::resetEntries() 758{ 759 instQueue.resetEntries(); 760 ldstQueue.resetEntries(); 761} 762 763template <class Impl> 764void 765DefaultIEW<Impl>::readStallSignals(unsigned tid) 766{ 767 if (fromCommit->commitBlock[tid]) { 768 stalls[tid].commit = true; 769 } 770 771 if (fromCommit->commitUnblock[tid]) { 772 assert(stalls[tid].commit); 773 stalls[tid].commit = false; 774 } 775} 776 777template <class Impl> 778bool 779DefaultIEW<Impl>::checkStall(unsigned tid) 780{ 781 bool ret_val(false); 782 783 if (stalls[tid].commit) { 784 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 785 ret_val = true; 786 } else if (instQueue.isFull(tid)) { 787 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 788 ret_val = true; 789 } else if (ldstQueue.isFull(tid)) { 790 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 791 792 if (ldstQueue.numLoads(tid) > 0 ) { 793 794 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 795 tid,ldstQueue.getLoadHeadSeqNum(tid)); 796 } 797 798 if (ldstQueue.numStores(tid) > 0) { 799 800 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 801 tid,ldstQueue.getStoreHeadSeqNum(tid)); 802 } 803 804 ret_val = true; 805 } else if (ldstQueue.isStalled(tid)) { 806 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 807 ret_val = true; 808 } 809 810 return ret_val; 811} 812 813template <class Impl> 814void 815DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 816{ 817 // Check if there's a squash signal, squash if there is 818 // Check stall signals, block if there is. 819 // If status was Blocked 820 // if so then go to unblocking 821 // If status was Squashing 822 // check if squashing is not high. Switch to running this cycle. 823 824 readStallSignals(tid); 825 826 if (fromCommit->commitInfo[tid].squash) { 827 squash(tid); 828 829 if (dispatchStatus[tid] == Blocked || 830 dispatchStatus[tid] == Unblocking) { 831 toRename->iewUnblock[tid] = true; 832 wroteToTimeBuffer = true; 833 } 834 835 dispatchStatus[tid] = Squashing; 836 837 fetchRedirect[tid] = false; 838 return; 839 } 840 841 if (fromCommit->commitInfo[tid].robSquashing) { 842 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 843 844 dispatchStatus[tid] = Squashing; 845 846 emptyRenameInsts(tid); 847 wroteToTimeBuffer = true; 848 return; 849 } 850 851 if (checkStall(tid)) { 852 block(tid); 853 dispatchStatus[tid] = Blocked; 854 return; 855 } 856 857 if (dispatchStatus[tid] == Blocked) { 858 // Status from previous cycle was blocked, but there are no more stall 859 // conditions. Switch over to unblocking. 860 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 861 tid); 862 863 dispatchStatus[tid] = Unblocking; 864 865 unblock(tid); 866 867 return; 868 } 869 870 if (dispatchStatus[tid] == Squashing) { 871 // Switch status to running if rename isn't being told to block or 872 // squash this cycle. 873 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 874 tid); 875 876 dispatchStatus[tid] = Running; 877 878 return; 879 } 880} 881 882template <class Impl> 883void 884DefaultIEW<Impl>::sortInsts() 885{ 886 int insts_from_rename = fromRename->size; 887#ifdef DEBUG 888#if !ISA_HAS_DELAY_SLOT 889 for (int i = 0; i < numThreads; i++) 890 assert(insts[i].empty()); 891#endif 892#endif 893 for (int i = 0; i < insts_from_rename; ++i) { 894 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 895 } 896} 897 898template <class Impl> 899void 900DefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 901{ 902 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions until " 903 "[sn:%i].\n", tid, bdelayDoneSeqNum[tid]); 904 905 while (!insts[tid].empty()) { 906#if ISA_HAS_DELAY_SLOT 907 if (insts[tid].front()->seqNum <= bdelayDoneSeqNum[tid]) { 908 DPRINTF(IEW, "[tid:%i]: Done removing, cannot remove instruction" 909 " that occurs at or before delay slot [sn:%i].\n", 910 tid, bdelayDoneSeqNum[tid]); 911 break; 912 } else { 913 DPRINTF(IEW, "[tid:%i]: Removing incoming rename instruction " 914 "[sn:%i].\n", tid, insts[tid].front()->seqNum); 915 } 916#endif 917 918 if (insts[tid].front()->isLoad() || 919 insts[tid].front()->isStore() ) { 920 toRename->iewInfo[tid].dispatchedToLSQ++; 921 } 922 923 toRename->iewInfo[tid].dispatched++; 924 925 insts[tid].pop(); 926 } 927} 928 929template <class Impl> 930void 931DefaultIEW<Impl>::wakeCPU() 932{ 933 cpu->wakeCPU(); 934} 935 936template <class Impl> 937void 938DefaultIEW<Impl>::activityThisCycle() 939{ 940 DPRINTF(Activity, "Activity this cycle.\n"); 941 cpu->activityThisCycle(); 942} 943 944template <class Impl> 945inline void 946DefaultIEW<Impl>::activateStage() 947{ 948 DPRINTF(Activity, "Activating stage.\n"); 949 cpu->activateStage(O3CPU::IEWIdx); 950} 951 952template <class Impl> 953inline void 954DefaultIEW<Impl>::deactivateStage() 955{ 956 DPRINTF(Activity, "Deactivating stage.\n"); 957 cpu->deactivateStage(O3CPU::IEWIdx); 958} 959 960template<class Impl> 961void 962DefaultIEW<Impl>::dispatch(unsigned tid) 963{ 964 // If status is Running or idle, 965 // call dispatchInsts() 966 // If status is Unblocking, 967 // buffer any instructions coming from rename 968 // continue trying to empty skid buffer 969 // check if stall conditions have passed 970 971 if (dispatchStatus[tid] == Blocked) { 972 ++iewBlockCycles; 973 974 } else if (dispatchStatus[tid] == Squashing) { 975 ++iewSquashCycles; 976 } 977 978 // Dispatch should try to dispatch as many instructions as its bandwidth 979 // will allow, as long as it is not currently blocked. 980 if (dispatchStatus[tid] == Running || 981 dispatchStatus[tid] == Idle) { 982 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 983 "dispatch.\n", tid); 984 985 dispatchInsts(tid); 986 } else if (dispatchStatus[tid] == Unblocking) { 987 // Make sure that the skid buffer has something in it if the 988 // status is unblocking. 989 assert(!skidsEmpty()); 990 991 // If the status was unblocking, then instructions from the skid 992 // buffer were used. Remove those instructions and handle 993 // the rest of unblocking. 994 dispatchInsts(tid); 995 996 ++iewUnblockCycles; 997 998 if (validInstsFromRename() && dispatchedAllInsts) { 999 // Add the current inputs to the skid buffer so they can be 1000 // reprocessed when this stage unblocks. 1001 skidInsert(tid); 1002 } 1003 1004 unblock(tid); 1005 } 1006} 1007 1008template <class Impl> 1009void 1010DefaultIEW<Impl>::dispatchInsts(unsigned tid) 1011{ 1012 dispatchedAllInsts = true; 1013 1014 // Obtain instructions from skid buffer if unblocking, or queue from rename 1015 // otherwise. 1016 std::queue<DynInstPtr> &insts_to_dispatch = 1017 dispatchStatus[tid] == Unblocking ? 1018 skidBuffer[tid] : insts[tid]; 1019 1020 int insts_to_add = insts_to_dispatch.size(); 1021 1022 DynInstPtr inst; 1023 bool add_to_iq = false; 1024 int dis_num_inst = 0; 1025 1026 // Loop through the instructions, putting them in the instruction 1027 // queue. 1028 for ( ; dis_num_inst < insts_to_add && 1029 dis_num_inst < dispatchWidth; 1030 ++dis_num_inst) 1031 { 1032 inst = insts_to_dispatch.front(); 1033 1034 if (dispatchStatus[tid] == Unblocking) { 1035 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 1036 "buffer\n", tid); 1037 } 1038 1039 // Make sure there's a valid instruction there. 1040 assert(inst); 1041 1042 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 1043 "IQ.\n", 1044 tid, inst->readPC(), inst->seqNum, inst->threadNumber); 1045 1046 // Be sure to mark these instructions as ready so that the 1047 // commit stage can go ahead and execute them, and mark 1048 // them as issued so the IQ doesn't reprocess them. 1049 1050 // Check for squashed instructions. 1051 if (inst->isSquashed()) { 1052 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 1053 "not adding to IQ.\n", tid); 1054 1055 ++iewDispSquashedInsts; 1056 1057 insts_to_dispatch.pop(); 1058 1059 //Tell Rename That An Instruction has been processed 1060 if (inst->isLoad() || inst->isStore()) { 1061 toRename->iewInfo[tid].dispatchedToLSQ++; 1062 } 1063 toRename->iewInfo[tid].dispatched++; 1064 1065 continue; 1066 } 1067 1068 // Check for full conditions. 1069 if (instQueue.isFull(tid)) { 1070 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 1071 1072 // Call function to start blocking. 1073 block(tid); 1074 1075 // Set unblock to false. Special case where we are using 1076 // skidbuffer (unblocking) instructions but then we still 1077 // get full in the IQ. 1078 toRename->iewUnblock[tid] = false; 1079 1080 dispatchedAllInsts = false; 1081 1082 ++iewIQFullEvents; 1083 break; 1084 } else if (ldstQueue.isFull(tid)) { 1085 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 1086 1087 // Call function to start blocking. 1088 block(tid); 1089 1090 // Set unblock to false. Special case where we are using 1091 // skidbuffer (unblocking) instructions but then we still 1092 // get full in the IQ. 1093 toRename->iewUnblock[tid] = false; 1094 1095 dispatchedAllInsts = false; 1096 1097 ++iewLSQFullEvents; 1098 break; 1099 } 1100 1101 // Otherwise issue the instruction just fine. 1102 if (inst->isLoad()) { 1103 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1104 "encountered, adding to LSQ.\n", tid); 1105 1106 // Reserve a spot in the load store queue for this 1107 // memory access. 1108 ldstQueue.insertLoad(inst); 1109 1110 ++iewDispLoadInsts; 1111 1112 add_to_iq = true; 1113 1114 toRename->iewInfo[tid].dispatchedToLSQ++; 1115 } else if (inst->isStore()) { 1116 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1117 "encountered, adding to LSQ.\n", tid); 1118 1119 ldstQueue.insertStore(inst); 1120 1121 ++iewDispStoreInsts; 1122 1123 if (inst->isStoreConditional()) { 1124 // Store conditionals need to be set as "canCommit()" 1125 // so that commit can process them when they reach the 1126 // head of commit. 1127 // @todo: This is somewhat specific to Alpha. 1128 inst->setCanCommit(); 1129 instQueue.insertNonSpec(inst); 1130 add_to_iq = false; 1131 1132 ++iewDispNonSpecInsts; 1133 } else { 1134 add_to_iq = true; 1135 } 1136 1137 toRename->iewInfo[tid].dispatchedToLSQ++; 1138#if FULL_SYSTEM 1139 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1140 // Same as non-speculative stores. 1141 inst->setCanCommit(); 1142 instQueue.insertBarrier(inst); 1143 add_to_iq = false; 1144#endif 1145 } else if (inst->isNonSpeculative()) { 1146 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1147 "encountered, skipping.\n", tid); 1148 1149 // Same as non-speculative stores. 1150 inst->setCanCommit(); 1151 1152 // Specifically insert it as nonspeculative. 1153 instQueue.insertNonSpec(inst); 1154 1155 ++iewDispNonSpecInsts; 1156 1157 add_to_iq = false; 1158 } else if (inst->isNop()) { 1159 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1160 "skipping.\n", tid); 1161 1162 inst->setIssued(); 1163 inst->setExecuted(); 1164 inst->setCanCommit(); 1165 1166 instQueue.recordProducer(inst); 1167 1168 iewExecutedNop[tid]++; 1169 1170 add_to_iq = false; 1171 } else if (inst->isExecuted()) { 1172 assert(0 && "Instruction shouldn't be executed.\n"); 1173 DPRINTF(IEW, "Issue: Executed branch encountered, " 1174 "skipping.\n"); 1175 1176 inst->setIssued(); 1177 inst->setCanCommit(); 1178 1179 instQueue.recordProducer(inst); 1180 1181 add_to_iq = false; 1182 } else { 1183 add_to_iq = true; 1184 } 1185 1186 // If the instruction queue is not full, then add the 1187 // instruction. 1188 if (add_to_iq) { 1189 instQueue.insert(inst); 1190 } 1191 1192 insts_to_dispatch.pop(); 1193 1194 toRename->iewInfo[tid].dispatched++; 1195 1196 ++iewDispatchedInsts; 1197 } 1198 1199 if (!insts_to_dispatch.empty()) { 1200 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 1201 block(tid); 1202 toRename->iewUnblock[tid] = false; 1203 } 1204 1205 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1206 dispatchStatus[tid] = Running; 1207 1208 updatedQueues = true; 1209 } 1210 1211 dis_num_inst = 0; 1212} 1213 1214template <class Impl> 1215void 1216DefaultIEW<Impl>::printAvailableInsts() 1217{ 1218 int inst = 0; 1219 1220 std::cout << "Available Instructions: "; 1221 1222 while (fromIssue->insts[inst]) { 1223 1224 if (inst%3==0) std::cout << "\n\t"; 1225 1226 std::cout << "PC: " << fromIssue->insts[inst]->readPC() 1227 << " TN: " << fromIssue->insts[inst]->threadNumber 1228 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1229 1230 inst++; 1231 1232 } 1233 1234 std::cout << "\n"; 1235} 1236 1237template <class Impl> 1238void 1239DefaultIEW<Impl>::executeInsts() 1240{ 1241 wbNumInst = 0; 1242 wbCycle = 0; 1243 1244 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 1245 1246 while (threads != (*activeThreads).end()) { 1247 unsigned tid = *threads++; 1248 fetchRedirect[tid] = false; 1249 } 1250 1251 // Uncomment this if you want to see all available instructions. 1252// printAvailableInsts(); 1253 1254 // Execute/writeback any instructions that are available. 1255 int insts_to_execute = fromIssue->size; 1256 int inst_num = 0; 1257 for (; inst_num < insts_to_execute; 1258 ++inst_num) { 1259 1260 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1261 1262 DynInstPtr inst = instQueue.getInstToExecute(); 1263 1264 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 1265 inst->readPC(), inst->threadNumber,inst->seqNum); 1266 1267 // Check if the instruction is squashed; if so then skip it 1268 if (inst->isSquashed()) { 1269 DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 1270 1271 // Consider this instruction executed so that commit can go 1272 // ahead and retire the instruction. 1273 inst->setExecuted(); 1274 1275 // Not sure if I should set this here or just let commit try to 1276 // commit any squashed instructions. I like the latter a bit more. 1277 inst->setCanCommit(); 1278 1279 ++iewExecSquashedInsts; 1280 1281 decrWb(inst->seqNum); 1282 continue; 1283 } 1284 1285 Fault fault = NoFault; 1286 1287 // Execute instruction. 1288 // Note that if the instruction faults, it will be handled 1289 // at the commit stage. 1290 if (inst->isMemRef() && 1291 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 1292 DPRINTF(IEW, "Execute: Calculating address for memory " 1293 "reference.\n"); 1294 1295 // Tell the LDSTQ to execute this instruction (if it is a load). 1296 if (inst->isLoad()) { 1297 // Loads will mark themselves as executed, and their writeback 1298 // event adds the instruction to the queue to commit 1299 fault = ldstQueue.executeLoad(inst); 1300 } else if (inst->isStore()) { 1301 fault = ldstQueue.executeStore(inst); 1302 1303 // If the store had a fault then it may not have a mem req 1304 if (!inst->isStoreConditional() && fault == NoFault) { 1305 inst->setExecuted(); 1306 1307 instToCommit(inst); 1308 } else if (fault != NoFault) { 1309 // If the instruction faulted, then we need to send it along to commit 1310 // without the instruction completing. 1311 DPRINTF(IEW, "Store has fault! [sn:%lli]\n", inst->seqNum); 1312 1313 // Send this instruction to commit, also make sure iew stage 1314 // realizes there is activity. 1315 inst->setExecuted(); 1316 1317 instToCommit(inst); 1318 activityThisCycle(); 1319 } 1320 1321 // Store conditionals will mark themselves as 1322 // executed, and their writeback event will add the 1323 // instruction to the queue to commit. 1324 } else { 1325 panic("Unexpected memory type!\n"); 1326 } 1327 1328 } else { 1329 inst->execute(); 1330 1331 inst->setExecuted(); 1332 1333 instToCommit(inst); 1334 } 1335 1336 updateExeInstStats(inst); 1337 1338 // Check if branch prediction was correct, if not then we need 1339 // to tell commit to squash in flight instructions. Only 1340 // handle this if there hasn't already been something that 1341 // redirects fetch in this group of instructions. 1342 1343 // This probably needs to prioritize the redirects if a different 1344 // scheduler is used. Currently the scheduler schedules the oldest 1345 // instruction first, so the branch resolution order will be correct. 1346 unsigned tid = inst->threadNumber; 1347 1348 if (!fetchRedirect[tid]) { 1349 1350 if (inst->mispredicted()) { 1351 fetchRedirect[tid] = true; 1352 1353 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1354 DPRINTF(IEW, "Predicted target was %#x.\n", inst->predPC); 1355#if ISA_HAS_DELAY_SLOT 1356 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 1357 inst->nextNPC); 1358#else 1359 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 1360 inst->nextPC); 1361#endif 1362 // If incorrect, then signal the ROB that it must be squashed. 1363 squashDueToBranch(inst, tid); 1364 1365 if (inst->readPredTaken()) { 1366 predictedTakenIncorrect++; 1367 } else { 1368 predictedNotTakenIncorrect++; 1369 } 1370 } else if (ldstQueue.violation(tid)) { 1371 fetchRedirect[tid] = true; 1372 1373 // If there was an ordering violation, then get the 1374 // DynInst that caused the violation. Note that this 1375 // clears the violation signal. 1376 DynInstPtr violator; 1377 violator = ldstQueue.getMemDepViolator(tid); 1378 1379 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1380 "%#x, inst PC: %#x. Addr is: %#x.\n", 1381 violator->readPC(), inst->readPC(), inst->physEffAddr); 1382 1383 // Tell the instruction queue that a violation has occured. 1384 instQueue.violation(inst, violator); 1385 1386 // Squash. 1387 squashDueToMemOrder(inst,tid); 1388 1389 ++memOrderViolationEvents; 1390 } else if (ldstQueue.loadBlocked(tid) && 1391 !ldstQueue.isLoadBlockedHandled(tid)) { 1392 fetchRedirect[tid] = true; 1393 1394 DPRINTF(IEW, "Load operation couldn't execute because the " 1395 "memory system is blocked. PC: %#x [sn:%lli]\n", 1396 inst->readPC(), inst->seqNum); 1397 1398 squashDueToMemBlocked(inst, tid); 1399 } 1400 } 1401 } 1402 1403 // Update and record activity if we processed any instructions. 1404 if (inst_num) { 1405 if (exeStatus == Idle) { 1406 exeStatus = Running; 1407 } 1408 1409 updatedQueues = true; 1410 1411 cpu->activityThisCycle(); 1412 } 1413 1414 // Need to reset this in case a writeback event needs to write into the 1415 // iew queue. That way the writeback event will write into the correct 1416 // spot in the queue. 1417 wbNumInst = 0; 1418} 1419 1420template <class Impl> 1421void 1422DefaultIEW<Impl>::writebackInsts() 1423{ 1424 // Loop through the head of the time buffer and wake any 1425 // dependents. These instructions are about to write back. Also 1426 // mark scoreboard that this instruction is finally complete. 1427 // Either have IEW have direct access to scoreboard, or have this 1428 // as part of backwards communication. 1429 for (int inst_num = 0; inst_num < issueWidth && 1430 toCommit->insts[inst_num]; inst_num++) { 1431 DynInstPtr inst = toCommit->insts[inst_num]; 1432 int tid = inst->threadNumber; 1433 1434 DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 1435 inst->seqNum, inst->readPC()); 1436 1437 iewInstsToCommit[tid]++; 1438 1439 // Some instructions will be sent to commit without having 1440 // executed because they need commit to handle them. 1441 // E.g. Uncached loads have not actually executed when they 1442 // are first sent to commit. Instead commit must tell the LSQ 1443 // when it's ready to execute the uncached load. 1444 if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 1445 int dependents = instQueue.wakeDependents(inst); 1446 1447 for (int i = 0; i < inst->numDestRegs(); i++) { 1448 //mark as Ready 1449 DPRINTF(IEW,"Setting Destination Register %i\n", 1450 inst->renamedDestRegIdx(i)); 1451 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1452 } 1453 1454 if (dependents) { 1455 producerInst[tid]++; 1456 consumerInst[tid]+= dependents; 1457 } 1458 writebackCount[tid]++; 1459 } 1460 1461 decrWb(inst->seqNum); 1462 } 1463} 1464 1465template<class Impl> 1466void 1467DefaultIEW<Impl>::tick() 1468{ 1469 wbNumInst = 0; 1470 wbCycle = 0; 1471 1472 wroteToTimeBuffer = false; 1473 updatedQueues = false; 1474 1475 sortInsts(); 1476 1477 // Free function units marked as being freed this cycle. 1478 fuPool->processFreeUnits(); 1479 1480 std::list<unsigned>::iterator threads = (*activeThreads).begin(); 1481 1482 // Check stall and squash signals, dispatch any instructions. 1483 while (threads != (*activeThreads).end()) { 1484 unsigned tid = *threads++; 1485 1486 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1487 1488 checkSignalsAndUpdate(tid); 1489 dispatch(tid); 1490 } 1491 1492 if (exeStatus != Squashing) { 1493 executeInsts(); 1494 1495 writebackInsts(); 1496 1497 // Have the instruction queue try to schedule any ready instructions. 1498 // (In actuality, this scheduling is for instructions that will 1499 // be executed next cycle.) 1500 instQueue.scheduleReadyInsts(); 1501 1502 // Also should advance its own time buffers if the stage ran. 1503 // Not the best place for it, but this works (hopefully). 1504 issueToExecQueue.advance(); 1505 } 1506 1507 bool broadcast_free_entries = false; 1508 1509 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1510 exeStatus = Idle; 1511 updateLSQNextCycle = false; 1512 1513 broadcast_free_entries = true; 1514 } 1515 1516 // Writeback any stores using any leftover bandwidth. 1517 ldstQueue.writebackStores(); 1518 1519 // Check the committed load/store signals to see if there's a load 1520 // or store to commit. Also check if it's being told to execute a 1521 // nonspeculative instruction. 1522 // This is pretty inefficient... 1523 1524 threads = (*activeThreads).begin(); 1525 while (threads != (*activeThreads).end()) { 1526 unsigned tid = (*threads++); 1527 1528 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1529 1530 // Update structures based on instructions committed. 1531 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1532 !fromCommit->commitInfo[tid].squash && 1533 !fromCommit->commitInfo[tid].robSquashing) { 1534 1535 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1536 1537 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1538 1539 updateLSQNextCycle = true; 1540 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1541 } 1542 1543 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1544 1545 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1546 if (fromCommit->commitInfo[tid].uncached) { 1547 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1548 } else { 1549 instQueue.scheduleNonSpec( 1550 fromCommit->commitInfo[tid].nonSpecSeqNum); 1551 } 1552 } 1553 1554 if (broadcast_free_entries) { 1555 toFetch->iewInfo[tid].iqCount = 1556 instQueue.getCount(tid); 1557 toFetch->iewInfo[tid].ldstqCount = 1558 ldstQueue.getCount(tid); 1559 1560 toRename->iewInfo[tid].usedIQ = true; 1561 toRename->iewInfo[tid].freeIQEntries = 1562 instQueue.numFreeEntries(); 1563 toRename->iewInfo[tid].usedLSQ = true; 1564 toRename->iewInfo[tid].freeLSQEntries = 1565 ldstQueue.numFreeEntries(tid); 1566 1567 wroteToTimeBuffer = true; 1568 } 1569 1570 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1571 tid, toRename->iewInfo[tid].dispatched); 1572 } 1573 1574 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1575 "LSQ has %i free entries.\n", 1576 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1577 ldstQueue.numFreeEntries()); 1578 1579 updateStatus(); 1580 1581 if (wroteToTimeBuffer) { 1582 DPRINTF(Activity, "Activity this cycle.\n"); 1583 cpu->activityThisCycle(); 1584 } 1585} 1586 1587template <class Impl> 1588void 1589DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1590{ 1591 int thread_number = inst->threadNumber; 1592 1593 // 1594 // Pick off the software prefetches 1595 // 1596#ifdef TARGET_ALPHA 1597 if (inst->isDataPrefetch()) 1598 iewExecutedSwp[thread_number]++; 1599 else 1600 iewIewExecutedcutedInsts++; 1601#else 1602 iewExecutedInsts++; 1603#endif 1604 1605 // 1606 // Control operations 1607 // 1608 if (inst->isControl()) 1609 iewExecutedBranches[thread_number]++; 1610 1611 // 1612 // Memory operations 1613 // 1614 if (inst->isMemRef()) { 1615 iewExecutedRefs[thread_number]++; 1616 1617 if (inst->isLoad()) { 1618 iewExecLoadInsts[thread_number]++; 1619 } 1620 } 1621} 1622