iew_impl.hh revision 2669
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29// @todo: Fix the instantaneous communication among all the stages within 30// iew. There's a clear delay between issue and execute, yet backwards 31// communication happens simultaneously. 32 33#include <queue> 34 35#include "base/timebuf.hh" 36#include "cpu/o3/fu_pool.hh" 37#include "cpu/o3/iew.hh" 38 39using namespace std; 40 41template<class Impl> 42DefaultIEW<Impl>::DefaultIEW(Params *params) 43 : // @todo: Make this into a parameter. 44 issueToExecQueue(5, 5), 45 instQueue(params), 46 ldstQueue(params), 47 fuPool(params->fuPool), 48 commitToIEWDelay(params->commitToIEWDelay), 49 renameToIEWDelay(params->renameToIEWDelay), 50 issueToExecuteDelay(params->issueToExecuteDelay), 51 issueReadWidth(params->issueWidth), 52 issueWidth(params->issueWidth), 53 executeWidth(params->executeWidth), 54 numThreads(params->numberOfThreads), 55 switchedOut(false) 56{ 57 _status = Active; 58 exeStatus = Running; 59 wbStatus = Idle; 60 61 // Setup wire to read instructions coming from issue. 62 fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 63 64 // Instruction queue needs the queue between issue and execute. 65 instQueue.setIssueToExecuteQueue(&issueToExecQueue); 66 67 instQueue.setIEW(this); 68 ldstQueue.setIEW(this); 69 70 for (int i=0; i < numThreads; i++) { 71 dispatchStatus[i] = Running; 72 stalls[i].commit = false; 73 fetchRedirect[i] = false; 74 } 75 76 updateLSQNextCycle = false; 77 78 skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 79} 80 81template <class Impl> 82std::string 83DefaultIEW<Impl>::name() const 84{ 85 return cpu->name() + ".iew"; 86} 87 88template <class Impl> 89void 90DefaultIEW<Impl>::regStats() 91{ 92 using namespace Stats; 93 94 instQueue.regStats(); 95 96 iewIdleCycles 97 .name(name() + ".iewIdleCycles") 98 .desc("Number of cycles IEW is idle"); 99 100 iewSquashCycles 101 .name(name() + ".iewSquashCycles") 102 .desc("Number of cycles IEW is squashing"); 103 104 iewBlockCycles 105 .name(name() + ".iewBlockCycles") 106 .desc("Number of cycles IEW is blocking"); 107 108 iewUnblockCycles 109 .name(name() + ".iewUnblockCycles") 110 .desc("Number of cycles IEW is unblocking"); 111 112 iewDispatchedInsts 113 .name(name() + ".iewDispatchedInsts") 114 .desc("Number of instructions dispatched to IQ"); 115 116 iewDispSquashedInsts 117 .name(name() + ".iewDispSquashedInsts") 118 .desc("Number of squashed instructions skipped by dispatch"); 119 120 iewDispLoadInsts 121 .name(name() + ".iewDispLoadInsts") 122 .desc("Number of dispatched load instructions"); 123 124 iewDispStoreInsts 125 .name(name() + ".iewDispStoreInsts") 126 .desc("Number of dispatched store instructions"); 127 128 iewDispNonSpecInsts 129 .name(name() + ".iewDispNonSpecInsts") 130 .desc("Number of dispatched non-speculative instructions"); 131 132 iewIQFullEvents 133 .name(name() + ".iewIQFullEvents") 134 .desc("Number of times the IQ has become full, causing a stall"); 135 136 iewLSQFullEvents 137 .name(name() + ".iewLSQFullEvents") 138 .desc("Number of times the LSQ has become full, causing a stall"); 139 140 iewExecutedInsts 141 .name(name() + ".iewExecutedInsts") 142 .desc("Number of executed instructions"); 143 144 iewExecLoadInsts 145 .init(cpu->number_of_threads) 146 .name(name() + ".iewExecLoadInsts") 147 .desc("Number of load instructions executed") 148 .flags(total); 149 150 iewExecSquashedInsts 151 .name(name() + ".iewExecSquashedInsts") 152 .desc("Number of squashed instructions skipped in execute"); 153 154 memOrderViolationEvents 155 .name(name() + ".memOrderViolationEvents") 156 .desc("Number of memory order violations"); 157 158 predictedTakenIncorrect 159 .name(name() + ".predictedTakenIncorrect") 160 .desc("Number of branches that were predicted taken incorrectly"); 161 162 predictedNotTakenIncorrect 163 .name(name() + ".predictedNotTakenIncorrect") 164 .desc("Number of branches that were predicted not taken incorrectly"); 165 166 branchMispredicts 167 .name(name() + ".branchMispredicts") 168 .desc("Number of branch mispredicts detected at execute"); 169 170 branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 171 172 exeSwp 173 .init(cpu->number_of_threads) 174 .name(name() + ".EXEC:swp") 175 .desc("number of swp insts executed") 176 .flags(total) 177 ; 178 179 exeNop 180 .init(cpu->number_of_threads) 181 .name(name() + ".EXEC:nop") 182 .desc("number of nop insts executed") 183 .flags(total) 184 ; 185 186 exeRefs 187 .init(cpu->number_of_threads) 188 .name(name() + ".EXEC:refs") 189 .desc("number of memory reference insts executed") 190 .flags(total) 191 ; 192 193 exeBranches 194 .init(cpu->number_of_threads) 195 .name(name() + ".EXEC:branches") 196 .desc("Number of branches executed") 197 .flags(total) 198 ; 199 200 issueRate 201 .name(name() + ".EXEC:rate") 202 .desc("Inst execution rate") 203 .flags(total) 204 ; 205 issueRate = iewExecutedInsts / cpu->numCycles; 206 207 iewExecStoreInsts 208 .name(name() + ".EXEC:stores") 209 .desc("Number of stores executed") 210 .flags(total) 211 ; 212 iewExecStoreInsts = exeRefs - iewExecLoadInsts; 213/* 214 for (int i=0; i<Num_OpClasses; ++i) { 215 stringstream subname; 216 subname << opClassStrings[i] << "_delay"; 217 issue_delay_dist.subname(i, subname.str()); 218 } 219*/ 220 // 221 // Other stats 222 // 223 224 iewInstsToCommit 225 .init(cpu->number_of_threads) 226 .name(name() + ".WB:sent") 227 .desc("cumulative count of insts sent to commit") 228 .flags(total) 229 ; 230 231 writebackCount 232 .init(cpu->number_of_threads) 233 .name(name() + ".WB:count") 234 .desc("cumulative count of insts written-back") 235 .flags(total) 236 ; 237 238 producerInst 239 .init(cpu->number_of_threads) 240 .name(name() + ".WB:producers") 241 .desc("num instructions producing a value") 242 .flags(total) 243 ; 244 245 consumerInst 246 .init(cpu->number_of_threads) 247 .name(name() + ".WB:consumers") 248 .desc("num instructions consuming a value") 249 .flags(total) 250 ; 251 252 wbPenalized 253 .init(cpu->number_of_threads) 254 .name(name() + ".WB:penalized") 255 .desc("number of instrctions required to write to 'other' IQ") 256 .flags(total) 257 ; 258 259 wbPenalizedRate 260 .name(name() + ".WB:penalized_rate") 261 .desc ("fraction of instructions written-back that wrote to 'other' IQ") 262 .flags(total) 263 ; 264 265 wbPenalizedRate = wbPenalized / writebackCount; 266 267 wbFanout 268 .name(name() + ".WB:fanout") 269 .desc("average fanout of values written-back") 270 .flags(total) 271 ; 272 273 wbFanout = producerInst / consumerInst; 274 275 wbRate 276 .name(name() + ".WB:rate") 277 .desc("insts written-back per cycle") 278 .flags(total) 279 ; 280 wbRate = writebackCount / cpu->numCycles; 281} 282 283template<class Impl> 284void 285DefaultIEW<Impl>::initStage() 286{ 287 for (int tid=0; tid < numThreads; tid++) { 288 toRename->iewInfo[tid].usedIQ = true; 289 toRename->iewInfo[tid].freeIQEntries = 290 instQueue.numFreeEntries(tid); 291 292 toRename->iewInfo[tid].usedLSQ = true; 293 toRename->iewInfo[tid].freeLSQEntries = 294 ldstQueue.numFreeEntries(tid); 295 } 296} 297 298template<class Impl> 299void 300DefaultIEW<Impl>::setCPU(FullCPU *cpu_ptr) 301{ 302 DPRINTF(IEW, "Setting CPU pointer.\n"); 303 cpu = cpu_ptr; 304 305 instQueue.setCPU(cpu_ptr); 306 ldstQueue.setCPU(cpu_ptr); 307 308 cpu->activateStage(FullCPU::IEWIdx); 309} 310 311template<class Impl> 312void 313DefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 314{ 315 DPRINTF(IEW, "Setting time buffer pointer.\n"); 316 timeBuffer = tb_ptr; 317 318 // Setup wire to read information from time buffer, from commit. 319 fromCommit = timeBuffer->getWire(-commitToIEWDelay); 320 321 // Setup wire to write information back to previous stages. 322 toRename = timeBuffer->getWire(0); 323 324 toFetch = timeBuffer->getWire(0); 325 326 // Instruction queue also needs main time buffer. 327 instQueue.setTimeBuffer(tb_ptr); 328} 329 330template<class Impl> 331void 332DefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 333{ 334 DPRINTF(IEW, "Setting rename queue pointer.\n"); 335 renameQueue = rq_ptr; 336 337 // Setup wire to read information from rename queue. 338 fromRename = renameQueue->getWire(-renameToIEWDelay); 339} 340 341template<class Impl> 342void 343DefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 344{ 345 DPRINTF(IEW, "Setting IEW queue pointer.\n"); 346 iewQueue = iq_ptr; 347 348 // Setup wire to write instructions to commit. 349 toCommit = iewQueue->getWire(0); 350} 351 352template<class Impl> 353void 354DefaultIEW<Impl>::setActiveThreads(list<unsigned> *at_ptr) 355{ 356 DPRINTF(IEW, "Setting active threads list pointer.\n"); 357 activeThreads = at_ptr; 358 359 ldstQueue.setActiveThreads(at_ptr); 360 instQueue.setActiveThreads(at_ptr); 361} 362 363template<class Impl> 364void 365DefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 366{ 367 DPRINTF(IEW, "Setting scoreboard pointer.\n"); 368 scoreboard = sb_ptr; 369} 370 371#if 0 372template<class Impl> 373void 374DefaultIEW<Impl>::setPageTable(PageTable *pt_ptr) 375{ 376 ldstQueue.setPageTable(pt_ptr); 377} 378#endif 379 380template <class Impl> 381void 382DefaultIEW<Impl>::switchOut() 383{ 384 cpu->signalSwitched(); 385} 386 387template <class Impl> 388void 389DefaultIEW<Impl>::doSwitchOut() 390{ 391 switchedOut = true; 392 393 instQueue.switchOut(); 394 ldstQueue.switchOut(); 395 fuPool->switchOut(); 396 397 for (int i = 0; i < numThreads; i++) { 398 while (!insts[i].empty()) 399 insts[i].pop(); 400 while (!skidBuffer[i].empty()) 401 skidBuffer[i].pop(); 402 } 403} 404 405template <class Impl> 406void 407DefaultIEW<Impl>::takeOverFrom() 408{ 409 _status = Active; 410 exeStatus = Running; 411 wbStatus = Idle; 412 switchedOut = false; 413 414 instQueue.takeOverFrom(); 415 ldstQueue.takeOverFrom(); 416 fuPool->takeOverFrom(); 417 418 initStage(); 419 cpu->activityThisCycle(); 420 421 for (int i=0; i < numThreads; i++) { 422 dispatchStatus[i] = Running; 423 stalls[i].commit = false; 424 fetchRedirect[i] = false; 425 } 426 427 updateLSQNextCycle = false; 428 429 // @todo: Fix hardcoded number 430 for (int i = 0; i < 6; ++i) { 431 issueToExecQueue.advance(); 432 } 433} 434 435template<class Impl> 436void 437DefaultIEW<Impl>::squash(unsigned tid) 438{ 439 DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 440 tid); 441 442 // Tell the IQ to start squashing. 443 instQueue.squash(tid); 444 445 // Tell the LDSTQ to start squashing. 446 ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 447 448 updatedQueues = true; 449 450 // Clear the skid buffer in case it has any data in it. 451 while (!skidBuffer[tid].empty()) { 452 453 if (skidBuffer[tid].front()->isLoad() || 454 skidBuffer[tid].front()->isStore() ) { 455 toRename->iewInfo[tid].dispatchedToLSQ++; 456 } 457 458 toRename->iewInfo[tid].dispatched++; 459 460 skidBuffer[tid].pop(); 461 } 462 463 while (!insts[tid].empty()) { 464 if (insts[tid].front()->isLoad() || 465 insts[tid].front()->isStore() ) { 466 toRename->iewInfo[tid].dispatchedToLSQ++; 467 } 468 469 toRename->iewInfo[tid].dispatched++; 470 471 insts[tid].pop(); 472 } 473} 474 475template<class Impl> 476void 477DefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 478{ 479 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 480 "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 481 482 toCommit->squash[tid] = true; 483 toCommit->squashedSeqNum[tid] = inst->seqNum; 484 toCommit->mispredPC[tid] = inst->readPC(); 485 toCommit->nextPC[tid] = inst->readNextPC(); 486 toCommit->branchMispredict[tid] = true; 487 toCommit->branchTaken[tid] = inst->readNextPC() != 488 (inst->readPC() + sizeof(TheISA::MachInst)); 489 490 toCommit->includeSquashInst[tid] = false; 491 492 wroteToTimeBuffer = true; 493} 494 495template<class Impl> 496void 497DefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 498{ 499 DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 500 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 501 502 toCommit->squash[tid] = true; 503 toCommit->squashedSeqNum[tid] = inst->seqNum; 504 toCommit->nextPC[tid] = inst->readNextPC(); 505 506 toCommit->includeSquashInst[tid] = false; 507 508 wroteToTimeBuffer = true; 509} 510 511template<class Impl> 512void 513DefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 514{ 515 DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 516 "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 517 518 toCommit->squash[tid] = true; 519 toCommit->squashedSeqNum[tid] = inst->seqNum; 520 toCommit->nextPC[tid] = inst->readPC(); 521 522 toCommit->includeSquashInst[tid] = true; 523 524 ldstQueue.setLoadBlockedHandled(tid); 525 526 wroteToTimeBuffer = true; 527} 528 529template<class Impl> 530void 531DefaultIEW<Impl>::block(unsigned tid) 532{ 533 DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 534 535 if (dispatchStatus[tid] != Blocked && 536 dispatchStatus[tid] != Unblocking) { 537 toRename->iewBlock[tid] = true; 538 wroteToTimeBuffer = true; 539 } 540 541 // Add the current inputs to the skid buffer so they can be 542 // reprocessed when this stage unblocks. 543 skidInsert(tid); 544 545 dispatchStatus[tid] = Blocked; 546} 547 548template<class Impl> 549void 550DefaultIEW<Impl>::unblock(unsigned tid) 551{ 552 DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 553 "buffer %u.\n",tid, tid); 554 555 // If the skid bufffer is empty, signal back to previous stages to unblock. 556 // Also switch status to running. 557 if (skidBuffer[tid].empty()) { 558 toRename->iewUnblock[tid] = true; 559 wroteToTimeBuffer = true; 560 DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 561 dispatchStatus[tid] = Running; 562 } 563} 564 565template<class Impl> 566void 567DefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 568{ 569 instQueue.wakeDependents(inst); 570} 571 572template<class Impl> 573void 574DefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 575{ 576 instQueue.rescheduleMemInst(inst); 577} 578 579template<class Impl> 580void 581DefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 582{ 583 instQueue.replayMemInst(inst); 584} 585 586template<class Impl> 587void 588DefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 589{ 590 // First check the time slot that this instruction will write 591 // to. If there are free write ports at the time, then go ahead 592 // and write the instruction to that time. If there are not, 593 // keep looking back to see where's the first time there's a 594 // free slot. 595 while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 596 ++wbNumInst; 597 if (wbNumInst == issueWidth) { 598 ++wbCycle; 599 wbNumInst = 0; 600 } 601 602 assert(wbCycle < 5); 603 } 604 605 // Add finished instruction to queue to commit. 606 (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 607 (*iewQueue)[wbCycle].size++; 608} 609 610template <class Impl> 611unsigned 612DefaultIEW<Impl>::validInstsFromRename() 613{ 614 unsigned inst_count = 0; 615 616 for (int i=0; i<fromRename->size; i++) { 617 if (!fromRename->insts[i]->squashed) 618 inst_count++; 619 } 620 621 return inst_count; 622} 623 624template<class Impl> 625void 626DefaultIEW<Impl>::skidInsert(unsigned tid) 627{ 628 DynInstPtr inst = NULL; 629 630 while (!insts[tid].empty()) { 631 inst = insts[tid].front(); 632 633 insts[tid].pop(); 634 635 DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 636 "dispatch skidBuffer %i\n",tid, inst->seqNum, 637 inst->readPC(),tid); 638 639 skidBuffer[tid].push(inst); 640 } 641 642 assert(skidBuffer[tid].size() <= skidBufferMax && 643 "Skidbuffer Exceeded Max Size"); 644} 645 646template<class Impl> 647int 648DefaultIEW<Impl>::skidCount() 649{ 650 int max=0; 651 652 list<unsigned>::iterator threads = (*activeThreads).begin(); 653 654 while (threads != (*activeThreads).end()) { 655 unsigned thread_count = skidBuffer[*threads++].size(); 656 if (max < thread_count) 657 max = thread_count; 658 } 659 660 return max; 661} 662 663template<class Impl> 664bool 665DefaultIEW<Impl>::skidsEmpty() 666{ 667 list<unsigned>::iterator threads = (*activeThreads).begin(); 668 669 while (threads != (*activeThreads).end()) { 670 if (!skidBuffer[*threads++].empty()) 671 return false; 672 } 673 674 return true; 675} 676 677template <class Impl> 678void 679DefaultIEW<Impl>::updateStatus() 680{ 681 bool any_unblocking = false; 682 683 list<unsigned>::iterator threads = (*activeThreads).begin(); 684 685 threads = (*activeThreads).begin(); 686 687 while (threads != (*activeThreads).end()) { 688 unsigned tid = *threads++; 689 690 if (dispatchStatus[tid] == Unblocking) { 691 any_unblocking = true; 692 break; 693 } 694 } 695 696 // If there are no ready instructions waiting to be scheduled by the IQ, 697 // and there's no stores waiting to write back, and dispatch is not 698 // unblocking, then there is no internal activity for the IEW stage. 699 if (_status == Active && !instQueue.hasReadyInsts() && 700 !ldstQueue.willWB() && !any_unblocking) { 701 DPRINTF(IEW, "IEW switching to idle\n"); 702 703 deactivateStage(); 704 705 _status = Inactive; 706 } else if (_status == Inactive && (instQueue.hasReadyInsts() || 707 ldstQueue.willWB() || 708 any_unblocking)) { 709 // Otherwise there is internal activity. Set to active. 710 DPRINTF(IEW, "IEW switching to active\n"); 711 712 activateStage(); 713 714 _status = Active; 715 } 716} 717 718template <class Impl> 719void 720DefaultIEW<Impl>::resetEntries() 721{ 722 instQueue.resetEntries(); 723 ldstQueue.resetEntries(); 724} 725 726template <class Impl> 727void 728DefaultIEW<Impl>::readStallSignals(unsigned tid) 729{ 730 if (fromCommit->commitBlock[tid]) { 731 stalls[tid].commit = true; 732 } 733 734 if (fromCommit->commitUnblock[tid]) { 735 assert(stalls[tid].commit); 736 stalls[tid].commit = false; 737 } 738} 739 740template <class Impl> 741bool 742DefaultIEW<Impl>::checkStall(unsigned tid) 743{ 744 bool ret_val(false); 745 746 if (stalls[tid].commit) { 747 DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 748 ret_val = true; 749 } else if (instQueue.isFull(tid)) { 750 DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 751 ret_val = true; 752 } else if (ldstQueue.isFull(tid)) { 753 DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 754 755 if (ldstQueue.numLoads(tid) > 0 ) { 756 757 DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 758 tid,ldstQueue.getLoadHeadSeqNum(tid)); 759 } 760 761 if (ldstQueue.numStores(tid) > 0) { 762 763 DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 764 tid,ldstQueue.getStoreHeadSeqNum(tid)); 765 } 766 767 ret_val = true; 768 } else if (ldstQueue.isStalled(tid)) { 769 DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 770 ret_val = true; 771 } 772 773 return ret_val; 774} 775 776template <class Impl> 777void 778DefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 779{ 780 // Check if there's a squash signal, squash if there is 781 // Check stall signals, block if there is. 782 // If status was Blocked 783 // if so then go to unblocking 784 // If status was Squashing 785 // check if squashing is not high. Switch to running this cycle. 786 787 readStallSignals(tid); 788 789 if (fromCommit->commitInfo[tid].squash) { 790 squash(tid); 791 792 if (dispatchStatus[tid] == Blocked || 793 dispatchStatus[tid] == Unblocking) { 794 toRename->iewUnblock[tid] = true; 795 wroteToTimeBuffer = true; 796 } 797 798 dispatchStatus[tid] = Squashing; 799 800 fetchRedirect[tid] = false; 801 return; 802 } 803 804 if (fromCommit->commitInfo[tid].robSquashing) { 805 DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n"); 806 807 dispatchStatus[tid] = Squashing; 808 809 return; 810 } 811 812 if (checkStall(tid)) { 813 block(tid); 814 dispatchStatus[tid] = Blocked; 815 return; 816 } 817 818 if (dispatchStatus[tid] == Blocked) { 819 // Status from previous cycle was blocked, but there are no more stall 820 // conditions. Switch over to unblocking. 821 DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 822 tid); 823 824 dispatchStatus[tid] = Unblocking; 825 826 unblock(tid); 827 828 return; 829 } 830 831 if (dispatchStatus[tid] == Squashing) { 832 // Switch status to running if rename isn't being told to block or 833 // squash this cycle. 834 DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 835 tid); 836 837 dispatchStatus[tid] = Running; 838 839 return; 840 } 841} 842 843template <class Impl> 844void 845DefaultIEW<Impl>::sortInsts() 846{ 847 int insts_from_rename = fromRename->size; 848#ifdef DEBUG 849 for (int i = 0; i < numThreads; i++) 850 assert(insts[i].empty()); 851#endif 852 for (int i = 0; i < insts_from_rename; ++i) { 853 insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 854 } 855} 856 857template <class Impl> 858void 859DefaultIEW<Impl>::wakeCPU() 860{ 861 cpu->wakeCPU(); 862} 863 864template <class Impl> 865void 866DefaultIEW<Impl>::activityThisCycle() 867{ 868 DPRINTF(Activity, "Activity this cycle.\n"); 869 cpu->activityThisCycle(); 870} 871 872template <class Impl> 873inline void 874DefaultIEW<Impl>::activateStage() 875{ 876 DPRINTF(Activity, "Activating stage.\n"); 877 cpu->activateStage(FullCPU::IEWIdx); 878} 879 880template <class Impl> 881inline void 882DefaultIEW<Impl>::deactivateStage() 883{ 884 DPRINTF(Activity, "Deactivating stage.\n"); 885 cpu->deactivateStage(FullCPU::IEWIdx); 886} 887 888template<class Impl> 889void 890DefaultIEW<Impl>::dispatch(unsigned tid) 891{ 892 // If status is Running or idle, 893 // call dispatchInsts() 894 // If status is Unblocking, 895 // buffer any instructions coming from rename 896 // continue trying to empty skid buffer 897 // check if stall conditions have passed 898 899 if (dispatchStatus[tid] == Blocked) { 900 ++iewBlockCycles; 901 902 } else if (dispatchStatus[tid] == Squashing) { 903 ++iewSquashCycles; 904 } 905 906 // Dispatch should try to dispatch as many instructions as its bandwidth 907 // will allow, as long as it is not currently blocked. 908 if (dispatchStatus[tid] == Running || 909 dispatchStatus[tid] == Idle) { 910 DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 911 "dispatch.\n", tid); 912 913 dispatchInsts(tid); 914 } else if (dispatchStatus[tid] == Unblocking) { 915 // Make sure that the skid buffer has something in it if the 916 // status is unblocking. 917 assert(!skidsEmpty()); 918 919 // If the status was unblocking, then instructions from the skid 920 // buffer were used. Remove those instructions and handle 921 // the rest of unblocking. 922 dispatchInsts(tid); 923 924 ++iewUnblockCycles; 925 926 if (validInstsFromRename() && dispatchedAllInsts) { 927 // Add the current inputs to the skid buffer so they can be 928 // reprocessed when this stage unblocks. 929 skidInsert(tid); 930 } 931 932 unblock(tid); 933 } 934} 935 936template <class Impl> 937void 938DefaultIEW<Impl>::dispatchInsts(unsigned tid) 939{ 940 dispatchedAllInsts = true; 941 942 // Obtain instructions from skid buffer if unblocking, or queue from rename 943 // otherwise. 944 std::queue<DynInstPtr> &insts_to_dispatch = 945 dispatchStatus[tid] == Unblocking ? 946 skidBuffer[tid] : insts[tid]; 947 948 int insts_to_add = insts_to_dispatch.size(); 949 950 DynInstPtr inst; 951 bool add_to_iq = false; 952 int dis_num_inst = 0; 953 954 // Loop through the instructions, putting them in the instruction 955 // queue. 956 for ( ; dis_num_inst < insts_to_add && 957 dis_num_inst < issueReadWidth; 958 ++dis_num_inst) 959 { 960 inst = insts_to_dispatch.front(); 961 962 if (dispatchStatus[tid] == Unblocking) { 963 DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 964 "buffer\n", tid); 965 } 966 967 // Make sure there's a valid instruction there. 968 assert(inst); 969 970 DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 971 "IQ.\n", 972 tid, inst->readPC(), inst->seqNum, inst->threadNumber); 973 974 // Be sure to mark these instructions as ready so that the 975 // commit stage can go ahead and execute them, and mark 976 // them as issued so the IQ doesn't reprocess them. 977 978 // Check for squashed instructions. 979 if (inst->isSquashed()) { 980 DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 981 "not adding to IQ.\n", tid); 982 983 ++iewDispSquashedInsts; 984 985 insts_to_dispatch.pop(); 986 987 //Tell Rename That An Instruction has been processed 988 if (inst->isLoad() || inst->isStore()) { 989 toRename->iewInfo[tid].dispatchedToLSQ++; 990 } 991 toRename->iewInfo[tid].dispatched++; 992 993 continue; 994 } 995 996 // Check for full conditions. 997 if (instQueue.isFull(tid)) { 998 DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 999 1000 // Call function to start blocking. 1001 block(tid); 1002 1003 // Set unblock to false. Special case where we are using 1004 // skidbuffer (unblocking) instructions but then we still 1005 // get full in the IQ. 1006 toRename->iewUnblock[tid] = false; 1007 1008 dispatchedAllInsts = false; 1009 1010 ++iewIQFullEvents; 1011 break; 1012 } else if (ldstQueue.isFull(tid)) { 1013 DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 1014 1015 // Call function to start blocking. 1016 block(tid); 1017 1018 // Set unblock to false. Special case where we are using 1019 // skidbuffer (unblocking) instructions but then we still 1020 // get full in the IQ. 1021 toRename->iewUnblock[tid] = false; 1022 1023 dispatchedAllInsts = false; 1024 1025 ++iewLSQFullEvents; 1026 break; 1027 } 1028 1029 // Otherwise issue the instruction just fine. 1030 if (inst->isLoad()) { 1031 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1032 "encountered, adding to LSQ.\n", tid); 1033 1034 // Reserve a spot in the load store queue for this 1035 // memory access. 1036 ldstQueue.insertLoad(inst); 1037 1038 ++iewDispLoadInsts; 1039 1040 add_to_iq = true; 1041 1042 toRename->iewInfo[tid].dispatchedToLSQ++; 1043 } else if (inst->isStore()) { 1044 DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 1045 "encountered, adding to LSQ.\n", tid); 1046 1047 ldstQueue.insertStore(inst); 1048 1049 ++iewDispStoreInsts; 1050 1051 if (inst->isStoreConditional()) { 1052 // Store conditionals need to be set as "canCommit()" 1053 // so that commit can process them when they reach the 1054 // head of commit. 1055 inst->setCanCommit(); 1056 instQueue.insertNonSpec(inst); 1057 add_to_iq = false; 1058 1059 ++iewDispNonSpecInsts; 1060 } else { 1061 add_to_iq = true; 1062 } 1063 1064 toRename->iewInfo[tid].dispatchedToLSQ++; 1065#if FULL_SYSTEM 1066 } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 1067 // Same as non-speculative stores. 1068 inst->setCanCommit(); 1069 instQueue.insertBarrier(inst); 1070 add_to_iq = false; 1071#endif 1072 } else if (inst->isNonSpeculative()) { 1073 DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 1074 "encountered, skipping.\n", tid); 1075 1076 // Same as non-speculative stores. 1077 inst->setCanCommit(); 1078 1079 // Specifically insert it as nonspeculative. 1080 instQueue.insertNonSpec(inst); 1081 1082 ++iewDispNonSpecInsts; 1083 1084 add_to_iq = false; 1085 } else if (inst->isNop()) { 1086 DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 1087 "skipping.\n", tid); 1088 1089 inst->setIssued(); 1090 inst->setExecuted(); 1091 inst->setCanCommit(); 1092 1093 instQueue.recordProducer(inst); 1094 1095 exeNop[tid]++; 1096 1097 add_to_iq = false; 1098 } else if (inst->isExecuted()) { 1099 assert(0 && "Instruction shouldn't be executed.\n"); 1100 DPRINTF(IEW, "Issue: Executed branch encountered, " 1101 "skipping.\n"); 1102 1103 inst->setIssued(); 1104 inst->setCanCommit(); 1105 1106 instQueue.recordProducer(inst); 1107 1108 add_to_iq = false; 1109 } else { 1110 add_to_iq = true; 1111 } 1112 1113 // If the instruction queue is not full, then add the 1114 // instruction. 1115 if (add_to_iq) { 1116 instQueue.insert(inst); 1117 } 1118 1119 insts_to_dispatch.pop(); 1120 1121 toRename->iewInfo[tid].dispatched++; 1122 1123 ++iewDispatchedInsts; 1124 } 1125 1126 if (!insts_to_dispatch.empty()) { 1127 DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n"); 1128 block(tid); 1129 toRename->iewUnblock[tid] = false; 1130 } 1131 1132 if (dispatchStatus[tid] == Idle && dis_num_inst) { 1133 dispatchStatus[tid] = Running; 1134 1135 updatedQueues = true; 1136 } 1137 1138 dis_num_inst = 0; 1139} 1140 1141template <class Impl> 1142void 1143DefaultIEW<Impl>::printAvailableInsts() 1144{ 1145 int inst = 0; 1146 1147 cout << "Available Instructions: "; 1148 1149 while (fromIssue->insts[inst]) { 1150 1151 if (inst%3==0) cout << "\n\t"; 1152 1153 cout << "PC: " << fromIssue->insts[inst]->readPC() 1154 << " TN: " << fromIssue->insts[inst]->threadNumber 1155 << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 1156 1157 inst++; 1158 1159 } 1160 1161 cout << "\n"; 1162} 1163 1164template <class Impl> 1165void 1166DefaultIEW<Impl>::executeInsts() 1167{ 1168 wbNumInst = 0; 1169 wbCycle = 0; 1170 1171 list<unsigned>::iterator threads = (*activeThreads).begin(); 1172 1173 while (threads != (*activeThreads).end()) { 1174 unsigned tid = *threads++; 1175 fetchRedirect[tid] = false; 1176 } 1177 1178#if 0 1179 printAvailableInsts(); 1180#endif 1181 1182 // Execute/writeback any instructions that are available. 1183 int insts_to_execute = fromIssue->size; 1184 int inst_num = 0; 1185 for (; inst_num < insts_to_execute; 1186 ++inst_num) { 1187 1188 DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 1189 1190 DynInstPtr inst = instQueue.getInstToExecute(); 1191 1192 DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 1193 inst->readPC(), inst->threadNumber,inst->seqNum); 1194 1195 // Check if the instruction is squashed; if so then skip it 1196 if (inst->isSquashed()) { 1197 DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 1198 1199 // Consider this instruction executed so that commit can go 1200 // ahead and retire the instruction. 1201 inst->setExecuted(); 1202 1203 // Not sure if I should set this here or just let commit try to 1204 // commit any squashed instructions. I like the latter a bit more. 1205 inst->setCanCommit(); 1206 1207 ++iewExecSquashedInsts; 1208 1209 continue; 1210 } 1211 1212 Fault fault = NoFault; 1213 1214 // Execute instruction. 1215 // Note that if the instruction faults, it will be handled 1216 // at the commit stage. 1217 if (inst->isMemRef() && 1218 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 1219 DPRINTF(IEW, "Execute: Calculating address for memory " 1220 "reference.\n"); 1221 1222 // Tell the LDSTQ to execute this instruction (if it is a load). 1223 if (inst->isLoad()) { 1224 // Loads will mark themselves as executed, and their writeback 1225 // event adds the instruction to the queue to commit 1226 fault = ldstQueue.executeLoad(inst); 1227 } else if (inst->isStore()) { 1228 ldstQueue.executeStore(inst); 1229 1230 // If the store had a fault then it may not have a mem req 1231 if (inst->req && !(inst->req->getFlags() & LOCKED)) { 1232 inst->setExecuted(); 1233 1234 instToCommit(inst); 1235 } 1236 1237 // Store conditionals will mark themselves as 1238 // executed, and their writeback event will add the 1239 // instruction to the queue to commit. 1240 } else { 1241 panic("Unexpected memory type!\n"); 1242 } 1243 1244 } else { 1245 inst->execute(); 1246 1247 inst->setExecuted(); 1248 1249 instToCommit(inst); 1250 } 1251 1252 updateExeInstStats(inst); 1253 1254 // Check if branch prediction was correct, if not then we need 1255 // to tell commit to squash in flight instructions. Only 1256 // handle this if there hasn't already been something that 1257 // redirects fetch in this group of instructions. 1258 1259 // This probably needs to prioritize the redirects if a different 1260 // scheduler is used. Currently the scheduler schedules the oldest 1261 // instruction first, so the branch resolution order will be correct. 1262 unsigned tid = inst->threadNumber; 1263 1264 if (!fetchRedirect[tid]) { 1265 1266 if (inst->mispredicted()) { 1267 fetchRedirect[tid] = true; 1268 1269 DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 1270 DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x.\n", 1271 inst->nextPC); 1272 1273 // If incorrect, then signal the ROB that it must be squashed. 1274 squashDueToBranch(inst, tid); 1275 1276 if (inst->predTaken()) { 1277 predictedTakenIncorrect++; 1278 } else { 1279 predictedNotTakenIncorrect++; 1280 } 1281 } else if (ldstQueue.violation(tid)) { 1282 fetchRedirect[tid] = true; 1283 1284 // If there was an ordering violation, then get the 1285 // DynInst that caused the violation. Note that this 1286 // clears the violation signal. 1287 DynInstPtr violator; 1288 violator = ldstQueue.getMemDepViolator(tid); 1289 1290 DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 1291 "%#x, inst PC: %#x. Addr is: %#x.\n", 1292 violator->readPC(), inst->readPC(), inst->physEffAddr); 1293 1294 // Tell the instruction queue that a violation has occured. 1295 instQueue.violation(inst, violator); 1296 1297 // Squash. 1298 squashDueToMemOrder(inst,tid); 1299 1300 ++memOrderViolationEvents; 1301 } else if (ldstQueue.loadBlocked(tid) && 1302 !ldstQueue.isLoadBlockedHandled(tid)) { 1303 fetchRedirect[tid] = true; 1304 1305 DPRINTF(IEW, "Load operation couldn't execute because the " 1306 "memory system is blocked. PC: %#x [sn:%lli]\n", 1307 inst->readPC(), inst->seqNum); 1308 1309 squashDueToMemBlocked(inst, tid); 1310 } 1311 } 1312 } 1313 1314 if (inst_num) { 1315 if (exeStatus == Idle) { 1316 exeStatus = Running; 1317 } 1318 1319 updatedQueues = true; 1320 1321 cpu->activityThisCycle(); 1322 } 1323 1324 // Need to reset this in case a writeback event needs to write into the 1325 // iew queue. That way the writeback event will write into the correct 1326 // spot in the queue. 1327 wbNumInst = 0; 1328} 1329 1330template <class Impl> 1331void 1332DefaultIEW<Impl>::writebackInsts() 1333{ 1334 // Loop through the head of the time buffer and wake any 1335 // dependents. These instructions are about to write back. Also 1336 // mark scoreboard that this instruction is finally complete. 1337 // Either have IEW have direct access to scoreboard, or have this 1338 // as part of backwards communication. 1339 for (int inst_num = 0; inst_num < issueWidth && 1340 toCommit->insts[inst_num]; inst_num++) { 1341 DynInstPtr inst = toCommit->insts[inst_num]; 1342 int tid = inst->threadNumber; 1343 1344 DPRINTF(IEW, "Sending instructions to commit, PC %#x.\n", 1345 inst->readPC()); 1346 1347 iewInstsToCommit[tid]++; 1348 1349 // Some instructions will be sent to commit without having 1350 // executed because they need commit to handle them. 1351 // E.g. Uncached loads have not actually executed when they 1352 // are first sent to commit. Instead commit must tell the LSQ 1353 // when it's ready to execute the uncached load. 1354 if (!inst->isSquashed() && inst->isExecuted()) { 1355 int dependents = instQueue.wakeDependents(inst); 1356 1357 for (int i = 0; i < inst->numDestRegs(); i++) { 1358 //mark as Ready 1359 DPRINTF(IEW,"Setting Destination Register %i\n", 1360 inst->renamedDestRegIdx(i)); 1361 scoreboard->setReg(inst->renamedDestRegIdx(i)); 1362 } 1363 1364 producerInst[tid]++; 1365 consumerInst[tid]+= dependents; 1366 writebackCount[tid]++; 1367 } 1368 } 1369} 1370 1371template<class Impl> 1372void 1373DefaultIEW<Impl>::tick() 1374{ 1375 wbNumInst = 0; 1376 wbCycle = 0; 1377 1378 wroteToTimeBuffer = false; 1379 updatedQueues = false; 1380 1381 sortInsts(); 1382 1383 // Free function units marked as being freed this cycle. 1384 fuPool->processFreeUnits(); 1385 1386 list<unsigned>::iterator threads = (*activeThreads).begin(); 1387 1388 // Check stall and squash signals, dispatch any instructions. 1389 while (threads != (*activeThreads).end()) { 1390 unsigned tid = *threads++; 1391 1392 DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 1393 1394 checkSignalsAndUpdate(tid); 1395 dispatch(tid); 1396 } 1397 1398 if (exeStatus != Squashing) { 1399 executeInsts(); 1400 1401 writebackInsts(); 1402 1403 // Have the instruction queue try to schedule any ready instructions. 1404 // (In actuality, this scheduling is for instructions that will 1405 // be executed next cycle.) 1406 instQueue.scheduleReadyInsts(); 1407 1408 // Also should advance its own time buffers if the stage ran. 1409 // Not the best place for it, but this works (hopefully). 1410 issueToExecQueue.advance(); 1411 } 1412 1413 bool broadcast_free_entries = false; 1414 1415 if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 1416 exeStatus = Idle; 1417 updateLSQNextCycle = false; 1418 1419 broadcast_free_entries = true; 1420 } 1421 1422 // Writeback any stores using any leftover bandwidth. 1423 ldstQueue.writebackStores(); 1424 1425 // Check the committed load/store signals to see if there's a load 1426 // or store to commit. Also check if it's being told to execute a 1427 // nonspeculative instruction. 1428 // This is pretty inefficient... 1429 1430 threads = (*activeThreads).begin(); 1431 while (threads != (*activeThreads).end()) { 1432 unsigned tid = (*threads++); 1433 1434 DPRINTF(IEW,"Processing [tid:%i]\n",tid); 1435 1436 if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 1437 !fromCommit->commitInfo[tid].squash && 1438 !fromCommit->commitInfo[tid].robSquashing) { 1439 1440 ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 1441 1442 ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 1443 1444 updateLSQNextCycle = true; 1445 instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 1446 } 1447 1448 if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 1449 1450 //DPRINTF(IEW,"NonspecInst from thread %i",tid); 1451 if (fromCommit->commitInfo[tid].uncached) { 1452 instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 1453 } else { 1454 instQueue.scheduleNonSpec( 1455 fromCommit->commitInfo[tid].nonSpecSeqNum); 1456 } 1457 } 1458 1459 if (broadcast_free_entries) { 1460 toFetch->iewInfo[tid].iqCount = 1461 instQueue.getCount(tid); 1462 toFetch->iewInfo[tid].ldstqCount = 1463 ldstQueue.getCount(tid); 1464 1465 toRename->iewInfo[tid].usedIQ = true; 1466 toRename->iewInfo[tid].freeIQEntries = 1467 instQueue.numFreeEntries(); 1468 toRename->iewInfo[tid].usedLSQ = true; 1469 toRename->iewInfo[tid].freeLSQEntries = 1470 ldstQueue.numFreeEntries(tid); 1471 1472 wroteToTimeBuffer = true; 1473 } 1474 1475 DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 1476 tid, toRename->iewInfo[tid].dispatched); 1477 } 1478 1479 DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 1480 "LSQ has %i free entries.\n", 1481 instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 1482 ldstQueue.numFreeEntries()); 1483 1484 updateStatus(); 1485 1486 if (wroteToTimeBuffer) { 1487 DPRINTF(Activity, "Activity this cycle.\n"); 1488 cpu->activityThisCycle(); 1489 } 1490} 1491 1492template <class Impl> 1493void 1494DefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 1495{ 1496 int thread_number = inst->threadNumber; 1497 1498 // 1499 // Pick off the software prefetches 1500 // 1501#ifdef TARGET_ALPHA 1502 if (inst->isDataPrefetch()) 1503 exeSwp[thread_number]++; 1504 else 1505 iewExecutedInsts++; 1506#else 1507 iewExecutedInsts++; 1508#endif 1509 1510 // 1511 // Control operations 1512 // 1513 if (inst->isControl()) 1514 exeBranches[thread_number]++; 1515 1516 // 1517 // Memory operations 1518 // 1519 if (inst->isMemRef()) { 1520 exeRefs[thread_number]++; 1521 1522 if (inst->isLoad()) { 1523 iewExecLoadInsts[thread_number]++; 1524 } 1525 } 1526} 1527