iew_impl.hh revision 9937
11689SN/A/* 29783Sandreas.hansson@arm.com * Copyright (c) 2010-2013 ARM Limited 37598Sminkyu.jeong@arm.com * All rights reserved. 47598Sminkyu.jeong@arm.com * 57598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97598Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137598Sminkyu.jeong@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 431060SN/A// @todo: Fix the instantaneous communication among all the stages within 441060SN/A// iew. There's a clear delay between issue and execute, yet backwards 451689SN/A// communication happens simultaneously. 461060SN/A 471060SN/A#include <queue> 481060SN/A 498230Snate@binkert.org#include "arch/utility.hh" 506658Snate@binkert.org#include "config/the_isa.hh" 518887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 522292SN/A#include "cpu/o3/fu_pool.hh" 531717SN/A#include "cpu/o3/iew.hh" 548229Snate@binkert.org#include "cpu/timebuf.hh" 558232Snate@binkert.org#include "debug/Activity.hh" 569444SAndreas.Sandberg@ARM.com#include "debug/Drain.hh" 578232Snate@binkert.org#include "debug/IEW.hh" 589527SMatt.Horsnell@arm.com#include "debug/O3PipeView.hh" 595529Snate@binkert.org#include "params/DerivO3CPU.hh" 601060SN/A 616221Snate@binkert.orgusing namespace std; 626221Snate@binkert.org 631681SN/Atemplate<class Impl> 645529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params) 652873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 664329Sktlim@umich.edu cpu(_cpu), 674329Sktlim@umich.edu instQueue(_cpu, this, params), 684329Sktlim@umich.edu ldstQueue(_cpu, this, params), 692292SN/A fuPool(params->fuPool), 702292SN/A commitToIEWDelay(params->commitToIEWDelay), 712292SN/A renameToIEWDelay(params->renameToIEWDelay), 722292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 732820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 742292SN/A issueWidth(params->issueWidth), 752820Sktlim@umich.edu wbOutstanding(0), 762820Sktlim@umich.edu wbWidth(params->wbWidth), 779444SAndreas.Sandberg@ARM.com numThreads(params->numThreads) 781060SN/A{ 792292SN/A _status = Active; 802292SN/A exeStatus = Running; 812292SN/A wbStatus = Idle; 821060SN/A 831060SN/A // Setup wire to read instructions coming from issue. 841060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 851060SN/A 861060SN/A // Instruction queue needs the queue between issue and execute. 871060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 881681SN/A 896221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 906221Snate@binkert.org dispatchStatus[tid] = Running; 916221Snate@binkert.org stalls[tid].commit = false; 926221Snate@binkert.org fetchRedirect[tid] = false; 932292SN/A } 942292SN/A 952820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 962820Sktlim@umich.edu 972292SN/A updateLSQNextCycle = false; 982292SN/A 992820Sktlim@umich.edu ableToIssue = true; 1002820Sktlim@umich.edu 1012292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 1022292SN/A} 1032292SN/A 1042292SN/Atemplate <class Impl> 1052292SN/Astd::string 1062292SN/ADefaultIEW<Impl>::name() const 1072292SN/A{ 1082292SN/A return cpu->name() + ".iew"; 1091060SN/A} 1101060SN/A 1111681SN/Atemplate <class Impl> 1121062SN/Avoid 1132292SN/ADefaultIEW<Impl>::regStats() 1141062SN/A{ 1152301SN/A using namespace Stats; 1162301SN/A 1171062SN/A instQueue.regStats(); 1182727Sktlim@umich.edu ldstQueue.regStats(); 1191062SN/A 1201062SN/A iewIdleCycles 1211062SN/A .name(name() + ".iewIdleCycles") 1221062SN/A .desc("Number of cycles IEW is idle"); 1231062SN/A 1241062SN/A iewSquashCycles 1251062SN/A .name(name() + ".iewSquashCycles") 1261062SN/A .desc("Number of cycles IEW is squashing"); 1271062SN/A 1281062SN/A iewBlockCycles 1291062SN/A .name(name() + ".iewBlockCycles") 1301062SN/A .desc("Number of cycles IEW is blocking"); 1311062SN/A 1321062SN/A iewUnblockCycles 1331062SN/A .name(name() + ".iewUnblockCycles") 1341062SN/A .desc("Number of cycles IEW is unblocking"); 1351062SN/A 1361062SN/A iewDispatchedInsts 1371062SN/A .name(name() + ".iewDispatchedInsts") 1381062SN/A .desc("Number of instructions dispatched to IQ"); 1391062SN/A 1401062SN/A iewDispSquashedInsts 1411062SN/A .name(name() + ".iewDispSquashedInsts") 1421062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1431062SN/A 1441062SN/A iewDispLoadInsts 1451062SN/A .name(name() + ".iewDispLoadInsts") 1461062SN/A .desc("Number of dispatched load instructions"); 1471062SN/A 1481062SN/A iewDispStoreInsts 1491062SN/A .name(name() + ".iewDispStoreInsts") 1501062SN/A .desc("Number of dispatched store instructions"); 1511062SN/A 1521062SN/A iewDispNonSpecInsts 1531062SN/A .name(name() + ".iewDispNonSpecInsts") 1541062SN/A .desc("Number of dispatched non-speculative instructions"); 1551062SN/A 1561062SN/A iewIQFullEvents 1571062SN/A .name(name() + ".iewIQFullEvents") 1581062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1591062SN/A 1602292SN/A iewLSQFullEvents 1612292SN/A .name(name() + ".iewLSQFullEvents") 1622292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1632292SN/A 1641062SN/A memOrderViolationEvents 1651062SN/A .name(name() + ".memOrderViolationEvents") 1661062SN/A .desc("Number of memory order violations"); 1671062SN/A 1681062SN/A predictedTakenIncorrect 1691062SN/A .name(name() + ".predictedTakenIncorrect") 1701062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1712292SN/A 1722292SN/A predictedNotTakenIncorrect 1732292SN/A .name(name() + ".predictedNotTakenIncorrect") 1742292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1752292SN/A 1762292SN/A branchMispredicts 1772292SN/A .name(name() + ".branchMispredicts") 1782292SN/A .desc("Number of branch mispredicts detected at execute"); 1792292SN/A 1802292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1812301SN/A 1822727Sktlim@umich.edu iewExecutedInsts 1832353SN/A .name(name() + ".iewExecutedInsts") 1842727Sktlim@umich.edu .desc("Number of executed instructions"); 1852727Sktlim@umich.edu 1862727Sktlim@umich.edu iewExecLoadInsts 1876221Snate@binkert.org .init(cpu->numThreads) 1882353SN/A .name(name() + ".iewExecLoadInsts") 1892727Sktlim@umich.edu .desc("Number of load instructions executed") 1902727Sktlim@umich.edu .flags(total); 1912727Sktlim@umich.edu 1922727Sktlim@umich.edu iewExecSquashedInsts 1932353SN/A .name(name() + ".iewExecSquashedInsts") 1942727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1952727Sktlim@umich.edu 1962727Sktlim@umich.edu iewExecutedSwp 1976221Snate@binkert.org .init(cpu->numThreads) 1988240Snate@binkert.org .name(name() + ".exec_swp") 1992301SN/A .desc("number of swp insts executed") 2002727Sktlim@umich.edu .flags(total); 2012301SN/A 2022727Sktlim@umich.edu iewExecutedNop 2036221Snate@binkert.org .init(cpu->numThreads) 2048240Snate@binkert.org .name(name() + ".exec_nop") 2052301SN/A .desc("number of nop insts executed") 2062727Sktlim@umich.edu .flags(total); 2072301SN/A 2082727Sktlim@umich.edu iewExecutedRefs 2096221Snate@binkert.org .init(cpu->numThreads) 2108240Snate@binkert.org .name(name() + ".exec_refs") 2112301SN/A .desc("number of memory reference insts executed") 2122727Sktlim@umich.edu .flags(total); 2132301SN/A 2142727Sktlim@umich.edu iewExecutedBranches 2156221Snate@binkert.org .init(cpu->numThreads) 2168240Snate@binkert.org .name(name() + ".exec_branches") 2172301SN/A .desc("Number of branches executed") 2182727Sktlim@umich.edu .flags(total); 2192301SN/A 2202301SN/A iewExecStoreInsts 2218240Snate@binkert.org .name(name() + ".exec_stores") 2222301SN/A .desc("Number of stores executed") 2232727Sktlim@umich.edu .flags(total); 2242727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2252727Sktlim@umich.edu 2262727Sktlim@umich.edu iewExecRate 2278240Snate@binkert.org .name(name() + ".exec_rate") 2282727Sktlim@umich.edu .desc("Inst execution rate") 2292727Sktlim@umich.edu .flags(total); 2302727Sktlim@umich.edu 2312727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2322301SN/A 2332301SN/A iewInstsToCommit 2346221Snate@binkert.org .init(cpu->numThreads) 2358240Snate@binkert.org .name(name() + ".wb_sent") 2362301SN/A .desc("cumulative count of insts sent to commit") 2372727Sktlim@umich.edu .flags(total); 2382301SN/A 2392326SN/A writebackCount 2406221Snate@binkert.org .init(cpu->numThreads) 2418240Snate@binkert.org .name(name() + ".wb_count") 2422301SN/A .desc("cumulative count of insts written-back") 2432727Sktlim@umich.edu .flags(total); 2442301SN/A 2452326SN/A producerInst 2466221Snate@binkert.org .init(cpu->numThreads) 2478240Snate@binkert.org .name(name() + ".wb_producers") 2482301SN/A .desc("num instructions producing a value") 2492727Sktlim@umich.edu .flags(total); 2502301SN/A 2512326SN/A consumerInst 2526221Snate@binkert.org .init(cpu->numThreads) 2538240Snate@binkert.org .name(name() + ".wb_consumers") 2542301SN/A .desc("num instructions consuming a value") 2552727Sktlim@umich.edu .flags(total); 2562301SN/A 2572326SN/A wbPenalized 2586221Snate@binkert.org .init(cpu->numThreads) 2598240Snate@binkert.org .name(name() + ".wb_penalized") 2602301SN/A .desc("number of instrctions required to write to 'other' IQ") 2612727Sktlim@umich.edu .flags(total); 2622301SN/A 2632326SN/A wbPenalizedRate 2648240Snate@binkert.org .name(name() + ".wb_penalized_rate") 2652301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2662727Sktlim@umich.edu .flags(total); 2672301SN/A 2682326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2692301SN/A 2702326SN/A wbFanout 2718240Snate@binkert.org .name(name() + ".wb_fanout") 2722301SN/A .desc("average fanout of values written-back") 2732727Sktlim@umich.edu .flags(total); 2742301SN/A 2752326SN/A wbFanout = producerInst / consumerInst; 2762301SN/A 2772326SN/A wbRate 2788240Snate@binkert.org .name(name() + ".wb_rate") 2792301SN/A .desc("insts written-back per cycle") 2802727Sktlim@umich.edu .flags(total); 2812326SN/A wbRate = writebackCount / cpu->numCycles; 2821062SN/A} 2831062SN/A 2841681SN/Atemplate<class Impl> 2851060SN/Avoid 2869427SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::startupStage() 2871060SN/A{ 2886221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 2892292SN/A toRename->iewInfo[tid].usedIQ = true; 2902292SN/A toRename->iewInfo[tid].freeIQEntries = 2912292SN/A instQueue.numFreeEntries(tid); 2922292SN/A 2932292SN/A toRename->iewInfo[tid].usedLSQ = true; 2942292SN/A toRename->iewInfo[tid].freeLSQEntries = 2952292SN/A ldstQueue.numFreeEntries(tid); 2962292SN/A } 2972292SN/A 2988887Sgeoffrey.blake@arm.com // Initialize the checker's dcache port here 2998733Sgeoffrey.blake@arm.com if (cpu->checker) { 3008850Sandreas.hansson@arm.com cpu->checker->setDcachePort(&cpu->getDataPort()); 3018887Sgeoffrey.blake@arm.com } 3028733Sgeoffrey.blake@arm.com 3032733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 3041060SN/A} 3051060SN/A 3061681SN/Atemplate<class Impl> 3071060SN/Avoid 3082292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 3091060SN/A{ 3101060SN/A timeBuffer = tb_ptr; 3111060SN/A 3121060SN/A // Setup wire to read information from time buffer, from commit. 3131060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 3141060SN/A 3151060SN/A // Setup wire to write information back to previous stages. 3161060SN/A toRename = timeBuffer->getWire(0); 3171060SN/A 3182292SN/A toFetch = timeBuffer->getWire(0); 3192292SN/A 3201060SN/A // Instruction queue also needs main time buffer. 3211060SN/A instQueue.setTimeBuffer(tb_ptr); 3221060SN/A} 3231060SN/A 3241681SN/Atemplate<class Impl> 3251060SN/Avoid 3262292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3271060SN/A{ 3281060SN/A renameQueue = rq_ptr; 3291060SN/A 3301060SN/A // Setup wire to read information from rename queue. 3311060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3321060SN/A} 3331060SN/A 3341681SN/Atemplate<class Impl> 3351060SN/Avoid 3362292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3371060SN/A{ 3381060SN/A iewQueue = iq_ptr; 3391060SN/A 3401060SN/A // Setup wire to write instructions to commit. 3411060SN/A toCommit = iewQueue->getWire(0); 3421060SN/A} 3431060SN/A 3441681SN/Atemplate<class Impl> 3451060SN/Avoid 3466221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr) 3471060SN/A{ 3482292SN/A activeThreads = at_ptr; 3492292SN/A 3502292SN/A ldstQueue.setActiveThreads(at_ptr); 3512292SN/A instQueue.setActiveThreads(at_ptr); 3521060SN/A} 3531060SN/A 3541681SN/Atemplate<class Impl> 3551060SN/Avoid 3562292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3571060SN/A{ 3582292SN/A scoreboard = sb_ptr; 3591060SN/A} 3601060SN/A 3612307SN/Atemplate <class Impl> 3622863Sktlim@umich.edubool 3639444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::isDrained() const 3642307SN/A{ 3659444SAndreas.Sandberg@ARM.com bool drained(ldstQueue.isDrained()); 3669444SAndreas.Sandberg@ARM.com 3679444SAndreas.Sandberg@ARM.com for (ThreadID tid = 0; tid < numThreads; tid++) { 3689444SAndreas.Sandberg@ARM.com if (!insts[tid].empty()) { 3699444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Insts not empty.\n", tid); 3709444SAndreas.Sandberg@ARM.com drained = false; 3719444SAndreas.Sandberg@ARM.com } 3729444SAndreas.Sandberg@ARM.com if (!skidBuffer[tid].empty()) { 3739444SAndreas.Sandberg@ARM.com DPRINTF(Drain, "%i: Skid buffer not empty.\n", tid); 3749444SAndreas.Sandberg@ARM.com drained = false; 3759444SAndreas.Sandberg@ARM.com } 3769444SAndreas.Sandberg@ARM.com } 3779444SAndreas.Sandberg@ARM.com 3789783Sandreas.hansson@arm.com // Also check the FU pool as instructions are "stored" in FU 3799783Sandreas.hansson@arm.com // completion events until they are done and not accounted for 3809783Sandreas.hansson@arm.com // above 3819783Sandreas.hansson@arm.com if (drained && !fuPool->isDrained()) { 3829783Sandreas.hansson@arm.com DPRINTF(Drain, "FU pool still busy.\n"); 3839783Sandreas.hansson@arm.com drained = false; 3849783Sandreas.hansson@arm.com } 3859783Sandreas.hansson@arm.com 3869444SAndreas.Sandberg@ARM.com return drained; 3871681SN/A} 3881681SN/A 3892316SN/Atemplate <class Impl> 3901681SN/Avoid 3919444SAndreas.Sandberg@ARM.comDefaultIEW<Impl>::drainSanityCheck() const 3922843Sktlim@umich.edu{ 3939444SAndreas.Sandberg@ARM.com assert(isDrained()); 3942843Sktlim@umich.edu 3959444SAndreas.Sandberg@ARM.com instQueue.drainSanityCheck(); 3969444SAndreas.Sandberg@ARM.com ldstQueue.drainSanityCheck(); 3971681SN/A} 3981681SN/A 3992307SN/Atemplate <class Impl> 4001681SN/Avoid 4012307SN/ADefaultIEW<Impl>::takeOverFrom() 4021060SN/A{ 4032348SN/A // Reset all state. 4042307SN/A _status = Active; 4052307SN/A exeStatus = Running; 4062307SN/A wbStatus = Idle; 4071060SN/A 4082307SN/A instQueue.takeOverFrom(); 4092307SN/A ldstQueue.takeOverFrom(); 4109444SAndreas.Sandberg@ARM.com fuPool->takeOverFrom(); 4111060SN/A 4129427SAndreas.Sandberg@ARM.com startupStage(); 4132307SN/A cpu->activityThisCycle(); 4141060SN/A 4156221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) { 4166221Snate@binkert.org dispatchStatus[tid] = Running; 4176221Snate@binkert.org stalls[tid].commit = false; 4186221Snate@binkert.org fetchRedirect[tid] = false; 4192307SN/A } 4201060SN/A 4212307SN/A updateLSQNextCycle = false; 4222307SN/A 4232873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 4242307SN/A issueToExecQueue.advance(); 4251060SN/A } 4261060SN/A} 4271060SN/A 4281681SN/Atemplate<class Impl> 4291060SN/Avoid 4306221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid) 4312107SN/A{ 4326221Snate@binkert.org DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid); 4332107SN/A 4342292SN/A // Tell the IQ to start squashing. 4352292SN/A instQueue.squash(tid); 4362107SN/A 4372292SN/A // Tell the LDSTQ to start squashing. 4382326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4392292SN/A updatedQueues = true; 4402107SN/A 4412292SN/A // Clear the skid buffer in case it has any data in it. 4422935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4434632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4442935Sksewell@umich.edu 4452292SN/A while (!skidBuffer[tid].empty()) { 4462292SN/A if (skidBuffer[tid].front()->isLoad() || 4472292SN/A skidBuffer[tid].front()->isStore() ) { 4482292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4492292SN/A } 4502107SN/A 4512292SN/A toRename->iewInfo[tid].dispatched++; 4522107SN/A 4532292SN/A skidBuffer[tid].pop(); 4542292SN/A } 4552107SN/A 4562702Sktlim@umich.edu emptyRenameInsts(tid); 4572107SN/A} 4582107SN/A 4592107SN/Atemplate<class Impl> 4602107SN/Avoid 4616221Snate@binkert.orgDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid) 4622292SN/A{ 4637720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s " 4647720Sgblack@eecs.umich.edu "[sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4652292SN/A 4667852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 4677852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 4687852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 4697852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 4707852SMatt.Horsnell@arm.com toCommit->branchTaken[tid] = inst->pcState().branching(); 4712935Sksewell@umich.edu 4727852SMatt.Horsnell@arm.com TheISA::PCState pc = inst->pcState(); 4737852SMatt.Horsnell@arm.com TheISA::advancePC(pc, inst->staticInst); 4742292SN/A 4757852SMatt.Horsnell@arm.com toCommit->pc[tid] = pc; 4767852SMatt.Horsnell@arm.com toCommit->mispredictInst[tid] = inst; 4777852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = false; 4782292SN/A 4797852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 4807852SMatt.Horsnell@arm.com } 4817852SMatt.Horsnell@arm.com 4822292SN/A} 4832292SN/A 4842292SN/Atemplate<class Impl> 4852292SN/Avoid 4866221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid) 4872292SN/A{ 4888513SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger " 4898513SGiacomo.Gabrielli@arm.com "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 4908513SGiacomo.Gabrielli@arm.com // Need to include inst->seqNum in the following comparison to cover the 4918513SGiacomo.Gabrielli@arm.com // corner case when a branch misprediction and a memory violation for the 4928513SGiacomo.Gabrielli@arm.com // same instruction (e.g. load PC) are detected in the same cycle. In this 4938513SGiacomo.Gabrielli@arm.com // case the memory violator should take precedence over the branch 4948513SGiacomo.Gabrielli@arm.com // misprediction because it requires the violator itself to be included in 4958513SGiacomo.Gabrielli@arm.com // the squash. 4968513SGiacomo.Gabrielli@arm.com if (toCommit->squash[tid] == false || 4978513SGiacomo.Gabrielli@arm.com inst->seqNum <= toCommit->squashedSeqNum[tid]) { 4988513SGiacomo.Gabrielli@arm.com toCommit->squash[tid] = true; 4992292SN/A 5007852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5018513SGiacomo.Gabrielli@arm.com toCommit->pc[tid] = inst->pcState(); 5028137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5032292SN/A 5048513SGiacomo.Gabrielli@arm.com // Must include the memory violator in the squash. 5058513SGiacomo.Gabrielli@arm.com toCommit->includeSquashInst[tid] = true; 5062292SN/A 5077852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5087852SMatt.Horsnell@arm.com } 5092292SN/A} 5102292SN/A 5112292SN/Atemplate<class Impl> 5122292SN/Avoid 5136221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid) 5142292SN/A{ 5152292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 5167720Sgblack@eecs.umich.edu "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum); 5177852SMatt.Horsnell@arm.com if (toCommit->squash[tid] == false || 5187852SMatt.Horsnell@arm.com inst->seqNum < toCommit->squashedSeqNum[tid]) { 5197852SMatt.Horsnell@arm.com toCommit->squash[tid] = true; 5202292SN/A 5217852SMatt.Horsnell@arm.com toCommit->squashedSeqNum[tid] = inst->seqNum; 5227852SMatt.Horsnell@arm.com toCommit->pc[tid] = inst->pcState(); 5238137SAli.Saidi@ARM.com toCommit->mispredictInst[tid] = NULL; 5242292SN/A 5257852SMatt.Horsnell@arm.com // Must include the broadcasted SN in the squash. 5267852SMatt.Horsnell@arm.com toCommit->includeSquashInst[tid] = true; 5272292SN/A 5287852SMatt.Horsnell@arm.com ldstQueue.setLoadBlockedHandled(tid); 5292292SN/A 5307852SMatt.Horsnell@arm.com wroteToTimeBuffer = true; 5317852SMatt.Horsnell@arm.com } 5322292SN/A} 5332292SN/A 5342292SN/Atemplate<class Impl> 5352292SN/Avoid 5366221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid) 5372292SN/A{ 5382292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5392292SN/A 5402292SN/A if (dispatchStatus[tid] != Blocked && 5412292SN/A dispatchStatus[tid] != Unblocking) { 5422292SN/A toRename->iewBlock[tid] = true; 5432292SN/A wroteToTimeBuffer = true; 5442292SN/A } 5452292SN/A 5462292SN/A // Add the current inputs to the skid buffer so they can be 5472292SN/A // reprocessed when this stage unblocks. 5482292SN/A skidInsert(tid); 5492292SN/A 5502292SN/A dispatchStatus[tid] = Blocked; 5512292SN/A} 5522292SN/A 5532292SN/Atemplate<class Impl> 5542292SN/Avoid 5556221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid) 5562292SN/A{ 5572292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5582292SN/A "buffer %u.\n",tid, tid); 5592292SN/A 5602292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5612292SN/A // Also switch status to running. 5622292SN/A if (skidBuffer[tid].empty()) { 5632292SN/A toRename->iewUnblock[tid] = true; 5642292SN/A wroteToTimeBuffer = true; 5652292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5662292SN/A dispatchStatus[tid] = Running; 5672292SN/A } 5682292SN/A} 5692292SN/A 5702292SN/Atemplate<class Impl> 5712292SN/Avoid 5722292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5731060SN/A{ 5741681SN/A instQueue.wakeDependents(inst); 5751060SN/A} 5761060SN/A 5772292SN/Atemplate<class Impl> 5782292SN/Avoid 5792292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5802292SN/A{ 5812292SN/A instQueue.rescheduleMemInst(inst); 5822292SN/A} 5831681SN/A 5841681SN/Atemplate<class Impl> 5851060SN/Avoid 5862292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5871060SN/A{ 5882292SN/A instQueue.replayMemInst(inst); 5892292SN/A} 5901060SN/A 5912292SN/Atemplate<class Impl> 5922292SN/Avoid 5932292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5942292SN/A{ 5953221Sktlim@umich.edu // This function should not be called after writebackInsts in a 5963221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 5973221Sktlim@umich.edu // being added to the queue to commit without being processed by 5983221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 5993221Sktlim@umich.edu 6002292SN/A // First check the time slot that this instruction will write 6012292SN/A // to. If there are free write ports at the time, then go ahead 6022292SN/A // and write the instruction to that time. If there are not, 6032292SN/A // keep looking back to see where's the first time there's a 6042326SN/A // free slot. 6052292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 6062292SN/A ++wbNumInst; 6072820Sktlim@umich.edu if (wbNumInst == wbWidth) { 6082292SN/A ++wbCycle; 6092292SN/A wbNumInst = 0; 6102292SN/A } 6112292SN/A 6122353SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 6132292SN/A } 6142292SN/A 6152353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 6162353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 6172292SN/A // Add finished instruction to queue to commit. 6182292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 6192292SN/A (*iewQueue)[wbCycle].size++; 6202292SN/A} 6212292SN/A 6222292SN/Atemplate <class Impl> 6232292SN/Aunsigned 6242292SN/ADefaultIEW<Impl>::validInstsFromRename() 6252292SN/A{ 6262292SN/A unsigned inst_count = 0; 6272292SN/A 6282292SN/A for (int i=0; i<fromRename->size; i++) { 6292731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 6302292SN/A inst_count++; 6312292SN/A } 6322292SN/A 6332292SN/A return inst_count; 6342292SN/A} 6352292SN/A 6362292SN/Atemplate<class Impl> 6372292SN/Avoid 6386221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid) 6392292SN/A{ 6402292SN/A DynInstPtr inst = NULL; 6412292SN/A 6422292SN/A while (!insts[tid].empty()) { 6432292SN/A inst = insts[tid].front(); 6442292SN/A 6452292SN/A insts[tid].pop(); 6462292SN/A 6479937SFaissal.Sleiman@arm.com DPRINTF(IEW,"[tid:%i]: Inserting [sn:%lli] PC:%s into " 6482292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6497720Sgblack@eecs.umich.edu inst->pcState(),tid); 6502292SN/A 6512292SN/A skidBuffer[tid].push(inst); 6522292SN/A } 6532292SN/A 6542292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6552292SN/A "Skidbuffer Exceeded Max Size"); 6562292SN/A} 6572292SN/A 6582292SN/Atemplate<class Impl> 6592292SN/Aint 6602292SN/ADefaultIEW<Impl>::skidCount() 6612292SN/A{ 6622292SN/A int max=0; 6632292SN/A 6646221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6656221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6662292SN/A 6673867Sbinkertn@umich.edu while (threads != end) { 6686221Snate@binkert.org ThreadID tid = *threads++; 6693867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6702292SN/A if (max < thread_count) 6712292SN/A max = thread_count; 6722292SN/A } 6732292SN/A 6742292SN/A return max; 6752292SN/A} 6762292SN/A 6772292SN/Atemplate<class Impl> 6782292SN/Abool 6792292SN/ADefaultIEW<Impl>::skidsEmpty() 6802292SN/A{ 6816221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 6826221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 6832292SN/A 6843867Sbinkertn@umich.edu while (threads != end) { 6856221Snate@binkert.org ThreadID tid = *threads++; 6863867Sbinkertn@umich.edu 6873867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 6882292SN/A return false; 6892292SN/A } 6902292SN/A 6912292SN/A return true; 6921062SN/A} 6931062SN/A 6941681SN/Atemplate <class Impl> 6951062SN/Avoid 6962292SN/ADefaultIEW<Impl>::updateStatus() 6971062SN/A{ 6982292SN/A bool any_unblocking = false; 6991062SN/A 7006221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 7016221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 7021062SN/A 7033867Sbinkertn@umich.edu while (threads != end) { 7046221Snate@binkert.org ThreadID tid = *threads++; 7051062SN/A 7062292SN/A if (dispatchStatus[tid] == Unblocking) { 7072292SN/A any_unblocking = true; 7082292SN/A break; 7092292SN/A } 7102292SN/A } 7111062SN/A 7122292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 7132292SN/A // and there's no stores waiting to write back, and dispatch is not 7142292SN/A // unblocking, then there is no internal activity for the IEW stage. 7157897Shestness@cs.utexas.edu instQueue.intInstQueueReads++; 7162292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 7172292SN/A !ldstQueue.willWB() && !any_unblocking) { 7182292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 7191062SN/A 7202292SN/A deactivateStage(); 7211062SN/A 7222292SN/A _status = Inactive; 7232292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 7242292SN/A ldstQueue.willWB() || 7252292SN/A any_unblocking)) { 7262292SN/A // Otherwise there is internal activity. Set to active. 7272292SN/A DPRINTF(IEW, "IEW switching to active\n"); 7281062SN/A 7292292SN/A activateStage(); 7301062SN/A 7312292SN/A _status = Active; 7321062SN/A } 7331062SN/A} 7341062SN/A 7351681SN/Atemplate <class Impl> 7361062SN/Avoid 7372292SN/ADefaultIEW<Impl>::resetEntries() 7381062SN/A{ 7392292SN/A instQueue.resetEntries(); 7402292SN/A ldstQueue.resetEntries(); 7412292SN/A} 7421062SN/A 7432292SN/Atemplate <class Impl> 7442292SN/Avoid 7456221Snate@binkert.orgDefaultIEW<Impl>::readStallSignals(ThreadID tid) 7462292SN/A{ 7472292SN/A if (fromCommit->commitBlock[tid]) { 7482292SN/A stalls[tid].commit = true; 7492292SN/A } 7501062SN/A 7512292SN/A if (fromCommit->commitUnblock[tid]) { 7522292SN/A assert(stalls[tid].commit); 7532292SN/A stalls[tid].commit = false; 7542292SN/A } 7552292SN/A} 7562292SN/A 7572292SN/Atemplate <class Impl> 7582292SN/Abool 7596221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid) 7602292SN/A{ 7612292SN/A bool ret_val(false); 7622292SN/A 7632292SN/A if (stalls[tid].commit) { 7642292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7652292SN/A ret_val = true; 7662292SN/A } else if (instQueue.isFull(tid)) { 7672292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7682292SN/A ret_val = true; 7692292SN/A } else if (ldstQueue.isFull(tid)) { 7702292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7712292SN/A 7722292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7732292SN/A 7742292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7752292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7762292SN/A } 7772292SN/A 7782292SN/A if (ldstQueue.numStores(tid) > 0) { 7792292SN/A 7802292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7812292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7822292SN/A } 7832292SN/A 7842292SN/A ret_val = true; 7852292SN/A } else if (ldstQueue.isStalled(tid)) { 7862292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7872292SN/A ret_val = true; 7882292SN/A } 7892292SN/A 7902292SN/A return ret_val; 7912292SN/A} 7922292SN/A 7932292SN/Atemplate <class Impl> 7942292SN/Avoid 7956221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid) 7962292SN/A{ 7972292SN/A // Check if there's a squash signal, squash if there is 7982292SN/A // Check stall signals, block if there is. 7992292SN/A // If status was Blocked 8002292SN/A // if so then go to unblocking 8012292SN/A // If status was Squashing 8022292SN/A // check if squashing is not high. Switch to running this cycle. 8032292SN/A 8042292SN/A readStallSignals(tid); 8052292SN/A 8062292SN/A if (fromCommit->commitInfo[tid].squash) { 8072292SN/A squash(tid); 8082292SN/A 8092292SN/A if (dispatchStatus[tid] == Blocked || 8102292SN/A dispatchStatus[tid] == Unblocking) { 8112292SN/A toRename->iewUnblock[tid] = true; 8122292SN/A wroteToTimeBuffer = true; 8132292SN/A } 8142292SN/A 8152292SN/A dispatchStatus[tid] = Squashing; 8162292SN/A fetchRedirect[tid] = false; 8172292SN/A return; 8182292SN/A } 8192292SN/A 8202292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 8212702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 8222292SN/A 8232292SN/A dispatchStatus[tid] = Squashing; 8242702Sktlim@umich.edu emptyRenameInsts(tid); 8252702Sktlim@umich.edu wroteToTimeBuffer = true; 8262292SN/A return; 8272292SN/A } 8282292SN/A 8292292SN/A if (checkStall(tid)) { 8302292SN/A block(tid); 8312292SN/A dispatchStatus[tid] = Blocked; 8322292SN/A return; 8332292SN/A } 8342292SN/A 8352292SN/A if (dispatchStatus[tid] == Blocked) { 8362292SN/A // Status from previous cycle was blocked, but there are no more stall 8372292SN/A // conditions. Switch over to unblocking. 8382292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8392292SN/A tid); 8402292SN/A 8412292SN/A dispatchStatus[tid] = Unblocking; 8422292SN/A 8432292SN/A unblock(tid); 8442292SN/A 8452292SN/A return; 8462292SN/A } 8472292SN/A 8482292SN/A if (dispatchStatus[tid] == Squashing) { 8492292SN/A // Switch status to running if rename isn't being told to block or 8502292SN/A // squash this cycle. 8512292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8522292SN/A tid); 8532292SN/A 8542292SN/A dispatchStatus[tid] = Running; 8552292SN/A 8562292SN/A return; 8572292SN/A } 8582292SN/A} 8592292SN/A 8602292SN/Atemplate <class Impl> 8612292SN/Avoid 8622292SN/ADefaultIEW<Impl>::sortInsts() 8632292SN/A{ 8642292SN/A int insts_from_rename = fromRename->size; 8652326SN/A#ifdef DEBUG 8666221Snate@binkert.org for (ThreadID tid = 0; tid < numThreads; tid++) 8676221Snate@binkert.org assert(insts[tid].empty()); 8682326SN/A#endif 8692292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8702292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8712292SN/A } 8722292SN/A} 8732292SN/A 8742292SN/Atemplate <class Impl> 8752292SN/Avoid 8766221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid) 8772702Sktlim@umich.edu{ 8784632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8792935Sksewell@umich.edu 8802702Sktlim@umich.edu while (!insts[tid].empty()) { 8812935Sksewell@umich.edu 8822702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8832702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8842702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8852702Sktlim@umich.edu } 8862702Sktlim@umich.edu 8872702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8882702Sktlim@umich.edu 8892702Sktlim@umich.edu insts[tid].pop(); 8902702Sktlim@umich.edu } 8912702Sktlim@umich.edu} 8922702Sktlim@umich.edu 8932702Sktlim@umich.edutemplate <class Impl> 8942702Sktlim@umich.eduvoid 8952292SN/ADefaultIEW<Impl>::wakeCPU() 8962292SN/A{ 8972292SN/A cpu->wakeCPU(); 8982292SN/A} 8992292SN/A 9002292SN/Atemplate <class Impl> 9012292SN/Avoid 9022292SN/ADefaultIEW<Impl>::activityThisCycle() 9032292SN/A{ 9042292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 9052292SN/A cpu->activityThisCycle(); 9062292SN/A} 9072292SN/A 9082292SN/Atemplate <class Impl> 9092292SN/Ainline void 9102292SN/ADefaultIEW<Impl>::activateStage() 9112292SN/A{ 9122292SN/A DPRINTF(Activity, "Activating stage.\n"); 9132733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 9142292SN/A} 9152292SN/A 9162292SN/Atemplate <class Impl> 9172292SN/Ainline void 9182292SN/ADefaultIEW<Impl>::deactivateStage() 9192292SN/A{ 9202292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 9212733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 9222292SN/A} 9232292SN/A 9242292SN/Atemplate<class Impl> 9252292SN/Avoid 9266221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid) 9272292SN/A{ 9282292SN/A // If status is Running or idle, 9292292SN/A // call dispatchInsts() 9302292SN/A // If status is Unblocking, 9312292SN/A // buffer any instructions coming from rename 9322292SN/A // continue trying to empty skid buffer 9332292SN/A // check if stall conditions have passed 9342292SN/A 9352292SN/A if (dispatchStatus[tid] == Blocked) { 9362292SN/A ++iewBlockCycles; 9372292SN/A 9382292SN/A } else if (dispatchStatus[tid] == Squashing) { 9392292SN/A ++iewSquashCycles; 9402292SN/A } 9412292SN/A 9422292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9432292SN/A // will allow, as long as it is not currently blocked. 9442292SN/A if (dispatchStatus[tid] == Running || 9452292SN/A dispatchStatus[tid] == Idle) { 9462292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9472292SN/A "dispatch.\n", tid); 9482292SN/A 9492292SN/A dispatchInsts(tid); 9502292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9512292SN/A // Make sure that the skid buffer has something in it if the 9522292SN/A // status is unblocking. 9532292SN/A assert(!skidsEmpty()); 9542292SN/A 9552292SN/A // If the status was unblocking, then instructions from the skid 9562292SN/A // buffer were used. Remove those instructions and handle 9572292SN/A // the rest of unblocking. 9582292SN/A dispatchInsts(tid); 9592292SN/A 9602292SN/A ++iewUnblockCycles; 9612292SN/A 9625215Sgblack@eecs.umich.edu if (validInstsFromRename()) { 9632292SN/A // Add the current inputs to the skid buffer so they can be 9642292SN/A // reprocessed when this stage unblocks. 9652292SN/A skidInsert(tid); 9662292SN/A } 9672292SN/A 9682292SN/A unblock(tid); 9692292SN/A } 9702292SN/A} 9712292SN/A 9722292SN/Atemplate <class Impl> 9732292SN/Avoid 9746221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid) 9752292SN/A{ 9762292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9772292SN/A // otherwise. 9782292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9792292SN/A dispatchStatus[tid] == Unblocking ? 9802292SN/A skidBuffer[tid] : insts[tid]; 9812292SN/A 9822292SN/A int insts_to_add = insts_to_dispatch.size(); 9832292SN/A 9842292SN/A DynInstPtr inst; 9852292SN/A bool add_to_iq = false; 9862292SN/A int dis_num_inst = 0; 9872292SN/A 9882292SN/A // Loop through the instructions, putting them in the instruction 9892292SN/A // queue. 9902292SN/A for ( ; dis_num_inst < insts_to_add && 9912820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9922292SN/A ++dis_num_inst) 9932292SN/A { 9942292SN/A inst = insts_to_dispatch.front(); 9952292SN/A 9962292SN/A if (dispatchStatus[tid] == Unblocking) { 9972292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9982292SN/A "buffer\n", tid); 9992292SN/A } 10002292SN/A 10012292SN/A // Make sure there's a valid instruction there. 10022292SN/A assert(inst); 10032292SN/A 10047720Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to " 10052292SN/A "IQ.\n", 10067720Sgblack@eecs.umich.edu tid, inst->pcState(), inst->seqNum, inst->threadNumber); 10072292SN/A 10082292SN/A // Be sure to mark these instructions as ready so that the 10092292SN/A // commit stage can go ahead and execute them, and mark 10102292SN/A // them as issued so the IQ doesn't reprocess them. 10112292SN/A 10122292SN/A // Check for squashed instructions. 10132292SN/A if (inst->isSquashed()) { 10142292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 10152292SN/A "not adding to IQ.\n", tid); 10162292SN/A 10172292SN/A ++iewDispSquashedInsts; 10182292SN/A 10192292SN/A insts_to_dispatch.pop(); 10202292SN/A 10212292SN/A //Tell Rename That An Instruction has been processed 10222292SN/A if (inst->isLoad() || inst->isStore()) { 10232292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10242292SN/A } 10252292SN/A toRename->iewInfo[tid].dispatched++; 10262292SN/A 10272292SN/A continue; 10282292SN/A } 10292292SN/A 10302292SN/A // Check for full conditions. 10312292SN/A if (instQueue.isFull(tid)) { 10322292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10332292SN/A 10342292SN/A // Call function to start blocking. 10352292SN/A block(tid); 10362292SN/A 10372292SN/A // Set unblock to false. Special case where we are using 10382292SN/A // skidbuffer (unblocking) instructions but then we still 10392292SN/A // get full in the IQ. 10402292SN/A toRename->iewUnblock[tid] = false; 10412292SN/A 10422292SN/A ++iewIQFullEvents; 10432292SN/A break; 10442292SN/A } else if (ldstQueue.isFull(tid)) { 10452292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10462292SN/A 10472292SN/A // Call function to start blocking. 10482292SN/A block(tid); 10492292SN/A 10502292SN/A // Set unblock to false. Special case where we are using 10512292SN/A // skidbuffer (unblocking) instructions but then we still 10522292SN/A // get full in the IQ. 10532292SN/A toRename->iewUnblock[tid] = false; 10542292SN/A 10552292SN/A ++iewLSQFullEvents; 10562292SN/A break; 10572292SN/A } 10582292SN/A 10592292SN/A // Otherwise issue the instruction just fine. 10602292SN/A if (inst->isLoad()) { 10612292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10622292SN/A "encountered, adding to LSQ.\n", tid); 10632292SN/A 10642292SN/A // Reserve a spot in the load store queue for this 10652292SN/A // memory access. 10662292SN/A ldstQueue.insertLoad(inst); 10672292SN/A 10682292SN/A ++iewDispLoadInsts; 10692292SN/A 10702292SN/A add_to_iq = true; 10712292SN/A 10722292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10732292SN/A } else if (inst->isStore()) { 10742292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10752292SN/A "encountered, adding to LSQ.\n", tid); 10762292SN/A 10772292SN/A ldstQueue.insertStore(inst); 10782292SN/A 10792292SN/A ++iewDispStoreInsts; 10802292SN/A 10812336SN/A if (inst->isStoreConditional()) { 10822336SN/A // Store conditionals need to be set as "canCommit()" 10832336SN/A // so that commit can process them when they reach the 10842336SN/A // head of commit. 10852348SN/A // @todo: This is somewhat specific to Alpha. 10862292SN/A inst->setCanCommit(); 10872292SN/A instQueue.insertNonSpec(inst); 10882292SN/A add_to_iq = false; 10892292SN/A 10902292SN/A ++iewDispNonSpecInsts; 10912292SN/A } else { 10922292SN/A add_to_iq = true; 10932292SN/A } 10942292SN/A 10952292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10962292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10972326SN/A // Same as non-speculative stores. 10982292SN/A inst->setCanCommit(); 10992292SN/A instQueue.insertBarrier(inst); 11002292SN/A add_to_iq = false; 11012292SN/A } else if (inst->isNop()) { 11022292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 11032292SN/A "skipping.\n", tid); 11042292SN/A 11052292SN/A inst->setIssued(); 11062292SN/A inst->setExecuted(); 11072292SN/A inst->setCanCommit(); 11082292SN/A 11092326SN/A instQueue.recordProducer(inst); 11102292SN/A 11112727Sktlim@umich.edu iewExecutedNop[tid]++; 11122301SN/A 11132292SN/A add_to_iq = false; 11142292SN/A } else if (inst->isExecuted()) { 11152292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 11162292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 11172292SN/A "skipping.\n"); 11182292SN/A 11192292SN/A inst->setIssued(); 11202292SN/A inst->setCanCommit(); 11212292SN/A 11222326SN/A instQueue.recordProducer(inst); 11232292SN/A 11242292SN/A add_to_iq = false; 11252292SN/A } else { 11262292SN/A add_to_iq = true; 11272292SN/A } 11284033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11294033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11304033Sktlim@umich.edu "encountered, skipping.\n", tid); 11314033Sktlim@umich.edu 11324033Sktlim@umich.edu // Same as non-speculative stores. 11334033Sktlim@umich.edu inst->setCanCommit(); 11344033Sktlim@umich.edu 11354033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11364033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11374033Sktlim@umich.edu 11384033Sktlim@umich.edu ++iewDispNonSpecInsts; 11394033Sktlim@umich.edu 11404033Sktlim@umich.edu add_to_iq = false; 11414033Sktlim@umich.edu } 11422292SN/A 11432292SN/A // If the instruction queue is not full, then add the 11442292SN/A // instruction. 11452292SN/A if (add_to_iq) { 11462292SN/A instQueue.insert(inst); 11472292SN/A } 11482292SN/A 11492292SN/A insts_to_dispatch.pop(); 11502292SN/A 11512292SN/A toRename->iewInfo[tid].dispatched++; 11522292SN/A 11532292SN/A ++iewDispatchedInsts; 11548471SGiacomo.Gabrielli@arm.com 11558471SGiacomo.Gabrielli@arm.com#if TRACING_ON 11569046SAli.Saidi@ARM.com inst->dispatchTick = curTick() - inst->fetchTick; 11578471SGiacomo.Gabrielli@arm.com#endif 11582292SN/A } 11592292SN/A 11602292SN/A if (!insts_to_dispatch.empty()) { 11612935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11622292SN/A block(tid); 11632292SN/A toRename->iewUnblock[tid] = false; 11642292SN/A } 11652292SN/A 11662292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11672292SN/A dispatchStatus[tid] = Running; 11682292SN/A 11692292SN/A updatedQueues = true; 11702292SN/A } 11712292SN/A 11722292SN/A dis_num_inst = 0; 11732292SN/A} 11742292SN/A 11752292SN/Atemplate <class Impl> 11762292SN/Avoid 11772292SN/ADefaultIEW<Impl>::printAvailableInsts() 11782292SN/A{ 11792292SN/A int inst = 0; 11802292SN/A 11812980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11822292SN/A 11832292SN/A while (fromIssue->insts[inst]) { 11842292SN/A 11852980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11862292SN/A 11877720Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->pcState() 11882292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11892292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11902292SN/A 11912292SN/A inst++; 11922292SN/A 11932292SN/A } 11942292SN/A 11952980Sgblack@eecs.umich.edu std::cout << "\n"; 11962292SN/A} 11972292SN/A 11982292SN/Atemplate <class Impl> 11992292SN/Avoid 12002292SN/ADefaultIEW<Impl>::executeInsts() 12012292SN/A{ 12022292SN/A wbNumInst = 0; 12032292SN/A wbCycle = 0; 12042292SN/A 12056221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 12066221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 12072292SN/A 12083867Sbinkertn@umich.edu while (threads != end) { 12096221Snate@binkert.org ThreadID tid = *threads++; 12102292SN/A fetchRedirect[tid] = false; 12112292SN/A } 12122292SN/A 12132698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 12147599Sminkyu.jeong@arm.com // @todo This doesn't actually work anymore, we should fix it. 12152698Sktlim@umich.edu// printAvailableInsts(); 12161062SN/A 12171062SN/A // Execute/writeback any instructions that are available. 12182333SN/A int insts_to_execute = fromIssue->size; 12192292SN/A int inst_num = 0; 12202333SN/A for (; inst_num < insts_to_execute; 12212326SN/A ++inst_num) { 12221062SN/A 12232292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 12241062SN/A 12252333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 12261062SN/A 12277720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n", 12287720Sgblack@eecs.umich.edu inst->pcState(), inst->threadNumber,inst->seqNum); 12291062SN/A 12301062SN/A // Check if the instruction is squashed; if so then skip it 12311062SN/A if (inst->isSquashed()) { 12328315Sgeoffrey.blake@arm.com DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]" 12338315Sgeoffrey.blake@arm.com " [sn:%i]\n", inst->pcState(), inst->threadNumber, 12348315Sgeoffrey.blake@arm.com inst->seqNum); 12351062SN/A 12361062SN/A // Consider this instruction executed so that commit can go 12371062SN/A // ahead and retire the instruction. 12381062SN/A inst->setExecuted(); 12391062SN/A 12402292SN/A // Not sure if I should set this here or just let commit try to 12412292SN/A // commit any squashed instructions. I like the latter a bit more. 12422292SN/A inst->setCanCommit(); 12431062SN/A 12441062SN/A ++iewExecSquashedInsts; 12451062SN/A 12462820Sktlim@umich.edu decrWb(inst->seqNum); 12471062SN/A continue; 12481062SN/A } 12491062SN/A 12502292SN/A Fault fault = NoFault; 12511062SN/A 12521062SN/A // Execute instruction. 12531062SN/A // Note that if the instruction faults, it will be handled 12541062SN/A // at the commit stage. 12557850SMatt.Horsnell@arm.com if (inst->isMemRef()) { 12562292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12571062SN/A "reference.\n"); 12581062SN/A 12591062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12601062SN/A if (inst->isLoad()) { 12612292SN/A // Loads will mark themselves as executed, and their writeback 12622292SN/A // event adds the instruction to the queue to commit 12632292SN/A fault = ldstQueue.executeLoad(inst); 12647944SGiacomo.Gabrielli@arm.com 12657944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12667944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12677944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12687944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12697944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12707944SGiacomo.Gabrielli@arm.com "load.\n"); 12717944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12727944SGiacomo.Gabrielli@arm.com continue; 12737944SGiacomo.Gabrielli@arm.com } 12747944SGiacomo.Gabrielli@arm.com 12757850SMatt.Horsnell@arm.com if (inst->isDataPrefetch() || inst->isInstPrefetch()) { 12768073SAli.Saidi@ARM.com inst->fault = NoFault; 12777850SMatt.Horsnell@arm.com } 12781062SN/A } else if (inst->isStore()) { 12792367SN/A fault = ldstQueue.executeStore(inst); 12801062SN/A 12817944SGiacomo.Gabrielli@arm.com if (inst->isTranslationDelayed() && 12827944SGiacomo.Gabrielli@arm.com fault == NoFault) { 12837944SGiacomo.Gabrielli@arm.com // A hw page table walk is currently going on; the 12847944SGiacomo.Gabrielli@arm.com // instruction must be deferred. 12857944SGiacomo.Gabrielli@arm.com DPRINTF(IEW, "Execute: Delayed translation, deferring " 12867944SGiacomo.Gabrielli@arm.com "store.\n"); 12877944SGiacomo.Gabrielli@arm.com instQueue.deferMemInst(inst); 12887944SGiacomo.Gabrielli@arm.com continue; 12897944SGiacomo.Gabrielli@arm.com } 12907944SGiacomo.Gabrielli@arm.com 12912292SN/A // If the store had a fault then it may not have a mem req 12927782Sminkyu.jeong@arm.com if (fault != NoFault || inst->readPredicate() == false || 12937782Sminkyu.jeong@arm.com !inst->isStoreConditional()) { 12947782Sminkyu.jeong@arm.com // If the instruction faulted, then we need to send it along 12957782Sminkyu.jeong@arm.com // to commit without the instruction completing. 12962367SN/A // Send this instruction to commit, also make sure iew stage 12972367SN/A // realizes there is activity. 12982367SN/A inst->setExecuted(); 12992367SN/A instToCommit(inst); 13002367SN/A activityThisCycle(); 13012292SN/A } 13022326SN/A 13032326SN/A // Store conditionals will mark themselves as 13042326SN/A // executed, and their writeback event will add the 13052326SN/A // instruction to the queue to commit. 13061062SN/A } else { 13072292SN/A panic("Unexpected memory type!\n"); 13081062SN/A } 13091062SN/A 13101062SN/A } else { 13117847Sminkyu.jeong@arm.com // If the instruction has already faulted, then skip executing it. 13127847Sminkyu.jeong@arm.com // Such case can happen when it faulted during ITLB translation. 13137847Sminkyu.jeong@arm.com // If we execute the instruction (even if it's a nop) the fault 13147847Sminkyu.jeong@arm.com // will be replaced and we will lose it. 13157847Sminkyu.jeong@arm.com if (inst->getFault() == NoFault) { 13167847Sminkyu.jeong@arm.com inst->execute(); 13177848SAli.Saidi@ARM.com if (inst->readPredicate() == false) 13187848SAli.Saidi@ARM.com inst->forwardOldRegs(); 13197847Sminkyu.jeong@arm.com } 13201062SN/A 13212292SN/A inst->setExecuted(); 13222292SN/A 13232292SN/A instToCommit(inst); 13241062SN/A } 13251062SN/A 13262301SN/A updateExeInstStats(inst); 13271681SN/A 13282326SN/A // Check if branch prediction was correct, if not then we need 13292326SN/A // to tell commit to squash in flight instructions. Only 13302326SN/A // handle this if there hasn't already been something that 13312107SN/A // redirects fetch in this group of instructions. 13321681SN/A 13332292SN/A // This probably needs to prioritize the redirects if a different 13342292SN/A // scheduler is used. Currently the scheduler schedules the oldest 13352292SN/A // instruction first, so the branch resolution order will be correct. 13366221Snate@binkert.org ThreadID tid = inst->threadNumber; 13371062SN/A 13383732Sktlim@umich.edu if (!fetchRedirect[tid] || 13397852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 13403732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 13411062SN/A 13427856SMatt.Horsnell@arm.com // Prevent testing for misprediction on load instructions, 13437856SMatt.Horsnell@arm.com // that have not been executed. 13447856SMatt.Horsnell@arm.com bool loadNotExecuted = !inst->isExecuted() && inst->isLoad(); 13457856SMatt.Horsnell@arm.com 13467856SMatt.Horsnell@arm.com if (inst->mispredicted() && !loadNotExecuted) { 13472292SN/A fetchRedirect[tid] = true; 13481062SN/A 13492292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 13508674Snilay@cs.wisc.edu DPRINTF(IEW, "Predicted target was PC: %s.\n", 13518674Snilay@cs.wisc.edu inst->readPredTarg()); 13527720Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n", 13538674Snilay@cs.wisc.edu inst->pcState()); 13541062SN/A // If incorrect, then signal the ROB that it must be squashed. 13552292SN/A squashDueToBranch(inst, tid); 13561062SN/A 13573795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 13581062SN/A predictedTakenIncorrect++; 13592292SN/A } else { 13602292SN/A predictedNotTakenIncorrect++; 13611062SN/A } 13622292SN/A } else if (ldstQueue.violation(tid)) { 13634033Sktlim@umich.edu assert(inst->isMemRef()); 13642326SN/A // If there was an ordering violation, then get the 13652326SN/A // DynInst that caused the violation. Note that this 13662292SN/A // clears the violation signal. 13672292SN/A DynInstPtr violator; 13682292SN/A violator = ldstQueue.getMemDepViolator(tid); 13691062SN/A 13707720Sgblack@eecs.umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s " 13717720Sgblack@eecs.umich.edu "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n", 13727720Sgblack@eecs.umich.edu violator->pcState(), violator->seqNum, 13737720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum, inst->physEffAddr); 13747720Sgblack@eecs.umich.edu 13753732Sktlim@umich.edu fetchRedirect[tid] = true; 13763732Sktlim@umich.edu 13771062SN/A // Tell the instruction queue that a violation has occured. 13781062SN/A instQueue.violation(inst, violator); 13791062SN/A 13801062SN/A // Squash. 13818513SGiacomo.Gabrielli@arm.com squashDueToMemOrder(violator, tid); 13821062SN/A 13831062SN/A ++memOrderViolationEvents; 13842292SN/A } else if (ldstQueue.loadBlocked(tid) && 13852292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13862292SN/A fetchRedirect[tid] = true; 13872292SN/A 13882292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13897720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 13907720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 13912292SN/A 13922292SN/A squashDueToMemBlocked(inst, tid); 13931062SN/A } 13944033Sktlim@umich.edu } else { 13954033Sktlim@umich.edu // Reset any state associated with redirects that will not 13964033Sktlim@umich.edu // be used. 13974033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 13984033Sktlim@umich.edu assert(inst->isMemRef()); 13994033Sktlim@umich.edu 14004033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 14014033Sktlim@umich.edu 14024033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 14037720Sgblack@eecs.umich.edu "%s, inst PC: %s. Addr is: %#x.\n", 14047720Sgblack@eecs.umich.edu violator->pcState(), inst->pcState(), 14057720Sgblack@eecs.umich.edu inst->physEffAddr); 14064033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 14074033Sktlim@umich.edu "already squashing\n"); 14084033Sktlim@umich.edu 14094033Sktlim@umich.edu ++memOrderViolationEvents; 14104033Sktlim@umich.edu } 14114033Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 14124033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 14134033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 14147720Sgblack@eecs.umich.edu "memory system is blocked. PC: %s [sn:%lli]\n", 14157720Sgblack@eecs.umich.edu inst->pcState(), inst->seqNum); 14164033Sktlim@umich.edu DPRINTF(IEW, "Blocked load will not be handled because " 14174033Sktlim@umich.edu "already squashing\n"); 14184033Sktlim@umich.edu 14194033Sktlim@umich.edu ldstQueue.setLoadBlockedHandled(tid); 14204033Sktlim@umich.edu } 14214033Sktlim@umich.edu 14221062SN/A } 14231062SN/A } 14242292SN/A 14252348SN/A // Update and record activity if we processed any instructions. 14262292SN/A if (inst_num) { 14272292SN/A if (exeStatus == Idle) { 14282292SN/A exeStatus = Running; 14292292SN/A } 14302292SN/A 14312292SN/A updatedQueues = true; 14322292SN/A 14332292SN/A cpu->activityThisCycle(); 14342292SN/A } 14352292SN/A 14362292SN/A // Need to reset this in case a writeback event needs to write into the 14372292SN/A // iew queue. That way the writeback event will write into the correct 14382292SN/A // spot in the queue. 14392292SN/A wbNumInst = 0; 14407852SMatt.Horsnell@arm.com 14412107SN/A} 14422107SN/A 14432292SN/Atemplate <class Impl> 14442107SN/Avoid 14452292SN/ADefaultIEW<Impl>::writebackInsts() 14462107SN/A{ 14472326SN/A // Loop through the head of the time buffer and wake any 14482326SN/A // dependents. These instructions are about to write back. Also 14492326SN/A // mark scoreboard that this instruction is finally complete. 14502326SN/A // Either have IEW have direct access to scoreboard, or have this 14512326SN/A // as part of backwards communication. 14523958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 14532292SN/A toCommit->insts[inst_num]; inst_num++) { 14542107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 14556221Snate@binkert.org ThreadID tid = inst->threadNumber; 14562107SN/A 14577720Sgblack@eecs.umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n", 14587720Sgblack@eecs.umich.edu inst->seqNum, inst->pcState()); 14592107SN/A 14602301SN/A iewInstsToCommit[tid]++; 14612301SN/A 14622292SN/A // Some instructions will be sent to commit without having 14632292SN/A // executed because they need commit to handle them. 14642292SN/A // E.g. Uncached loads have not actually executed when they 14652292SN/A // are first sent to commit. Instead commit must tell the LSQ 14662292SN/A // when it's ready to execute the uncached load. 14672367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14682301SN/A int dependents = instQueue.wakeDependents(inst); 14692107SN/A 14702292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14712292SN/A //mark as Ready 14722292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14732292SN/A inst->renamedDestRegIdx(i)); 14742292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14752107SN/A } 14762301SN/A 14772348SN/A if (dependents) { 14782348SN/A producerInst[tid]++; 14792348SN/A consumerInst[tid]+= dependents; 14802348SN/A } 14812326SN/A writebackCount[tid]++; 14822107SN/A } 14832820Sktlim@umich.edu 14842820Sktlim@umich.edu decrWb(inst->seqNum); 14852107SN/A } 14861060SN/A} 14871060SN/A 14881681SN/Atemplate<class Impl> 14891060SN/Avoid 14902292SN/ADefaultIEW<Impl>::tick() 14911060SN/A{ 14922292SN/A wbNumInst = 0; 14932292SN/A wbCycle = 0; 14941060SN/A 14952292SN/A wroteToTimeBuffer = false; 14962292SN/A updatedQueues = false; 14971060SN/A 14982292SN/A sortInsts(); 14991060SN/A 15002326SN/A // Free function units marked as being freed this cycle. 15012326SN/A fuPool->processFreeUnits(); 15021062SN/A 15036221Snate@binkert.org list<ThreadID>::iterator threads = activeThreads->begin(); 15046221Snate@binkert.org list<ThreadID>::iterator end = activeThreads->end(); 15051060SN/A 15062326SN/A // Check stall and squash signals, dispatch any instructions. 15073867Sbinkertn@umich.edu while (threads != end) { 15086221Snate@binkert.org ThreadID tid = *threads++; 15091060SN/A 15102292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 15111060SN/A 15122292SN/A checkSignalsAndUpdate(tid); 15132292SN/A dispatch(tid); 15141060SN/A } 15151060SN/A 15162292SN/A if (exeStatus != Squashing) { 15172292SN/A executeInsts(); 15181060SN/A 15192292SN/A writebackInsts(); 15202292SN/A 15212292SN/A // Have the instruction queue try to schedule any ready instructions. 15222292SN/A // (In actuality, this scheduling is for instructions that will 15232292SN/A // be executed next cycle.) 15242292SN/A instQueue.scheduleReadyInsts(); 15252292SN/A 15262292SN/A // Also should advance its own time buffers if the stage ran. 15272292SN/A // Not the best place for it, but this works (hopefully). 15282292SN/A issueToExecQueue.advance(); 15292292SN/A } 15302292SN/A 15312292SN/A bool broadcast_free_entries = false; 15322292SN/A 15332292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 15342292SN/A exeStatus = Idle; 15352292SN/A updateLSQNextCycle = false; 15362292SN/A 15372292SN/A broadcast_free_entries = true; 15382292SN/A } 15392292SN/A 15402292SN/A // Writeback any stores using any leftover bandwidth. 15411681SN/A ldstQueue.writebackStores(); 15421681SN/A 15431061SN/A // Check the committed load/store signals to see if there's a load 15441061SN/A // or store to commit. Also check if it's being told to execute a 15451061SN/A // nonspeculative instruction. 15461681SN/A // This is pretty inefficient... 15472292SN/A 15483867Sbinkertn@umich.edu threads = activeThreads->begin(); 15493867Sbinkertn@umich.edu while (threads != end) { 15506221Snate@binkert.org ThreadID tid = (*threads++); 15512292SN/A 15522292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 15532292SN/A 15542348SN/A // Update structures based on instructions committed. 15552292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15562292SN/A !fromCommit->commitInfo[tid].squash && 15572292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15582292SN/A 15592292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15602292SN/A 15612292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15622292SN/A 15632292SN/A updateLSQNextCycle = true; 15642292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15652292SN/A } 15662292SN/A 15672292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15682292SN/A 15692292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15702292SN/A if (fromCommit->commitInfo[tid].uncached) { 15712292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15724033Sktlim@umich.edu fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15732292SN/A } else { 15742292SN/A instQueue.scheduleNonSpec( 15752292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15762292SN/A } 15772292SN/A } 15782292SN/A 15792292SN/A if (broadcast_free_entries) { 15802292SN/A toFetch->iewInfo[tid].iqCount = 15812292SN/A instQueue.getCount(tid); 15822292SN/A toFetch->iewInfo[tid].ldstqCount = 15832292SN/A ldstQueue.getCount(tid); 15842292SN/A 15852292SN/A toRename->iewInfo[tid].usedIQ = true; 15862292SN/A toRename->iewInfo[tid].freeIQEntries = 15872292SN/A instQueue.numFreeEntries(); 15882292SN/A toRename->iewInfo[tid].usedLSQ = true; 15892292SN/A toRename->iewInfo[tid].freeLSQEntries = 15902292SN/A ldstQueue.numFreeEntries(tid); 15912292SN/A 15922292SN/A wroteToTimeBuffer = true; 15932292SN/A } 15942292SN/A 15952292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15962292SN/A tid, toRename->iewInfo[tid].dispatched); 15971061SN/A } 15981061SN/A 15992292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 16002292SN/A "LSQ has %i free entries.\n", 16012292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 16022292SN/A ldstQueue.numFreeEntries()); 16032292SN/A 16042292SN/A updateStatus(); 16052292SN/A 16062292SN/A if (wroteToTimeBuffer) { 16072292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 16082292SN/A cpu->activityThisCycle(); 16091061SN/A } 16101060SN/A} 16111060SN/A 16122301SN/Atemplate <class Impl> 16131060SN/Avoid 16142301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 16151060SN/A{ 16166221Snate@binkert.org ThreadID tid = inst->threadNumber; 16171060SN/A 16182669Sktlim@umich.edu iewExecutedInsts++; 16191060SN/A 16208471SGiacomo.Gabrielli@arm.com#if TRACING_ON 16219527SMatt.Horsnell@arm.com if (DTRACE(O3PipeView)) { 16229527SMatt.Horsnell@arm.com inst->completeTick = curTick() - inst->fetchTick; 16239527SMatt.Horsnell@arm.com } 16248471SGiacomo.Gabrielli@arm.com#endif 16258471SGiacomo.Gabrielli@arm.com 16262301SN/A // 16272301SN/A // Control operations 16282301SN/A // 16292301SN/A if (inst->isControl()) 16306221Snate@binkert.org iewExecutedBranches[tid]++; 16311060SN/A 16322301SN/A // 16332301SN/A // Memory operations 16342301SN/A // 16352301SN/A if (inst->isMemRef()) { 16366221Snate@binkert.org iewExecutedRefs[tid]++; 16371060SN/A 16382301SN/A if (inst->isLoad()) { 16396221Snate@binkert.org iewExecLoadInsts[tid]++; 16401060SN/A } 16411060SN/A } 16421060SN/A} 16437598Sminkyu.jeong@arm.com 16447598Sminkyu.jeong@arm.comtemplate <class Impl> 16457598Sminkyu.jeong@arm.comvoid 16467598Sminkyu.jeong@arm.comDefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst) 16477598Sminkyu.jeong@arm.com{ 16487598Sminkyu.jeong@arm.com ThreadID tid = inst->threadNumber; 16497598Sminkyu.jeong@arm.com 16507598Sminkyu.jeong@arm.com if (!fetchRedirect[tid] || 16517852SMatt.Horsnell@arm.com !toCommit->squash[tid] || 16527598Sminkyu.jeong@arm.com toCommit->squashedSeqNum[tid] > inst->seqNum) { 16537598Sminkyu.jeong@arm.com 16547598Sminkyu.jeong@arm.com if (inst->mispredicted()) { 16557598Sminkyu.jeong@arm.com fetchRedirect[tid] = true; 16567598Sminkyu.jeong@arm.com 16577598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 16587598Sminkyu.jeong@arm.com DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n", 16597720Sgblack@eecs.umich.edu inst->predInstAddr(), inst->predNextInstAddr()); 16607598Sminkyu.jeong@arm.com DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 16617720Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->nextInstAddr(), 16627720Sgblack@eecs.umich.edu inst->nextInstAddr()); 16637598Sminkyu.jeong@arm.com // If incorrect, then signal the ROB that it must be squashed. 16647598Sminkyu.jeong@arm.com squashDueToBranch(inst, tid); 16657598Sminkyu.jeong@arm.com 16667598Sminkyu.jeong@arm.com if (inst->readPredTaken()) { 16677598Sminkyu.jeong@arm.com predictedTakenIncorrect++; 16687598Sminkyu.jeong@arm.com } else { 16697598Sminkyu.jeong@arm.com predictedNotTakenIncorrect++; 16707598Sminkyu.jeong@arm.com } 16717598Sminkyu.jeong@arm.com } 16727598Sminkyu.jeong@arm.com } 16737598Sminkyu.jeong@arm.com} 1674