iew_impl.hh revision 8850
11689SN/A/*
28733Sgeoffrey.blake@arm.com * Copyright (c) 2010-2011 ARM Limited
37598Sminkyu.jeong@arm.com * All rights reserved.
47598Sminkyu.jeong@arm.com *
57598Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall
67598Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual
77598Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating
87598Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software
97598Sminkyu.jeong@arm.com * licensed hereunder.  You may use the software subject to the license
107598Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated
117598Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software,
127598Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form.
137598Sminkyu.jeong@arm.com *
142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan
151689SN/A * All rights reserved.
161689SN/A *
171689SN/A * Redistribution and use in source and binary forms, with or without
181689SN/A * modification, are permitted provided that the following conditions are
191689SN/A * met: redistributions of source code must retain the above copyright
201689SN/A * notice, this list of conditions and the following disclaimer;
211689SN/A * redistributions in binary form must reproduce the above copyright
221689SN/A * notice, this list of conditions and the following disclaimer in the
231689SN/A * documentation and/or other materials provided with the distribution;
241689SN/A * neither the name of the copyright holders nor the names of its
251689SN/A * contributors may be used to endorse or promote products derived from
261689SN/A * this software without specific prior written permission.
271689SN/A *
281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
392665Ssaidi@eecs.umich.edu *
402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim
411689SN/A */
421689SN/A
431060SN/A// @todo: Fix the instantaneous communication among all the stages within
441060SN/A// iew.  There's a clear delay between issue and execute, yet backwards
451689SN/A// communication happens simultaneously.
461060SN/A
471060SN/A#include <queue>
481060SN/A
498230Snate@binkert.org#include "arch/utility.hh"
506658Snate@binkert.org#include "config/the_isa.hh"
518733Sgeoffrey.blake@arm.com#include "config/use_checker.hh"
522292SN/A#include "cpu/o3/fu_pool.hh"
531717SN/A#include "cpu/o3/iew.hh"
548229Snate@binkert.org#include "cpu/timebuf.hh"
558232Snate@binkert.org#include "debug/Activity.hh"
568232Snate@binkert.org#include "debug/Decode.hh"
578232Snate@binkert.org#include "debug/IEW.hh"
585529Snate@binkert.org#include "params/DerivO3CPU.hh"
591060SN/A
608733Sgeoffrey.blake@arm.com#if USE_CHECKER
618733Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh"
628733Sgeoffrey.blake@arm.com#endif // USE_CHECKER
638733Sgeoffrey.blake@arm.com
646221Snate@binkert.orgusing namespace std;
656221Snate@binkert.org
661681SN/Atemplate<class Impl>
675529Snate@binkert.orgDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params)
682873Sktlim@umich.edu    : issueToExecQueue(params->backComSize, params->forwardComSize),
694329Sktlim@umich.edu      cpu(_cpu),
704329Sktlim@umich.edu      instQueue(_cpu, this, params),
714329Sktlim@umich.edu      ldstQueue(_cpu, this, params),
722292SN/A      fuPool(params->fuPool),
732292SN/A      commitToIEWDelay(params->commitToIEWDelay),
742292SN/A      renameToIEWDelay(params->renameToIEWDelay),
752292SN/A      issueToExecuteDelay(params->issueToExecuteDelay),
762820Sktlim@umich.edu      dispatchWidth(params->dispatchWidth),
772292SN/A      issueWidth(params->issueWidth),
782820Sktlim@umich.edu      wbOutstanding(0),
792820Sktlim@umich.edu      wbWidth(params->wbWidth),
805529Snate@binkert.org      numThreads(params->numThreads),
812307SN/A      switchedOut(false)
821060SN/A{
832292SN/A    _status = Active;
842292SN/A    exeStatus = Running;
852292SN/A    wbStatus = Idle;
861060SN/A
871060SN/A    // Setup wire to read instructions coming from issue.
881060SN/A    fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay);
891060SN/A
901060SN/A    // Instruction queue needs the queue between issue and execute.
911060SN/A    instQueue.setIssueToExecuteQueue(&issueToExecQueue);
921681SN/A
936221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; tid++) {
946221Snate@binkert.org        dispatchStatus[tid] = Running;
956221Snate@binkert.org        stalls[tid].commit = false;
966221Snate@binkert.org        fetchRedirect[tid] = false;
972292SN/A    }
982292SN/A
992820Sktlim@umich.edu    wbMax = wbWidth * params->wbDepth;
1002820Sktlim@umich.edu
1012292SN/A    updateLSQNextCycle = false;
1022292SN/A
1032820Sktlim@umich.edu    ableToIssue = true;
1042820Sktlim@umich.edu
1052292SN/A    skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth;
1062292SN/A}
1072292SN/A
1082292SN/Atemplate <class Impl>
1092292SN/Astd::string
1102292SN/ADefaultIEW<Impl>::name() const
1112292SN/A{
1122292SN/A    return cpu->name() + ".iew";
1131060SN/A}
1141060SN/A
1151681SN/Atemplate <class Impl>
1161062SN/Avoid
1172292SN/ADefaultIEW<Impl>::regStats()
1181062SN/A{
1192301SN/A    using namespace Stats;
1202301SN/A
1211062SN/A    instQueue.regStats();
1222727Sktlim@umich.edu    ldstQueue.regStats();
1231062SN/A
1241062SN/A    iewIdleCycles
1251062SN/A        .name(name() + ".iewIdleCycles")
1261062SN/A        .desc("Number of cycles IEW is idle");
1271062SN/A
1281062SN/A    iewSquashCycles
1291062SN/A        .name(name() + ".iewSquashCycles")
1301062SN/A        .desc("Number of cycles IEW is squashing");
1311062SN/A
1321062SN/A    iewBlockCycles
1331062SN/A        .name(name() + ".iewBlockCycles")
1341062SN/A        .desc("Number of cycles IEW is blocking");
1351062SN/A
1361062SN/A    iewUnblockCycles
1371062SN/A        .name(name() + ".iewUnblockCycles")
1381062SN/A        .desc("Number of cycles IEW is unblocking");
1391062SN/A
1401062SN/A    iewDispatchedInsts
1411062SN/A        .name(name() + ".iewDispatchedInsts")
1421062SN/A        .desc("Number of instructions dispatched to IQ");
1431062SN/A
1441062SN/A    iewDispSquashedInsts
1451062SN/A        .name(name() + ".iewDispSquashedInsts")
1461062SN/A        .desc("Number of squashed instructions skipped by dispatch");
1471062SN/A
1481062SN/A    iewDispLoadInsts
1491062SN/A        .name(name() + ".iewDispLoadInsts")
1501062SN/A        .desc("Number of dispatched load instructions");
1511062SN/A
1521062SN/A    iewDispStoreInsts
1531062SN/A        .name(name() + ".iewDispStoreInsts")
1541062SN/A        .desc("Number of dispatched store instructions");
1551062SN/A
1561062SN/A    iewDispNonSpecInsts
1571062SN/A        .name(name() + ".iewDispNonSpecInsts")
1581062SN/A        .desc("Number of dispatched non-speculative instructions");
1591062SN/A
1601062SN/A    iewIQFullEvents
1611062SN/A        .name(name() + ".iewIQFullEvents")
1621062SN/A        .desc("Number of times the IQ has become full, causing a stall");
1631062SN/A
1642292SN/A    iewLSQFullEvents
1652292SN/A        .name(name() + ".iewLSQFullEvents")
1662292SN/A        .desc("Number of times the LSQ has become full, causing a stall");
1672292SN/A
1681062SN/A    memOrderViolationEvents
1691062SN/A        .name(name() + ".memOrderViolationEvents")
1701062SN/A        .desc("Number of memory order violations");
1711062SN/A
1721062SN/A    predictedTakenIncorrect
1731062SN/A        .name(name() + ".predictedTakenIncorrect")
1741062SN/A        .desc("Number of branches that were predicted taken incorrectly");
1752292SN/A
1762292SN/A    predictedNotTakenIncorrect
1772292SN/A        .name(name() + ".predictedNotTakenIncorrect")
1782292SN/A        .desc("Number of branches that were predicted not taken incorrectly");
1792292SN/A
1802292SN/A    branchMispredicts
1812292SN/A        .name(name() + ".branchMispredicts")
1822292SN/A        .desc("Number of branch mispredicts detected at execute");
1832292SN/A
1842292SN/A    branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect;
1852301SN/A
1862727Sktlim@umich.edu    iewExecutedInsts
1872353SN/A        .name(name() + ".iewExecutedInsts")
1882727Sktlim@umich.edu        .desc("Number of executed instructions");
1892727Sktlim@umich.edu
1902727Sktlim@umich.edu    iewExecLoadInsts
1916221Snate@binkert.org        .init(cpu->numThreads)
1922353SN/A        .name(name() + ".iewExecLoadInsts")
1932727Sktlim@umich.edu        .desc("Number of load instructions executed")
1942727Sktlim@umich.edu        .flags(total);
1952727Sktlim@umich.edu
1962727Sktlim@umich.edu    iewExecSquashedInsts
1972353SN/A        .name(name() + ".iewExecSquashedInsts")
1982727Sktlim@umich.edu        .desc("Number of squashed instructions skipped in execute");
1992727Sktlim@umich.edu
2002727Sktlim@umich.edu    iewExecutedSwp
2016221Snate@binkert.org        .init(cpu->numThreads)
2028240Snate@binkert.org        .name(name() + ".exec_swp")
2032301SN/A        .desc("number of swp insts executed")
2042727Sktlim@umich.edu        .flags(total);
2052301SN/A
2062727Sktlim@umich.edu    iewExecutedNop
2076221Snate@binkert.org        .init(cpu->numThreads)
2088240Snate@binkert.org        .name(name() + ".exec_nop")
2092301SN/A        .desc("number of nop insts executed")
2102727Sktlim@umich.edu        .flags(total);
2112301SN/A
2122727Sktlim@umich.edu    iewExecutedRefs
2136221Snate@binkert.org        .init(cpu->numThreads)
2148240Snate@binkert.org        .name(name() + ".exec_refs")
2152301SN/A        .desc("number of memory reference insts executed")
2162727Sktlim@umich.edu        .flags(total);
2172301SN/A
2182727Sktlim@umich.edu    iewExecutedBranches
2196221Snate@binkert.org        .init(cpu->numThreads)
2208240Snate@binkert.org        .name(name() + ".exec_branches")
2212301SN/A        .desc("Number of branches executed")
2222727Sktlim@umich.edu        .flags(total);
2232301SN/A
2242301SN/A    iewExecStoreInsts
2258240Snate@binkert.org        .name(name() + ".exec_stores")
2262301SN/A        .desc("Number of stores executed")
2272727Sktlim@umich.edu        .flags(total);
2282727Sktlim@umich.edu    iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts;
2292727Sktlim@umich.edu
2302727Sktlim@umich.edu    iewExecRate
2318240Snate@binkert.org        .name(name() + ".exec_rate")
2322727Sktlim@umich.edu        .desc("Inst execution rate")
2332727Sktlim@umich.edu        .flags(total);
2342727Sktlim@umich.edu
2352727Sktlim@umich.edu    iewExecRate = iewExecutedInsts / cpu->numCycles;
2362301SN/A
2372301SN/A    iewInstsToCommit
2386221Snate@binkert.org        .init(cpu->numThreads)
2398240Snate@binkert.org        .name(name() + ".wb_sent")
2402301SN/A        .desc("cumulative count of insts sent to commit")
2412727Sktlim@umich.edu        .flags(total);
2422301SN/A
2432326SN/A    writebackCount
2446221Snate@binkert.org        .init(cpu->numThreads)
2458240Snate@binkert.org        .name(name() + ".wb_count")
2462301SN/A        .desc("cumulative count of insts written-back")
2472727Sktlim@umich.edu        .flags(total);
2482301SN/A
2492326SN/A    producerInst
2506221Snate@binkert.org        .init(cpu->numThreads)
2518240Snate@binkert.org        .name(name() + ".wb_producers")
2522301SN/A        .desc("num instructions producing a value")
2532727Sktlim@umich.edu        .flags(total);
2542301SN/A
2552326SN/A    consumerInst
2566221Snate@binkert.org        .init(cpu->numThreads)
2578240Snate@binkert.org        .name(name() + ".wb_consumers")
2582301SN/A        .desc("num instructions consuming a value")
2592727Sktlim@umich.edu        .flags(total);
2602301SN/A
2612326SN/A    wbPenalized
2626221Snate@binkert.org        .init(cpu->numThreads)
2638240Snate@binkert.org        .name(name() + ".wb_penalized")
2642301SN/A        .desc("number of instrctions required to write to 'other' IQ")
2652727Sktlim@umich.edu        .flags(total);
2662301SN/A
2672326SN/A    wbPenalizedRate
2688240Snate@binkert.org        .name(name() + ".wb_penalized_rate")
2692301SN/A        .desc ("fraction of instructions written-back that wrote to 'other' IQ")
2702727Sktlim@umich.edu        .flags(total);
2712301SN/A
2722326SN/A    wbPenalizedRate = wbPenalized / writebackCount;
2732301SN/A
2742326SN/A    wbFanout
2758240Snate@binkert.org        .name(name() + ".wb_fanout")
2762301SN/A        .desc("average fanout of values written-back")
2772727Sktlim@umich.edu        .flags(total);
2782301SN/A
2792326SN/A    wbFanout = producerInst / consumerInst;
2802301SN/A
2812326SN/A    wbRate
2828240Snate@binkert.org        .name(name() + ".wb_rate")
2832301SN/A        .desc("insts written-back per cycle")
2842727Sktlim@umich.edu        .flags(total);
2852326SN/A    wbRate = writebackCount / cpu->numCycles;
2861062SN/A}
2871062SN/A
2881681SN/Atemplate<class Impl>
2891060SN/Avoid
2902292SN/ADefaultIEW<Impl>::initStage()
2911060SN/A{
2926221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; tid++) {
2932292SN/A        toRename->iewInfo[tid].usedIQ = true;
2942292SN/A        toRename->iewInfo[tid].freeIQEntries =
2952292SN/A            instQueue.numFreeEntries(tid);
2962292SN/A
2972292SN/A        toRename->iewInfo[tid].usedLSQ = true;
2982292SN/A        toRename->iewInfo[tid].freeLSQEntries =
2992292SN/A            ldstQueue.numFreeEntries(tid);
3002292SN/A    }
3012292SN/A
3028733Sgeoffrey.blake@arm.com// Initialize the checker's dcache port here
3038733Sgeoffrey.blake@arm.com#if USE_CHECKER
3048733Sgeoffrey.blake@arm.com    if (cpu->checker) {
3058850Sandreas.hansson@arm.com        cpu->checker->setDcachePort(&cpu->getDataPort());
3068733Sgeoffrey.blake@arm.com     }
3078733Sgeoffrey.blake@arm.com#endif
3088733Sgeoffrey.blake@arm.com
3092733Sktlim@umich.edu    cpu->activateStage(O3CPU::IEWIdx);
3101060SN/A}
3111060SN/A
3121681SN/Atemplate<class Impl>
3131060SN/Avoid
3142292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
3151060SN/A{
3161060SN/A    timeBuffer = tb_ptr;
3171060SN/A
3181060SN/A    // Setup wire to read information from time buffer, from commit.
3191060SN/A    fromCommit = timeBuffer->getWire(-commitToIEWDelay);
3201060SN/A
3211060SN/A    // Setup wire to write information back to previous stages.
3221060SN/A    toRename = timeBuffer->getWire(0);
3231060SN/A
3242292SN/A    toFetch = timeBuffer->getWire(0);
3252292SN/A
3261060SN/A    // Instruction queue also needs main time buffer.
3271060SN/A    instQueue.setTimeBuffer(tb_ptr);
3281060SN/A}
3291060SN/A
3301681SN/Atemplate<class Impl>
3311060SN/Avoid
3322292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr)
3331060SN/A{
3341060SN/A    renameQueue = rq_ptr;
3351060SN/A
3361060SN/A    // Setup wire to read information from rename queue.
3371060SN/A    fromRename = renameQueue->getWire(-renameToIEWDelay);
3381060SN/A}
3391060SN/A
3401681SN/Atemplate<class Impl>
3411060SN/Avoid
3422292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr)
3431060SN/A{
3441060SN/A    iewQueue = iq_ptr;
3451060SN/A
3461060SN/A    // Setup wire to write instructions to commit.
3471060SN/A    toCommit = iewQueue->getWire(0);
3481060SN/A}
3491060SN/A
3501681SN/Atemplate<class Impl>
3511060SN/Avoid
3526221Snate@binkert.orgDefaultIEW<Impl>::setActiveThreads(list<ThreadID> *at_ptr)
3531060SN/A{
3542292SN/A    activeThreads = at_ptr;
3552292SN/A
3562292SN/A    ldstQueue.setActiveThreads(at_ptr);
3572292SN/A    instQueue.setActiveThreads(at_ptr);
3581060SN/A}
3591060SN/A
3601681SN/Atemplate<class Impl>
3611060SN/Avoid
3622292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr)
3631060SN/A{
3642292SN/A    scoreboard = sb_ptr;
3651060SN/A}
3661060SN/A
3672307SN/Atemplate <class Impl>
3682863Sktlim@umich.edubool
3692843Sktlim@umich.eduDefaultIEW<Impl>::drain()
3702307SN/A{
3712843Sktlim@umich.edu    // IEW is ready to drain at any time.
3722843Sktlim@umich.edu    cpu->signalDrained();
3732863Sktlim@umich.edu    return true;
3741681SN/A}
3751681SN/A
3762316SN/Atemplate <class Impl>
3771681SN/Avoid
3782843Sktlim@umich.eduDefaultIEW<Impl>::resume()
3792843Sktlim@umich.edu{
3802843Sktlim@umich.edu}
3812843Sktlim@umich.edu
3822843Sktlim@umich.edutemplate <class Impl>
3832843Sktlim@umich.eduvoid
3842843Sktlim@umich.eduDefaultIEW<Impl>::switchOut()
3851681SN/A{
3862348SN/A    // Clear any state.
3872307SN/A    switchedOut = true;
3882367SN/A    assert(insts[0].empty());
3892367SN/A    assert(skidBuffer[0].empty());
3901681SN/A
3912307SN/A    instQueue.switchOut();
3922307SN/A    ldstQueue.switchOut();
3932307SN/A    fuPool->switchOut();
3942307SN/A
3956221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; tid++) {
3966221Snate@binkert.org        while (!insts[tid].empty())
3976221Snate@binkert.org            insts[tid].pop();
3986221Snate@binkert.org        while (!skidBuffer[tid].empty())
3996221Snate@binkert.org            skidBuffer[tid].pop();
4002307SN/A    }
4011681SN/A}
4021681SN/A
4032307SN/Atemplate <class Impl>
4041681SN/Avoid
4052307SN/ADefaultIEW<Impl>::takeOverFrom()
4061060SN/A{
4072348SN/A    // Reset all state.
4082307SN/A    _status = Active;
4092307SN/A    exeStatus = Running;
4102307SN/A    wbStatus = Idle;
4112307SN/A    switchedOut = false;
4121060SN/A
4132307SN/A    instQueue.takeOverFrom();
4142307SN/A    ldstQueue.takeOverFrom();
4158737Skoansin.tan@gmail.com    fuPool->takeOver();
4161060SN/A
4172307SN/A    initStage();
4182307SN/A    cpu->activityThisCycle();
4191060SN/A
4206221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; tid++) {
4216221Snate@binkert.org        dispatchStatus[tid] = Running;
4226221Snate@binkert.org        stalls[tid].commit = false;
4236221Snate@binkert.org        fetchRedirect[tid] = false;
4242307SN/A    }
4251060SN/A
4262307SN/A    updateLSQNextCycle = false;
4272307SN/A
4282873Sktlim@umich.edu    for (int i = 0; i < issueToExecQueue.getSize(); ++i) {
4292307SN/A        issueToExecQueue.advance();
4301060SN/A    }
4311060SN/A}
4321060SN/A
4331681SN/Atemplate<class Impl>
4341060SN/Avoid
4356221Snate@binkert.orgDefaultIEW<Impl>::squash(ThreadID tid)
4362107SN/A{
4376221Snate@binkert.org    DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", tid);
4382107SN/A
4392292SN/A    // Tell the IQ to start squashing.
4402292SN/A    instQueue.squash(tid);
4412107SN/A
4422292SN/A    // Tell the LDSTQ to start squashing.
4432326SN/A    ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid);
4442292SN/A    updatedQueues = true;
4452107SN/A
4462292SN/A    // Clear the skid buffer in case it has any data in it.
4472935Sksewell@umich.edu    DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n",
4484632Sgblack@eecs.umich.edu            tid, fromCommit->commitInfo[tid].doneSeqNum);
4492935Sksewell@umich.edu
4502292SN/A    while (!skidBuffer[tid].empty()) {
4512292SN/A        if (skidBuffer[tid].front()->isLoad() ||
4522292SN/A            skidBuffer[tid].front()->isStore() ) {
4532292SN/A            toRename->iewInfo[tid].dispatchedToLSQ++;
4542292SN/A        }
4552107SN/A
4562292SN/A        toRename->iewInfo[tid].dispatched++;
4572107SN/A
4582292SN/A        skidBuffer[tid].pop();
4592292SN/A    }
4602107SN/A
4612702Sktlim@umich.edu    emptyRenameInsts(tid);
4622107SN/A}
4632107SN/A
4642107SN/Atemplate<class Impl>
4652107SN/Avoid
4666221Snate@binkert.orgDefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, ThreadID tid)
4672292SN/A{
4687720Sgblack@eecs.umich.edu    DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %s "
4697720Sgblack@eecs.umich.edu            "[sn:%i].\n", tid, inst->pcState(), inst->seqNum);
4702292SN/A
4717852SMatt.Horsnell@arm.com    if (toCommit->squash[tid] == false ||
4727852SMatt.Horsnell@arm.com            inst->seqNum < toCommit->squashedSeqNum[tid]) {
4737852SMatt.Horsnell@arm.com        toCommit->squash[tid] = true;
4747852SMatt.Horsnell@arm.com        toCommit->squashedSeqNum[tid] = inst->seqNum;
4757852SMatt.Horsnell@arm.com        toCommit->branchTaken[tid] = inst->pcState().branching();
4762935Sksewell@umich.edu
4777852SMatt.Horsnell@arm.com        TheISA::PCState pc = inst->pcState();
4787852SMatt.Horsnell@arm.com        TheISA::advancePC(pc, inst->staticInst);
4792292SN/A
4807852SMatt.Horsnell@arm.com        toCommit->pc[tid] = pc;
4817852SMatt.Horsnell@arm.com        toCommit->mispredictInst[tid] = inst;
4827852SMatt.Horsnell@arm.com        toCommit->includeSquashInst[tid] = false;
4832292SN/A
4847852SMatt.Horsnell@arm.com        wroteToTimeBuffer = true;
4857852SMatt.Horsnell@arm.com    }
4867852SMatt.Horsnell@arm.com
4872292SN/A}
4882292SN/A
4892292SN/Atemplate<class Impl>
4902292SN/Avoid
4916221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, ThreadID tid)
4922292SN/A{
4938513SGiacomo.Gabrielli@arm.com    DPRINTF(IEW, "[tid:%i]: Memory violation, squashing violator and younger "
4948513SGiacomo.Gabrielli@arm.com            "insts, PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
4958513SGiacomo.Gabrielli@arm.com    // Need to include inst->seqNum in the following comparison to cover the
4968513SGiacomo.Gabrielli@arm.com    // corner case when a branch misprediction and a memory violation for the
4978513SGiacomo.Gabrielli@arm.com    // same instruction (e.g. load PC) are detected in the same cycle.  In this
4988513SGiacomo.Gabrielli@arm.com    // case the memory violator should take precedence over the branch
4998513SGiacomo.Gabrielli@arm.com    // misprediction because it requires the violator itself to be included in
5008513SGiacomo.Gabrielli@arm.com    // the squash.
5018513SGiacomo.Gabrielli@arm.com    if (toCommit->squash[tid] == false ||
5028513SGiacomo.Gabrielli@arm.com            inst->seqNum <= toCommit->squashedSeqNum[tid]) {
5038513SGiacomo.Gabrielli@arm.com        toCommit->squash[tid] = true;
5042292SN/A
5057852SMatt.Horsnell@arm.com        toCommit->squashedSeqNum[tid] = inst->seqNum;
5068513SGiacomo.Gabrielli@arm.com        toCommit->pc[tid] = inst->pcState();
5078137SAli.Saidi@ARM.com        toCommit->mispredictInst[tid] = NULL;
5082292SN/A
5098513SGiacomo.Gabrielli@arm.com        // Must include the memory violator in the squash.
5108513SGiacomo.Gabrielli@arm.com        toCommit->includeSquashInst[tid] = true;
5112292SN/A
5127852SMatt.Horsnell@arm.com        wroteToTimeBuffer = true;
5137852SMatt.Horsnell@arm.com    }
5142292SN/A}
5152292SN/A
5162292SN/Atemplate<class Impl>
5172292SN/Avoid
5186221Snate@binkert.orgDefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid)
5192292SN/A{
5202292SN/A    DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, "
5217720Sgblack@eecs.umich.edu            "PC: %s [sn:%i].\n", tid, inst->pcState(), inst->seqNum);
5227852SMatt.Horsnell@arm.com    if (toCommit->squash[tid] == false ||
5237852SMatt.Horsnell@arm.com            inst->seqNum < toCommit->squashedSeqNum[tid]) {
5247852SMatt.Horsnell@arm.com        toCommit->squash[tid] = true;
5252292SN/A
5267852SMatt.Horsnell@arm.com        toCommit->squashedSeqNum[tid] = inst->seqNum;
5277852SMatt.Horsnell@arm.com        toCommit->pc[tid] = inst->pcState();
5288137SAli.Saidi@ARM.com        toCommit->mispredictInst[tid] = NULL;
5292292SN/A
5307852SMatt.Horsnell@arm.com        // Must include the broadcasted SN in the squash.
5317852SMatt.Horsnell@arm.com        toCommit->includeSquashInst[tid] = true;
5322292SN/A
5337852SMatt.Horsnell@arm.com        ldstQueue.setLoadBlockedHandled(tid);
5342292SN/A
5357852SMatt.Horsnell@arm.com        wroteToTimeBuffer = true;
5367852SMatt.Horsnell@arm.com    }
5372292SN/A}
5382292SN/A
5392292SN/Atemplate<class Impl>
5402292SN/Avoid
5416221Snate@binkert.orgDefaultIEW<Impl>::block(ThreadID tid)
5422292SN/A{
5432292SN/A    DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid);
5442292SN/A
5452292SN/A    if (dispatchStatus[tid] != Blocked &&
5462292SN/A        dispatchStatus[tid] != Unblocking) {
5472292SN/A        toRename->iewBlock[tid] = true;
5482292SN/A        wroteToTimeBuffer = true;
5492292SN/A    }
5502292SN/A
5512292SN/A    // Add the current inputs to the skid buffer so they can be
5522292SN/A    // reprocessed when this stage unblocks.
5532292SN/A    skidInsert(tid);
5542292SN/A
5552292SN/A    dispatchStatus[tid] = Blocked;
5562292SN/A}
5572292SN/A
5582292SN/Atemplate<class Impl>
5592292SN/Avoid
5606221Snate@binkert.orgDefaultIEW<Impl>::unblock(ThreadID tid)
5612292SN/A{
5622292SN/A    DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid "
5632292SN/A            "buffer %u.\n",tid, tid);
5642292SN/A
5652292SN/A    // If the skid bufffer is empty, signal back to previous stages to unblock.
5662292SN/A    // Also switch status to running.
5672292SN/A    if (skidBuffer[tid].empty()) {
5682292SN/A        toRename->iewUnblock[tid] = true;
5692292SN/A        wroteToTimeBuffer = true;
5702292SN/A        DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid);
5712292SN/A        dispatchStatus[tid] = Running;
5722292SN/A    }
5732292SN/A}
5742292SN/A
5752292SN/Atemplate<class Impl>
5762292SN/Avoid
5772292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst)
5781060SN/A{
5791681SN/A    instQueue.wakeDependents(inst);
5801060SN/A}
5811060SN/A
5822292SN/Atemplate<class Impl>
5832292SN/Avoid
5842292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst)
5852292SN/A{
5862292SN/A    instQueue.rescheduleMemInst(inst);
5872292SN/A}
5881681SN/A
5891681SN/Atemplate<class Impl>
5901060SN/Avoid
5912292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst)
5921060SN/A{
5932292SN/A    instQueue.replayMemInst(inst);
5942292SN/A}
5951060SN/A
5962292SN/Atemplate<class Impl>
5972292SN/Avoid
5982292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst)
5992292SN/A{
6003221Sktlim@umich.edu    // This function should not be called after writebackInsts in a
6013221Sktlim@umich.edu    // single cycle.  That will cause problems with an instruction
6023221Sktlim@umich.edu    // being added to the queue to commit without being processed by
6033221Sktlim@umich.edu    // writebackInsts prior to being sent to commit.
6043221Sktlim@umich.edu
6052292SN/A    // First check the time slot that this instruction will write
6062292SN/A    // to.  If there are free write ports at the time, then go ahead
6072292SN/A    // and write the instruction to that time.  If there are not,
6082292SN/A    // keep looking back to see where's the first time there's a
6092326SN/A    // free slot.
6102292SN/A    while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
6112292SN/A        ++wbNumInst;
6122820Sktlim@umich.edu        if (wbNumInst == wbWidth) {
6132292SN/A            ++wbCycle;
6142292SN/A            wbNumInst = 0;
6152292SN/A        }
6162292SN/A
6172353SN/A        assert((wbCycle * wbWidth + wbNumInst) <= wbMax);
6182292SN/A    }
6192292SN/A
6202353SN/A    DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n",
6212353SN/A            wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst);
6222292SN/A    // Add finished instruction to queue to commit.
6232292SN/A    (*iewQueue)[wbCycle].insts[wbNumInst] = inst;
6242292SN/A    (*iewQueue)[wbCycle].size++;
6252292SN/A}
6262292SN/A
6272292SN/Atemplate <class Impl>
6282292SN/Aunsigned
6292292SN/ADefaultIEW<Impl>::validInstsFromRename()
6302292SN/A{
6312292SN/A    unsigned inst_count = 0;
6322292SN/A
6332292SN/A    for (int i=0; i<fromRename->size; i++) {
6342731Sktlim@umich.edu        if (!fromRename->insts[i]->isSquashed())
6352292SN/A            inst_count++;
6362292SN/A    }
6372292SN/A
6382292SN/A    return inst_count;
6392292SN/A}
6402292SN/A
6412292SN/Atemplate<class Impl>
6422292SN/Avoid
6436221Snate@binkert.orgDefaultIEW<Impl>::skidInsert(ThreadID tid)
6442292SN/A{
6452292SN/A    DynInstPtr inst = NULL;
6462292SN/A
6472292SN/A    while (!insts[tid].empty()) {
6482292SN/A        inst = insts[tid].front();
6492292SN/A
6502292SN/A        insts[tid].pop();
6512292SN/A
6527720Sgblack@eecs.umich.edu        DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%s into "
6532292SN/A                "dispatch skidBuffer %i\n",tid, inst->seqNum,
6547720Sgblack@eecs.umich.edu                inst->pcState(),tid);
6552292SN/A
6562292SN/A        skidBuffer[tid].push(inst);
6572292SN/A    }
6582292SN/A
6592292SN/A    assert(skidBuffer[tid].size() <= skidBufferMax &&
6602292SN/A           "Skidbuffer Exceeded Max Size");
6612292SN/A}
6622292SN/A
6632292SN/Atemplate<class Impl>
6642292SN/Aint
6652292SN/ADefaultIEW<Impl>::skidCount()
6662292SN/A{
6672292SN/A    int max=0;
6682292SN/A
6696221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
6706221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
6712292SN/A
6723867Sbinkertn@umich.edu    while (threads != end) {
6736221Snate@binkert.org        ThreadID tid = *threads++;
6743867Sbinkertn@umich.edu        unsigned thread_count = skidBuffer[tid].size();
6752292SN/A        if (max < thread_count)
6762292SN/A            max = thread_count;
6772292SN/A    }
6782292SN/A
6792292SN/A    return max;
6802292SN/A}
6812292SN/A
6822292SN/Atemplate<class Impl>
6832292SN/Abool
6842292SN/ADefaultIEW<Impl>::skidsEmpty()
6852292SN/A{
6866221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
6876221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
6882292SN/A
6893867Sbinkertn@umich.edu    while (threads != end) {
6906221Snate@binkert.org        ThreadID tid = *threads++;
6913867Sbinkertn@umich.edu
6923867Sbinkertn@umich.edu        if (!skidBuffer[tid].empty())
6932292SN/A            return false;
6942292SN/A    }
6952292SN/A
6962292SN/A    return true;
6971062SN/A}
6981062SN/A
6991681SN/Atemplate <class Impl>
7001062SN/Avoid
7012292SN/ADefaultIEW<Impl>::updateStatus()
7021062SN/A{
7032292SN/A    bool any_unblocking = false;
7041062SN/A
7056221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
7066221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
7071062SN/A
7083867Sbinkertn@umich.edu    while (threads != end) {
7096221Snate@binkert.org        ThreadID tid = *threads++;
7101062SN/A
7112292SN/A        if (dispatchStatus[tid] == Unblocking) {
7122292SN/A            any_unblocking = true;
7132292SN/A            break;
7142292SN/A        }
7152292SN/A    }
7161062SN/A
7172292SN/A    // If there are no ready instructions waiting to be scheduled by the IQ,
7182292SN/A    // and there's no stores waiting to write back, and dispatch is not
7192292SN/A    // unblocking, then there is no internal activity for the IEW stage.
7207897Shestness@cs.utexas.edu    instQueue.intInstQueueReads++;
7212292SN/A    if (_status == Active && !instQueue.hasReadyInsts() &&
7222292SN/A        !ldstQueue.willWB() && !any_unblocking) {
7232292SN/A        DPRINTF(IEW, "IEW switching to idle\n");
7241062SN/A
7252292SN/A        deactivateStage();
7261062SN/A
7272292SN/A        _status = Inactive;
7282292SN/A    } else if (_status == Inactive && (instQueue.hasReadyInsts() ||
7292292SN/A                                       ldstQueue.willWB() ||
7302292SN/A                                       any_unblocking)) {
7312292SN/A        // Otherwise there is internal activity.  Set to active.
7322292SN/A        DPRINTF(IEW, "IEW switching to active\n");
7331062SN/A
7342292SN/A        activateStage();
7351062SN/A
7362292SN/A        _status = Active;
7371062SN/A    }
7381062SN/A}
7391062SN/A
7401681SN/Atemplate <class Impl>
7411062SN/Avoid
7422292SN/ADefaultIEW<Impl>::resetEntries()
7431062SN/A{
7442292SN/A    instQueue.resetEntries();
7452292SN/A    ldstQueue.resetEntries();
7462292SN/A}
7471062SN/A
7482292SN/Atemplate <class Impl>
7492292SN/Avoid
7506221Snate@binkert.orgDefaultIEW<Impl>::readStallSignals(ThreadID tid)
7512292SN/A{
7522292SN/A    if (fromCommit->commitBlock[tid]) {
7532292SN/A        stalls[tid].commit = true;
7542292SN/A    }
7551062SN/A
7562292SN/A    if (fromCommit->commitUnblock[tid]) {
7572292SN/A        assert(stalls[tid].commit);
7582292SN/A        stalls[tid].commit = false;
7592292SN/A    }
7602292SN/A}
7612292SN/A
7622292SN/Atemplate <class Impl>
7632292SN/Abool
7646221Snate@binkert.orgDefaultIEW<Impl>::checkStall(ThreadID tid)
7652292SN/A{
7662292SN/A    bool ret_val(false);
7672292SN/A
7682292SN/A    if (stalls[tid].commit) {
7692292SN/A        DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid);
7702292SN/A        ret_val = true;
7712292SN/A    } else if (instQueue.isFull(tid)) {
7722292SN/A        DPRINTF(IEW,"[tid:%i]: Stall: IQ  is full.\n",tid);
7732292SN/A        ret_val = true;
7742292SN/A    } else if (ldstQueue.isFull(tid)) {
7752292SN/A        DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid);
7762292SN/A
7772292SN/A        if (ldstQueue.numLoads(tid) > 0 ) {
7782292SN/A
7792292SN/A            DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n",
7802292SN/A                    tid,ldstQueue.getLoadHeadSeqNum(tid));
7812292SN/A        }
7822292SN/A
7832292SN/A        if (ldstQueue.numStores(tid) > 0) {
7842292SN/A
7852292SN/A            DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n",
7862292SN/A                    tid,ldstQueue.getStoreHeadSeqNum(tid));
7872292SN/A        }
7882292SN/A
7892292SN/A        ret_val = true;
7902292SN/A    } else if (ldstQueue.isStalled(tid)) {
7912292SN/A        DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid);
7922292SN/A        ret_val = true;
7932292SN/A    }
7942292SN/A
7952292SN/A    return ret_val;
7962292SN/A}
7972292SN/A
7982292SN/Atemplate <class Impl>
7992292SN/Avoid
8006221Snate@binkert.orgDefaultIEW<Impl>::checkSignalsAndUpdate(ThreadID tid)
8012292SN/A{
8022292SN/A    // Check if there's a squash signal, squash if there is
8032292SN/A    // Check stall signals, block if there is.
8042292SN/A    // If status was Blocked
8052292SN/A    //     if so then go to unblocking
8062292SN/A    // If status was Squashing
8072292SN/A    //     check if squashing is not high.  Switch to running this cycle.
8082292SN/A
8092292SN/A    readStallSignals(tid);
8102292SN/A
8112292SN/A    if (fromCommit->commitInfo[tid].squash) {
8122292SN/A        squash(tid);
8132292SN/A
8142292SN/A        if (dispatchStatus[tid] == Blocked ||
8152292SN/A            dispatchStatus[tid] == Unblocking) {
8162292SN/A            toRename->iewUnblock[tid] = true;
8172292SN/A            wroteToTimeBuffer = true;
8182292SN/A        }
8192292SN/A
8202292SN/A        dispatchStatus[tid] = Squashing;
8212292SN/A        fetchRedirect[tid] = false;
8222292SN/A        return;
8232292SN/A    }
8242292SN/A
8252292SN/A    if (fromCommit->commitInfo[tid].robSquashing) {
8262702Sktlim@umich.edu        DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid);
8272292SN/A
8282292SN/A        dispatchStatus[tid] = Squashing;
8292702Sktlim@umich.edu        emptyRenameInsts(tid);
8302702Sktlim@umich.edu        wroteToTimeBuffer = true;
8312292SN/A        return;
8322292SN/A    }
8332292SN/A
8342292SN/A    if (checkStall(tid)) {
8352292SN/A        block(tid);
8362292SN/A        dispatchStatus[tid] = Blocked;
8372292SN/A        return;
8382292SN/A    }
8392292SN/A
8402292SN/A    if (dispatchStatus[tid] == Blocked) {
8412292SN/A        // Status from previous cycle was blocked, but there are no more stall
8422292SN/A        // conditions.  Switch over to unblocking.
8432292SN/A        DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n",
8442292SN/A                tid);
8452292SN/A
8462292SN/A        dispatchStatus[tid] = Unblocking;
8472292SN/A
8482292SN/A        unblock(tid);
8492292SN/A
8502292SN/A        return;
8512292SN/A    }
8522292SN/A
8532292SN/A    if (dispatchStatus[tid] == Squashing) {
8542292SN/A        // Switch status to running if rename isn't being told to block or
8552292SN/A        // squash this cycle.
8562292SN/A        DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n",
8572292SN/A                tid);
8582292SN/A
8592292SN/A        dispatchStatus[tid] = Running;
8602292SN/A
8612292SN/A        return;
8622292SN/A    }
8632292SN/A}
8642292SN/A
8652292SN/Atemplate <class Impl>
8662292SN/Avoid
8672292SN/ADefaultIEW<Impl>::sortInsts()
8682292SN/A{
8692292SN/A    int insts_from_rename = fromRename->size;
8702326SN/A#ifdef DEBUG
8716221Snate@binkert.org    for (ThreadID tid = 0; tid < numThreads; tid++)
8726221Snate@binkert.org        assert(insts[tid].empty());
8732326SN/A#endif
8742292SN/A    for (int i = 0; i < insts_from_rename; ++i) {
8752292SN/A        insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]);
8762292SN/A    }
8772292SN/A}
8782292SN/A
8792292SN/Atemplate <class Impl>
8802292SN/Avoid
8816221Snate@binkert.orgDefaultIEW<Impl>::emptyRenameInsts(ThreadID tid)
8822702Sktlim@umich.edu{
8834632Sgblack@eecs.umich.edu    DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid);
8842935Sksewell@umich.edu
8852702Sktlim@umich.edu    while (!insts[tid].empty()) {
8862935Sksewell@umich.edu
8872702Sktlim@umich.edu        if (insts[tid].front()->isLoad() ||
8882702Sktlim@umich.edu            insts[tid].front()->isStore() ) {
8892702Sktlim@umich.edu            toRename->iewInfo[tid].dispatchedToLSQ++;
8902702Sktlim@umich.edu        }
8912702Sktlim@umich.edu
8922702Sktlim@umich.edu        toRename->iewInfo[tid].dispatched++;
8932702Sktlim@umich.edu
8942702Sktlim@umich.edu        insts[tid].pop();
8952702Sktlim@umich.edu    }
8962702Sktlim@umich.edu}
8972702Sktlim@umich.edu
8982702Sktlim@umich.edutemplate <class Impl>
8992702Sktlim@umich.eduvoid
9002292SN/ADefaultIEW<Impl>::wakeCPU()
9012292SN/A{
9022292SN/A    cpu->wakeCPU();
9032292SN/A}
9042292SN/A
9052292SN/Atemplate <class Impl>
9062292SN/Avoid
9072292SN/ADefaultIEW<Impl>::activityThisCycle()
9082292SN/A{
9092292SN/A    DPRINTF(Activity, "Activity this cycle.\n");
9102292SN/A    cpu->activityThisCycle();
9112292SN/A}
9122292SN/A
9132292SN/Atemplate <class Impl>
9142292SN/Ainline void
9152292SN/ADefaultIEW<Impl>::activateStage()
9162292SN/A{
9172292SN/A    DPRINTF(Activity, "Activating stage.\n");
9182733Sktlim@umich.edu    cpu->activateStage(O3CPU::IEWIdx);
9192292SN/A}
9202292SN/A
9212292SN/Atemplate <class Impl>
9222292SN/Ainline void
9232292SN/ADefaultIEW<Impl>::deactivateStage()
9242292SN/A{
9252292SN/A    DPRINTF(Activity, "Deactivating stage.\n");
9262733Sktlim@umich.edu    cpu->deactivateStage(O3CPU::IEWIdx);
9272292SN/A}
9282292SN/A
9292292SN/Atemplate<class Impl>
9302292SN/Avoid
9316221Snate@binkert.orgDefaultIEW<Impl>::dispatch(ThreadID tid)
9322292SN/A{
9332292SN/A    // If status is Running or idle,
9342292SN/A    //     call dispatchInsts()
9352292SN/A    // If status is Unblocking,
9362292SN/A    //     buffer any instructions coming from rename
9372292SN/A    //     continue trying to empty skid buffer
9382292SN/A    //     check if stall conditions have passed
9392292SN/A
9402292SN/A    if (dispatchStatus[tid] == Blocked) {
9412292SN/A        ++iewBlockCycles;
9422292SN/A
9432292SN/A    } else if (dispatchStatus[tid] == Squashing) {
9442292SN/A        ++iewSquashCycles;
9452292SN/A    }
9462292SN/A
9472292SN/A    // Dispatch should try to dispatch as many instructions as its bandwidth
9482292SN/A    // will allow, as long as it is not currently blocked.
9492292SN/A    if (dispatchStatus[tid] == Running ||
9502292SN/A        dispatchStatus[tid] == Idle) {
9512292SN/A        DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run "
9522292SN/A                "dispatch.\n", tid);
9532292SN/A
9542292SN/A        dispatchInsts(tid);
9552292SN/A    } else if (dispatchStatus[tid] == Unblocking) {
9562292SN/A        // Make sure that the skid buffer has something in it if the
9572292SN/A        // status is unblocking.
9582292SN/A        assert(!skidsEmpty());
9592292SN/A
9602292SN/A        // If the status was unblocking, then instructions from the skid
9612292SN/A        // buffer were used.  Remove those instructions and handle
9622292SN/A        // the rest of unblocking.
9632292SN/A        dispatchInsts(tid);
9642292SN/A
9652292SN/A        ++iewUnblockCycles;
9662292SN/A
9675215Sgblack@eecs.umich.edu        if (validInstsFromRename()) {
9682292SN/A            // Add the current inputs to the skid buffer so they can be
9692292SN/A            // reprocessed when this stage unblocks.
9702292SN/A            skidInsert(tid);
9712292SN/A        }
9722292SN/A
9732292SN/A        unblock(tid);
9742292SN/A    }
9752292SN/A}
9762292SN/A
9772292SN/Atemplate <class Impl>
9782292SN/Avoid
9796221Snate@binkert.orgDefaultIEW<Impl>::dispatchInsts(ThreadID tid)
9802292SN/A{
9812292SN/A    // Obtain instructions from skid buffer if unblocking, or queue from rename
9822292SN/A    // otherwise.
9832292SN/A    std::queue<DynInstPtr> &insts_to_dispatch =
9842292SN/A        dispatchStatus[tid] == Unblocking ?
9852292SN/A        skidBuffer[tid] : insts[tid];
9862292SN/A
9872292SN/A    int insts_to_add = insts_to_dispatch.size();
9882292SN/A
9892292SN/A    DynInstPtr inst;
9902292SN/A    bool add_to_iq = false;
9912292SN/A    int dis_num_inst = 0;
9922292SN/A
9932292SN/A    // Loop through the instructions, putting them in the instruction
9942292SN/A    // queue.
9952292SN/A    for ( ; dis_num_inst < insts_to_add &&
9962820Sktlim@umich.edu              dis_num_inst < dispatchWidth;
9972292SN/A          ++dis_num_inst)
9982292SN/A    {
9992292SN/A        inst = insts_to_dispatch.front();
10002292SN/A
10012292SN/A        if (dispatchStatus[tid] == Unblocking) {
10022292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid "
10032292SN/A                    "buffer\n", tid);
10042292SN/A        }
10052292SN/A
10062292SN/A        // Make sure there's a valid instruction there.
10072292SN/A        assert(inst);
10082292SN/A
10097720Sgblack@eecs.umich.edu        DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %s [sn:%lli] [tid:%i] to "
10102292SN/A                "IQ.\n",
10117720Sgblack@eecs.umich.edu                tid, inst->pcState(), inst->seqNum, inst->threadNumber);
10122292SN/A
10132292SN/A        // Be sure to mark these instructions as ready so that the
10142292SN/A        // commit stage can go ahead and execute them, and mark
10152292SN/A        // them as issued so the IQ doesn't reprocess them.
10162292SN/A
10172292SN/A        // Check for squashed instructions.
10182292SN/A        if (inst->isSquashed()) {
10192292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, "
10202292SN/A                    "not adding to IQ.\n", tid);
10212292SN/A
10222292SN/A            ++iewDispSquashedInsts;
10232292SN/A
10242292SN/A            insts_to_dispatch.pop();
10252292SN/A
10262292SN/A            //Tell Rename That An Instruction has been processed
10272292SN/A            if (inst->isLoad() || inst->isStore()) {
10282292SN/A                toRename->iewInfo[tid].dispatchedToLSQ++;
10292292SN/A            }
10302292SN/A            toRename->iewInfo[tid].dispatched++;
10312292SN/A
10322292SN/A            continue;
10332292SN/A        }
10342292SN/A
10352292SN/A        // Check for full conditions.
10362292SN/A        if (instQueue.isFull(tid)) {
10372292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid);
10382292SN/A
10392292SN/A            // Call function to start blocking.
10402292SN/A            block(tid);
10412292SN/A
10422292SN/A            // Set unblock to false. Special case where we are using
10432292SN/A            // skidbuffer (unblocking) instructions but then we still
10442292SN/A            // get full in the IQ.
10452292SN/A            toRename->iewUnblock[tid] = false;
10462292SN/A
10472292SN/A            ++iewIQFullEvents;
10482292SN/A            break;
10492292SN/A        } else if (ldstQueue.isFull(tid)) {
10502292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid);
10512292SN/A
10522292SN/A            // Call function to start blocking.
10532292SN/A            block(tid);
10542292SN/A
10552292SN/A            // Set unblock to false. Special case where we are using
10562292SN/A            // skidbuffer (unblocking) instructions but then we still
10572292SN/A            // get full in the IQ.
10582292SN/A            toRename->iewUnblock[tid] = false;
10592292SN/A
10602292SN/A            ++iewLSQFullEvents;
10612292SN/A            break;
10622292SN/A        }
10632292SN/A
10642292SN/A        // Otherwise issue the instruction just fine.
10652292SN/A        if (inst->isLoad()) {
10662292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
10672292SN/A                    "encountered, adding to LSQ.\n", tid);
10682292SN/A
10692292SN/A            // Reserve a spot in the load store queue for this
10702292SN/A            // memory access.
10712292SN/A            ldstQueue.insertLoad(inst);
10722292SN/A
10732292SN/A            ++iewDispLoadInsts;
10742292SN/A
10752292SN/A            add_to_iq = true;
10762292SN/A
10772292SN/A            toRename->iewInfo[tid].dispatchedToLSQ++;
10782292SN/A        } else if (inst->isStore()) {
10792292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction "
10802292SN/A                    "encountered, adding to LSQ.\n", tid);
10812292SN/A
10822292SN/A            ldstQueue.insertStore(inst);
10832292SN/A
10842292SN/A            ++iewDispStoreInsts;
10852292SN/A
10862336SN/A            if (inst->isStoreConditional()) {
10872336SN/A                // Store conditionals need to be set as "canCommit()"
10882336SN/A                // so that commit can process them when they reach the
10892336SN/A                // head of commit.
10902348SN/A                // @todo: This is somewhat specific to Alpha.
10912292SN/A                inst->setCanCommit();
10922292SN/A                instQueue.insertNonSpec(inst);
10932292SN/A                add_to_iq = false;
10942292SN/A
10952292SN/A                ++iewDispNonSpecInsts;
10962292SN/A            } else {
10972292SN/A                add_to_iq = true;
10982292SN/A            }
10992292SN/A
11002292SN/A            toRename->iewInfo[tid].dispatchedToLSQ++;
11012292SN/A        } else if (inst->isMemBarrier() || inst->isWriteBarrier()) {
11022326SN/A            // Same as non-speculative stores.
11032292SN/A            inst->setCanCommit();
11042292SN/A            instQueue.insertBarrier(inst);
11052292SN/A            add_to_iq = false;
11062292SN/A        } else if (inst->isNop()) {
11072292SN/A            DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, "
11082292SN/A                    "skipping.\n", tid);
11092292SN/A
11102292SN/A            inst->setIssued();
11112292SN/A            inst->setExecuted();
11122292SN/A            inst->setCanCommit();
11132292SN/A
11142326SN/A            instQueue.recordProducer(inst);
11152292SN/A
11162727Sktlim@umich.edu            iewExecutedNop[tid]++;
11172301SN/A
11182292SN/A            add_to_iq = false;
11192292SN/A        } else if (inst->isExecuted()) {
11202292SN/A            assert(0 && "Instruction shouldn't be executed.\n");
11212292SN/A            DPRINTF(IEW, "Issue: Executed branch encountered, "
11222292SN/A                    "skipping.\n");
11232292SN/A
11242292SN/A            inst->setIssued();
11252292SN/A            inst->setCanCommit();
11262292SN/A
11272326SN/A            instQueue.recordProducer(inst);
11282292SN/A
11292292SN/A            add_to_iq = false;
11302292SN/A        } else {
11312292SN/A            add_to_iq = true;
11322292SN/A        }
11334033Sktlim@umich.edu        if (inst->isNonSpeculative()) {
11344033Sktlim@umich.edu            DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction "
11354033Sktlim@umich.edu                    "encountered, skipping.\n", tid);
11364033Sktlim@umich.edu
11374033Sktlim@umich.edu            // Same as non-speculative stores.
11384033Sktlim@umich.edu            inst->setCanCommit();
11394033Sktlim@umich.edu
11404033Sktlim@umich.edu            // Specifically insert it as nonspeculative.
11414033Sktlim@umich.edu            instQueue.insertNonSpec(inst);
11424033Sktlim@umich.edu
11434033Sktlim@umich.edu            ++iewDispNonSpecInsts;
11444033Sktlim@umich.edu
11454033Sktlim@umich.edu            add_to_iq = false;
11464033Sktlim@umich.edu        }
11472292SN/A
11482292SN/A        // If the instruction queue is not full, then add the
11492292SN/A        // instruction.
11502292SN/A        if (add_to_iq) {
11512292SN/A            instQueue.insert(inst);
11522292SN/A        }
11532292SN/A
11542292SN/A        insts_to_dispatch.pop();
11552292SN/A
11562292SN/A        toRename->iewInfo[tid].dispatched++;
11572292SN/A
11582292SN/A        ++iewDispatchedInsts;
11598471SGiacomo.Gabrielli@arm.com
11608471SGiacomo.Gabrielli@arm.com#if TRACING_ON
11618471SGiacomo.Gabrielli@arm.com        inst->dispatchTick = curTick();
11628471SGiacomo.Gabrielli@arm.com#endif
11632292SN/A    }
11642292SN/A
11652292SN/A    if (!insts_to_dispatch.empty()) {
11662935Sksewell@umich.edu        DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid);
11672292SN/A        block(tid);
11682292SN/A        toRename->iewUnblock[tid] = false;
11692292SN/A    }
11702292SN/A
11712292SN/A    if (dispatchStatus[tid] == Idle && dis_num_inst) {
11722292SN/A        dispatchStatus[tid] = Running;
11732292SN/A
11742292SN/A        updatedQueues = true;
11752292SN/A    }
11762292SN/A
11772292SN/A    dis_num_inst = 0;
11782292SN/A}
11792292SN/A
11802292SN/Atemplate <class Impl>
11812292SN/Avoid
11822292SN/ADefaultIEW<Impl>::printAvailableInsts()
11832292SN/A{
11842292SN/A    int inst = 0;
11852292SN/A
11862980Sgblack@eecs.umich.edu    std::cout << "Available Instructions: ";
11872292SN/A
11882292SN/A    while (fromIssue->insts[inst]) {
11892292SN/A
11902980Sgblack@eecs.umich.edu        if (inst%3==0) std::cout << "\n\t";
11912292SN/A
11927720Sgblack@eecs.umich.edu        std::cout << "PC: " << fromIssue->insts[inst]->pcState()
11932292SN/A             << " TN: " << fromIssue->insts[inst]->threadNumber
11942292SN/A             << " SN: " << fromIssue->insts[inst]->seqNum << " | ";
11952292SN/A
11962292SN/A        inst++;
11972292SN/A
11982292SN/A    }
11992292SN/A
12002980Sgblack@eecs.umich.edu    std::cout << "\n";
12012292SN/A}
12022292SN/A
12032292SN/Atemplate <class Impl>
12042292SN/Avoid
12052292SN/ADefaultIEW<Impl>::executeInsts()
12062292SN/A{
12072292SN/A    wbNumInst = 0;
12082292SN/A    wbCycle = 0;
12092292SN/A
12106221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
12116221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
12122292SN/A
12133867Sbinkertn@umich.edu    while (threads != end) {
12146221Snate@binkert.org        ThreadID tid = *threads++;
12152292SN/A        fetchRedirect[tid] = false;
12162292SN/A    }
12172292SN/A
12182698Sktlim@umich.edu    // Uncomment this if you want to see all available instructions.
12197599Sminkyu.jeong@arm.com    // @todo This doesn't actually work anymore, we should fix it.
12202698Sktlim@umich.edu//    printAvailableInsts();
12211062SN/A
12221062SN/A    // Execute/writeback any instructions that are available.
12232333SN/A    int insts_to_execute = fromIssue->size;
12242292SN/A    int inst_num = 0;
12252333SN/A    for (; inst_num < insts_to_execute;
12262326SN/A          ++inst_num) {
12271062SN/A
12282292SN/A        DPRINTF(IEW, "Execute: Executing instructions from IQ.\n");
12291062SN/A
12302333SN/A        DynInstPtr inst = instQueue.getInstToExecute();
12311062SN/A
12327720Sgblack@eecs.umich.edu        DPRINTF(IEW, "Execute: Processing PC %s, [tid:%i] [sn:%i].\n",
12337720Sgblack@eecs.umich.edu                inst->pcState(), inst->threadNumber,inst->seqNum);
12341062SN/A
12351062SN/A        // Check if the instruction is squashed; if so then skip it
12361062SN/A        if (inst->isSquashed()) {
12378315Sgeoffrey.blake@arm.com            DPRINTF(IEW, "Execute: Instruction was squashed. PC: %s, [tid:%i]"
12388315Sgeoffrey.blake@arm.com                         " [sn:%i]\n", inst->pcState(), inst->threadNumber,
12398315Sgeoffrey.blake@arm.com                         inst->seqNum);
12401062SN/A
12411062SN/A            // Consider this instruction executed so that commit can go
12421062SN/A            // ahead and retire the instruction.
12431062SN/A            inst->setExecuted();
12441062SN/A
12452292SN/A            // Not sure if I should set this here or just let commit try to
12462292SN/A            // commit any squashed instructions.  I like the latter a bit more.
12472292SN/A            inst->setCanCommit();
12481062SN/A
12491062SN/A            ++iewExecSquashedInsts;
12501062SN/A
12512820Sktlim@umich.edu            decrWb(inst->seqNum);
12521062SN/A            continue;
12531062SN/A        }
12541062SN/A
12552292SN/A        Fault fault = NoFault;
12561062SN/A
12571062SN/A        // Execute instruction.
12581062SN/A        // Note that if the instruction faults, it will be handled
12591062SN/A        // at the commit stage.
12607850SMatt.Horsnell@arm.com        if (inst->isMemRef()) {
12612292SN/A            DPRINTF(IEW, "Execute: Calculating address for memory "
12621062SN/A                    "reference.\n");
12631062SN/A
12641062SN/A            // Tell the LDSTQ to execute this instruction (if it is a load).
12651062SN/A            if (inst->isLoad()) {
12662292SN/A                // Loads will mark themselves as executed, and their writeback
12672292SN/A                // event adds the instruction to the queue to commit
12682292SN/A                fault = ldstQueue.executeLoad(inst);
12697944SGiacomo.Gabrielli@arm.com
12707944SGiacomo.Gabrielli@arm.com                if (inst->isTranslationDelayed() &&
12717944SGiacomo.Gabrielli@arm.com                    fault == NoFault) {
12727944SGiacomo.Gabrielli@arm.com                    // A hw page table walk is currently going on; the
12737944SGiacomo.Gabrielli@arm.com                    // instruction must be deferred.
12747944SGiacomo.Gabrielli@arm.com                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
12757944SGiacomo.Gabrielli@arm.com                            "load.\n");
12767944SGiacomo.Gabrielli@arm.com                    instQueue.deferMemInst(inst);
12777944SGiacomo.Gabrielli@arm.com                    continue;
12787944SGiacomo.Gabrielli@arm.com                }
12797944SGiacomo.Gabrielli@arm.com
12807850SMatt.Horsnell@arm.com                if (inst->isDataPrefetch() || inst->isInstPrefetch()) {
12818073SAli.Saidi@ARM.com                    inst->fault = NoFault;
12827850SMatt.Horsnell@arm.com                }
12831062SN/A            } else if (inst->isStore()) {
12842367SN/A                fault = ldstQueue.executeStore(inst);
12851062SN/A
12867944SGiacomo.Gabrielli@arm.com                if (inst->isTranslationDelayed() &&
12877944SGiacomo.Gabrielli@arm.com                    fault == NoFault) {
12887944SGiacomo.Gabrielli@arm.com                    // A hw page table walk is currently going on; the
12897944SGiacomo.Gabrielli@arm.com                    // instruction must be deferred.
12907944SGiacomo.Gabrielli@arm.com                    DPRINTF(IEW, "Execute: Delayed translation, deferring "
12917944SGiacomo.Gabrielli@arm.com                            "store.\n");
12927944SGiacomo.Gabrielli@arm.com                    instQueue.deferMemInst(inst);
12937944SGiacomo.Gabrielli@arm.com                    continue;
12947944SGiacomo.Gabrielli@arm.com                }
12957944SGiacomo.Gabrielli@arm.com
12962292SN/A                // If the store had a fault then it may not have a mem req
12977782Sminkyu.jeong@arm.com                if (fault != NoFault || inst->readPredicate() == false ||
12987782Sminkyu.jeong@arm.com                        !inst->isStoreConditional()) {
12997782Sminkyu.jeong@arm.com                    // If the instruction faulted, then we need to send it along
13007782Sminkyu.jeong@arm.com                    // to commit without the instruction completing.
13012367SN/A                    // Send this instruction to commit, also make sure iew stage
13022367SN/A                    // realizes there is activity.
13032367SN/A                    inst->setExecuted();
13042367SN/A                    instToCommit(inst);
13052367SN/A                    activityThisCycle();
13062292SN/A                }
13072326SN/A
13082326SN/A                // Store conditionals will mark themselves as
13092326SN/A                // executed, and their writeback event will add the
13102326SN/A                // instruction to the queue to commit.
13111062SN/A            } else {
13122292SN/A                panic("Unexpected memory type!\n");
13131062SN/A            }
13141062SN/A
13151062SN/A        } else {
13167847Sminkyu.jeong@arm.com            // If the instruction has already faulted, then skip executing it.
13177847Sminkyu.jeong@arm.com            // Such case can happen when it faulted during ITLB translation.
13187847Sminkyu.jeong@arm.com            // If we execute the instruction (even if it's a nop) the fault
13197847Sminkyu.jeong@arm.com            // will be replaced and we will lose it.
13207847Sminkyu.jeong@arm.com            if (inst->getFault() == NoFault) {
13217847Sminkyu.jeong@arm.com                inst->execute();
13227848SAli.Saidi@ARM.com                if (inst->readPredicate() == false)
13237848SAli.Saidi@ARM.com                    inst->forwardOldRegs();
13247847Sminkyu.jeong@arm.com            }
13251062SN/A
13262292SN/A            inst->setExecuted();
13272292SN/A
13282292SN/A            instToCommit(inst);
13291062SN/A        }
13301062SN/A
13312301SN/A        updateExeInstStats(inst);
13321681SN/A
13332326SN/A        // Check if branch prediction was correct, if not then we need
13342326SN/A        // to tell commit to squash in flight instructions.  Only
13352326SN/A        // handle this if there hasn't already been something that
13362107SN/A        // redirects fetch in this group of instructions.
13371681SN/A
13382292SN/A        // This probably needs to prioritize the redirects if a different
13392292SN/A        // scheduler is used.  Currently the scheduler schedules the oldest
13402292SN/A        // instruction first, so the branch resolution order will be correct.
13416221Snate@binkert.org        ThreadID tid = inst->threadNumber;
13421062SN/A
13433732Sktlim@umich.edu        if (!fetchRedirect[tid] ||
13447852SMatt.Horsnell@arm.com            !toCommit->squash[tid] ||
13453732Sktlim@umich.edu            toCommit->squashedSeqNum[tid] > inst->seqNum) {
13461062SN/A
13477856SMatt.Horsnell@arm.com            // Prevent testing for misprediction on load instructions,
13487856SMatt.Horsnell@arm.com            // that have not been executed.
13497856SMatt.Horsnell@arm.com            bool loadNotExecuted = !inst->isExecuted() && inst->isLoad();
13507856SMatt.Horsnell@arm.com
13517856SMatt.Horsnell@arm.com            if (inst->mispredicted() && !loadNotExecuted) {
13522292SN/A                fetchRedirect[tid] = true;
13531062SN/A
13542292SN/A                DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
13558674Snilay@cs.wisc.edu                DPRINTF(IEW, "Predicted target was PC: %s.\n",
13568674Snilay@cs.wisc.edu                        inst->readPredTarg());
13577720Sgblack@eecs.umich.edu                DPRINTF(IEW, "Execute: Redirecting fetch to PC: %s.\n",
13588674Snilay@cs.wisc.edu                        inst->pcState());
13591062SN/A                // If incorrect, then signal the ROB that it must be squashed.
13602292SN/A                squashDueToBranch(inst, tid);
13611062SN/A
13623795Sgblack@eecs.umich.edu                if (inst->readPredTaken()) {
13631062SN/A                    predictedTakenIncorrect++;
13642292SN/A                } else {
13652292SN/A                    predictedNotTakenIncorrect++;
13661062SN/A                }
13672292SN/A            } else if (ldstQueue.violation(tid)) {
13684033Sktlim@umich.edu                assert(inst->isMemRef());
13692326SN/A                // If there was an ordering violation, then get the
13702326SN/A                // DynInst that caused the violation.  Note that this
13712292SN/A                // clears the violation signal.
13722292SN/A                DynInstPtr violator;
13732292SN/A                violator = ldstQueue.getMemDepViolator(tid);
13741062SN/A
13757720Sgblack@eecs.umich.edu                DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: %s "
13767720Sgblack@eecs.umich.edu                        "[sn:%lli], inst PC: %s [sn:%lli]. Addr is: %#x.\n",
13777720Sgblack@eecs.umich.edu                        violator->pcState(), violator->seqNum,
13787720Sgblack@eecs.umich.edu                        inst->pcState(), inst->seqNum, inst->physEffAddr);
13797720Sgblack@eecs.umich.edu
13803732Sktlim@umich.edu                fetchRedirect[tid] = true;
13813732Sktlim@umich.edu
13821062SN/A                // Tell the instruction queue that a violation has occured.
13831062SN/A                instQueue.violation(inst, violator);
13841062SN/A
13851062SN/A                // Squash.
13868513SGiacomo.Gabrielli@arm.com                squashDueToMemOrder(violator, tid);
13871062SN/A
13881062SN/A                ++memOrderViolationEvents;
13892292SN/A            } else if (ldstQueue.loadBlocked(tid) &&
13902292SN/A                       !ldstQueue.isLoadBlockedHandled(tid)) {
13912292SN/A                fetchRedirect[tid] = true;
13922292SN/A
13932292SN/A                DPRINTF(IEW, "Load operation couldn't execute because the "
13947720Sgblack@eecs.umich.edu                        "memory system is blocked.  PC: %s [sn:%lli]\n",
13957720Sgblack@eecs.umich.edu                        inst->pcState(), inst->seqNum);
13962292SN/A
13972292SN/A                squashDueToMemBlocked(inst, tid);
13981062SN/A            }
13994033Sktlim@umich.edu        } else {
14004033Sktlim@umich.edu            // Reset any state associated with redirects that will not
14014033Sktlim@umich.edu            // be used.
14024033Sktlim@umich.edu            if (ldstQueue.violation(tid)) {
14034033Sktlim@umich.edu                assert(inst->isMemRef());
14044033Sktlim@umich.edu
14054033Sktlim@umich.edu                DynInstPtr violator = ldstQueue.getMemDepViolator(tid);
14064033Sktlim@umich.edu
14074033Sktlim@umich.edu                DPRINTF(IEW, "LDSTQ detected a violation.  Violator PC: "
14087720Sgblack@eecs.umich.edu                        "%s, inst PC: %s.  Addr is: %#x.\n",
14097720Sgblack@eecs.umich.edu                        violator->pcState(), inst->pcState(),
14107720Sgblack@eecs.umich.edu                        inst->physEffAddr);
14114033Sktlim@umich.edu                DPRINTF(IEW, "Violation will not be handled because "
14124033Sktlim@umich.edu                        "already squashing\n");
14134033Sktlim@umich.edu
14144033Sktlim@umich.edu                ++memOrderViolationEvents;
14154033Sktlim@umich.edu            }
14164033Sktlim@umich.edu            if (ldstQueue.loadBlocked(tid) &&
14174033Sktlim@umich.edu                !ldstQueue.isLoadBlockedHandled(tid)) {
14184033Sktlim@umich.edu                DPRINTF(IEW, "Load operation couldn't execute because the "
14197720Sgblack@eecs.umich.edu                        "memory system is blocked.  PC: %s [sn:%lli]\n",
14207720Sgblack@eecs.umich.edu                        inst->pcState(), inst->seqNum);
14214033Sktlim@umich.edu                DPRINTF(IEW, "Blocked load will not be handled because "
14224033Sktlim@umich.edu                        "already squashing\n");
14234033Sktlim@umich.edu
14244033Sktlim@umich.edu                ldstQueue.setLoadBlockedHandled(tid);
14254033Sktlim@umich.edu            }
14264033Sktlim@umich.edu
14271062SN/A        }
14281062SN/A    }
14292292SN/A
14302348SN/A    // Update and record activity if we processed any instructions.
14312292SN/A    if (inst_num) {
14322292SN/A        if (exeStatus == Idle) {
14332292SN/A            exeStatus = Running;
14342292SN/A        }
14352292SN/A
14362292SN/A        updatedQueues = true;
14372292SN/A
14382292SN/A        cpu->activityThisCycle();
14392292SN/A    }
14402292SN/A
14412292SN/A    // Need to reset this in case a writeback event needs to write into the
14422292SN/A    // iew queue.  That way the writeback event will write into the correct
14432292SN/A    // spot in the queue.
14442292SN/A    wbNumInst = 0;
14457852SMatt.Horsnell@arm.com
14462107SN/A}
14472107SN/A
14482292SN/Atemplate <class Impl>
14492107SN/Avoid
14502292SN/ADefaultIEW<Impl>::writebackInsts()
14512107SN/A{
14522326SN/A    // Loop through the head of the time buffer and wake any
14532326SN/A    // dependents.  These instructions are about to write back.  Also
14542326SN/A    // mark scoreboard that this instruction is finally complete.
14552326SN/A    // Either have IEW have direct access to scoreboard, or have this
14562326SN/A    // as part of backwards communication.
14573958Sgblack@eecs.umich.edu    for (int inst_num = 0; inst_num < wbWidth &&
14582292SN/A             toCommit->insts[inst_num]; inst_num++) {
14592107SN/A        DynInstPtr inst = toCommit->insts[inst_num];
14606221Snate@binkert.org        ThreadID tid = inst->threadNumber;
14612107SN/A
14627720Sgblack@eecs.umich.edu        DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %s.\n",
14637720Sgblack@eecs.umich.edu                inst->seqNum, inst->pcState());
14642107SN/A
14652301SN/A        iewInstsToCommit[tid]++;
14662301SN/A
14672292SN/A        // Some instructions will be sent to commit without having
14682292SN/A        // executed because they need commit to handle them.
14692292SN/A        // E.g. Uncached loads have not actually executed when they
14702292SN/A        // are first sent to commit.  Instead commit must tell the LSQ
14712292SN/A        // when it's ready to execute the uncached load.
14722367SN/A        if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) {
14732301SN/A            int dependents = instQueue.wakeDependents(inst);
14742107SN/A
14752292SN/A            for (int i = 0; i < inst->numDestRegs(); i++) {
14762292SN/A                //mark as Ready
14772292SN/A                DPRINTF(IEW,"Setting Destination Register %i\n",
14782292SN/A                        inst->renamedDestRegIdx(i));
14792292SN/A                scoreboard->setReg(inst->renamedDestRegIdx(i));
14802107SN/A            }
14812301SN/A
14822348SN/A            if (dependents) {
14832348SN/A                producerInst[tid]++;
14842348SN/A                consumerInst[tid]+= dependents;
14852348SN/A            }
14862326SN/A            writebackCount[tid]++;
14872107SN/A        }
14882820Sktlim@umich.edu
14892820Sktlim@umich.edu        decrWb(inst->seqNum);
14902107SN/A    }
14911060SN/A}
14921060SN/A
14931681SN/Atemplate<class Impl>
14941060SN/Avoid
14952292SN/ADefaultIEW<Impl>::tick()
14961060SN/A{
14972292SN/A    wbNumInst = 0;
14982292SN/A    wbCycle = 0;
14991060SN/A
15002292SN/A    wroteToTimeBuffer = false;
15012292SN/A    updatedQueues = false;
15021060SN/A
15032292SN/A    sortInsts();
15041060SN/A
15052326SN/A    // Free function units marked as being freed this cycle.
15062326SN/A    fuPool->processFreeUnits();
15071062SN/A
15086221Snate@binkert.org    list<ThreadID>::iterator threads = activeThreads->begin();
15096221Snate@binkert.org    list<ThreadID>::iterator end = activeThreads->end();
15101060SN/A
15112326SN/A    // Check stall and squash signals, dispatch any instructions.
15123867Sbinkertn@umich.edu    while (threads != end) {
15136221Snate@binkert.org        ThreadID tid = *threads++;
15141060SN/A
15152292SN/A        DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid);
15161060SN/A
15172292SN/A        checkSignalsAndUpdate(tid);
15182292SN/A        dispatch(tid);
15191060SN/A    }
15201060SN/A
15212292SN/A    if (exeStatus != Squashing) {
15222292SN/A        executeInsts();
15231060SN/A
15242292SN/A        writebackInsts();
15252292SN/A
15262292SN/A        // Have the instruction queue try to schedule any ready instructions.
15272292SN/A        // (In actuality, this scheduling is for instructions that will
15282292SN/A        // be executed next cycle.)
15292292SN/A        instQueue.scheduleReadyInsts();
15302292SN/A
15312292SN/A        // Also should advance its own time buffers if the stage ran.
15322292SN/A        // Not the best place for it, but this works (hopefully).
15332292SN/A        issueToExecQueue.advance();
15342292SN/A    }
15352292SN/A
15362292SN/A    bool broadcast_free_entries = false;
15372292SN/A
15382292SN/A    if (updatedQueues || exeStatus == Running || updateLSQNextCycle) {
15392292SN/A        exeStatus = Idle;
15402292SN/A        updateLSQNextCycle = false;
15412292SN/A
15422292SN/A        broadcast_free_entries = true;
15432292SN/A    }
15442292SN/A
15452292SN/A    // Writeback any stores using any leftover bandwidth.
15461681SN/A    ldstQueue.writebackStores();
15471681SN/A
15481061SN/A    // Check the committed load/store signals to see if there's a load
15491061SN/A    // or store to commit.  Also check if it's being told to execute a
15501061SN/A    // nonspeculative instruction.
15511681SN/A    // This is pretty inefficient...
15522292SN/A
15533867Sbinkertn@umich.edu    threads = activeThreads->begin();
15543867Sbinkertn@umich.edu    while (threads != end) {
15556221Snate@binkert.org        ThreadID tid = (*threads++);
15562292SN/A
15572292SN/A        DPRINTF(IEW,"Processing [tid:%i]\n",tid);
15582292SN/A
15592348SN/A        // Update structures based on instructions committed.
15602292SN/A        if (fromCommit->commitInfo[tid].doneSeqNum != 0 &&
15612292SN/A            !fromCommit->commitInfo[tid].squash &&
15622292SN/A            !fromCommit->commitInfo[tid].robSquashing) {
15632292SN/A
15642292SN/A            ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid);
15652292SN/A
15662292SN/A            ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid);
15672292SN/A
15682292SN/A            updateLSQNextCycle = true;
15692292SN/A            instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid);
15702292SN/A        }
15712292SN/A
15722292SN/A        if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) {
15732292SN/A
15742292SN/A            //DPRINTF(IEW,"NonspecInst from thread %i",tid);
15752292SN/A            if (fromCommit->commitInfo[tid].uncached) {
15762292SN/A                instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad);
15774033Sktlim@umich.edu                fromCommit->commitInfo[tid].uncachedLoad->setAtCommit();
15782292SN/A            } else {
15792292SN/A                instQueue.scheduleNonSpec(
15802292SN/A                    fromCommit->commitInfo[tid].nonSpecSeqNum);
15812292SN/A            }
15822292SN/A        }
15832292SN/A
15842292SN/A        if (broadcast_free_entries) {
15852292SN/A            toFetch->iewInfo[tid].iqCount =
15862292SN/A                instQueue.getCount(tid);
15872292SN/A            toFetch->iewInfo[tid].ldstqCount =
15882292SN/A                ldstQueue.getCount(tid);
15892292SN/A
15902292SN/A            toRename->iewInfo[tid].usedIQ = true;
15912292SN/A            toRename->iewInfo[tid].freeIQEntries =
15922292SN/A                instQueue.numFreeEntries();
15932292SN/A            toRename->iewInfo[tid].usedLSQ = true;
15942292SN/A            toRename->iewInfo[tid].freeLSQEntries =
15952292SN/A                ldstQueue.numFreeEntries(tid);
15962292SN/A
15972292SN/A            wroteToTimeBuffer = true;
15982292SN/A        }
15992292SN/A
16002292SN/A        DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n",
16012292SN/A                tid, toRename->iewInfo[tid].dispatched);
16021061SN/A    }
16031061SN/A
16042292SN/A    DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i).  "
16052292SN/A            "LSQ has %i free entries.\n",
16062292SN/A            instQueue.numFreeEntries(), instQueue.hasReadyInsts(),
16072292SN/A            ldstQueue.numFreeEntries());
16082292SN/A
16092292SN/A    updateStatus();
16102292SN/A
16112292SN/A    if (wroteToTimeBuffer) {
16122292SN/A        DPRINTF(Activity, "Activity this cycle.\n");
16132292SN/A        cpu->activityThisCycle();
16141061SN/A    }
16151060SN/A}
16161060SN/A
16172301SN/Atemplate <class Impl>
16181060SN/Avoid
16192301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst)
16201060SN/A{
16216221Snate@binkert.org    ThreadID tid = inst->threadNumber;
16221060SN/A
16232301SN/A    //
16242301SN/A    //  Pick off the software prefetches
16252301SN/A    //
16262301SN/A#ifdef TARGET_ALPHA
16272301SN/A    if (inst->isDataPrefetch())
16286221Snate@binkert.org        iewExecutedSwp[tid]++;
16292301SN/A    else
16302727Sktlim@umich.edu        iewIewExecutedcutedInsts++;
16312301SN/A#else
16322669Sktlim@umich.edu    iewExecutedInsts++;
16332301SN/A#endif
16341060SN/A
16358471SGiacomo.Gabrielli@arm.com#if TRACING_ON
16368471SGiacomo.Gabrielli@arm.com    inst->completeTick = curTick();
16378471SGiacomo.Gabrielli@arm.com#endif
16388471SGiacomo.Gabrielli@arm.com
16392301SN/A    //
16402301SN/A    //  Control operations
16412301SN/A    //
16422301SN/A    if (inst->isControl())
16436221Snate@binkert.org        iewExecutedBranches[tid]++;
16441060SN/A
16452301SN/A    //
16462301SN/A    //  Memory operations
16472301SN/A    //
16482301SN/A    if (inst->isMemRef()) {
16496221Snate@binkert.org        iewExecutedRefs[tid]++;
16501060SN/A
16512301SN/A        if (inst->isLoad()) {
16526221Snate@binkert.org            iewExecLoadInsts[tid]++;
16531060SN/A        }
16541060SN/A    }
16551060SN/A}
16567598Sminkyu.jeong@arm.com
16577598Sminkyu.jeong@arm.comtemplate <class Impl>
16587598Sminkyu.jeong@arm.comvoid
16597598Sminkyu.jeong@arm.comDefaultIEW<Impl>::checkMisprediction(DynInstPtr &inst)
16607598Sminkyu.jeong@arm.com{
16617598Sminkyu.jeong@arm.com    ThreadID tid = inst->threadNumber;
16627598Sminkyu.jeong@arm.com
16637598Sminkyu.jeong@arm.com    if (!fetchRedirect[tid] ||
16647852SMatt.Horsnell@arm.com        !toCommit->squash[tid] ||
16657598Sminkyu.jeong@arm.com        toCommit->squashedSeqNum[tid] > inst->seqNum) {
16667598Sminkyu.jeong@arm.com
16677598Sminkyu.jeong@arm.com        if (inst->mispredicted()) {
16687598Sminkyu.jeong@arm.com            fetchRedirect[tid] = true;
16697598Sminkyu.jeong@arm.com
16707598Sminkyu.jeong@arm.com            DPRINTF(IEW, "Execute: Branch mispredict detected.\n");
16717598Sminkyu.jeong@arm.com            DPRINTF(IEW, "Predicted target was PC:%#x, NPC:%#x.\n",
16727720Sgblack@eecs.umich.edu                    inst->predInstAddr(), inst->predNextInstAddr());
16737598Sminkyu.jeong@arm.com            DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x,"
16747720Sgblack@eecs.umich.edu                    " NPC: %#x.\n", inst->nextInstAddr(),
16757720Sgblack@eecs.umich.edu                    inst->nextInstAddr());
16767598Sminkyu.jeong@arm.com            // If incorrect, then signal the ROB that it must be squashed.
16777598Sminkyu.jeong@arm.com            squashDueToBranch(inst, tid);
16787598Sminkyu.jeong@arm.com
16797598Sminkyu.jeong@arm.com            if (inst->readPredTaken()) {
16807598Sminkyu.jeong@arm.com                predictedTakenIncorrect++;
16817598Sminkyu.jeong@arm.com            } else {
16827598Sminkyu.jeong@arm.com                predictedNotTakenIncorrect++;
16837598Sminkyu.jeong@arm.com            }
16847598Sminkyu.jeong@arm.com        }
16857598Sminkyu.jeong@arm.com    }
16867598Sminkyu.jeong@arm.com}
1687