iew_impl.hh revision 4636
11689SN/A/* 22326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 31689SN/A * All rights reserved. 41689SN/A * 51689SN/A * Redistribution and use in source and binary forms, with or without 61689SN/A * modification, are permitted provided that the following conditions are 71689SN/A * met: redistributions of source code must retain the above copyright 81689SN/A * notice, this list of conditions and the following disclaimer; 91689SN/A * redistributions in binary form must reproduce the above copyright 101689SN/A * notice, this list of conditions and the following disclaimer in the 111689SN/A * documentation and/or other materials provided with the distribution; 121689SN/A * neither the name of the copyright holders nor the names of its 131689SN/A * contributors may be used to endorse or promote products derived from 141689SN/A * this software without specific prior written permission. 151689SN/A * 161689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 171689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 181689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 191689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 201689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 211689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 221689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 231689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 241689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 251689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 261689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 291689SN/A */ 301689SN/A 311060SN/A// @todo: Fix the instantaneous communication among all the stages within 321060SN/A// iew. There's a clear delay between issue and execute, yet backwards 331689SN/A// communication happens simultaneously. 341060SN/A 351060SN/A#include <queue> 361060SN/A 371060SN/A#include "base/timebuf.hh" 382292SN/A#include "cpu/o3/fu_pool.hh" 391717SN/A#include "cpu/o3/iew.hh" 401060SN/A 411681SN/Atemplate<class Impl> 424329Sktlim@umich.eduDefaultIEW<Impl>::DefaultIEW(O3CPU *_cpu, Params *params) 432873Sktlim@umich.edu : issueToExecQueue(params->backComSize, params->forwardComSize), 444329Sktlim@umich.edu cpu(_cpu), 454329Sktlim@umich.edu instQueue(_cpu, this, params), 464329Sktlim@umich.edu ldstQueue(_cpu, this, params), 472292SN/A fuPool(params->fuPool), 482292SN/A commitToIEWDelay(params->commitToIEWDelay), 492292SN/A renameToIEWDelay(params->renameToIEWDelay), 502292SN/A issueToExecuteDelay(params->issueToExecuteDelay), 512820Sktlim@umich.edu dispatchWidth(params->dispatchWidth), 522292SN/A issueWidth(params->issueWidth), 532820Sktlim@umich.edu wbOutstanding(0), 542820Sktlim@umich.edu wbWidth(params->wbWidth), 552307SN/A numThreads(params->numberOfThreads), 562307SN/A switchedOut(false) 571060SN/A{ 582292SN/A _status = Active; 592292SN/A exeStatus = Running; 602292SN/A wbStatus = Idle; 611060SN/A 621060SN/A // Setup wire to read instructions coming from issue. 631060SN/A fromIssue = issueToExecQueue.getWire(-issueToExecuteDelay); 641060SN/A 651060SN/A // Instruction queue needs the queue between issue and execute. 661060SN/A instQueue.setIssueToExecuteQueue(&issueToExecQueue); 671681SN/A 682292SN/A for (int i=0; i < numThreads; i++) { 692292SN/A dispatchStatus[i] = Running; 702292SN/A stalls[i].commit = false; 712292SN/A fetchRedirect[i] = false; 722292SN/A } 732292SN/A 742820Sktlim@umich.edu wbMax = wbWidth * params->wbDepth; 752820Sktlim@umich.edu 762292SN/A updateLSQNextCycle = false; 772292SN/A 782820Sktlim@umich.edu ableToIssue = true; 792820Sktlim@umich.edu 802292SN/A skidBufferMax = (3 * (renameToIEWDelay * params->renameWidth)) + issueWidth; 812292SN/A} 822292SN/A 832292SN/Atemplate <class Impl> 842292SN/Astd::string 852292SN/ADefaultIEW<Impl>::name() const 862292SN/A{ 872292SN/A return cpu->name() + ".iew"; 881060SN/A} 891060SN/A 901681SN/Atemplate <class Impl> 911062SN/Avoid 922292SN/ADefaultIEW<Impl>::regStats() 931062SN/A{ 942301SN/A using namespace Stats; 952301SN/A 961062SN/A instQueue.regStats(); 972727Sktlim@umich.edu ldstQueue.regStats(); 981062SN/A 991062SN/A iewIdleCycles 1001062SN/A .name(name() + ".iewIdleCycles") 1011062SN/A .desc("Number of cycles IEW is idle"); 1021062SN/A 1031062SN/A iewSquashCycles 1041062SN/A .name(name() + ".iewSquashCycles") 1051062SN/A .desc("Number of cycles IEW is squashing"); 1061062SN/A 1071062SN/A iewBlockCycles 1081062SN/A .name(name() + ".iewBlockCycles") 1091062SN/A .desc("Number of cycles IEW is blocking"); 1101062SN/A 1111062SN/A iewUnblockCycles 1121062SN/A .name(name() + ".iewUnblockCycles") 1131062SN/A .desc("Number of cycles IEW is unblocking"); 1141062SN/A 1151062SN/A iewDispatchedInsts 1161062SN/A .name(name() + ".iewDispatchedInsts") 1171062SN/A .desc("Number of instructions dispatched to IQ"); 1181062SN/A 1191062SN/A iewDispSquashedInsts 1201062SN/A .name(name() + ".iewDispSquashedInsts") 1211062SN/A .desc("Number of squashed instructions skipped by dispatch"); 1221062SN/A 1231062SN/A iewDispLoadInsts 1241062SN/A .name(name() + ".iewDispLoadInsts") 1251062SN/A .desc("Number of dispatched load instructions"); 1261062SN/A 1271062SN/A iewDispStoreInsts 1281062SN/A .name(name() + ".iewDispStoreInsts") 1291062SN/A .desc("Number of dispatched store instructions"); 1301062SN/A 1311062SN/A iewDispNonSpecInsts 1321062SN/A .name(name() + ".iewDispNonSpecInsts") 1331062SN/A .desc("Number of dispatched non-speculative instructions"); 1341062SN/A 1351062SN/A iewIQFullEvents 1361062SN/A .name(name() + ".iewIQFullEvents") 1371062SN/A .desc("Number of times the IQ has become full, causing a stall"); 1381062SN/A 1392292SN/A iewLSQFullEvents 1402292SN/A .name(name() + ".iewLSQFullEvents") 1412292SN/A .desc("Number of times the LSQ has become full, causing a stall"); 1422292SN/A 1431062SN/A memOrderViolationEvents 1441062SN/A .name(name() + ".memOrderViolationEvents") 1451062SN/A .desc("Number of memory order violations"); 1461062SN/A 1471062SN/A predictedTakenIncorrect 1481062SN/A .name(name() + ".predictedTakenIncorrect") 1491062SN/A .desc("Number of branches that were predicted taken incorrectly"); 1502292SN/A 1512292SN/A predictedNotTakenIncorrect 1522292SN/A .name(name() + ".predictedNotTakenIncorrect") 1532292SN/A .desc("Number of branches that were predicted not taken incorrectly"); 1542292SN/A 1552292SN/A branchMispredicts 1562292SN/A .name(name() + ".branchMispredicts") 1572292SN/A .desc("Number of branch mispredicts detected at execute"); 1582292SN/A 1592292SN/A branchMispredicts = predictedTakenIncorrect + predictedNotTakenIncorrect; 1602301SN/A 1612727Sktlim@umich.edu iewExecutedInsts 1622353SN/A .name(name() + ".iewExecutedInsts") 1632727Sktlim@umich.edu .desc("Number of executed instructions"); 1642727Sktlim@umich.edu 1652727Sktlim@umich.edu iewExecLoadInsts 1662727Sktlim@umich.edu .init(cpu->number_of_threads) 1672353SN/A .name(name() + ".iewExecLoadInsts") 1682727Sktlim@umich.edu .desc("Number of load instructions executed") 1692727Sktlim@umich.edu .flags(total); 1702727Sktlim@umich.edu 1712727Sktlim@umich.edu iewExecSquashedInsts 1722353SN/A .name(name() + ".iewExecSquashedInsts") 1732727Sktlim@umich.edu .desc("Number of squashed instructions skipped in execute"); 1742727Sktlim@umich.edu 1752727Sktlim@umich.edu iewExecutedSwp 1762301SN/A .init(cpu->number_of_threads) 1772301SN/A .name(name() + ".EXEC:swp") 1782301SN/A .desc("number of swp insts executed") 1792727Sktlim@umich.edu .flags(total); 1802301SN/A 1812727Sktlim@umich.edu iewExecutedNop 1822301SN/A .init(cpu->number_of_threads) 1832301SN/A .name(name() + ".EXEC:nop") 1842301SN/A .desc("number of nop insts executed") 1852727Sktlim@umich.edu .flags(total); 1862301SN/A 1872727Sktlim@umich.edu iewExecutedRefs 1882301SN/A .init(cpu->number_of_threads) 1892301SN/A .name(name() + ".EXEC:refs") 1902301SN/A .desc("number of memory reference insts executed") 1912727Sktlim@umich.edu .flags(total); 1922301SN/A 1932727Sktlim@umich.edu iewExecutedBranches 1942301SN/A .init(cpu->number_of_threads) 1952301SN/A .name(name() + ".EXEC:branches") 1962301SN/A .desc("Number of branches executed") 1972727Sktlim@umich.edu .flags(total); 1982301SN/A 1992301SN/A iewExecStoreInsts 2002301SN/A .name(name() + ".EXEC:stores") 2012301SN/A .desc("Number of stores executed") 2022727Sktlim@umich.edu .flags(total); 2032727Sktlim@umich.edu iewExecStoreInsts = iewExecutedRefs - iewExecLoadInsts; 2042727Sktlim@umich.edu 2052727Sktlim@umich.edu iewExecRate 2062727Sktlim@umich.edu .name(name() + ".EXEC:rate") 2072727Sktlim@umich.edu .desc("Inst execution rate") 2082727Sktlim@umich.edu .flags(total); 2092727Sktlim@umich.edu 2102727Sktlim@umich.edu iewExecRate = iewExecutedInsts / cpu->numCycles; 2112301SN/A 2122301SN/A iewInstsToCommit 2132301SN/A .init(cpu->number_of_threads) 2142301SN/A .name(name() + ".WB:sent") 2152301SN/A .desc("cumulative count of insts sent to commit") 2162727Sktlim@umich.edu .flags(total); 2172301SN/A 2182326SN/A writebackCount 2192301SN/A .init(cpu->number_of_threads) 2202301SN/A .name(name() + ".WB:count") 2212301SN/A .desc("cumulative count of insts written-back") 2222727Sktlim@umich.edu .flags(total); 2232301SN/A 2242326SN/A producerInst 2252301SN/A .init(cpu->number_of_threads) 2262301SN/A .name(name() + ".WB:producers") 2272301SN/A .desc("num instructions producing a value") 2282727Sktlim@umich.edu .flags(total); 2292301SN/A 2302326SN/A consumerInst 2312301SN/A .init(cpu->number_of_threads) 2322301SN/A .name(name() + ".WB:consumers") 2332301SN/A .desc("num instructions consuming a value") 2342727Sktlim@umich.edu .flags(total); 2352301SN/A 2362326SN/A wbPenalized 2372301SN/A .init(cpu->number_of_threads) 2382301SN/A .name(name() + ".WB:penalized") 2392301SN/A .desc("number of instrctions required to write to 'other' IQ") 2402727Sktlim@umich.edu .flags(total); 2412301SN/A 2422326SN/A wbPenalizedRate 2432301SN/A .name(name() + ".WB:penalized_rate") 2442301SN/A .desc ("fraction of instructions written-back that wrote to 'other' IQ") 2452727Sktlim@umich.edu .flags(total); 2462301SN/A 2472326SN/A wbPenalizedRate = wbPenalized / writebackCount; 2482301SN/A 2492326SN/A wbFanout 2502301SN/A .name(name() + ".WB:fanout") 2512301SN/A .desc("average fanout of values written-back") 2522727Sktlim@umich.edu .flags(total); 2532301SN/A 2542326SN/A wbFanout = producerInst / consumerInst; 2552301SN/A 2562326SN/A wbRate 2572301SN/A .name(name() + ".WB:rate") 2582301SN/A .desc("insts written-back per cycle") 2592727Sktlim@umich.edu .flags(total); 2602326SN/A wbRate = writebackCount / cpu->numCycles; 2611062SN/A} 2621062SN/A 2631681SN/Atemplate<class Impl> 2641060SN/Avoid 2652292SN/ADefaultIEW<Impl>::initStage() 2661060SN/A{ 2672292SN/A for (int tid=0; tid < numThreads; tid++) { 2682292SN/A toRename->iewInfo[tid].usedIQ = true; 2692292SN/A toRename->iewInfo[tid].freeIQEntries = 2702292SN/A instQueue.numFreeEntries(tid); 2712292SN/A 2722292SN/A toRename->iewInfo[tid].usedLSQ = true; 2732292SN/A toRename->iewInfo[tid].freeLSQEntries = 2742292SN/A ldstQueue.numFreeEntries(tid); 2752292SN/A } 2762292SN/A 2772733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 2781060SN/A} 2791060SN/A 2801681SN/Atemplate<class Impl> 2811060SN/Avoid 2822292SN/ADefaultIEW<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr) 2831060SN/A{ 2841060SN/A timeBuffer = tb_ptr; 2851060SN/A 2861060SN/A // Setup wire to read information from time buffer, from commit. 2871060SN/A fromCommit = timeBuffer->getWire(-commitToIEWDelay); 2881060SN/A 2891060SN/A // Setup wire to write information back to previous stages. 2901060SN/A toRename = timeBuffer->getWire(0); 2911060SN/A 2922292SN/A toFetch = timeBuffer->getWire(0); 2932292SN/A 2941060SN/A // Instruction queue also needs main time buffer. 2951060SN/A instQueue.setTimeBuffer(tb_ptr); 2961060SN/A} 2971060SN/A 2981681SN/Atemplate<class Impl> 2991060SN/Avoid 3002292SN/ADefaultIEW<Impl>::setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr) 3011060SN/A{ 3021060SN/A renameQueue = rq_ptr; 3031060SN/A 3041060SN/A // Setup wire to read information from rename queue. 3051060SN/A fromRename = renameQueue->getWire(-renameToIEWDelay); 3061060SN/A} 3071060SN/A 3081681SN/Atemplate<class Impl> 3091060SN/Avoid 3102292SN/ADefaultIEW<Impl>::setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr) 3111060SN/A{ 3121060SN/A iewQueue = iq_ptr; 3131060SN/A 3141060SN/A // Setup wire to write instructions to commit. 3151060SN/A toCommit = iewQueue->getWire(0); 3161060SN/A} 3171060SN/A 3181681SN/Atemplate<class Impl> 3191060SN/Avoid 3202980Sgblack@eecs.umich.eduDefaultIEW<Impl>::setActiveThreads(std::list<unsigned> *at_ptr) 3211060SN/A{ 3222292SN/A activeThreads = at_ptr; 3232292SN/A 3242292SN/A ldstQueue.setActiveThreads(at_ptr); 3252292SN/A instQueue.setActiveThreads(at_ptr); 3261060SN/A} 3271060SN/A 3281681SN/Atemplate<class Impl> 3291060SN/Avoid 3302292SN/ADefaultIEW<Impl>::setScoreboard(Scoreboard *sb_ptr) 3311060SN/A{ 3322292SN/A scoreboard = sb_ptr; 3331060SN/A} 3341060SN/A 3352307SN/Atemplate <class Impl> 3362863Sktlim@umich.edubool 3372843Sktlim@umich.eduDefaultIEW<Impl>::drain() 3382307SN/A{ 3392843Sktlim@umich.edu // IEW is ready to drain at any time. 3402843Sktlim@umich.edu cpu->signalDrained(); 3412863Sktlim@umich.edu return true; 3421681SN/A} 3431681SN/A 3442316SN/Atemplate <class Impl> 3451681SN/Avoid 3462843Sktlim@umich.eduDefaultIEW<Impl>::resume() 3472843Sktlim@umich.edu{ 3482843Sktlim@umich.edu} 3492843Sktlim@umich.edu 3502843Sktlim@umich.edutemplate <class Impl> 3512843Sktlim@umich.eduvoid 3522843Sktlim@umich.eduDefaultIEW<Impl>::switchOut() 3531681SN/A{ 3542348SN/A // Clear any state. 3552307SN/A switchedOut = true; 3562367SN/A assert(insts[0].empty()); 3572367SN/A assert(skidBuffer[0].empty()); 3581681SN/A 3592307SN/A instQueue.switchOut(); 3602307SN/A ldstQueue.switchOut(); 3612307SN/A fuPool->switchOut(); 3622307SN/A 3632307SN/A for (int i = 0; i < numThreads; i++) { 3642307SN/A while (!insts[i].empty()) 3652307SN/A insts[i].pop(); 3662307SN/A while (!skidBuffer[i].empty()) 3672307SN/A skidBuffer[i].pop(); 3682307SN/A } 3691681SN/A} 3701681SN/A 3712307SN/Atemplate <class Impl> 3721681SN/Avoid 3732307SN/ADefaultIEW<Impl>::takeOverFrom() 3741060SN/A{ 3752348SN/A // Reset all state. 3762307SN/A _status = Active; 3772307SN/A exeStatus = Running; 3782307SN/A wbStatus = Idle; 3792307SN/A switchedOut = false; 3801060SN/A 3812307SN/A instQueue.takeOverFrom(); 3822307SN/A ldstQueue.takeOverFrom(); 3832307SN/A fuPool->takeOverFrom(); 3841060SN/A 3852307SN/A initStage(); 3862307SN/A cpu->activityThisCycle(); 3871060SN/A 3882307SN/A for (int i=0; i < numThreads; i++) { 3892307SN/A dispatchStatus[i] = Running; 3902307SN/A stalls[i].commit = false; 3912307SN/A fetchRedirect[i] = false; 3922307SN/A } 3931060SN/A 3942307SN/A updateLSQNextCycle = false; 3952307SN/A 3962873Sktlim@umich.edu for (int i = 0; i < issueToExecQueue.getSize(); ++i) { 3972307SN/A issueToExecQueue.advance(); 3981060SN/A } 3991060SN/A} 4001060SN/A 4011681SN/Atemplate<class Impl> 4021060SN/Avoid 4032292SN/ADefaultIEW<Impl>::squash(unsigned tid) 4042107SN/A{ 4052292SN/A DPRINTF(IEW, "[tid:%i]: Squashing all instructions.\n", 4062292SN/A tid); 4072107SN/A 4082292SN/A // Tell the IQ to start squashing. 4092292SN/A instQueue.squash(tid); 4102107SN/A 4112292SN/A // Tell the LDSTQ to start squashing. 4122326SN/A ldstQueue.squash(fromCommit->commitInfo[tid].doneSeqNum, tid); 4132292SN/A updatedQueues = true; 4142107SN/A 4152292SN/A // Clear the skid buffer in case it has any data in it. 4162935Sksewell@umich.edu DPRINTF(IEW, "[tid:%i]: Removing skidbuffer instructions until [sn:%i].\n", 4174632Sgblack@eecs.umich.edu tid, fromCommit->commitInfo[tid].doneSeqNum); 4182935Sksewell@umich.edu 4192292SN/A while (!skidBuffer[tid].empty()) { 4202292SN/A if (skidBuffer[tid].front()->isLoad() || 4212292SN/A skidBuffer[tid].front()->isStore() ) { 4222292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 4232292SN/A } 4242107SN/A 4252292SN/A toRename->iewInfo[tid].dispatched++; 4262107SN/A 4272292SN/A skidBuffer[tid].pop(); 4282292SN/A } 4292107SN/A 4302702Sktlim@umich.edu emptyRenameInsts(tid); 4312107SN/A} 4322107SN/A 4332107SN/Atemplate<class Impl> 4342107SN/Avoid 4352292SN/ADefaultIEW<Impl>::squashDueToBranch(DynInstPtr &inst, unsigned tid) 4362292SN/A{ 4372292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, PC: %#x " 4382292SN/A "[sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4392292SN/A 4402292SN/A toCommit->squash[tid] = true; 4412292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4422292SN/A toCommit->mispredPC[tid] = inst->readPC(); 4432292SN/A toCommit->branchMispredict[tid] = true; 4442935Sksewell@umich.edu 4454632Sgblack@eecs.umich.edu#if ISA_HAS_DELAY_SLOT 4463969Sgblack@eecs.umich.edu int instSize = sizeof(TheISA::MachInst); 4474632Sgblack@eecs.umich.edu toCommit->branchTaken[tid] = 4483795Sgblack@eecs.umich.edu !(inst->readNextPC() + instSize == inst->readNextNPC() && 4493795Sgblack@eecs.umich.edu (inst->readNextPC() == inst->readPC() + instSize || 4503795Sgblack@eecs.umich.edu inst->readNextPC() == inst->readPC() + 2 * instSize)); 4513093Sksewell@umich.edu#else 4523093Sksewell@umich.edu toCommit->branchTaken[tid] = inst->readNextPC() != 4533093Sksewell@umich.edu (inst->readPC() + sizeof(TheISA::MachInst)); 4544632Sgblack@eecs.umich.edu#endif 4553093Sksewell@umich.edu toCommit->nextPC[tid] = inst->readNextPC(); 4564632Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextNPC(); 4574636Sgblack@eecs.umich.edu toCommit->nextMicroPC[tid] = inst->readNextMicroPC(); 4582292SN/A 4592292SN/A toCommit->includeSquashInst[tid] = false; 4602292SN/A 4612292SN/A wroteToTimeBuffer = true; 4622292SN/A} 4632292SN/A 4642292SN/Atemplate<class Impl> 4652292SN/Avoid 4662292SN/ADefaultIEW<Impl>::squashDueToMemOrder(DynInstPtr &inst, unsigned tid) 4672292SN/A{ 4682292SN/A DPRINTF(IEW, "[tid:%i]: Squashing from a specific instruction, " 4692292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4702292SN/A 4712292SN/A toCommit->squash[tid] = true; 4722292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4732292SN/A toCommit->nextPC[tid] = inst->readNextPC(); 4743795Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextNPC(); 4753732Sktlim@umich.edu toCommit->branchMispredict[tid] = false; 4762292SN/A 4772292SN/A toCommit->includeSquashInst[tid] = false; 4782292SN/A 4792292SN/A wroteToTimeBuffer = true; 4802292SN/A} 4812292SN/A 4822292SN/Atemplate<class Impl> 4832292SN/Avoid 4842292SN/ADefaultIEW<Impl>::squashDueToMemBlocked(DynInstPtr &inst, unsigned tid) 4852292SN/A{ 4862292SN/A DPRINTF(IEW, "[tid:%i]: Memory blocked, squashing load and younger insts, " 4872292SN/A "PC: %#x [sn:%i].\n", tid, inst->readPC(), inst->seqNum); 4882292SN/A 4892292SN/A toCommit->squash[tid] = true; 4902292SN/A toCommit->squashedSeqNum[tid] = inst->seqNum; 4912292SN/A toCommit->nextPC[tid] = inst->readPC(); 4923958Sgblack@eecs.umich.edu toCommit->nextNPC[tid] = inst->readNextPC(); 4933732Sktlim@umich.edu toCommit->branchMispredict[tid] = false; 4942292SN/A 4952348SN/A // Must include the broadcasted SN in the squash. 4962292SN/A toCommit->includeSquashInst[tid] = true; 4972292SN/A 4982292SN/A ldstQueue.setLoadBlockedHandled(tid); 4992292SN/A 5002292SN/A wroteToTimeBuffer = true; 5012292SN/A} 5022292SN/A 5032292SN/Atemplate<class Impl> 5042292SN/Avoid 5052292SN/ADefaultIEW<Impl>::block(unsigned tid) 5062292SN/A{ 5072292SN/A DPRINTF(IEW, "[tid:%u]: Blocking.\n", tid); 5082292SN/A 5092292SN/A if (dispatchStatus[tid] != Blocked && 5102292SN/A dispatchStatus[tid] != Unblocking) { 5112292SN/A toRename->iewBlock[tid] = true; 5122292SN/A wroteToTimeBuffer = true; 5132292SN/A } 5142292SN/A 5152292SN/A // Add the current inputs to the skid buffer so they can be 5162292SN/A // reprocessed when this stage unblocks. 5172292SN/A skidInsert(tid); 5182292SN/A 5192292SN/A dispatchStatus[tid] = Blocked; 5202292SN/A} 5212292SN/A 5222292SN/Atemplate<class Impl> 5232292SN/Avoid 5242292SN/ADefaultIEW<Impl>::unblock(unsigned tid) 5252292SN/A{ 5262292SN/A DPRINTF(IEW, "[tid:%i]: Reading instructions out of the skid " 5272292SN/A "buffer %u.\n",tid, tid); 5282292SN/A 5292292SN/A // If the skid bufffer is empty, signal back to previous stages to unblock. 5302292SN/A // Also switch status to running. 5312292SN/A if (skidBuffer[tid].empty()) { 5322292SN/A toRename->iewUnblock[tid] = true; 5332292SN/A wroteToTimeBuffer = true; 5342292SN/A DPRINTF(IEW, "[tid:%i]: Done unblocking.\n",tid); 5352292SN/A dispatchStatus[tid] = Running; 5362292SN/A } 5372292SN/A} 5382292SN/A 5392292SN/Atemplate<class Impl> 5402292SN/Avoid 5412292SN/ADefaultIEW<Impl>::wakeDependents(DynInstPtr &inst) 5421060SN/A{ 5431681SN/A instQueue.wakeDependents(inst); 5441060SN/A} 5451060SN/A 5462292SN/Atemplate<class Impl> 5472292SN/Avoid 5482292SN/ADefaultIEW<Impl>::rescheduleMemInst(DynInstPtr &inst) 5492292SN/A{ 5502292SN/A instQueue.rescheduleMemInst(inst); 5512292SN/A} 5521681SN/A 5531681SN/Atemplate<class Impl> 5541060SN/Avoid 5552292SN/ADefaultIEW<Impl>::replayMemInst(DynInstPtr &inst) 5561060SN/A{ 5572292SN/A instQueue.replayMemInst(inst); 5582292SN/A} 5591060SN/A 5602292SN/Atemplate<class Impl> 5612292SN/Avoid 5622292SN/ADefaultIEW<Impl>::instToCommit(DynInstPtr &inst) 5632292SN/A{ 5643221Sktlim@umich.edu // This function should not be called after writebackInsts in a 5653221Sktlim@umich.edu // single cycle. That will cause problems with an instruction 5663221Sktlim@umich.edu // being added to the queue to commit without being processed by 5673221Sktlim@umich.edu // writebackInsts prior to being sent to commit. 5683221Sktlim@umich.edu 5692292SN/A // First check the time slot that this instruction will write 5702292SN/A // to. If there are free write ports at the time, then go ahead 5712292SN/A // and write the instruction to that time. If there are not, 5722292SN/A // keep looking back to see where's the first time there's a 5732326SN/A // free slot. 5742292SN/A while ((*iewQueue)[wbCycle].insts[wbNumInst]) { 5752292SN/A ++wbNumInst; 5762820Sktlim@umich.edu if (wbNumInst == wbWidth) { 5772292SN/A ++wbCycle; 5782292SN/A wbNumInst = 0; 5792292SN/A } 5802292SN/A 5812353SN/A assert((wbCycle * wbWidth + wbNumInst) <= wbMax); 5822292SN/A } 5832292SN/A 5842353SN/A DPRINTF(IEW, "Current wb cycle: %i, width: %i, numInst: %i\nwbActual:%i\n", 5852353SN/A wbCycle, wbWidth, wbNumInst, wbCycle * wbWidth + wbNumInst); 5862292SN/A // Add finished instruction to queue to commit. 5872292SN/A (*iewQueue)[wbCycle].insts[wbNumInst] = inst; 5882292SN/A (*iewQueue)[wbCycle].size++; 5892292SN/A} 5902292SN/A 5912292SN/Atemplate <class Impl> 5922292SN/Aunsigned 5932292SN/ADefaultIEW<Impl>::validInstsFromRename() 5942292SN/A{ 5952292SN/A unsigned inst_count = 0; 5962292SN/A 5972292SN/A for (int i=0; i<fromRename->size; i++) { 5982731Sktlim@umich.edu if (!fromRename->insts[i]->isSquashed()) 5992292SN/A inst_count++; 6002292SN/A } 6012292SN/A 6022292SN/A return inst_count; 6032292SN/A} 6042292SN/A 6052292SN/Atemplate<class Impl> 6062292SN/Avoid 6072292SN/ADefaultIEW<Impl>::skidInsert(unsigned tid) 6082292SN/A{ 6092292SN/A DynInstPtr inst = NULL; 6102292SN/A 6112292SN/A while (!insts[tid].empty()) { 6122292SN/A inst = insts[tid].front(); 6132292SN/A 6142292SN/A insts[tid].pop(); 6152292SN/A 6162292SN/A DPRINTF(Decode,"[tid:%i]: Inserting [sn:%lli] PC:%#x into " 6172292SN/A "dispatch skidBuffer %i\n",tid, inst->seqNum, 6182292SN/A inst->readPC(),tid); 6192292SN/A 6202292SN/A skidBuffer[tid].push(inst); 6212292SN/A } 6222292SN/A 6232292SN/A assert(skidBuffer[tid].size() <= skidBufferMax && 6242292SN/A "Skidbuffer Exceeded Max Size"); 6252292SN/A} 6262292SN/A 6272292SN/Atemplate<class Impl> 6282292SN/Aint 6292292SN/ADefaultIEW<Impl>::skidCount() 6302292SN/A{ 6312292SN/A int max=0; 6322292SN/A 6333867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 6343867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 6352292SN/A 6363867Sbinkertn@umich.edu while (threads != end) { 6373867Sbinkertn@umich.edu unsigned tid = *threads++; 6383867Sbinkertn@umich.edu unsigned thread_count = skidBuffer[tid].size(); 6392292SN/A if (max < thread_count) 6402292SN/A max = thread_count; 6412292SN/A } 6422292SN/A 6432292SN/A return max; 6442292SN/A} 6452292SN/A 6462292SN/Atemplate<class Impl> 6472292SN/Abool 6482292SN/ADefaultIEW<Impl>::skidsEmpty() 6492292SN/A{ 6503867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 6513867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 6522292SN/A 6533867Sbinkertn@umich.edu while (threads != end) { 6543867Sbinkertn@umich.edu unsigned tid = *threads++; 6553867Sbinkertn@umich.edu 6563867Sbinkertn@umich.edu if (!skidBuffer[tid].empty()) 6572292SN/A return false; 6582292SN/A } 6592292SN/A 6602292SN/A return true; 6611062SN/A} 6621062SN/A 6631681SN/Atemplate <class Impl> 6641062SN/Avoid 6652292SN/ADefaultIEW<Impl>::updateStatus() 6661062SN/A{ 6672292SN/A bool any_unblocking = false; 6681062SN/A 6693867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 6703867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 6711062SN/A 6723867Sbinkertn@umich.edu while (threads != end) { 6732292SN/A unsigned tid = *threads++; 6741062SN/A 6752292SN/A if (dispatchStatus[tid] == Unblocking) { 6762292SN/A any_unblocking = true; 6772292SN/A break; 6782292SN/A } 6792292SN/A } 6801062SN/A 6812292SN/A // If there are no ready instructions waiting to be scheduled by the IQ, 6822292SN/A // and there's no stores waiting to write back, and dispatch is not 6832292SN/A // unblocking, then there is no internal activity for the IEW stage. 6842292SN/A if (_status == Active && !instQueue.hasReadyInsts() && 6852292SN/A !ldstQueue.willWB() && !any_unblocking) { 6862292SN/A DPRINTF(IEW, "IEW switching to idle\n"); 6871062SN/A 6882292SN/A deactivateStage(); 6891062SN/A 6902292SN/A _status = Inactive; 6912292SN/A } else if (_status == Inactive && (instQueue.hasReadyInsts() || 6922292SN/A ldstQueue.willWB() || 6932292SN/A any_unblocking)) { 6942292SN/A // Otherwise there is internal activity. Set to active. 6952292SN/A DPRINTF(IEW, "IEW switching to active\n"); 6961062SN/A 6972292SN/A activateStage(); 6981062SN/A 6992292SN/A _status = Active; 7001062SN/A } 7011062SN/A} 7021062SN/A 7031681SN/Atemplate <class Impl> 7041062SN/Avoid 7052292SN/ADefaultIEW<Impl>::resetEntries() 7061062SN/A{ 7072292SN/A instQueue.resetEntries(); 7082292SN/A ldstQueue.resetEntries(); 7092292SN/A} 7101062SN/A 7112292SN/Atemplate <class Impl> 7122292SN/Avoid 7132292SN/ADefaultIEW<Impl>::readStallSignals(unsigned tid) 7142292SN/A{ 7152292SN/A if (fromCommit->commitBlock[tid]) { 7162292SN/A stalls[tid].commit = true; 7172292SN/A } 7181062SN/A 7192292SN/A if (fromCommit->commitUnblock[tid]) { 7202292SN/A assert(stalls[tid].commit); 7212292SN/A stalls[tid].commit = false; 7222292SN/A } 7232292SN/A} 7242292SN/A 7252292SN/Atemplate <class Impl> 7262292SN/Abool 7272292SN/ADefaultIEW<Impl>::checkStall(unsigned tid) 7282292SN/A{ 7292292SN/A bool ret_val(false); 7302292SN/A 7312292SN/A if (stalls[tid].commit) { 7322292SN/A DPRINTF(IEW,"[tid:%i]: Stall from Commit stage detected.\n",tid); 7332292SN/A ret_val = true; 7342292SN/A } else if (instQueue.isFull(tid)) { 7352292SN/A DPRINTF(IEW,"[tid:%i]: Stall: IQ is full.\n",tid); 7362292SN/A ret_val = true; 7372292SN/A } else if (ldstQueue.isFull(tid)) { 7382292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ is full\n",tid); 7392292SN/A 7402292SN/A if (ldstQueue.numLoads(tid) > 0 ) { 7412292SN/A 7422292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest load: [sn:%i] \n", 7432292SN/A tid,ldstQueue.getLoadHeadSeqNum(tid)); 7442292SN/A } 7452292SN/A 7462292SN/A if (ldstQueue.numStores(tid) > 0) { 7472292SN/A 7482292SN/A DPRINTF(IEW,"[tid:%i]: LSQ oldest store: [sn:%i] \n", 7492292SN/A tid,ldstQueue.getStoreHeadSeqNum(tid)); 7502292SN/A } 7512292SN/A 7522292SN/A ret_val = true; 7532292SN/A } else if (ldstQueue.isStalled(tid)) { 7542292SN/A DPRINTF(IEW,"[tid:%i]: Stall: LSQ stall detected.\n",tid); 7552292SN/A ret_val = true; 7562292SN/A } 7572292SN/A 7582292SN/A return ret_val; 7592292SN/A} 7602292SN/A 7612292SN/Atemplate <class Impl> 7622292SN/Avoid 7632292SN/ADefaultIEW<Impl>::checkSignalsAndUpdate(unsigned tid) 7642292SN/A{ 7652292SN/A // Check if there's a squash signal, squash if there is 7662292SN/A // Check stall signals, block if there is. 7672292SN/A // If status was Blocked 7682292SN/A // if so then go to unblocking 7692292SN/A // If status was Squashing 7702292SN/A // check if squashing is not high. Switch to running this cycle. 7712292SN/A 7722292SN/A readStallSignals(tid); 7732292SN/A 7742292SN/A if (fromCommit->commitInfo[tid].squash) { 7752292SN/A squash(tid); 7762292SN/A 7772292SN/A if (dispatchStatus[tid] == Blocked || 7782292SN/A dispatchStatus[tid] == Unblocking) { 7792292SN/A toRename->iewUnblock[tid] = true; 7802292SN/A wroteToTimeBuffer = true; 7812292SN/A } 7822292SN/A 7832292SN/A dispatchStatus[tid] = Squashing; 7842292SN/A 7852292SN/A fetchRedirect[tid] = false; 7862292SN/A return; 7872292SN/A } 7882292SN/A 7892292SN/A if (fromCommit->commitInfo[tid].robSquashing) { 7902702Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: ROB is still squashing.\n", tid); 7912292SN/A 7922292SN/A dispatchStatus[tid] = Squashing; 7932292SN/A 7942702Sktlim@umich.edu emptyRenameInsts(tid); 7952702Sktlim@umich.edu wroteToTimeBuffer = true; 7962292SN/A return; 7972292SN/A } 7982292SN/A 7992292SN/A if (checkStall(tid)) { 8002292SN/A block(tid); 8012292SN/A dispatchStatus[tid] = Blocked; 8022292SN/A return; 8032292SN/A } 8042292SN/A 8052292SN/A if (dispatchStatus[tid] == Blocked) { 8062292SN/A // Status from previous cycle was blocked, but there are no more stall 8072292SN/A // conditions. Switch over to unblocking. 8082292SN/A DPRINTF(IEW, "[tid:%i]: Done blocking, switching to unblocking.\n", 8092292SN/A tid); 8102292SN/A 8112292SN/A dispatchStatus[tid] = Unblocking; 8122292SN/A 8132292SN/A unblock(tid); 8142292SN/A 8152292SN/A return; 8162292SN/A } 8172292SN/A 8182292SN/A if (dispatchStatus[tid] == Squashing) { 8192292SN/A // Switch status to running if rename isn't being told to block or 8202292SN/A // squash this cycle. 8212292SN/A DPRINTF(IEW, "[tid:%i]: Done squashing, switching to running.\n", 8222292SN/A tid); 8232292SN/A 8242292SN/A dispatchStatus[tid] = Running; 8252292SN/A 8262292SN/A return; 8272292SN/A } 8282292SN/A} 8292292SN/A 8302292SN/Atemplate <class Impl> 8312292SN/Avoid 8322292SN/ADefaultIEW<Impl>::sortInsts() 8332292SN/A{ 8342292SN/A int insts_from_rename = fromRename->size; 8352326SN/A#ifdef DEBUG 8362292SN/A for (int i = 0; i < numThreads; i++) 8372292SN/A assert(insts[i].empty()); 8382326SN/A#endif 8392292SN/A for (int i = 0; i < insts_from_rename; ++i) { 8402292SN/A insts[fromRename->insts[i]->threadNumber].push(fromRename->insts[i]); 8412292SN/A } 8422292SN/A} 8432292SN/A 8442292SN/Atemplate <class Impl> 8452292SN/Avoid 8462702Sktlim@umich.eduDefaultIEW<Impl>::emptyRenameInsts(unsigned tid) 8472702Sktlim@umich.edu{ 8484632Sgblack@eecs.umich.edu DPRINTF(IEW, "[tid:%i]: Removing incoming rename instructions\n", tid); 8492935Sksewell@umich.edu 8502702Sktlim@umich.edu while (!insts[tid].empty()) { 8512935Sksewell@umich.edu 8522702Sktlim@umich.edu if (insts[tid].front()->isLoad() || 8532702Sktlim@umich.edu insts[tid].front()->isStore() ) { 8542702Sktlim@umich.edu toRename->iewInfo[tid].dispatchedToLSQ++; 8552702Sktlim@umich.edu } 8562702Sktlim@umich.edu 8572702Sktlim@umich.edu toRename->iewInfo[tid].dispatched++; 8582702Sktlim@umich.edu 8592702Sktlim@umich.edu insts[tid].pop(); 8602702Sktlim@umich.edu } 8612702Sktlim@umich.edu} 8622702Sktlim@umich.edu 8632702Sktlim@umich.edutemplate <class Impl> 8642702Sktlim@umich.eduvoid 8652292SN/ADefaultIEW<Impl>::wakeCPU() 8662292SN/A{ 8672292SN/A cpu->wakeCPU(); 8682292SN/A} 8692292SN/A 8702292SN/Atemplate <class Impl> 8712292SN/Avoid 8722292SN/ADefaultIEW<Impl>::activityThisCycle() 8732292SN/A{ 8742292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 8752292SN/A cpu->activityThisCycle(); 8762292SN/A} 8772292SN/A 8782292SN/Atemplate <class Impl> 8792292SN/Ainline void 8802292SN/ADefaultIEW<Impl>::activateStage() 8812292SN/A{ 8822292SN/A DPRINTF(Activity, "Activating stage.\n"); 8832733Sktlim@umich.edu cpu->activateStage(O3CPU::IEWIdx); 8842292SN/A} 8852292SN/A 8862292SN/Atemplate <class Impl> 8872292SN/Ainline void 8882292SN/ADefaultIEW<Impl>::deactivateStage() 8892292SN/A{ 8902292SN/A DPRINTF(Activity, "Deactivating stage.\n"); 8912733Sktlim@umich.edu cpu->deactivateStage(O3CPU::IEWIdx); 8922292SN/A} 8932292SN/A 8942292SN/Atemplate<class Impl> 8952292SN/Avoid 8962292SN/ADefaultIEW<Impl>::dispatch(unsigned tid) 8972292SN/A{ 8982292SN/A // If status is Running or idle, 8992292SN/A // call dispatchInsts() 9002292SN/A // If status is Unblocking, 9012292SN/A // buffer any instructions coming from rename 9022292SN/A // continue trying to empty skid buffer 9032292SN/A // check if stall conditions have passed 9042292SN/A 9052292SN/A if (dispatchStatus[tid] == Blocked) { 9062292SN/A ++iewBlockCycles; 9072292SN/A 9082292SN/A } else if (dispatchStatus[tid] == Squashing) { 9092292SN/A ++iewSquashCycles; 9102292SN/A } 9112292SN/A 9122292SN/A // Dispatch should try to dispatch as many instructions as its bandwidth 9132292SN/A // will allow, as long as it is not currently blocked. 9142292SN/A if (dispatchStatus[tid] == Running || 9152292SN/A dispatchStatus[tid] == Idle) { 9162292SN/A DPRINTF(IEW, "[tid:%i] Not blocked, so attempting to run " 9172292SN/A "dispatch.\n", tid); 9182292SN/A 9192292SN/A dispatchInsts(tid); 9202292SN/A } else if (dispatchStatus[tid] == Unblocking) { 9212292SN/A // Make sure that the skid buffer has something in it if the 9222292SN/A // status is unblocking. 9232292SN/A assert(!skidsEmpty()); 9242292SN/A 9252292SN/A // If the status was unblocking, then instructions from the skid 9262292SN/A // buffer were used. Remove those instructions and handle 9272292SN/A // the rest of unblocking. 9282292SN/A dispatchInsts(tid); 9292292SN/A 9302292SN/A ++iewUnblockCycles; 9312292SN/A 9322292SN/A if (validInstsFromRename() && dispatchedAllInsts) { 9332292SN/A // Add the current inputs to the skid buffer so they can be 9342292SN/A // reprocessed when this stage unblocks. 9352292SN/A skidInsert(tid); 9362292SN/A } 9372292SN/A 9382292SN/A unblock(tid); 9392292SN/A } 9402292SN/A} 9412292SN/A 9422292SN/Atemplate <class Impl> 9432292SN/Avoid 9442292SN/ADefaultIEW<Impl>::dispatchInsts(unsigned tid) 9452292SN/A{ 9462292SN/A dispatchedAllInsts = true; 9472292SN/A 9482292SN/A // Obtain instructions from skid buffer if unblocking, or queue from rename 9492292SN/A // otherwise. 9502292SN/A std::queue<DynInstPtr> &insts_to_dispatch = 9512292SN/A dispatchStatus[tid] == Unblocking ? 9522292SN/A skidBuffer[tid] : insts[tid]; 9532292SN/A 9542292SN/A int insts_to_add = insts_to_dispatch.size(); 9552292SN/A 9562292SN/A DynInstPtr inst; 9572292SN/A bool add_to_iq = false; 9582292SN/A int dis_num_inst = 0; 9592292SN/A 9602292SN/A // Loop through the instructions, putting them in the instruction 9612292SN/A // queue. 9622292SN/A for ( ; dis_num_inst < insts_to_add && 9632820Sktlim@umich.edu dis_num_inst < dispatchWidth; 9642292SN/A ++dis_num_inst) 9652292SN/A { 9662292SN/A inst = insts_to_dispatch.front(); 9672292SN/A 9682292SN/A if (dispatchStatus[tid] == Unblocking) { 9692292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Examining instruction from skid " 9702292SN/A "buffer\n", tid); 9712292SN/A } 9722292SN/A 9732292SN/A // Make sure there's a valid instruction there. 9742292SN/A assert(inst); 9752292SN/A 9762292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Adding PC %#x [sn:%lli] [tid:%i] to " 9772292SN/A "IQ.\n", 9782292SN/A tid, inst->readPC(), inst->seqNum, inst->threadNumber); 9792292SN/A 9802292SN/A // Be sure to mark these instructions as ready so that the 9812292SN/A // commit stage can go ahead and execute them, and mark 9822292SN/A // them as issued so the IQ doesn't reprocess them. 9832292SN/A 9842292SN/A // Check for squashed instructions. 9852292SN/A if (inst->isSquashed()) { 9862292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Squashed instruction encountered, " 9872292SN/A "not adding to IQ.\n", tid); 9882292SN/A 9892292SN/A ++iewDispSquashedInsts; 9902292SN/A 9912292SN/A insts_to_dispatch.pop(); 9922292SN/A 9932292SN/A //Tell Rename That An Instruction has been processed 9942292SN/A if (inst->isLoad() || inst->isStore()) { 9952292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 9962292SN/A } 9972292SN/A toRename->iewInfo[tid].dispatched++; 9982292SN/A 9992292SN/A continue; 10002292SN/A } 10012292SN/A 10022292SN/A // Check for full conditions. 10032292SN/A if (instQueue.isFull(tid)) { 10042292SN/A DPRINTF(IEW, "[tid:%i]: Issue: IQ has become full.\n", tid); 10052292SN/A 10062292SN/A // Call function to start blocking. 10072292SN/A block(tid); 10082292SN/A 10092292SN/A // Set unblock to false. Special case where we are using 10102292SN/A // skidbuffer (unblocking) instructions but then we still 10112292SN/A // get full in the IQ. 10122292SN/A toRename->iewUnblock[tid] = false; 10132292SN/A 10142292SN/A dispatchedAllInsts = false; 10152292SN/A 10162292SN/A ++iewIQFullEvents; 10172292SN/A break; 10182292SN/A } else if (ldstQueue.isFull(tid)) { 10192292SN/A DPRINTF(IEW, "[tid:%i]: Issue: LSQ has become full.\n",tid); 10202292SN/A 10212292SN/A // Call function to start blocking. 10222292SN/A block(tid); 10232292SN/A 10242292SN/A // Set unblock to false. Special case where we are using 10252292SN/A // skidbuffer (unblocking) instructions but then we still 10262292SN/A // get full in the IQ. 10272292SN/A toRename->iewUnblock[tid] = false; 10282292SN/A 10292292SN/A dispatchedAllInsts = false; 10302292SN/A 10312292SN/A ++iewLSQFullEvents; 10322292SN/A break; 10332292SN/A } 10342292SN/A 10352292SN/A // Otherwise issue the instruction just fine. 10362292SN/A if (inst->isLoad()) { 10372292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10382292SN/A "encountered, adding to LSQ.\n", tid); 10392292SN/A 10402292SN/A // Reserve a spot in the load store queue for this 10412292SN/A // memory access. 10422292SN/A ldstQueue.insertLoad(inst); 10432292SN/A 10442292SN/A ++iewDispLoadInsts; 10452292SN/A 10462292SN/A add_to_iq = true; 10472292SN/A 10482292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10492292SN/A } else if (inst->isStore()) { 10502292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Memory instruction " 10512292SN/A "encountered, adding to LSQ.\n", tid); 10522292SN/A 10532292SN/A ldstQueue.insertStore(inst); 10542292SN/A 10552292SN/A ++iewDispStoreInsts; 10562292SN/A 10572336SN/A if (inst->isStoreConditional()) { 10582336SN/A // Store conditionals need to be set as "canCommit()" 10592336SN/A // so that commit can process them when they reach the 10602336SN/A // head of commit. 10612348SN/A // @todo: This is somewhat specific to Alpha. 10622292SN/A inst->setCanCommit(); 10632292SN/A instQueue.insertNonSpec(inst); 10642292SN/A add_to_iq = false; 10652292SN/A 10662292SN/A ++iewDispNonSpecInsts; 10672292SN/A } else { 10682292SN/A add_to_iq = true; 10692292SN/A } 10702292SN/A 10712292SN/A toRename->iewInfo[tid].dispatchedToLSQ++; 10722292SN/A } else if (inst->isMemBarrier() || inst->isWriteBarrier()) { 10732326SN/A // Same as non-speculative stores. 10742292SN/A inst->setCanCommit(); 10752292SN/A instQueue.insertBarrier(inst); 10762292SN/A add_to_iq = false; 10772292SN/A } else if (inst->isNop()) { 10782292SN/A DPRINTF(IEW, "[tid:%i]: Issue: Nop instruction encountered, " 10792292SN/A "skipping.\n", tid); 10802292SN/A 10812292SN/A inst->setIssued(); 10822292SN/A inst->setExecuted(); 10832292SN/A inst->setCanCommit(); 10842292SN/A 10852326SN/A instQueue.recordProducer(inst); 10862292SN/A 10872727Sktlim@umich.edu iewExecutedNop[tid]++; 10882301SN/A 10892292SN/A add_to_iq = false; 10902292SN/A } else if (inst->isExecuted()) { 10912292SN/A assert(0 && "Instruction shouldn't be executed.\n"); 10922292SN/A DPRINTF(IEW, "Issue: Executed branch encountered, " 10932292SN/A "skipping.\n"); 10942292SN/A 10952292SN/A inst->setIssued(); 10962292SN/A inst->setCanCommit(); 10972292SN/A 10982326SN/A instQueue.recordProducer(inst); 10992292SN/A 11002292SN/A add_to_iq = false; 11012292SN/A } else { 11022292SN/A add_to_iq = true; 11032292SN/A } 11044033Sktlim@umich.edu if (inst->isNonSpeculative()) { 11054033Sktlim@umich.edu DPRINTF(IEW, "[tid:%i]: Issue: Nonspeculative instruction " 11064033Sktlim@umich.edu "encountered, skipping.\n", tid); 11074033Sktlim@umich.edu 11084033Sktlim@umich.edu // Same as non-speculative stores. 11094033Sktlim@umich.edu inst->setCanCommit(); 11104033Sktlim@umich.edu 11114033Sktlim@umich.edu // Specifically insert it as nonspeculative. 11124033Sktlim@umich.edu instQueue.insertNonSpec(inst); 11134033Sktlim@umich.edu 11144033Sktlim@umich.edu ++iewDispNonSpecInsts; 11154033Sktlim@umich.edu 11164033Sktlim@umich.edu add_to_iq = false; 11174033Sktlim@umich.edu } 11182292SN/A 11192292SN/A // If the instruction queue is not full, then add the 11202292SN/A // instruction. 11212292SN/A if (add_to_iq) { 11222292SN/A instQueue.insert(inst); 11232292SN/A } 11242292SN/A 11252292SN/A insts_to_dispatch.pop(); 11262292SN/A 11272292SN/A toRename->iewInfo[tid].dispatched++; 11282292SN/A 11292292SN/A ++iewDispatchedInsts; 11302292SN/A } 11312292SN/A 11322292SN/A if (!insts_to_dispatch.empty()) { 11332935Sksewell@umich.edu DPRINTF(IEW,"[tid:%i]: Issue: Bandwidth Full. Blocking.\n", tid); 11342292SN/A block(tid); 11352292SN/A toRename->iewUnblock[tid] = false; 11362292SN/A } 11372292SN/A 11382292SN/A if (dispatchStatus[tid] == Idle && dis_num_inst) { 11392292SN/A dispatchStatus[tid] = Running; 11402292SN/A 11412292SN/A updatedQueues = true; 11422292SN/A } 11432292SN/A 11442292SN/A dis_num_inst = 0; 11452292SN/A} 11462292SN/A 11472292SN/Atemplate <class Impl> 11482292SN/Avoid 11492292SN/ADefaultIEW<Impl>::printAvailableInsts() 11502292SN/A{ 11512292SN/A int inst = 0; 11522292SN/A 11532980Sgblack@eecs.umich.edu std::cout << "Available Instructions: "; 11542292SN/A 11552292SN/A while (fromIssue->insts[inst]) { 11562292SN/A 11572980Sgblack@eecs.umich.edu if (inst%3==0) std::cout << "\n\t"; 11582292SN/A 11592980Sgblack@eecs.umich.edu std::cout << "PC: " << fromIssue->insts[inst]->readPC() 11602292SN/A << " TN: " << fromIssue->insts[inst]->threadNumber 11612292SN/A << " SN: " << fromIssue->insts[inst]->seqNum << " | "; 11622292SN/A 11632292SN/A inst++; 11642292SN/A 11652292SN/A } 11662292SN/A 11672980Sgblack@eecs.umich.edu std::cout << "\n"; 11682292SN/A} 11692292SN/A 11702292SN/Atemplate <class Impl> 11712292SN/Avoid 11722292SN/ADefaultIEW<Impl>::executeInsts() 11732292SN/A{ 11742292SN/A wbNumInst = 0; 11752292SN/A wbCycle = 0; 11762292SN/A 11773867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 11783867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 11792292SN/A 11803867Sbinkertn@umich.edu while (threads != end) { 11812292SN/A unsigned tid = *threads++; 11822292SN/A fetchRedirect[tid] = false; 11832292SN/A } 11842292SN/A 11852698Sktlim@umich.edu // Uncomment this if you want to see all available instructions. 11862698Sktlim@umich.edu// printAvailableInsts(); 11871062SN/A 11881062SN/A // Execute/writeback any instructions that are available. 11892333SN/A int insts_to_execute = fromIssue->size; 11902292SN/A int inst_num = 0; 11912333SN/A for (; inst_num < insts_to_execute; 11922326SN/A ++inst_num) { 11931062SN/A 11942292SN/A DPRINTF(IEW, "Execute: Executing instructions from IQ.\n"); 11951062SN/A 11962333SN/A DynInstPtr inst = instQueue.getInstToExecute(); 11971062SN/A 11982292SN/A DPRINTF(IEW, "Execute: Processing PC %#x, [tid:%i] [sn:%i].\n", 11992292SN/A inst->readPC(), inst->threadNumber,inst->seqNum); 12001062SN/A 12011062SN/A // Check if the instruction is squashed; if so then skip it 12021062SN/A if (inst->isSquashed()) { 12032292SN/A DPRINTF(IEW, "Execute: Instruction was squashed.\n"); 12041062SN/A 12051062SN/A // Consider this instruction executed so that commit can go 12061062SN/A // ahead and retire the instruction. 12071062SN/A inst->setExecuted(); 12081062SN/A 12092292SN/A // Not sure if I should set this here or just let commit try to 12102292SN/A // commit any squashed instructions. I like the latter a bit more. 12112292SN/A inst->setCanCommit(); 12121062SN/A 12131062SN/A ++iewExecSquashedInsts; 12141062SN/A 12152820Sktlim@umich.edu decrWb(inst->seqNum); 12161062SN/A continue; 12171062SN/A } 12181062SN/A 12192292SN/A Fault fault = NoFault; 12201062SN/A 12211062SN/A // Execute instruction. 12221062SN/A // Note that if the instruction faults, it will be handled 12231062SN/A // at the commit stage. 12242292SN/A if (inst->isMemRef() && 12252292SN/A (!inst->isDataPrefetch() && !inst->isInstPrefetch())) { 12262292SN/A DPRINTF(IEW, "Execute: Calculating address for memory " 12271062SN/A "reference.\n"); 12281062SN/A 12291062SN/A // Tell the LDSTQ to execute this instruction (if it is a load). 12301062SN/A if (inst->isLoad()) { 12312292SN/A // Loads will mark themselves as executed, and their writeback 12322292SN/A // event adds the instruction to the queue to commit 12332292SN/A fault = ldstQueue.executeLoad(inst); 12341062SN/A } else if (inst->isStore()) { 12352367SN/A fault = ldstQueue.executeStore(inst); 12361062SN/A 12372292SN/A // If the store had a fault then it may not have a mem req 12382367SN/A if (!inst->isStoreConditional() && fault == NoFault) { 12392292SN/A inst->setExecuted(); 12402292SN/A 12412292SN/A instToCommit(inst); 12422367SN/A } else if (fault != NoFault) { 12432367SN/A // If the instruction faulted, then we need to send it along to commit 12442367SN/A // without the instruction completing. 12453732Sktlim@umich.edu DPRINTF(IEW, "Store has fault %s! [sn:%lli]\n", 12463732Sktlim@umich.edu fault->name(), inst->seqNum); 12472367SN/A 12482367SN/A // Send this instruction to commit, also make sure iew stage 12492367SN/A // realizes there is activity. 12502367SN/A inst->setExecuted(); 12512367SN/A 12522367SN/A instToCommit(inst); 12532367SN/A activityThisCycle(); 12542292SN/A } 12552326SN/A 12562326SN/A // Store conditionals will mark themselves as 12572326SN/A // executed, and their writeback event will add the 12582326SN/A // instruction to the queue to commit. 12591062SN/A } else { 12602292SN/A panic("Unexpected memory type!\n"); 12611062SN/A } 12621062SN/A 12631062SN/A } else { 12641062SN/A inst->execute(); 12651062SN/A 12662292SN/A inst->setExecuted(); 12672292SN/A 12682292SN/A instToCommit(inst); 12691062SN/A } 12701062SN/A 12712301SN/A updateExeInstStats(inst); 12721681SN/A 12732326SN/A // Check if branch prediction was correct, if not then we need 12742326SN/A // to tell commit to squash in flight instructions. Only 12752326SN/A // handle this if there hasn't already been something that 12762107SN/A // redirects fetch in this group of instructions. 12771681SN/A 12782292SN/A // This probably needs to prioritize the redirects if a different 12792292SN/A // scheduler is used. Currently the scheduler schedules the oldest 12802292SN/A // instruction first, so the branch resolution order will be correct. 12812292SN/A unsigned tid = inst->threadNumber; 12821062SN/A 12833732Sktlim@umich.edu if (!fetchRedirect[tid] || 12843732Sktlim@umich.edu toCommit->squashedSeqNum[tid] > inst->seqNum) { 12851062SN/A 12861062SN/A if (inst->mispredicted()) { 12872292SN/A fetchRedirect[tid] = true; 12881062SN/A 12892292SN/A DPRINTF(IEW, "Execute: Branch mispredict detected.\n"); 12903969Sgblack@eecs.umich.edu DPRINTF(IEW, "Predicted target was %#x, %#x.\n", 12913969Sgblack@eecs.umich.edu inst->readPredPC(), inst->readPredNPC()); 12923969Sgblack@eecs.umich.edu DPRINTF(IEW, "Execute: Redirecting fetch to PC: %#x," 12933969Sgblack@eecs.umich.edu " NPC: %#x.\n", inst->readNextPC(), 12943969Sgblack@eecs.umich.edu inst->readNextNPC()); 12951062SN/A // If incorrect, then signal the ROB that it must be squashed. 12962292SN/A squashDueToBranch(inst, tid); 12971062SN/A 12983795Sgblack@eecs.umich.edu if (inst->readPredTaken()) { 12991062SN/A predictedTakenIncorrect++; 13002292SN/A } else { 13012292SN/A predictedNotTakenIncorrect++; 13021062SN/A } 13032292SN/A } else if (ldstQueue.violation(tid)) { 13044033Sktlim@umich.edu assert(inst->isMemRef()); 13052326SN/A // If there was an ordering violation, then get the 13062326SN/A // DynInst that caused the violation. Note that this 13072292SN/A // clears the violation signal. 13082292SN/A DynInstPtr violator; 13092292SN/A violator = ldstQueue.getMemDepViolator(tid); 13101062SN/A 13112292SN/A DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13121062SN/A "%#x, inst PC: %#x. Addr is: %#x.\n", 13131062SN/A violator->readPC(), inst->readPC(), inst->physEffAddr); 13141062SN/A 13153732Sktlim@umich.edu // Ensure the violating instruction is older than 13163732Sktlim@umich.edu // current squash 13174033Sktlim@umich.edu/* if (fetchRedirect[tid] && 13184033Sktlim@umich.edu violator->seqNum >= toCommit->squashedSeqNum[tid] + 1) 13193732Sktlim@umich.edu continue; 13204033Sktlim@umich.edu*/ 13213732Sktlim@umich.edu fetchRedirect[tid] = true; 13223732Sktlim@umich.edu 13231062SN/A // Tell the instruction queue that a violation has occured. 13241062SN/A instQueue.violation(inst, violator); 13251062SN/A 13261062SN/A // Squash. 13272292SN/A squashDueToMemOrder(inst,tid); 13281062SN/A 13291062SN/A ++memOrderViolationEvents; 13302292SN/A } else if (ldstQueue.loadBlocked(tid) && 13312292SN/A !ldstQueue.isLoadBlockedHandled(tid)) { 13322292SN/A fetchRedirect[tid] = true; 13332292SN/A 13342292SN/A DPRINTF(IEW, "Load operation couldn't execute because the " 13352292SN/A "memory system is blocked. PC: %#x [sn:%lli]\n", 13362292SN/A inst->readPC(), inst->seqNum); 13372292SN/A 13382292SN/A squashDueToMemBlocked(inst, tid); 13391062SN/A } 13404033Sktlim@umich.edu } else { 13414033Sktlim@umich.edu // Reset any state associated with redirects that will not 13424033Sktlim@umich.edu // be used. 13434033Sktlim@umich.edu if (ldstQueue.violation(tid)) { 13444033Sktlim@umich.edu assert(inst->isMemRef()); 13454033Sktlim@umich.edu 13464033Sktlim@umich.edu DynInstPtr violator = ldstQueue.getMemDepViolator(tid); 13474033Sktlim@umich.edu 13484033Sktlim@umich.edu DPRINTF(IEW, "LDSTQ detected a violation. Violator PC: " 13494033Sktlim@umich.edu "%#x, inst PC: %#x. Addr is: %#x.\n", 13504033Sktlim@umich.edu violator->readPC(), inst->readPC(), inst->physEffAddr); 13514033Sktlim@umich.edu DPRINTF(IEW, "Violation will not be handled because " 13524033Sktlim@umich.edu "already squashing\n"); 13534033Sktlim@umich.edu 13544033Sktlim@umich.edu ++memOrderViolationEvents; 13554033Sktlim@umich.edu } 13564033Sktlim@umich.edu if (ldstQueue.loadBlocked(tid) && 13574033Sktlim@umich.edu !ldstQueue.isLoadBlockedHandled(tid)) { 13584033Sktlim@umich.edu DPRINTF(IEW, "Load operation couldn't execute because the " 13594033Sktlim@umich.edu "memory system is blocked. PC: %#x [sn:%lli]\n", 13604033Sktlim@umich.edu inst->readPC(), inst->seqNum); 13614033Sktlim@umich.edu DPRINTF(IEW, "Blocked load will not be handled because " 13624033Sktlim@umich.edu "already squashing\n"); 13634033Sktlim@umich.edu 13644033Sktlim@umich.edu ldstQueue.setLoadBlockedHandled(tid); 13654033Sktlim@umich.edu } 13664033Sktlim@umich.edu 13671062SN/A } 13681062SN/A } 13692292SN/A 13702348SN/A // Update and record activity if we processed any instructions. 13712292SN/A if (inst_num) { 13722292SN/A if (exeStatus == Idle) { 13732292SN/A exeStatus = Running; 13742292SN/A } 13752292SN/A 13762292SN/A updatedQueues = true; 13772292SN/A 13782292SN/A cpu->activityThisCycle(); 13792292SN/A } 13802292SN/A 13812292SN/A // Need to reset this in case a writeback event needs to write into the 13822292SN/A // iew queue. That way the writeback event will write into the correct 13832292SN/A // spot in the queue. 13842292SN/A wbNumInst = 0; 13852107SN/A} 13862107SN/A 13872292SN/Atemplate <class Impl> 13882107SN/Avoid 13892292SN/ADefaultIEW<Impl>::writebackInsts() 13902107SN/A{ 13912326SN/A // Loop through the head of the time buffer and wake any 13922326SN/A // dependents. These instructions are about to write back. Also 13932326SN/A // mark scoreboard that this instruction is finally complete. 13942326SN/A // Either have IEW have direct access to scoreboard, or have this 13952326SN/A // as part of backwards communication. 13963958Sgblack@eecs.umich.edu for (int inst_num = 0; inst_num < wbWidth && 13972292SN/A toCommit->insts[inst_num]; inst_num++) { 13982107SN/A DynInstPtr inst = toCommit->insts[inst_num]; 13992301SN/A int tid = inst->threadNumber; 14002107SN/A 14012698Sktlim@umich.edu DPRINTF(IEW, "Sending instructions to commit, [sn:%lli] PC %#x.\n", 14022698Sktlim@umich.edu inst->seqNum, inst->readPC()); 14032107SN/A 14042301SN/A iewInstsToCommit[tid]++; 14052301SN/A 14062292SN/A // Some instructions will be sent to commit without having 14072292SN/A // executed because they need commit to handle them. 14082292SN/A // E.g. Uncached loads have not actually executed when they 14092292SN/A // are first sent to commit. Instead commit must tell the LSQ 14102292SN/A // when it's ready to execute the uncached load. 14112367SN/A if (!inst->isSquashed() && inst->isExecuted() && inst->getFault() == NoFault) { 14122301SN/A int dependents = instQueue.wakeDependents(inst); 14132107SN/A 14142292SN/A for (int i = 0; i < inst->numDestRegs(); i++) { 14152292SN/A //mark as Ready 14162292SN/A DPRINTF(IEW,"Setting Destination Register %i\n", 14172292SN/A inst->renamedDestRegIdx(i)); 14182292SN/A scoreboard->setReg(inst->renamedDestRegIdx(i)); 14192107SN/A } 14202301SN/A 14212348SN/A if (dependents) { 14222348SN/A producerInst[tid]++; 14232348SN/A consumerInst[tid]+= dependents; 14242348SN/A } 14252326SN/A writebackCount[tid]++; 14262107SN/A } 14272820Sktlim@umich.edu 14282820Sktlim@umich.edu decrWb(inst->seqNum); 14292107SN/A } 14301060SN/A} 14311060SN/A 14321681SN/Atemplate<class Impl> 14331060SN/Avoid 14342292SN/ADefaultIEW<Impl>::tick() 14351060SN/A{ 14362292SN/A wbNumInst = 0; 14372292SN/A wbCycle = 0; 14381060SN/A 14392292SN/A wroteToTimeBuffer = false; 14402292SN/A updatedQueues = false; 14411060SN/A 14422292SN/A sortInsts(); 14431060SN/A 14442326SN/A // Free function units marked as being freed this cycle. 14452326SN/A fuPool->processFreeUnits(); 14461062SN/A 14473867Sbinkertn@umich.edu std::list<unsigned>::iterator threads = activeThreads->begin(); 14483867Sbinkertn@umich.edu std::list<unsigned>::iterator end = activeThreads->end(); 14491060SN/A 14502326SN/A // Check stall and squash signals, dispatch any instructions. 14513867Sbinkertn@umich.edu while (threads != end) { 14523867Sbinkertn@umich.edu unsigned tid = *threads++; 14531060SN/A 14542292SN/A DPRINTF(IEW,"Issue: Processing [tid:%i]\n",tid); 14551060SN/A 14562292SN/A checkSignalsAndUpdate(tid); 14572292SN/A dispatch(tid); 14581060SN/A } 14591060SN/A 14602292SN/A if (exeStatus != Squashing) { 14612292SN/A executeInsts(); 14621060SN/A 14632292SN/A writebackInsts(); 14642292SN/A 14652292SN/A // Have the instruction queue try to schedule any ready instructions. 14662292SN/A // (In actuality, this scheduling is for instructions that will 14672292SN/A // be executed next cycle.) 14682292SN/A instQueue.scheduleReadyInsts(); 14692292SN/A 14702292SN/A // Also should advance its own time buffers if the stage ran. 14712292SN/A // Not the best place for it, but this works (hopefully). 14722292SN/A issueToExecQueue.advance(); 14732292SN/A } 14742292SN/A 14752292SN/A bool broadcast_free_entries = false; 14762292SN/A 14772292SN/A if (updatedQueues || exeStatus == Running || updateLSQNextCycle) { 14782292SN/A exeStatus = Idle; 14792292SN/A updateLSQNextCycle = false; 14802292SN/A 14812292SN/A broadcast_free_entries = true; 14822292SN/A } 14832292SN/A 14842292SN/A // Writeback any stores using any leftover bandwidth. 14851681SN/A ldstQueue.writebackStores(); 14861681SN/A 14871061SN/A // Check the committed load/store signals to see if there's a load 14881061SN/A // or store to commit. Also check if it's being told to execute a 14891061SN/A // nonspeculative instruction. 14901681SN/A // This is pretty inefficient... 14912292SN/A 14923867Sbinkertn@umich.edu threads = activeThreads->begin(); 14933867Sbinkertn@umich.edu while (threads != end) { 14942292SN/A unsigned tid = (*threads++); 14952292SN/A 14962292SN/A DPRINTF(IEW,"Processing [tid:%i]\n",tid); 14972292SN/A 14982348SN/A // Update structures based on instructions committed. 14992292SN/A if (fromCommit->commitInfo[tid].doneSeqNum != 0 && 15002292SN/A !fromCommit->commitInfo[tid].squash && 15012292SN/A !fromCommit->commitInfo[tid].robSquashing) { 15022292SN/A 15032292SN/A ldstQueue.commitStores(fromCommit->commitInfo[tid].doneSeqNum,tid); 15042292SN/A 15052292SN/A ldstQueue.commitLoads(fromCommit->commitInfo[tid].doneSeqNum,tid); 15062292SN/A 15072292SN/A updateLSQNextCycle = true; 15082292SN/A instQueue.commit(fromCommit->commitInfo[tid].doneSeqNum,tid); 15092292SN/A } 15102292SN/A 15112292SN/A if (fromCommit->commitInfo[tid].nonSpecSeqNum != 0) { 15122292SN/A 15132292SN/A //DPRINTF(IEW,"NonspecInst from thread %i",tid); 15142292SN/A if (fromCommit->commitInfo[tid].uncached) { 15152292SN/A instQueue.replayMemInst(fromCommit->commitInfo[tid].uncachedLoad); 15164033Sktlim@umich.edu fromCommit->commitInfo[tid].uncachedLoad->setAtCommit(); 15172292SN/A } else { 15182292SN/A instQueue.scheduleNonSpec( 15192292SN/A fromCommit->commitInfo[tid].nonSpecSeqNum); 15202292SN/A } 15212292SN/A } 15222292SN/A 15232292SN/A if (broadcast_free_entries) { 15242292SN/A toFetch->iewInfo[tid].iqCount = 15252292SN/A instQueue.getCount(tid); 15262292SN/A toFetch->iewInfo[tid].ldstqCount = 15272292SN/A ldstQueue.getCount(tid); 15282292SN/A 15292292SN/A toRename->iewInfo[tid].usedIQ = true; 15302292SN/A toRename->iewInfo[tid].freeIQEntries = 15312292SN/A instQueue.numFreeEntries(); 15322292SN/A toRename->iewInfo[tid].usedLSQ = true; 15332292SN/A toRename->iewInfo[tid].freeLSQEntries = 15342292SN/A ldstQueue.numFreeEntries(tid); 15352292SN/A 15362292SN/A wroteToTimeBuffer = true; 15372292SN/A } 15382292SN/A 15392292SN/A DPRINTF(IEW, "[tid:%i], Dispatch dispatched %i instructions.\n", 15402292SN/A tid, toRename->iewInfo[tid].dispatched); 15411061SN/A } 15421061SN/A 15432292SN/A DPRINTF(IEW, "IQ has %i free entries (Can schedule: %i). " 15442292SN/A "LSQ has %i free entries.\n", 15452292SN/A instQueue.numFreeEntries(), instQueue.hasReadyInsts(), 15462292SN/A ldstQueue.numFreeEntries()); 15472292SN/A 15482292SN/A updateStatus(); 15492292SN/A 15502292SN/A if (wroteToTimeBuffer) { 15512292SN/A DPRINTF(Activity, "Activity this cycle.\n"); 15522292SN/A cpu->activityThisCycle(); 15531061SN/A } 15541060SN/A} 15551060SN/A 15562301SN/Atemplate <class Impl> 15571060SN/Avoid 15582301SN/ADefaultIEW<Impl>::updateExeInstStats(DynInstPtr &inst) 15591060SN/A{ 15602301SN/A int thread_number = inst->threadNumber; 15611060SN/A 15622301SN/A // 15632301SN/A // Pick off the software prefetches 15642301SN/A // 15652301SN/A#ifdef TARGET_ALPHA 15662301SN/A if (inst->isDataPrefetch()) 15672727Sktlim@umich.edu iewExecutedSwp[thread_number]++; 15682301SN/A else 15692727Sktlim@umich.edu iewIewExecutedcutedInsts++; 15702301SN/A#else 15712669Sktlim@umich.edu iewExecutedInsts++; 15722301SN/A#endif 15731060SN/A 15742301SN/A // 15752301SN/A // Control operations 15762301SN/A // 15772301SN/A if (inst->isControl()) 15782727Sktlim@umich.edu iewExecutedBranches[thread_number]++; 15791060SN/A 15802301SN/A // 15812301SN/A // Memory operations 15822301SN/A // 15832301SN/A if (inst->isMemRef()) { 15842727Sktlim@umich.edu iewExecutedRefs[thread_number]++; 15851060SN/A 15862301SN/A if (inst->isLoad()) { 15872301SN/A iewExecLoadInsts[thread_number]++; 15881060SN/A } 15891060SN/A } 15901060SN/A} 1591