iew.hh revision 6221:58a3c04e6344
12SN/A/* 212109SRekai.GonzalezAlberquilla@arm.com * Copyright (c) 2004-2006 The Regents of The University of Michigan 39920Syasuko.eckert@amd.com * All rights reserved. 48733Sgeoffrey.blake@arm.com * 58733Sgeoffrey.blake@arm.com * Redistribution and use in source and binary forms, with or without 68733Sgeoffrey.blake@arm.com * modification, are permitted provided that the following conditions are 78733Sgeoffrey.blake@arm.com * met: redistributions of source code must retain the above copyright 88733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer; 98733Sgeoffrey.blake@arm.com * redistributions in binary form must reproduce the above copyright 108733Sgeoffrey.blake@arm.com * notice, this list of conditions and the following disclaimer in the 118733Sgeoffrey.blake@arm.com * documentation and/or other materials provided with the distribution; 128733Sgeoffrey.blake@arm.com * neither the name of the copyright holders nor the names of its 138733Sgeoffrey.blake@arm.com * contributors may be used to endorse or promote products derived from 148733Sgeoffrey.blake@arm.com * this software without specific prior written permission. 152190SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272SN/A * 282SN/A * Authors: Kevin Lim 292SN/A */ 302SN/A 312SN/A#ifndef __CPU_O3_IEW_HH__ 322SN/A#define __CPU_O3_IEW_HH__ 332SN/A 342SN/A#include <queue> 352SN/A 362SN/A#include "base/statistics.hh" 372SN/A#include "base/timebuf.hh" 382SN/A#include "config/full_system.hh" 392SN/A#include "cpu/o3/comm.hh" 402665SN/A#include "cpu/o3/scoreboard.hh" 412665SN/A#include "cpu/o3/lsq.hh" 422SN/A 432SN/Aclass DerivO3CPUParams; 442680Sktlim@umich.educlass FUPool; 452680Sktlim@umich.edu 462SN/A/** 478229Snate@binkert.org * DefaultIEW handles both single threaded and SMT IEW 487680Sgblack@eecs.umich.edu * (issue/execute/writeback). It handles the dispatching of 497680Sgblack@eecs.umich.edu * instructions to the LSQ/IQ as part of the issue stage, and has the 506329Sgblack@eecs.umich.edu * IQ try to issue instructions each cycle. The execute latency is 513453Sgblack@eecs.umich.edu * actually tied into the issue latency to allow the IQ to be able to 526216Snate@binkert.org * do back-to-back scheduling without having to speculatively schedule 536658Snate@binkert.org * instructions. This happens by having the IQ have access to the 5412104Snathanael.premillieu@arm.com * functional units, and the IQ gets the execution latencies from the 552SN/A * FUs when it issues instructions. Instructions reach the execute 562190SN/A * stage on the last cycle of their execution, which is when the IQ 572190SN/A * knows to wake up any dependent instructions, allowing back to back 583453Sgblack@eecs.umich.edu * scheduling. The execute portion of IEW separates memory 593453Sgblack@eecs.umich.edu * instructions from non-memory instructions, either telling the LSQ 609020Sgblack@eecs.umich.edu * to execute the instruction, or executing the instruction directly. 616022Sgblack@eecs.umich.edu * The writeback portion of IEW completes the instructions by waking 623453Sgblack@eecs.umich.edu * up any dependents, and marking the register ready on the 632190SN/A * scoreboard. 648887Sgeoffrey.blake@arm.com */ 657680Sgblack@eecs.umich.edutemplate<class Impl> 662313SN/Aclass DefaultIEW 678706Sandreas.hansson@arm.com{ 688706Sandreas.hansson@arm.com private: 698706Sandreas.hansson@arm.com //Typedefs from Impl 702190SN/A typedef typename Impl::CPUPol CPUPol; 712190SN/A typedef typename Impl::DynInstPtr DynInstPtr; 723548Sgblack@eecs.umich.edu typedef typename Impl::O3CPU O3CPU; 733548Sgblack@eecs.umich.edu 743548Sgblack@eecs.umich.edu typedef typename CPUPol::IQ IQ; 758902Sandreas.hansson@arm.com typedef typename CPUPol::RenameMap RenameMap; 768902Sandreas.hansson@arm.com typedef typename CPUPol::LSQ LSQ; 772SN/A 782680Sktlim@umich.edu typedef typename CPUPol::TimeStruct TimeStruct; 792680Sktlim@umich.edu typedef typename CPUPol::IEWStruct IEWStruct; 802680Sktlim@umich.edu typedef typename CPUPol::RenameStruct RenameStruct; 812680Sktlim@umich.edu typedef typename CPUPol::IssueStruct IssueStruct; 822680Sktlim@umich.edu 832680Sktlim@umich.edu friend class Impl::O3CPU; 842680Sktlim@umich.edu friend class CPUPol::IQ; 852680Sktlim@umich.edu 862680Sktlim@umich.edu public: 872680Sktlim@umich.edu /** Overall IEW stage status. Used to determine if the CPU can 882680Sktlim@umich.edu * deschedule itself due to a lack of activity. 892682Sktlim@umich.edu */ 902680Sktlim@umich.edu enum Status { 912680Sktlim@umich.edu Active, 922680Sktlim@umich.edu Inactive 932680Sktlim@umich.edu }; 942680Sktlim@umich.edu 952SN/A /** Status for Issue, Execute, and Writeback stages. */ 962107SN/A enum StageStatus { 972107SN/A Running, 982190SN/A Blocked, 992455SN/A Idle, 1002455SN/A StartSquash, 1019920Syasuko.eckert@amd.com Squashing, 1022159SN/A Unblocking 10312109SRekai.GonzalezAlberquilla@arm.com }; 10412109SRekai.GonzalezAlberquilla@arm.com 1052SN/A private: 1066029Ssteve.reinhardt@amd.com /** Overall stage status. */ 107246SN/A Status _status; 108246SN/A /** Dispatch status. */ 109246SN/A StageStatus dispatchStatus[Impl::MaxThreads]; 110246SN/A /** Execute status. */ 111246SN/A StageStatus exeStatus; 112246SN/A /** Writeback status. */ 113246SN/A StageStatus wbStatus; 1142190SN/A 115246SN/A public: 116246SN/A /** Constructs a DefaultIEW with the given parameters. */ 117246SN/A DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params); 118246SN/A 119246SN/A /** Returns the name of the DefaultIEW stage. */ 120246SN/A std::string name() const; 121246SN/A 1222SN/A /** Registers statistics. */ 1232680Sktlim@umich.edu void regStats(); 1242423SN/A 1252190SN/A /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 126180SN/A void initStage(); 12710110Sandreas.hansson@arm.com 1282190SN/A /** Returns the dcache port. */ 12910190Sakash.bagdia@arm.com Port *getDcachePort() { return ldstQueue.getDcachePort(); } 13010190Sakash.bagdia@arm.com 13110110Sandreas.hansson@arm.com /** Sets main time buffer used for backwards communication. */ 1325715Shsul@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1335715Shsul@eecs.umich.edu 1345714Shsul@eecs.umich.edu /** Sets time buffer for getting instructions coming from rename. */ 13510110Sandreas.hansson@arm.com void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1365714Shsul@eecs.umich.edu 1375714Shsul@eecs.umich.edu /** Sets time buffer to pass on instructions to commit. */ 1385714Shsul@eecs.umich.edu void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1396022Sgblack@eecs.umich.edu 1402190SN/A /** Sets pointer to list of active threads. */ 1416022Sgblack@eecs.umich.edu void setActiveThreads(std::list<ThreadID> *at_ptr); 1422521SN/A 1438887Sgeoffrey.blake@arm.com /** Sets pointer to the scoreboard. */ 1448733Sgeoffrey.blake@arm.com void setScoreboard(Scoreboard *sb_ptr); 1459020Sgblack@eecs.umich.edu 1468541Sgblack@eecs.umich.edu /** Drains IEW stage. */ 1474997Sgblack@eecs.umich.edu bool drain(); 1484997Sgblack@eecs.umich.edu 1493548Sgblack@eecs.umich.edu /** Resumes execution after a drain. */ 1502654SN/A void resume(); 1518852Sandreas.hansson@arm.com 1522521SN/A /** Completes switch out of IEW stage. */ 1538852Sandreas.hansson@arm.com void switchOut(); 1543673Srdreslin@umich.edu 1558706Sandreas.hansson@arm.com /** Takes over from another CPU's thread. */ 1568706Sandreas.hansson@arm.com void takeOverFrom(); 1578706Sandreas.hansson@arm.com 1588706Sandreas.hansson@arm.com /** Returns if IEW is switched out. */ 1598706Sandreas.hansson@arm.com bool isSwitchedOut() { return switchedOut; } 1608706Sandreas.hansson@arm.com 1618706Sandreas.hansson@arm.com /** Squashes instructions in IEW for a specific thread. */ 1628799Sgblack@eecs.umich.edu void squash(ThreadID tid); 1638852Sandreas.hansson@arm.com 1642518SN/A /** Wakes all dependents of a completed instruction. */ 1652190SN/A void wakeDependents(DynInstPtr &inst); 1662190SN/A 16711886Sbrandon.potter@amd.com /** Tells memory dependence unit that a memory instruction needs to be 16811886Sbrandon.potter@amd.com * rescheduled. It will re-execute once replayMemInst() is called. 1692190SN/A */ 1702159SN/A void rescheduleMemInst(DynInstPtr &inst); 1712235SN/A 1722103SN/A /** Re-executes all rescheduled memory instructions. */ 17310407Smitch.hayenga@arm.com void replayMemInst(DynInstPtr &inst); 17410407Smitch.hayenga@arm.com 175393SN/A /** Sends an instruction to commit through the time buffer. */ 176393SN/A void instToCommit(DynInstPtr &inst); 17710407Smitch.hayenga@arm.com 178393SN/A /** Inserts unused instructions of a thread into the skid buffer. */ 179393SN/A void skidInsert(ThreadID tid); 18010407Smitch.hayenga@arm.com 1812159SN/A /** Returns the max of the number of entries in all of the skid buffers. */ 18211627Smichael.lebeane@amd.com int skidCount(); 18311627Smichael.lebeane@amd.com 18411627Smichael.lebeane@amd.com /** Returns if all of the skid buffers are empty. */ 18511627Smichael.lebeane@amd.com bool skidsEmpty(); 18611627Smichael.lebeane@amd.com 18711627Smichael.lebeane@amd.com /** Updates overall IEW status based on all of the stages' statuses. */ 1882190SN/A void updateStatus(); 1892159SN/A 1902680Sktlim@umich.edu /** Resets entries of the IQ and the LSQ. */ 1912159SN/A void resetEntries(); 1922190SN/A 1932159SN/A /** Tells the CPU to wakeup if it has descheduled itself due to no 1942313SN/A * activity. Used mainly by the LdWritebackEvent. 1952235SN/A */ 1962235SN/A void wakeCPU(); 1972235SN/A 1982235SN/A /** Reports to the CPU that there is activity this cycle. */ 1992235SN/A void activityThisCycle(); 2002254SN/A 2012254SN/A /** Tells CPU that the IEW stage is active and running. */ 2022254SN/A inline void activateStage(); 2032235SN/A 2042680Sktlim@umich.edu /** Tells CPU that the IEW stage is inactive and idle. */ 2052159SN/A inline void deactivateStage(); 2062190SN/A 2072159SN/A /** Returns if the LSQ has any stores to writeback. */ 2082159SN/A bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 2092159SN/A 2102159SN/A /** Returns if the LSQ has any stores to writeback. */ 2112190SN/A bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); } 2122159SN/A 2132455SN/A void incrWb(InstSeqNum &sn) 2142159SN/A { 2152455SN/A if (++wbOutstanding == wbMax) 2162159SN/A ableToIssue = false; 21712109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); 21812109SRekai.GonzalezAlberquilla@arm.com assert(wbOutstanding <= wbMax); 21912109SRekai.GonzalezAlberquilla@arm.com#ifdef DEBUG 22012109SRekai.GonzalezAlberquilla@arm.com wbList.insert(sn); 22112109SRekai.GonzalezAlberquilla@arm.com#endif 22212109SRekai.GonzalezAlberquilla@arm.com } 22312109SRekai.GonzalezAlberquilla@arm.com 22412109SRekai.GonzalezAlberquilla@arm.com void decrWb(InstSeqNum &sn) 22512109SRekai.GonzalezAlberquilla@arm.com { 22612109SRekai.GonzalezAlberquilla@arm.com if (wbOutstanding-- == wbMax) 22712109SRekai.GonzalezAlberquilla@arm.com ableToIssue = true; 22812109SRekai.GonzalezAlberquilla@arm.com DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); 22912109SRekai.GonzalezAlberquilla@arm.com assert(wbOutstanding >= 0); 23012109SRekai.GonzalezAlberquilla@arm.com#ifdef DEBUG 23112109SRekai.GonzalezAlberquilla@arm.com assert(wbList.find(sn) != wbList.end()); 23212109SRekai.GonzalezAlberquilla@arm.com wbList.erase(sn); 23312109SRekai.GonzalezAlberquilla@arm.com#endif 23412109SRekai.GonzalezAlberquilla@arm.com } 23512109SRekai.GonzalezAlberquilla@arm.com 23612109SRekai.GonzalezAlberquilla@arm.com#ifdef DEBUG 23712109SRekai.GonzalezAlberquilla@arm.com std::set<InstSeqNum> wbList; 23812109SRekai.GonzalezAlberquilla@arm.com 23912109SRekai.GonzalezAlberquilla@arm.com void dumpWb() 24012109SRekai.GonzalezAlberquilla@arm.com { 24112109SRekai.GonzalezAlberquilla@arm.com std::set<InstSeqNum>::iterator wb_it = wbList.begin(); 24212109SRekai.GonzalezAlberquilla@arm.com while (wb_it != wbList.end()) { 24312109SRekai.GonzalezAlberquilla@arm.com cprintf("[sn:%lli]\n", 24412109SRekai.GonzalezAlberquilla@arm.com (*wb_it)); 24512109SRekai.GonzalezAlberquilla@arm.com wb_it++; 24612109SRekai.GonzalezAlberquilla@arm.com } 24712109SRekai.GonzalezAlberquilla@arm.com } 24812109SRekai.GonzalezAlberquilla@arm.com#endif 24912109SRekai.GonzalezAlberquilla@arm.com 25012109SRekai.GonzalezAlberquilla@arm.com bool canIssue() { return ableToIssue; } 2519920Syasuko.eckert@amd.com 2529920Syasuko.eckert@amd.com bool ableToIssue; 2532190SN/A 2542159SN/A private: 2552455SN/A /** Sends commit proper information for a squash due to a branch 2562159SN/A * mispredict. 2572455SN/A */ 2582455SN/A void squashDueToBranch(DynInstPtr &inst, ThreadID tid); 25912109SRekai.GonzalezAlberquilla@arm.com 26012109SRekai.GonzalezAlberquilla@arm.com /** Sends commit proper information for a squash due to a memory order 26112109SRekai.GonzalezAlberquilla@arm.com * violation. 26212109SRekai.GonzalezAlberquilla@arm.com */ 2639920Syasuko.eckert@amd.com void squashDueToMemOrder(DynInstPtr &inst, ThreadID tid); 2649920Syasuko.eckert@amd.com 2657720Sgblack@eecs.umich.edu /** Sends commit proper information for a squash due to memory becoming 2662159SN/A * blocked (younger issued instructions must be retried). 2677720Sgblack@eecs.umich.edu */ 2682159SN/A void squashDueToMemBlocked(DynInstPtr &inst, ThreadID tid); 26911886Sbrandon.potter@amd.com 27011886Sbrandon.potter@amd.com /** Sets Dispatch to blocked, and signals back to other stages to block. */ 27111886Sbrandon.potter@amd.com void block(ThreadID tid); 27211886Sbrandon.potter@amd.com 27311886Sbrandon.potter@amd.com /** Unblocks Dispatch if the skid buffer is empty, and signals back to 27411886Sbrandon.potter@amd.com * other stages to unblock. 27511886Sbrandon.potter@amd.com */ 27611886Sbrandon.potter@amd.com void unblock(ThreadID tid); 2778733Sgeoffrey.blake@arm.com 2788733Sgeoffrey.blake@arm.com /** Determines proper actions to take given Dispatch's status. */ 2797720Sgblack@eecs.umich.edu void dispatch(ThreadID tid); 2802159SN/A 2817720Sgblack@eecs.umich.edu /** Dispatches instructions to IQ and LSQ. */ 2822159SN/A void dispatchInsts(ThreadID tid); 2837720Sgblack@eecs.umich.edu 2845260Sksewell@umich.edu /** Executes instructions. In the case of memory operations, it informs the 28510698Sandreas.hansson@arm.com * LSQ to execute the instructions. Also handles any redirects that occur 2864172Ssaidi@eecs.umich.edu * due to the executed instructions. 2872190SN/A */ 2882159SN/A void executeInsts(); 2894172Ssaidi@eecs.umich.edu 2902190SN/A /** Writebacks instructions. In our model, the instruction's execute() 2913468Sgblack@eecs.umich.edu * function atomically reads registers, executes, and writes registers. 2922190SN/A * Thus this writeback only wakes up dependent instructions, and informs 29312106SRekai.GonzalezAlberquilla@arm.com * the scoreboard of registers becoming ready. 2946313Sgblack@eecs.umich.edu */ 2956221Snate@binkert.org void writebackInsts(); 29612106SRekai.GonzalezAlberquilla@arm.com 2976221Snate@binkert.org /** Returns the number of valid, non-squashed instructions coming from 2986221Snate@binkert.org * rename to dispatch. 2996221Snate@binkert.org */ 3004661Sksewell@umich.edu unsigned validInstsFromRename(); 3016221Snate@binkert.org 30212106SRekai.GonzalezAlberquilla@arm.com /** Reads the stall signals. */ 3036221Snate@binkert.org void readStallSignals(ThreadID tid); 3046221Snate@binkert.org 3054661Sksewell@umich.edu /** Checks if any of the stall conditions are currently true. */ 3062235SN/A bool checkStall(ThreadID tid); 3072235SN/A 3082190SN/A /** Processes inputs and changes state accordingly. */ 3092190SN/A void checkSignalsAndUpdate(ThreadID tid); 3102190SN/A 3112159SN/A /** Removes instructions from rename from a thread's instruction list. */ 3122235SN/A void emptyRenameInsts(ThreadID tid); 3132190SN/A 3142834Sksewell@umich.edu /** Sorts instructions coming from rename into lists separated by thread. */ 31511877Sbrandon.potter@amd.com void sortInsts(); 3164111Sgblack@eecs.umich.edu 3172834Sksewell@umich.edu public: 3182834Sksewell@umich.edu /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 3192834Sksewell@umich.edu * Writeback to run for one cycle. 3202834Sksewell@umich.edu */ 3212525SN/A void tick(); 3225217Ssaidi@eecs.umich.edu 3235217Ssaidi@eecs.umich.edu private: 3249426SAndreas.Sandberg@ARM.com /** Updates execution stats based on the instruction. */ 3259426SAndreas.Sandberg@ARM.com void updateExeInstStats(DynInstPtr &inst); 3269426SAndreas.Sandberg@ARM.com 3279426SAndreas.Sandberg@ARM.com /** Pointer to main time buffer used for backwards communication. */ 3289426SAndreas.Sandberg@ARM.com TimeBuffer<TimeStruct> *timeBuffer; 3299426SAndreas.Sandberg@ARM.com 3309426SAndreas.Sandberg@ARM.com /** Wire to write information heading to previous stages. */ 33112106SRekai.GonzalezAlberquilla@arm.com typename TimeBuffer<TimeStruct>::wire toFetch; 3329426SAndreas.Sandberg@ARM.com 3339426SAndreas.Sandberg@ARM.com /** Wire to get commit's output from backwards time buffer. */ 3349426SAndreas.Sandberg@ARM.com typename TimeBuffer<TimeStruct>::wire fromCommit; 3359426SAndreas.Sandberg@ARM.com 3369426SAndreas.Sandberg@ARM.com /** Wire to write information heading to previous stages. */ 3379426SAndreas.Sandberg@ARM.com typename TimeBuffer<TimeStruct>::wire toRename; 3389426SAndreas.Sandberg@ARM.com 3399426SAndreas.Sandberg@ARM.com /** Rename instruction queue interface. */ 3409426SAndreas.Sandberg@ARM.com TimeBuffer<RenameStruct> *renameQueue; 3419426SAndreas.Sandberg@ARM.com 3429426SAndreas.Sandberg@ARM.com /** Wire to get rename's output from rename queue. */ 3439426SAndreas.Sandberg@ARM.com typename TimeBuffer<RenameStruct>::wire fromRename; 3449426SAndreas.Sandberg@ARM.com 3459426SAndreas.Sandberg@ARM.com /** Issue stage queue. */ 34612109SRekai.GonzalezAlberquilla@arm.com TimeBuffer<IssueStruct> issueToExecQueue; 34712109SRekai.GonzalezAlberquilla@arm.com 34812109SRekai.GonzalezAlberquilla@arm.com /** Wire to read information from the issue stage time queue. */ 34912109SRekai.GonzalezAlberquilla@arm.com typename TimeBuffer<IssueStruct>::wire fromIssue; 35012109SRekai.GonzalezAlberquilla@arm.com 35112109SRekai.GonzalezAlberquilla@arm.com /** 35212109SRekai.GonzalezAlberquilla@arm.com * IEW stage time buffer. Holds ROB indices of instructions that 35312109SRekai.GonzalezAlberquilla@arm.com * can be marked as completed. 35412109SRekai.GonzalezAlberquilla@arm.com */ 3559920Syasuko.eckert@amd.com TimeBuffer<IEWStruct> *iewQueue; 3569920Syasuko.eckert@amd.com 3579426SAndreas.Sandberg@ARM.com /** Wire to write infromation heading to commit. */ 3589426SAndreas.Sandberg@ARM.com typename TimeBuffer<IEWStruct>::wire toCommit; 3592159SN/A 3602159SN/A /** Queue of all instructions coming from rename this cycle. */ 3612682Sktlim@umich.edu std::queue<DynInstPtr> insts[Impl::MaxThreads]; 3622682Sktlim@umich.edu 3632682Sktlim@umich.edu /** Skid buffer between rename and IEW. */ 3642682Sktlim@umich.edu std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 3652682Sktlim@umich.edu 3662682Sktlim@umich.edu /** Scoreboard pointer. */ 3672682Sktlim@umich.edu Scoreboard* scoreboard; 3682682Sktlim@umich.edu 3692682Sktlim@umich.edu private: 3702682Sktlim@umich.edu /** CPU pointer. */ 3712680Sktlim@umich.edu O3CPU *cpu; 3722680Sktlim@umich.edu 3732190SN/A /** Records if IEW has written to the time buffer this cycle, so that the 3742190SN/A * CPU can deschedule itself if there is no activity. 3752680Sktlim@umich.edu */ 3762680Sktlim@umich.edu bool wroteToTimeBuffer; 3772159SN/A 3782190SN/A /** Source of possible stalls. */ 3792680Sktlim@umich.edu struct Stalls { 3802SN/A bool commit; 3812SN/A }; 3822SN/A 3832680Sktlim@umich.edu /** Stages that are telling IEW to stall. */ 3842SN/A Stalls stalls[Impl::MaxThreads]; 38510110Sandreas.hansson@arm.com 3862SN/A /** Debug function to print instructions that are issued this cycle. */ 38710190Sakash.bagdia@arm.com void printAvailableInsts(); 38810190Sakash.bagdia@arm.com 38910110Sandreas.hansson@arm.com public: 3905715Shsul@eecs.umich.edu /** Instruction queue. */ 39110110Sandreas.hansson@arm.com IQ instQueue; 3925714Shsul@eecs.umich.edu 39310110Sandreas.hansson@arm.com /** Load / store queue. */ 3945714Shsul@eecs.umich.edu LSQ ldstQueue; 3955714Shsul@eecs.umich.edu 3965714Shsul@eecs.umich.edu /** Pointer to the functional unit pool. */ 3976022Sgblack@eecs.umich.edu FUPool *fuPool; 3981917SN/A /** Records if the LSQ needs to be updated on the next cycle, so that 3996022Sgblack@eecs.umich.edu * IEW knows if there will be activity on the next cycle. 4002521SN/A */ 4018887Sgeoffrey.blake@arm.com bool updateLSQNextCycle; 4028733Sgeoffrey.blake@arm.com 4039020Sgblack@eecs.umich.edu private: 4048541Sgblack@eecs.umich.edu /** Records if there is a fetch redirect on this cycle for each thread. */ 4054997Sgblack@eecs.umich.edu bool fetchRedirect[Impl::MaxThreads]; 4064997Sgblack@eecs.umich.edu 4073548Sgblack@eecs.umich.edu /** Records if the queues have been changed (inserted or issued insts), 4083548Sgblack@eecs.umich.edu * so that IEW knows to broadcast the updated amount of free entries. 4092654SN/A */ 4108852Sandreas.hansson@arm.com bool updatedQueues; 4112521SN/A 4128852Sandreas.hansson@arm.com /** Commit to IEW delay, in ticks. */ 4133673Srdreslin@umich.edu unsigned commitToIEWDelay; 4148706Sandreas.hansson@arm.com 4158799Sgblack@eecs.umich.edu /** Rename to IEW delay, in ticks. */ 4168852Sandreas.hansson@arm.com unsigned renameToIEWDelay; 4172518SN/A 4182680Sktlim@umich.edu /** 4192SN/A * Issue to execute delay, in ticks. What this actually represents is 42011886Sbrandon.potter@amd.com * the amount of time it takes for an instruction to wake up, be 42111886Sbrandon.potter@amd.com * scheduled, and sent to a FU for execution. 4222680Sktlim@umich.edu */ 423595SN/A unsigned issueToExecuteDelay; 4242680Sktlim@umich.edu 4252SN/A /** Width of dispatch, in instructions. */ 42610407Smitch.hayenga@arm.com unsigned dispatchWidth; 42710407Smitch.hayenga@arm.com 4282SN/A /** Width of issue, in instructions. */ 4292190SN/A unsigned issueWidth; 43010407Smitch.hayenga@arm.com 4312SN/A /** Index into queue of instructions being written back. */ 4322190SN/A unsigned wbNumInst; 43310407Smitch.hayenga@arm.com 434217SN/A /** Cycle number within the queue of instructions being written back. 43511627Smichael.lebeane@amd.com * Used in case there are too many instructions writing back at the current 43611627Smichael.lebeane@amd.com * cycle and writesbacks need to be scheduled for the future. See comments 43711627Smichael.lebeane@amd.com * in instToCommit(). 43811627Smichael.lebeane@amd.com */ 43911627Smichael.lebeane@amd.com unsigned wbCycle; 44011627Smichael.lebeane@amd.com 4412680Sktlim@umich.edu /** Number of instructions in flight that will writeback. */ 4422190SN/A 4432680Sktlim@umich.edu /** Number of instructions in flight that will writeback. */ 4442680Sktlim@umich.edu int wbOutstanding; 4452190SN/A 4462680Sktlim@umich.edu /** Writeback width. */ 4472190SN/A unsigned wbWidth; 4482680Sktlim@umich.edu 4492235SN/A /** Writeback width * writeback depth, where writeback depth is 4502680Sktlim@umich.edu * the number of cycles of writing back instructions that can be 4512680Sktlim@umich.edu * buffered. */ 4522254SN/A unsigned wbMax; 4532680Sktlim@umich.edu 4542680Sktlim@umich.edu /** Number of active threads. */ 4552SN/A ThreadID numThreads; 4562190SN/A 4572680Sktlim@umich.edu /** Pointer to list of active threads. */ 4582SN/A std::list<ThreadID> *activeThreads; 4592680Sktlim@umich.edu 460716SN/A /** Maximum size of the skid buffer. */ 4612SN/A unsigned skidBufferMax; 4622SN/A 4632SN/A /** Is this stage switched out. */ 4642SN/A bool switchedOut; 4652680Sktlim@umich.edu 4662SN/A /** Stat for total number of idle cycles. */ 4672455SN/A Stats::Scalar iewIdleCycles; 4682680Sktlim@umich.edu /** Stat for total number of squashing cycles. */ 4692SN/A Stats::Scalar iewSquashCycles; 4702455SN/A /** Stat for total number of blocking cycles. */ 4712680Sktlim@umich.edu Stats::Scalar iewBlockCycles; 4722SN/A /** Stat for total number of unblocking cycles. */ 47312109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar iewUnblockCycles; 47412109SRekai.GonzalezAlberquilla@arm.com /** Stat for total number of instructions dispatched. */ 47512109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar iewDispatchedInsts; 47612109SRekai.GonzalezAlberquilla@arm.com /** Stat for total number of squashed instructions dispatch skips. */ 47712109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar iewDispSquashedInsts; 47812109SRekai.GonzalezAlberquilla@arm.com /** Stat for total number of dispatched load instructions. */ 47912109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar iewDispLoadInsts; 48012109SRekai.GonzalezAlberquilla@arm.com /** Stat for total number of dispatched store instructions. */ 48112109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar iewDispStoreInsts; 48212109SRekai.GonzalezAlberquilla@arm.com /** Stat for total number of dispatched non speculative instructions. */ 48312109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar iewDispNonSpecInsts; 48412109SRekai.GonzalezAlberquilla@arm.com /** Stat for number of times the IQ becomes full. */ 48512109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar iewIQFullEvents; 48612109SRekai.GonzalezAlberquilla@arm.com /** Stat for number of times the LSQ becomes full. */ 48712109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar iewLSQFullEvents; 48812109SRekai.GonzalezAlberquilla@arm.com /** Stat for total number of memory ordering violation events. */ 48912109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar memOrderViolationEvents; 49012109SRekai.GonzalezAlberquilla@arm.com /** Stat for total number of incorrect predicted taken branches. */ 49112109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar predictedTakenIncorrect; 49212109SRekai.GonzalezAlberquilla@arm.com /** Stat for total number of incorrect predicted not taken branches. */ 49312109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar predictedNotTakenIncorrect; 49412109SRekai.GonzalezAlberquilla@arm.com /** Stat for total number of mispredicted branches detected at execute. */ 49512109SRekai.GonzalezAlberquilla@arm.com Stats::Formula branchMispredicts; 49612109SRekai.GonzalezAlberquilla@arm.com 49712109SRekai.GonzalezAlberquilla@arm.com /** Stat for total number of executed instructions. */ 49812109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar iewExecutedInsts; 49912109SRekai.GonzalezAlberquilla@arm.com /** Stat for total number of executed load instructions. */ 50012109SRekai.GonzalezAlberquilla@arm.com Stats::Vector iewExecLoadInsts; 50112109SRekai.GonzalezAlberquilla@arm.com /** Stat for total number of executed store instructions. */ 50212109SRekai.GonzalezAlberquilla@arm.com// Stats::Scalar iewExecStoreInsts; 50312109SRekai.GonzalezAlberquilla@arm.com /** Stat for total number of squashed instructions skipped at execute. */ 50412109SRekai.GonzalezAlberquilla@arm.com Stats::Scalar iewExecSquashedInsts; 50512109SRekai.GonzalezAlberquilla@arm.com /** Number of executed software prefetches. */ 50612109SRekai.GonzalezAlberquilla@arm.com Stats::Vector iewExecutedSwp; 50712109SRekai.GonzalezAlberquilla@arm.com /** Number of executed nops. */ 50812109SRekai.GonzalezAlberquilla@arm.com Stats::Vector iewExecutedNop; 50912109SRekai.GonzalezAlberquilla@arm.com /** Number of executed meomory references. */ 51012109SRekai.GonzalezAlberquilla@arm.com Stats::Vector iewExecutedRefs; 51112109SRekai.GonzalezAlberquilla@arm.com /** Number of executed branches. */ 51212109SRekai.GonzalezAlberquilla@arm.com Stats::Vector iewExecutedBranches; 51312109SRekai.GonzalezAlberquilla@arm.com /** Number of executed store instructions. */ 51412109SRekai.GonzalezAlberquilla@arm.com Stats::Formula iewExecStoreInsts; 51512109SRekai.GonzalezAlberquilla@arm.com /** Number of instructions executed per cycle. */ 51612109SRekai.GonzalezAlberquilla@arm.com Stats::Formula iewExecRate; 51712109SRekai.GonzalezAlberquilla@arm.com 51812109SRekai.GonzalezAlberquilla@arm.com /** Number of instructions sent to commit. */ 5199920Syasuko.eckert@amd.com Stats::Vector iewInstsToCommit; 5209920Syasuko.eckert@amd.com /** Number of instructions that writeback. */ 5219920Syasuko.eckert@amd.com Stats::Vector writebackCount; 5222SN/A /** Number of instructions that wake consumers. */ 5232680Sktlim@umich.edu Stats::Vector producerInst; 5242SN/A /** Number of instructions that wake up from producers. */ 5252455SN/A Stats::Vector consumerInst; 5262680Sktlim@umich.edu /** Number of instructions that were delayed in writing back due 5272SN/A * to resource contention. 5282455SN/A */ 5292680Sktlim@umich.edu Stats::Vector wbPenalized; 5302SN/A /** Number of instructions per cycle written back. */ 53112109SRekai.GonzalezAlberquilla@arm.com Stats::Formula wbRate; 53212109SRekai.GonzalezAlberquilla@arm.com /** Average number of woken instructions per writeback. */ 53312109SRekai.GonzalezAlberquilla@arm.com Stats::Formula wbFanout; 53412109SRekai.GonzalezAlberquilla@arm.com /** Number of instructions per cycle delayed in writing back . */ 53512109SRekai.GonzalezAlberquilla@arm.com Stats::Formula wbPenalizedRate; 53612109SRekai.GonzalezAlberquilla@arm.com}; 5379920Syasuko.eckert@amd.com 5389920Syasuko.eckert@amd.com#endif // __CPU_O3_IEW_HH__ 5399920Syasuko.eckert@amd.com