iew.hh revision 2863:2592e056dc5c
16145Snate@binkert.org/* 210012Snilay@cs.wisc.edu * Copyright (c) 2004-2006 The Regents of The University of Michigan 36145Snate@binkert.org * All rights reserved. 46145Snate@binkert.org * 56145Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66145Snate@binkert.org * modification, are permitted provided that the following conditions are 76145Snate@binkert.org * met: redistributions of source code must retain the above copyright 86145Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96145Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106145Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116145Snate@binkert.org * documentation and/or other materials provided with the distribution; 126145Snate@binkert.org * neither the name of the copyright holders nor the names of its 136145Snate@binkert.org * contributors may be used to endorse or promote products derived from 146145Snate@binkert.org * this software without specific prior written permission. 156145Snate@binkert.org * 166145Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145Snate@binkert.org * 286145Snate@binkert.org * Authors: Kevin Lim 296145Snate@binkert.org */ 306145Snate@binkert.org 316145Snate@binkert.org#ifndef __CPU_O3_IEW_HH__ 326145Snate@binkert.org#define __CPU_O3_IEW_HH__ 336145Snate@binkert.org 346145Snate@binkert.org#include <queue> 356145Snate@binkert.org 366145Snate@binkert.org#include "base/statistics.hh" 376145Snate@binkert.org#include "base/timebuf.hh" 386145Snate@binkert.org#include "config/full_system.hh" 396145Snate@binkert.org#include "cpu/o3/comm.hh" 406145Snate@binkert.org#include "cpu/o3/scoreboard.hh" 416145Snate@binkert.org#include "cpu/o3/lsq.hh" 426145Snate@binkert.org 436145Snate@binkert.orgclass FUPool; 446145Snate@binkert.org 4511309Sdavid.hashe@amd.com/** 4611309Sdavid.hashe@amd.com * DefaultIEW handles both single threaded and SMT IEW 478946Sandreas.hansson@arm.com * (issue/execute/writeback). It handles the dispatching of 488946Sandreas.hansson@arm.com * instructions to the LSQ/IQ as part of the issue stage, and has the 497002Snate@binkert.org * IQ try to issue instructions each cycle. The execute latency is 507454Snate@binkert.org * actually tied into the issue latency to allow the IQ to be able to 517832Snate@binkert.org * do back-to-back scheduling without having to speculatively schedule 527454Snate@binkert.org * instructions. This happens by having the IQ have access to the 537454Snate@binkert.org * functional units, and the IQ gets the execution latencies from the 547056Snate@binkert.org * FUs when it issues instructions. Instructions reach the execute 557048Snate@binkert.org * stage on the last cycle of their execution, which is when the IQ 567048Snate@binkert.org * knows to wake up any dependent instructions, allowing back to back 5714184Sgabeblack@google.com * scheduling. The execute portion of IEW separates memory 5814184Sgabeblack@google.com * instructions from non-memory instructions, either telling the LSQ 5911798Santhony.gutierrez@amd.com * to execute the instruction, or executing the instruction directly. 6011798Santhony.gutierrez@amd.com * The writeback portion of IEW completes the instructions by waking 6111798Santhony.gutierrez@amd.com * up any dependents, and marking the register ready on the 6211798Santhony.gutierrez@amd.com * scoreboard. 6311798Santhony.gutierrez@amd.com */ 6411798Santhony.gutierrez@amd.comtemplate<class Impl> 6511798Santhony.gutierrez@amd.comclass DefaultIEW 6611798Santhony.gutierrez@amd.com{ 6711798Santhony.gutierrez@amd.com private: 6811798Santhony.gutierrez@amd.com //Typedefs from Impl 6911798Santhony.gutierrez@amd.com typedef typename Impl::CPUPol CPUPol; 7011798Santhony.gutierrez@amd.com typedef typename Impl::DynInstPtr DynInstPtr; 7111798Santhony.gutierrez@amd.com typedef typename Impl::O3CPU O3CPU; 7211798Santhony.gutierrez@amd.com typedef typename Impl::Params Params; 7311798Santhony.gutierrez@amd.com 7411309Sdavid.hashe@amd.com typedef typename CPUPol::IQ IQ; 7514184Sgabeblack@google.com typedef typename CPUPol::RenameMap RenameMap; 7611798Santhony.gutierrez@amd.com typedef typename CPUPol::LSQ LSQ; 7711798Santhony.gutierrez@amd.com 789598Snilay@cs.wisc.edu typedef typename CPUPol::TimeStruct TimeStruct; 796876Ssteve.reinhardt@amd.com typedef typename CPUPol::IEWStruct IEWStruct; 807055Snate@binkert.org typedef typename CPUPol::RenameStruct RenameStruct; 817454Snate@binkert.org typedef typename CPUPol::IssueStruct IssueStruct; 827055Snate@binkert.org 8310920Sbrandon.potter@amd.com friend class Impl::O3CPU; 8411172Snilay@cs.wisc.edu friend class CPUPol::IQ; 8511172Snilay@cs.wisc.edu 8611172Snilay@cs.wisc.edu public: 876145Snate@binkert.org /** Overall IEW stage status. Used to determine if the CPU can 8810919Sbrandon.potter@amd.com * deschedule itself due to a lack of activity. 897048Snate@binkert.org */ 907048Snate@binkert.org enum Status { 916285Snate@binkert.org Active, 927048Snate@binkert.org Inactive 9310919Sbrandon.potter@amd.com }; 947048Snate@binkert.org 957048Snate@binkert.org /** Status for Issue, Execute, and Writeback stages. */ 967048Snate@binkert.org enum StageStatus { 976285Snate@binkert.org Running, 986285Snate@binkert.org Blocked, 996889SBrad.Beckmann@amd.com Idle, 1006889SBrad.Beckmann@amd.com StartSquash, 1017048Snate@binkert.org Squashing, 1027048Snate@binkert.org Unblocking 1037048Snate@binkert.org }; 10410012Snilay@cs.wisc.edu 1057048Snate@binkert.org private: 10610012Snilay@cs.wisc.edu /** Overall stage status. */ 10710012Snilay@cs.wisc.edu Status _status; 10810012Snilay@cs.wisc.edu /** Dispatch status. */ 10910012Snilay@cs.wisc.edu StageStatus dispatchStatus[Impl::MaxThreads]; 11010012Snilay@cs.wisc.edu /** Execute status. */ 11110012Snilay@cs.wisc.edu StageStatus exeStatus; 11210012Snilay@cs.wisc.edu /** Writeback status. */ 11310012Snilay@cs.wisc.edu StageStatus wbStatus; 11410012Snilay@cs.wisc.edu 11510012Snilay@cs.wisc.edu public: 11610012Snilay@cs.wisc.edu /** Constructs a DefaultIEW with the given parameters. */ 11710012Snilay@cs.wisc.edu DefaultIEW(Params *params); 11810012Snilay@cs.wisc.edu 11910012Snilay@cs.wisc.edu /** Returns the name of the DefaultIEW stage. */ 12011172Snilay@cs.wisc.edu std::string name() const; 12110012Snilay@cs.wisc.edu 12210012Snilay@cs.wisc.edu /** Registers statistics. */ 12310012Snilay@cs.wisc.edu void regStats(); 12410012Snilay@cs.wisc.edu 12510012Snilay@cs.wisc.edu /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 12610012Snilay@cs.wisc.edu void initStage(); 12710012Snilay@cs.wisc.edu 12810012Snilay@cs.wisc.edu /** Sets CPU pointer for IEW, IQ, and LSQ. */ 12911309Sdavid.hashe@amd.com void setCPU(O3CPU *cpu_ptr); 13010012Snilay@cs.wisc.edu 13111309Sdavid.hashe@amd.com /** Sets main time buffer used for backwards communication. */ 13210012Snilay@cs.wisc.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 13310012Snilay@cs.wisc.edu 13410012Snilay@cs.wisc.edu /** Sets time buffer for getting instructions coming from rename. */ 13511309Sdavid.hashe@amd.com void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 13610012Snilay@cs.wisc.edu 13711309Sdavid.hashe@amd.com /** Sets time buffer to pass on instructions to commit. */ 13810012Snilay@cs.wisc.edu void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 13910012Snilay@cs.wisc.edu 14010012Snilay@cs.wisc.edu /** Sets pointer to list of active threads. */ 14111309Sdavid.hashe@amd.com void setActiveThreads(std::list<unsigned> *at_ptr); 14210012Snilay@cs.wisc.edu 14311309Sdavid.hashe@amd.com /** Sets pointer to the scoreboard. */ 14410012Snilay@cs.wisc.edu void setScoreboard(Scoreboard *sb_ptr); 14510012Snilay@cs.wisc.edu 14610012Snilay@cs.wisc.edu /** Drains IEW stage. */ 14711309Sdavid.hashe@amd.com bool drain(); 14810012Snilay@cs.wisc.edu 14911309Sdavid.hashe@amd.com /** Resumes execution after a drain. */ 15011309Sdavid.hashe@amd.com void resume(); 15111309Sdavid.hashe@amd.com 15211309Sdavid.hashe@amd.com /** Completes switch out of IEW stage. */ 15311309Sdavid.hashe@amd.com void switchOut(); 15411309Sdavid.hashe@amd.com 15511309Sdavid.hashe@amd.com /** Takes over from another CPU's thread. */ 15611309Sdavid.hashe@amd.com void takeOverFrom(); 15711309Sdavid.hashe@amd.com 15811309Sdavid.hashe@amd.com /** Returns if IEW is switched out. */ 15911309Sdavid.hashe@amd.com bool isSwitchedOut() { return switchedOut; } 16011309Sdavid.hashe@amd.com 16111309Sdavid.hashe@amd.com /** Squashes instructions in IEW for a specific thread. */ 16211309Sdavid.hashe@amd.com void squash(unsigned tid); 16311309Sdavid.hashe@amd.com 16411309Sdavid.hashe@amd.com /** Wakes all dependents of a completed instruction. */ 16511309Sdavid.hashe@amd.com void wakeDependents(DynInstPtr &inst); 16611309Sdavid.hashe@amd.com 16711309Sdavid.hashe@amd.com /** Tells memory dependence unit that a memory instruction needs to be 16810012Snilay@cs.wisc.edu * rescheduled. It will re-execute once replayMemInst() is called. 16910012Snilay@cs.wisc.edu */ 17010012Snilay@cs.wisc.edu void rescheduleMemInst(DynInstPtr &inst); 17110012Snilay@cs.wisc.edu 17211309Sdavid.hashe@amd.com /** Re-executes all rescheduled memory instructions. */ 17311309Sdavid.hashe@amd.com void replayMemInst(DynInstPtr &inst); 17410012Snilay@cs.wisc.edu 17511309Sdavid.hashe@amd.com /** Sends an instruction to commit through the time buffer. */ 17610012Snilay@cs.wisc.edu void instToCommit(DynInstPtr &inst); 17710012Snilay@cs.wisc.edu 17810012Snilay@cs.wisc.edu /** Inserts unused instructions of a thread into the skid buffer. */ 17910012Snilay@cs.wisc.edu void skidInsert(unsigned tid); 18011309Sdavid.hashe@amd.com 18111309Sdavid.hashe@amd.com /** Returns the max of the number of entries in all of the skid buffers. */ 18210012Snilay@cs.wisc.edu int skidCount(); 18311309Sdavid.hashe@amd.com 18410012Snilay@cs.wisc.edu /** Returns if all of the skid buffers are empty. */ 18510012Snilay@cs.wisc.edu bool skidsEmpty(); 18610012Snilay@cs.wisc.edu 18710012Snilay@cs.wisc.edu /** Updates overall IEW status based on all of the stages' statuses. */ 18811309Sdavid.hashe@amd.com void updateStatus(); 18911309Sdavid.hashe@amd.com 19010012Snilay@cs.wisc.edu /** Resets entries of the IQ and the LSQ. */ 19111309Sdavid.hashe@amd.com void resetEntries(); 19211309Sdavid.hashe@amd.com 19311309Sdavid.hashe@amd.com /** Tells the CPU to wakeup if it has descheduled itself due to no 19411309Sdavid.hashe@amd.com * activity. Used mainly by the LdWritebackEvent. 19511309Sdavid.hashe@amd.com */ 19611309Sdavid.hashe@amd.com void wakeCPU(); 19711309Sdavid.hashe@amd.com 19811309Sdavid.hashe@amd.com /** Reports to the CPU that there is activity this cycle. */ 19911309Sdavid.hashe@amd.com void activityThisCycle(); 20011309Sdavid.hashe@amd.com 20111309Sdavid.hashe@amd.com /** Tells CPU that the IEW stage is active and running. */ 20211309Sdavid.hashe@amd.com inline void activateStage(); 20311309Sdavid.hashe@amd.com 20411309Sdavid.hashe@amd.com /** Tells CPU that the IEW stage is inactive and idle. */ 20511309Sdavid.hashe@amd.com inline void deactivateStage(); 20611309Sdavid.hashe@amd.com 20711309Sdavid.hashe@amd.com /** Returns if the LSQ has any stores to writeback. */ 20810012Snilay@cs.wisc.edu bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 20910012Snilay@cs.wisc.edu 21010012Snilay@cs.wisc.edu void incrWb(InstSeqNum &sn) 21110012Snilay@cs.wisc.edu { 21210012Snilay@cs.wisc.edu if (++wbOutstanding == wbMax) 21310012Snilay@cs.wisc.edu ableToIssue = false; 21411309Sdavid.hashe@amd.com DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); 21511309Sdavid.hashe@amd.com#if DEBUG 21610012Snilay@cs.wisc.edu wbList.insert(sn); 21711309Sdavid.hashe@amd.com#endif 21810012Snilay@cs.wisc.edu } 21910012Snilay@cs.wisc.edu 22010012Snilay@cs.wisc.edu void decrWb(InstSeqNum &sn) 22110012Snilay@cs.wisc.edu { 22211309Sdavid.hashe@amd.com if (wbOutstanding-- == wbMax) 22311309Sdavid.hashe@amd.com ableToIssue = true; 22410012Snilay@cs.wisc.edu DPRINTF(IEW, "wbOutstanding: %i\n", wbOutstanding); 22511309Sdavid.hashe@amd.com#if DEBUG 22610012Snilay@cs.wisc.edu assert(wbList.find(sn) != wbList.end()); 22710012Snilay@cs.wisc.edu wbList.erase(sn); 22810012Snilay@cs.wisc.edu#endif 22910012Snilay@cs.wisc.edu } 23011309Sdavid.hashe@amd.com 23111309Sdavid.hashe@amd.com#if DEBUG 23211309Sdavid.hashe@amd.com std::set<InstSeqNum> wbList; 23311309Sdavid.hashe@amd.com 23411309Sdavid.hashe@amd.com void dumpWb() 23511309Sdavid.hashe@amd.com { 23611309Sdavid.hashe@amd.com std::set<InstSeqNum>::iterator wb_it = wbList.begin(); 23711309Sdavid.hashe@amd.com while (wb_it != wbList.end()) { 23811309Sdavid.hashe@amd.com cprintf("[sn:%lli]\n", 23911309Sdavid.hashe@amd.com (*wb_it)); 24010012Snilay@cs.wisc.edu wb_it++; 24110012Snilay@cs.wisc.edu } 24211309Sdavid.hashe@amd.com } 24310012Snilay@cs.wisc.edu#endif 24410012Snilay@cs.wisc.edu 24510012Snilay@cs.wisc.edu bool canIssue() { return ableToIssue; } 24610012Snilay@cs.wisc.edu 24711309Sdavid.hashe@amd.com bool ableToIssue; 24811309Sdavid.hashe@amd.com 24910012Snilay@cs.wisc.edu private: 25011309Sdavid.hashe@amd.com /** Sends commit proper information for a squash due to a branch 25111309Sdavid.hashe@amd.com * mispredict. 25211309Sdavid.hashe@amd.com */ 25311309Sdavid.hashe@amd.com void squashDueToBranch(DynInstPtr &inst, unsigned thread_id); 25411309Sdavid.hashe@amd.com 25511309Sdavid.hashe@amd.com /** Sends commit proper information for a squash due to a memory order 25611309Sdavid.hashe@amd.com * violation. 25711309Sdavid.hashe@amd.com */ 25811309Sdavid.hashe@amd.com void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id); 25911309Sdavid.hashe@amd.com 26010012Snilay@cs.wisc.edu /** Sends commit proper information for a squash due to memory becoming 26110012Snilay@cs.wisc.edu * blocked (younger issued instructions must be retried). 26210012Snilay@cs.wisc.edu */ 26310012Snilay@cs.wisc.edu void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id); 26411309Sdavid.hashe@amd.com 26511309Sdavid.hashe@amd.com /** Sets Dispatch to blocked, and signals back to other stages to block. */ 26611309Sdavid.hashe@amd.com void block(unsigned thread_id); 26711309Sdavid.hashe@amd.com 26811309Sdavid.hashe@amd.com /** Unblocks Dispatch if the skid buffer is empty, and signals back to 26911309Sdavid.hashe@amd.com * other stages to unblock. 27011309Sdavid.hashe@amd.com */ 27111309Sdavid.hashe@amd.com void unblock(unsigned thread_id); 27211309Sdavid.hashe@amd.com 27311309Sdavid.hashe@amd.com /** Determines proper actions to take given Dispatch's status. */ 27410012Snilay@cs.wisc.edu void dispatch(unsigned tid); 27510012Snilay@cs.wisc.edu 27611309Sdavid.hashe@amd.com /** Dispatches instructions to IQ and LSQ. */ 27710012Snilay@cs.wisc.edu void dispatchInsts(unsigned tid); 27810012Snilay@cs.wisc.edu 27910012Snilay@cs.wisc.edu /** Executes instructions. In the case of memory operations, it informs the 28010012Snilay@cs.wisc.edu * LSQ to execute the instructions. Also handles any redirects that occur 28111309Sdavid.hashe@amd.com * due to the executed instructions. 28211309Sdavid.hashe@amd.com */ 28310012Snilay@cs.wisc.edu void executeInsts(); 28410012Snilay@cs.wisc.edu 28511309Sdavid.hashe@amd.com /** Writebacks instructions. In our model, the instruction's execute() 28610012Snilay@cs.wisc.edu * function atomically reads registers, executes, and writes registers. 28710012Snilay@cs.wisc.edu * Thus this writeback only wakes up dependent instructions, and informs 28810012Snilay@cs.wisc.edu * the scoreboard of registers becoming ready. 28910012Snilay@cs.wisc.edu */ 29011309Sdavid.hashe@amd.com void writebackInsts(); 29111309Sdavid.hashe@amd.com 29211309Sdavid.hashe@amd.com /** Returns the number of valid, non-squashed instructions coming from 29311309Sdavid.hashe@amd.com * rename to dispatch. 29411309Sdavid.hashe@amd.com */ 29511309Sdavid.hashe@amd.com unsigned validInstsFromRename(); 29611309Sdavid.hashe@amd.com 29711309Sdavid.hashe@amd.com /** Reads the stall signals. */ 29811309Sdavid.hashe@amd.com void readStallSignals(unsigned tid); 29911309Sdavid.hashe@amd.com 30011309Sdavid.hashe@amd.com /** Checks if any of the stall conditions are currently true. */ 30111309Sdavid.hashe@amd.com bool checkStall(unsigned tid); 30211309Sdavid.hashe@amd.com 30311309Sdavid.hashe@amd.com /** Processes inputs and changes state accordingly. */ 30411309Sdavid.hashe@amd.com void checkSignalsAndUpdate(unsigned tid); 30511309Sdavid.hashe@amd.com 30611309Sdavid.hashe@amd.com /** Removes instructions from rename from a thread's instruction list. */ 30711309Sdavid.hashe@amd.com void emptyRenameInsts(unsigned tid); 30811309Sdavid.hashe@amd.com 30911309Sdavid.hashe@amd.com /** Sorts instructions coming from rename into lists separated by thread. */ 31010012Snilay@cs.wisc.edu void sortInsts(); 31110012Snilay@cs.wisc.edu 31210012Snilay@cs.wisc.edu public: 31310012Snilay@cs.wisc.edu /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 31410012Snilay@cs.wisc.edu * Writeback to run for one cycle. 31511309Sdavid.hashe@amd.com */ 31611309Sdavid.hashe@amd.com void tick(); 31711309Sdavid.hashe@amd.com 31810012Snilay@cs.wisc.edu private: 31910012Snilay@cs.wisc.edu /** Updates execution stats based on the instruction. */ 32011309Sdavid.hashe@amd.com void updateExeInstStats(DynInstPtr &inst); 32111309Sdavid.hashe@amd.com 32210012Snilay@cs.wisc.edu /** Pointer to main time buffer used for backwards communication. */ 32311309Sdavid.hashe@amd.com TimeBuffer<TimeStruct> *timeBuffer; 32410012Snilay@cs.wisc.edu 32510012Snilay@cs.wisc.edu /** Wire to write information heading to previous stages. */ 32610012Snilay@cs.wisc.edu typename TimeBuffer<TimeStruct>::wire toFetch; 32710012Snilay@cs.wisc.edu 32811309Sdavid.hashe@amd.com /** Wire to get commit's output from backwards time buffer. */ 32911309Sdavid.hashe@amd.com typename TimeBuffer<TimeStruct>::wire fromCommit; 33010012Snilay@cs.wisc.edu 33111309Sdavid.hashe@amd.com /** Wire to write information heading to previous stages. */ 33211309Sdavid.hashe@amd.com typename TimeBuffer<TimeStruct>::wire toRename; 33311309Sdavid.hashe@amd.com 33411309Sdavid.hashe@amd.com /** Rename instruction queue interface. */ 33511309Sdavid.hashe@amd.com TimeBuffer<RenameStruct> *renameQueue; 33611309Sdavid.hashe@amd.com 33711309Sdavid.hashe@amd.com /** Wire to get rename's output from rename queue. */ 33811309Sdavid.hashe@amd.com typename TimeBuffer<RenameStruct>::wire fromRename; 33911309Sdavid.hashe@amd.com 34010012Snilay@cs.wisc.edu /** Issue stage queue. */ 34110012Snilay@cs.wisc.edu TimeBuffer<IssueStruct> issueToExecQueue; 34210012Snilay@cs.wisc.edu 34310012Snilay@cs.wisc.edu /** Wire to read information from the issue stage time queue. */ 34410012Snilay@cs.wisc.edu typename TimeBuffer<IssueStruct>::wire fromIssue; 3457048Snate@binkert.org 3467048Snate@binkert.org /** 3477048Snate@binkert.org * IEW stage time buffer. Holds ROB indices of instructions that 34810012Snilay@cs.wisc.edu * can be marked as completed. 3499496Snilay@cs.wisc.edu */ 35010012Snilay@cs.wisc.edu TimeBuffer<IEWStruct> *iewQueue; 35110012Snilay@cs.wisc.edu 3529496Snilay@cs.wisc.edu /** Wire to write infromation heading to commit. */ 3539496Snilay@cs.wisc.edu typename TimeBuffer<IEWStruct>::wire toCommit; 35410012Snilay@cs.wisc.edu 35510012Snilay@cs.wisc.edu /** Queue of all instructions coming from rename this cycle. */ 3569496Snilay@cs.wisc.edu std::queue<DynInstPtr> insts[Impl::MaxThreads]; 3579497Snilay@cs.wisc.edu 3589497Snilay@cs.wisc.edu /** Skid buffer between rename and IEW. */ 3599497Snilay@cs.wisc.edu std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 36010920Sbrandon.potter@amd.com 36110920Sbrandon.potter@amd.com /** Scoreboard pointer. */ 3629497Snilay@cs.wisc.edu Scoreboard* scoreboard; 3639497Snilay@cs.wisc.edu 3649497Snilay@cs.wisc.edu public: 3659497Snilay@cs.wisc.edu /** Instruction queue. */ 36611172Snilay@cs.wisc.edu IQ instQueue; 36710012Snilay@cs.wisc.edu 3689497Snilay@cs.wisc.edu /** Load / store queue. */ 3699497Snilay@cs.wisc.edu LSQ ldstQueue; 3709497Snilay@cs.wisc.edu 3719497Snilay@cs.wisc.edu /** Pointer to the functional unit pool. */ 3729598Snilay@cs.wisc.edu FUPool *fuPool; 3739598Snilay@cs.wisc.edu 37410920Sbrandon.potter@amd.com private: 37510920Sbrandon.potter@amd.com /** CPU pointer. */ 3769598Snilay@cs.wisc.edu O3CPU *cpu; 3779598Snilay@cs.wisc.edu 37811308Santhony.gutierrez@amd.com /** Records if IEW has written to the time buffer this cycle, so that the 3799598Snilay@cs.wisc.edu * CPU can deschedule itself if there is no activity. 38011309Sdavid.hashe@amd.com */ 38111309Sdavid.hashe@amd.com bool wroteToTimeBuffer; 38211798Santhony.gutierrez@amd.com 38311309Sdavid.hashe@amd.com /** Source of possible stalls. */ 38411309Sdavid.hashe@amd.com struct Stalls { 38511309Sdavid.hashe@amd.com bool commit; 3869598Snilay@cs.wisc.edu }; 38711798Santhony.gutierrez@amd.com 3889598Snilay@cs.wisc.edu /** Stages that are telling IEW to stall. */ 3899598Snilay@cs.wisc.edu Stalls stalls[Impl::MaxThreads]; 3909598Snilay@cs.wisc.edu 3919773Snilay@cs.wisc.edu /** Debug function to print instructions that are issued this cycle. */ 3929773Snilay@cs.wisc.edu void printAvailableInsts(); 39310920Sbrandon.potter@amd.com 39410920Sbrandon.potter@amd.com public: 3959773Snilay@cs.wisc.edu /** Records if the LSQ needs to be updated on the next cycle, so that 3969773Snilay@cs.wisc.edu * IEW knows if there will be activity on the next cycle. 39711308Santhony.gutierrez@amd.com */ 3989773Snilay@cs.wisc.edu bool updateLSQNextCycle; 3999773Snilay@cs.wisc.edu 40011309Sdavid.hashe@amd.com private: 40111309Sdavid.hashe@amd.com /** Records if there is a fetch redirect on this cycle for each thread. */ 40211309Sdavid.hashe@amd.com bool fetchRedirect[Impl::MaxThreads]; 4039773Snilay@cs.wisc.edu 4049773Snilay@cs.wisc.edu /** Used to track if all instructions have been dispatched this cycle. 4059773Snilay@cs.wisc.edu * If they have not, then blocking must have occurred, and the instructions 40611309Sdavid.hashe@amd.com * would already be added to the skid buffer. 40710012Snilay@cs.wisc.edu * @todo: Fix this hack. 40811309Sdavid.hashe@amd.com */ 40910012Snilay@cs.wisc.edu bool dispatchedAllInsts; 41011309Sdavid.hashe@amd.com 41110012Snilay@cs.wisc.edu /** Records if the queues have been changed (inserted or issued insts), 4129773Snilay@cs.wisc.edu * so that IEW knows to broadcast the updated amount of free entries. 4139773Snilay@cs.wisc.edu */ 4149773Snilay@cs.wisc.edu bool updatedQueues; 4159773Snilay@cs.wisc.edu 41611309Sdavid.hashe@amd.com /** Commit to IEW delay, in ticks. */ 41710012Snilay@cs.wisc.edu unsigned commitToIEWDelay; 41811309Sdavid.hashe@amd.com 41910012Snilay@cs.wisc.edu /** Rename to IEW delay, in ticks. */ 4209773Snilay@cs.wisc.edu unsigned renameToIEWDelay; 42111309Sdavid.hashe@amd.com 4229773Snilay@cs.wisc.edu /** 4239773Snilay@cs.wisc.edu * Issue to execute delay, in ticks. What this actually represents is 42411309Sdavid.hashe@amd.com * the amount of time it takes for an instruction to wake up, be 4259773Snilay@cs.wisc.edu * scheduled, and sent to a FU for execution. 42611309Sdavid.hashe@amd.com */ 4279773Snilay@cs.wisc.edu unsigned issueToExecuteDelay; 4289773Snilay@cs.wisc.edu 42911309Sdavid.hashe@amd.com /** Width of dispatch, in instructions. */ 43010012Snilay@cs.wisc.edu unsigned dispatchWidth; 43110012Snilay@cs.wisc.edu 43211309Sdavid.hashe@amd.com /** Width of issue, in instructions. */ 4339773Snilay@cs.wisc.edu unsigned issueWidth; 4349773Snilay@cs.wisc.edu 4359773Snilay@cs.wisc.edu /** Index into queue of instructions being written back. */ 4369773Snilay@cs.wisc.edu unsigned wbNumInst; 4379773Snilay@cs.wisc.edu 4389773Snilay@cs.wisc.edu /** Cycle number within the queue of instructions being written back. 43911309Sdavid.hashe@amd.com * Used in case there are too many instructions writing back at the current 44010012Snilay@cs.wisc.edu * cycle and writesbacks need to be scheduled for the future. See comments 44111309Sdavid.hashe@amd.com * in instToCommit(). 44210012Snilay@cs.wisc.edu */ 4439773Snilay@cs.wisc.edu unsigned wbCycle; 4449773Snilay@cs.wisc.edu 4459773Snilay@cs.wisc.edu /** Number of instructions in flight that will writeback. */ 44611798Santhony.gutierrez@amd.com unsigned wbOutstanding; 44711309Sdavid.hashe@amd.com 44811309Sdavid.hashe@amd.com /** Writeback width. */ 44911309Sdavid.hashe@amd.com unsigned wbWidth; 45011309Sdavid.hashe@amd.com 45111309Sdavid.hashe@amd.com /** Writeback width * writeback depth, where writeback depth is 45211309Sdavid.hashe@amd.com * the number of cycles of writing back instructions that can be 45311309Sdavid.hashe@amd.com * buffered. */ 45411309Sdavid.hashe@amd.com unsigned wbMax; 45511309Sdavid.hashe@amd.com 45611309Sdavid.hashe@amd.com /** Number of active threads. */ 45711309Sdavid.hashe@amd.com unsigned numThreads; 45811309Sdavid.hashe@amd.com 45911309Sdavid.hashe@amd.com /** Pointer to list of active threads. */ 46011309Sdavid.hashe@amd.com std::list<unsigned> *activeThreads; 46111309Sdavid.hashe@amd.com 46211309Sdavid.hashe@amd.com /** Maximum size of the skid buffer. */ 46311309Sdavid.hashe@amd.com unsigned skidBufferMax; 46411309Sdavid.hashe@amd.com 46511309Sdavid.hashe@amd.com /** Is this stage switched out. */ 46611309Sdavid.hashe@amd.com bool switchedOut; 46711309Sdavid.hashe@amd.com 46811309Sdavid.hashe@amd.com /** Stat for total number of idle cycles. */ 46911309Sdavid.hashe@amd.com Stats::Scalar<> iewIdleCycles; 47011309Sdavid.hashe@amd.com /** Stat for total number of squashing cycles. */ 47111309Sdavid.hashe@amd.com Stats::Scalar<> iewSquashCycles; 47211309Sdavid.hashe@amd.com /** Stat for total number of blocking cycles. */ 47311309Sdavid.hashe@amd.com Stats::Scalar<> iewBlockCycles; 47411309Sdavid.hashe@amd.com /** Stat for total number of unblocking cycles. */ 47511309Sdavid.hashe@amd.com Stats::Scalar<> iewUnblockCycles; 47611309Sdavid.hashe@amd.com /** Stat for total number of instructions dispatched. */ 47711309Sdavid.hashe@amd.com Stats::Scalar<> iewDispatchedInsts; 47811309Sdavid.hashe@amd.com /** Stat for total number of squashed instructions dispatch skips. */ 47911309Sdavid.hashe@amd.com Stats::Scalar<> iewDispSquashedInsts; 48011309Sdavid.hashe@amd.com /** Stat for total number of dispatched load instructions. */ 48111309Sdavid.hashe@amd.com Stats::Scalar<> iewDispLoadInsts; 48211309Sdavid.hashe@amd.com /** Stat for total number of dispatched store instructions. */ 48311309Sdavid.hashe@amd.com Stats::Scalar<> iewDispStoreInsts; 48411309Sdavid.hashe@amd.com /** Stat for total number of dispatched non speculative instructions. */ 48511309Sdavid.hashe@amd.com Stats::Scalar<> iewDispNonSpecInsts; 48611309Sdavid.hashe@amd.com /** Stat for number of times the IQ becomes full. */ 48711798Santhony.gutierrez@amd.com Stats::Scalar<> iewIQFullEvents; 4889773Snilay@cs.wisc.edu /** Stat for number of times the LSQ becomes full. */ 4899773Snilay@cs.wisc.edu Stats::Scalar<> iewLSQFullEvents; 4906145Snate@binkert.org /** Stat for total number of memory ordering violation events. */ 4916145Snate@binkert.org Stats::Scalar<> memOrderViolationEvents; 4927048Snate@binkert.org /** Stat for total number of incorrect predicted taken branches. */ 4938174Snilay@cs.wisc.edu Stats::Scalar<> predictedTakenIncorrect; 4946145Snate@binkert.org /** Stat for total number of incorrect predicted not taken branches. */ 4958165Snilay@cs.wisc.edu Stats::Scalar<> predictedNotTakenIncorrect; 4967048Snate@binkert.org /** Stat for total number of mispredicted branches detected at execute. */ 4977048Snate@binkert.org Stats::Formula branchMispredicts; 4987048Snate@binkert.org 4996145Snate@binkert.org /** Stat for total number of executed instructions. */ 5007048Snate@binkert.org Stats::Scalar<> iewExecutedInsts; 5017048Snate@binkert.org /** Stat for total number of executed load instructions. */ 5027048Snate@binkert.org Stats::Vector<> iewExecLoadInsts; 5037048Snate@binkert.org /** Stat for total number of squashed instructions skipped at execute. */ 5047048Snate@binkert.org Stats::Scalar<> iewExecSquashedInsts; 5057048Snate@binkert.org /** Number of executed software prefetches. */ 5066145Snate@binkert.org Stats::Vector<> iewExecutedSwp; 507 /** Number of executed nops. */ 508 Stats::Vector<> iewExecutedNop; 509 /** Number of executed meomory references. */ 510 Stats::Vector<> iewExecutedRefs; 511 /** Number of executed branches. */ 512 Stats::Vector<> iewExecutedBranches; 513 /** Number of executed store instructions. */ 514 Stats::Formula iewExecStoreInsts; 515 /** Number of instructions executed per cycle. */ 516 Stats::Formula iewExecRate; 517 518 /** Number of instructions sent to commit. */ 519 Stats::Vector<> iewInstsToCommit; 520 /** Number of instructions that writeback. */ 521 Stats::Vector<> writebackCount; 522 /** Number of instructions that wake consumers. */ 523 Stats::Vector<> producerInst; 524 /** Number of instructions that wake up from producers. */ 525 Stats::Vector<> consumerInst; 526 /** Number of instructions that were delayed in writing back due 527 * to resource contention. 528 */ 529 Stats::Vector<> wbPenalized; 530 /** Number of instructions per cycle written back. */ 531 Stats::Formula wbRate; 532 /** Average number of woken instructions per writeback. */ 533 Stats::Formula wbFanout; 534 /** Number of instructions per cycle delayed in writing back . */ 535 Stats::Formula wbPenalizedRate; 536}; 537 538#endif // __CPU_O3_IEW_HH__ 539