iew.hh revision 2733:e0eac8fc5774
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Kevin Lim 29 */ 30 31#ifndef __CPU_O3_IEW_HH__ 32#define __CPU_O3_IEW_HH__ 33 34#include <queue> 35 36#include "base/statistics.hh" 37#include "base/timebuf.hh" 38#include "config/full_system.hh" 39#include "cpu/o3/comm.hh" 40#include "cpu/o3/scoreboard.hh" 41#include "cpu/o3/lsq.hh" 42 43class FUPool; 44 45/** 46 * DefaultIEW handles both single threaded and SMT IEW 47 * (issue/execute/writeback). It handles the dispatching of 48 * instructions to the LSQ/IQ as part of the issue stage, and has the 49 * IQ try to issue instructions each cycle. The execute latency is 50 * actually tied into the issue latency to allow the IQ to be able to 51 * do back-to-back scheduling without having to speculatively schedule 52 * instructions. This happens by having the IQ have access to the 53 * functional units, and the IQ gets the execution latencies from the 54 * FUs when it issues instructions. Instructions reach the execute 55 * stage on the last cycle of their execution, which is when the IQ 56 * knows to wake up any dependent instructions, allowing back to back 57 * scheduling. The execute portion of IEW separates memory 58 * instructions from non-memory instructions, either telling the LSQ 59 * to execute the instruction, or executing the instruction directly. 60 * The writeback portion of IEW completes the instructions by waking 61 * up any dependents, and marking the register ready on the 62 * scoreboard. 63 */ 64template<class Impl> 65class DefaultIEW 66{ 67 private: 68 //Typedefs from Impl 69 typedef typename Impl::CPUPol CPUPol; 70 typedef typename Impl::DynInstPtr DynInstPtr; 71 typedef typename Impl::O3CPU O3CPU; 72 typedef typename Impl::Params Params; 73 74 typedef typename CPUPol::IQ IQ; 75 typedef typename CPUPol::RenameMap RenameMap; 76 typedef typename CPUPol::LSQ LSQ; 77 78 typedef typename CPUPol::TimeStruct TimeStruct; 79 typedef typename CPUPol::IEWStruct IEWStruct; 80 typedef typename CPUPol::RenameStruct RenameStruct; 81 typedef typename CPUPol::IssueStruct IssueStruct; 82 83 friend class Impl::O3CPU; 84 friend class CPUPol::IQ; 85 86 public: 87 /** Overall IEW stage status. Used to determine if the CPU can 88 * deschedule itself due to a lack of activity. 89 */ 90 enum Status { 91 Active, 92 Inactive 93 }; 94 95 /** Status for Issue, Execute, and Writeback stages. */ 96 enum StageStatus { 97 Running, 98 Blocked, 99 Idle, 100 StartSquash, 101 Squashing, 102 Unblocking 103 }; 104 105 private: 106 /** Overall stage status. */ 107 Status _status; 108 /** Dispatch status. */ 109 StageStatus dispatchStatus[Impl::MaxThreads]; 110 /** Execute status. */ 111 StageStatus exeStatus; 112 /** Writeback status. */ 113 StageStatus wbStatus; 114 115 public: 116 /** Constructs a DefaultIEW with the given parameters. */ 117 DefaultIEW(Params *params); 118 119 /** Returns the name of the DefaultIEW stage. */ 120 std::string name() const; 121 122 /** Registers statistics. */ 123 void regStats(); 124 125 /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 126 void initStage(); 127 128 /** Sets CPU pointer for IEW, IQ, and LSQ. */ 129 void setCPU(O3CPU *cpu_ptr); 130 131 /** Sets main time buffer used for backwards communication. */ 132 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 133 134 /** Sets time buffer for getting instructions coming from rename. */ 135 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 136 137 /** Sets time buffer to pass on instructions to commit. */ 138 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 139 140 /** Sets pointer to list of active threads. */ 141 void setActiveThreads(std::list<unsigned> *at_ptr); 142 143 /** Sets pointer to the scoreboard. */ 144 void setScoreboard(Scoreboard *sb_ptr); 145 146 /** Starts switch out of IEW stage. */ 147 void switchOut(); 148 149 /** Completes switch out of IEW stage. */ 150 void doSwitchOut(); 151 152 /** Takes over from another CPU's thread. */ 153 void takeOverFrom(); 154 155 /** Returns if IEW is switched out. */ 156 bool isSwitchedOut() { return switchedOut; } 157 158 /** Squashes instructions in IEW for a specific thread. */ 159 void squash(unsigned tid); 160 161 /** Wakes all dependents of a completed instruction. */ 162 void wakeDependents(DynInstPtr &inst); 163 164 /** Tells memory dependence unit that a memory instruction needs to be 165 * rescheduled. It will re-execute once replayMemInst() is called. 166 */ 167 void rescheduleMemInst(DynInstPtr &inst); 168 169 /** Re-executes all rescheduled memory instructions. */ 170 void replayMemInst(DynInstPtr &inst); 171 172 /** Sends an instruction to commit through the time buffer. */ 173 void instToCommit(DynInstPtr &inst); 174 175 /** Inserts unused instructions of a thread into the skid buffer. */ 176 void skidInsert(unsigned tid); 177 178 /** Returns the max of the number of entries in all of the skid buffers. */ 179 int skidCount(); 180 181 /** Returns if all of the skid buffers are empty. */ 182 bool skidsEmpty(); 183 184 /** Updates overall IEW status based on all of the stages' statuses. */ 185 void updateStatus(); 186 187 /** Resets entries of the IQ and the LSQ. */ 188 void resetEntries(); 189 190 /** Tells the CPU to wakeup if it has descheduled itself due to no 191 * activity. Used mainly by the LdWritebackEvent. 192 */ 193 void wakeCPU(); 194 195 /** Reports to the CPU that there is activity this cycle. */ 196 void activityThisCycle(); 197 198 /** Tells CPU that the IEW stage is active and running. */ 199 inline void activateStage(); 200 201 /** Tells CPU that the IEW stage is inactive and idle. */ 202 inline void deactivateStage(); 203 204 /** Returns if the LSQ has any stores to writeback. */ 205 bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 206 207 private: 208 /** Sends commit proper information for a squash due to a branch 209 * mispredict. 210 */ 211 void squashDueToBranch(DynInstPtr &inst, unsigned thread_id); 212 213 /** Sends commit proper information for a squash due to a memory order 214 * violation. 215 */ 216 void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id); 217 218 /** Sends commit proper information for a squash due to memory becoming 219 * blocked (younger issued instructions must be retried). 220 */ 221 void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id); 222 223 /** Sets Dispatch to blocked, and signals back to other stages to block. */ 224 void block(unsigned thread_id); 225 226 /** Unblocks Dispatch if the skid buffer is empty, and signals back to 227 * other stages to unblock. 228 */ 229 void unblock(unsigned thread_id); 230 231 /** Determines proper actions to take given Dispatch's status. */ 232 void dispatch(unsigned tid); 233 234 /** Dispatches instructions to IQ and LSQ. */ 235 void dispatchInsts(unsigned tid); 236 237 /** Executes instructions. In the case of memory operations, it informs the 238 * LSQ to execute the instructions. Also handles any redirects that occur 239 * due to the executed instructions. 240 */ 241 void executeInsts(); 242 243 /** Writebacks instructions. In our model, the instruction's execute() 244 * function atomically reads registers, executes, and writes registers. 245 * Thus this writeback only wakes up dependent instructions, and informs 246 * the scoreboard of registers becoming ready. 247 */ 248 void writebackInsts(); 249 250 /** Returns the number of valid, non-squashed instructions coming from 251 * rename to dispatch. 252 */ 253 unsigned validInstsFromRename(); 254 255 /** Reads the stall signals. */ 256 void readStallSignals(unsigned tid); 257 258 /** Checks if any of the stall conditions are currently true. */ 259 bool checkStall(unsigned tid); 260 261 /** Processes inputs and changes state accordingly. */ 262 void checkSignalsAndUpdate(unsigned tid); 263 264 /** Removes instructions from rename from a thread's instruction list. */ 265 void emptyRenameInsts(unsigned tid); 266 267 /** Sorts instructions coming from rename into lists separated by thread. */ 268 void sortInsts(); 269 270 public: 271 /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 272 * Writeback to run for one cycle. 273 */ 274 void tick(); 275 276 private: 277 /** Updates execution stats based on the instruction. */ 278 void updateExeInstStats(DynInstPtr &inst); 279 280 /** Pointer to main time buffer used for backwards communication. */ 281 TimeBuffer<TimeStruct> *timeBuffer; 282 283 /** Wire to write information heading to previous stages. */ 284 typename TimeBuffer<TimeStruct>::wire toFetch; 285 286 /** Wire to get commit's output from backwards time buffer. */ 287 typename TimeBuffer<TimeStruct>::wire fromCommit; 288 289 /** Wire to write information heading to previous stages. */ 290 typename TimeBuffer<TimeStruct>::wire toRename; 291 292 /** Rename instruction queue interface. */ 293 TimeBuffer<RenameStruct> *renameQueue; 294 295 /** Wire to get rename's output from rename queue. */ 296 typename TimeBuffer<RenameStruct>::wire fromRename; 297 298 /** Issue stage queue. */ 299 TimeBuffer<IssueStruct> issueToExecQueue; 300 301 /** Wire to read information from the issue stage time queue. */ 302 typename TimeBuffer<IssueStruct>::wire fromIssue; 303 304 /** 305 * IEW stage time buffer. Holds ROB indices of instructions that 306 * can be marked as completed. 307 */ 308 TimeBuffer<IEWStruct> *iewQueue; 309 310 /** Wire to write infromation heading to commit. */ 311 typename TimeBuffer<IEWStruct>::wire toCommit; 312 313 /** Queue of all instructions coming from rename this cycle. */ 314 std::queue<DynInstPtr> insts[Impl::MaxThreads]; 315 316 /** Skid buffer between rename and IEW. */ 317 std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 318 319 /** Scoreboard pointer. */ 320 Scoreboard* scoreboard; 321 322 public: 323 /** Instruction queue. */ 324 IQ instQueue; 325 326 /** Load / store queue. */ 327 LSQ ldstQueue; 328 329 /** Pointer to the functional unit pool. */ 330 FUPool *fuPool; 331 332 private: 333 /** CPU pointer. */ 334 O3CPU *cpu; 335 336 /** Records if IEW has written to the time buffer this cycle, so that the 337 * CPU can deschedule itself if there is no activity. 338 */ 339 bool wroteToTimeBuffer; 340 341 /** Source of possible stalls. */ 342 struct Stalls { 343 bool commit; 344 }; 345 346 /** Stages that are telling IEW to stall. */ 347 Stalls stalls[Impl::MaxThreads]; 348 349 /** Debug function to print instructions that are issued this cycle. */ 350 void printAvailableInsts(); 351 352 public: 353 /** Records if the LSQ needs to be updated on the next cycle, so that 354 * IEW knows if there will be activity on the next cycle. 355 */ 356 bool updateLSQNextCycle; 357 358 private: 359 /** Records if there is a fetch redirect on this cycle for each thread. */ 360 bool fetchRedirect[Impl::MaxThreads]; 361 362 /** Used to track if all instructions have been dispatched this cycle. 363 * If they have not, then blocking must have occurred, and the instructions 364 * would already be added to the skid buffer. 365 * @todo: Fix this hack. 366 */ 367 bool dispatchedAllInsts; 368 369 /** Records if the queues have been changed (inserted or issued insts), 370 * so that IEW knows to broadcast the updated amount of free entries. 371 */ 372 bool updatedQueues; 373 374 /** Commit to IEW delay, in ticks. */ 375 unsigned commitToIEWDelay; 376 377 /** Rename to IEW delay, in ticks. */ 378 unsigned renameToIEWDelay; 379 380 /** 381 * Issue to execute delay, in ticks. What this actually represents is 382 * the amount of time it takes for an instruction to wake up, be 383 * scheduled, and sent to a FU for execution. 384 */ 385 unsigned issueToExecuteDelay; 386 387 /** Width of issue's read path, in instructions. The read path is both 388 * the skid buffer and the rename instruction queue. 389 * Note to self: is this really different than issueWidth? 390 */ 391 unsigned issueReadWidth; 392 393 /** Width of issue, in instructions. */ 394 unsigned issueWidth; 395 396 /** Index into queue of instructions being written back. */ 397 unsigned wbNumInst; 398 399 /** Cycle number within the queue of instructions being written back. 400 * Used in case there are too many instructions writing back at the current 401 * cycle and writesbacks need to be scheduled for the future. See comments 402 * in instToCommit(). 403 */ 404 unsigned wbCycle; 405 406 /** Number of active threads. */ 407 unsigned numThreads; 408 409 /** Pointer to list of active threads. */ 410 std::list<unsigned> *activeThreads; 411 412 /** Maximum size of the skid buffer. */ 413 unsigned skidBufferMax; 414 415 /** Is this stage switched out. */ 416 bool switchedOut; 417 418 /** Stat for total number of idle cycles. */ 419 Stats::Scalar<> iewIdleCycles; 420 /** Stat for total number of squashing cycles. */ 421 Stats::Scalar<> iewSquashCycles; 422 /** Stat for total number of blocking cycles. */ 423 Stats::Scalar<> iewBlockCycles; 424 /** Stat for total number of unblocking cycles. */ 425 Stats::Scalar<> iewUnblockCycles; 426 /** Stat for total number of instructions dispatched. */ 427 Stats::Scalar<> iewDispatchedInsts; 428 /** Stat for total number of squashed instructions dispatch skips. */ 429 Stats::Scalar<> iewDispSquashedInsts; 430 /** Stat for total number of dispatched load instructions. */ 431 Stats::Scalar<> iewDispLoadInsts; 432 /** Stat for total number of dispatched store instructions. */ 433 Stats::Scalar<> iewDispStoreInsts; 434 /** Stat for total number of dispatched non speculative instructions. */ 435 Stats::Scalar<> iewDispNonSpecInsts; 436 /** Stat for number of times the IQ becomes full. */ 437 Stats::Scalar<> iewIQFullEvents; 438 /** Stat for number of times the LSQ becomes full. */ 439 Stats::Scalar<> iewLSQFullEvents; 440 /** Stat for total number of memory ordering violation events. */ 441 Stats::Scalar<> memOrderViolationEvents; 442 /** Stat for total number of incorrect predicted taken branches. */ 443 Stats::Scalar<> predictedTakenIncorrect; 444 /** Stat for total number of incorrect predicted not taken branches. */ 445 Stats::Scalar<> predictedNotTakenIncorrect; 446 /** Stat for total number of mispredicted branches detected at execute. */ 447 Stats::Formula branchMispredicts; 448 449 /** Stat for total number of executed instructions. */ 450 Stats::Scalar<> iewExecutedInsts; 451 /** Stat for total number of executed load instructions. */ 452 Stats::Vector<> iewExecLoadInsts; 453 /** Stat for total number of squashed instructions skipped at execute. */ 454 Stats::Scalar<> iewExecSquashedInsts; 455 /** Number of executed software prefetches. */ 456 Stats::Vector<> iewExecutedSwp; 457 /** Number of executed nops. */ 458 Stats::Vector<> iewExecutedNop; 459 /** Number of executed meomory references. */ 460 Stats::Vector<> iewExecutedRefs; 461 /** Number of executed branches. */ 462 Stats::Vector<> iewExecutedBranches; 463 /** Number of executed store instructions. */ 464 Stats::Formula iewExecStoreInsts; 465 /** Number of instructions executed per cycle. */ 466 Stats::Formula iewExecRate; 467 468 /** Number of instructions sent to commit. */ 469 Stats::Vector<> iewInstsToCommit; 470 /** Number of instructions that writeback. */ 471 Stats::Vector<> writebackCount; 472 /** Number of instructions that wake consumers. */ 473 Stats::Vector<> producerInst; 474 /** Number of instructions that wake up from producers. */ 475 Stats::Vector<> consumerInst; 476 /** Number of instructions that were delayed in writing back due 477 * to resource contention. 478 */ 479 Stats::Vector<> wbPenalized; 480 /** Number of instructions per cycle written back. */ 481 Stats::Formula wbRate; 482 /** Average number of woken instructions per writeback. */ 483 Stats::Formula wbFanout; 484 /** Number of instructions per cycle delayed in writing back . */ 485 Stats::Formula wbPenalizedRate; 486}; 487 488#endif // __CPU_O3_IEW_HH__ 489