iew.hh revision 2669:f2b336e89d2a
1695SN/A/* 21762SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 3695SN/A * All rights reserved. 4695SN/A * 5695SN/A * Redistribution and use in source and binary forms, with or without 6695SN/A * modification, are permitted provided that the following conditions are 7695SN/A * met: redistributions of source code must retain the above copyright 8695SN/A * notice, this list of conditions and the following disclaimer; 9695SN/A * redistributions in binary form must reproduce the above copyright 10695SN/A * notice, this list of conditions and the following disclaimer in the 11695SN/A * documentation and/or other materials provided with the distribution; 12695SN/A * neither the name of the copyright holders nor the names of its 13695SN/A * contributors may be used to endorse or promote products derived from 14695SN/A * this software without specific prior written permission. 15695SN/A * 16695SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17695SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18695SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19695SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20695SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21695SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22695SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23695SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24695SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25695SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26695SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu */ 282665Ssaidi@eecs.umich.edu 29695SN/A#ifndef __CPU_O3_IEW_HH__ 30695SN/A#define __CPU_O3_IEW_HH__ 31873SN/A 32873SN/A#include <queue> 33873SN/A 34873SN/A#include "base/statistics.hh" 35695SN/A#include "base/timebuf.hh" 362621SN/A#include "config/full_system.hh" 37695SN/A#include "cpu/o3/comm.hh" 38695SN/A#include "cpu/o3/scoreboard.hh" 39695SN/A#include "cpu/o3/lsq.hh" 40695SN/A 41695SN/Aclass FUPool; 42695SN/A 43695SN/A/** 44695SN/A * DefaultIEW handles both single threaded and SMT IEW 45695SN/A * (issue/execute/writeback). It handles the dispatching of 46695SN/A * instructions to the LSQ/IQ as part of the issue stage, and has the 47695SN/A * IQ try to issue instructions each cycle. The execute latency is 48695SN/A * actually tied into the issue latency to allow the IQ to be able to 49695SN/A * do back-to-back scheduling without having to speculatively schedule 50695SN/A * instructions. This happens by having the IQ have access to the 51695SN/A * functional units, and the IQ gets the execution latencies from the 52695SN/A * FUs when it issues instructions. Instructions reach the execute 53695SN/A * stage on the last cycle of their execution, which is when the IQ 54695SN/A * knows to wake up any dependent instructions, allowing back to back 55695SN/A * scheduling. The execute portion of IEW separates memory 56695SN/A * instructions from non-memory instructions, either telling the LSQ 57695SN/A * to execute the instruction, or executing the instruction directly. 58695SN/A * The writeback portion of IEW completes the instructions by waking 59695SN/A * up any dependents, and marking the register ready on the 60695SN/A * scoreboard. 61695SN/A */ 62695SN/Atemplate<class Impl> 63695SN/Aclass DefaultIEW 64695SN/A{ 65695SN/A private: 66695SN/A //Typedefs from Impl 67695SN/A typedef typename Impl::CPUPol CPUPol; 68695SN/A typedef typename Impl::DynInstPtr DynInstPtr; 69695SN/A typedef typename Impl::FullCPU FullCPU; 70729SN/A typedef typename Impl::Params Params; 71695SN/A 72695SN/A typedef typename CPUPol::IQ IQ; 73695SN/A typedef typename CPUPol::RenameMap RenameMap; 74695SN/A typedef typename CPUPol::LSQ LSQ; 75695SN/A 76695SN/A typedef typename CPUPol::TimeStruct TimeStruct; 77695SN/A typedef typename CPUPol::IEWStruct IEWStruct; 78695SN/A typedef typename CPUPol::RenameStruct RenameStruct; 79695SN/A typedef typename CPUPol::IssueStruct IssueStruct; 80695SN/A 81695SN/A friend class Impl::FullCPU; 82695SN/A friend class CPUPol::IQ; 83695SN/A 84695SN/A public: 85695SN/A /** Overall IEW stage status. Used to determine if the CPU can 86695SN/A * deschedule itself due to a lack of activity. 87695SN/A */ 88695SN/A enum Status { 89695SN/A Active, 90695SN/A Inactive 91695SN/A }; 92695SN/A 93695SN/A /** Status for Issue, Execute, and Writeback stages. */ 94695SN/A enum StageStatus { 95695SN/A Running, 96695SN/A Blocked, 97695SN/A Idle, 98695SN/A StartSquash, 99695SN/A Squashing, 100695SN/A Unblocking 101695SN/A }; 102695SN/A 103695SN/A private: 104695SN/A /** Overall stage status. */ 105695SN/A Status _status; 106695SN/A /** Dispatch status. */ 107695SN/A StageStatus dispatchStatus[Impl::MaxThreads]; 108695SN/A /** Execute status. */ 109695SN/A StageStatus exeStatus; 110695SN/A /** Writeback status. */ 111695SN/A StageStatus wbStatus; 112695SN/A 113695SN/A public: 114695SN/A /** Constructs a DefaultIEW with the given parameters. */ 115695SN/A DefaultIEW(Params *params); 116695SN/A 117695SN/A /** Returns the name of the DefaultIEW stage. */ 118695SN/A std::string name() const; 119695SN/A 120695SN/A /** Registers statistics. */ 121695SN/A void regStats(); 122695SN/A 123695SN/A /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 124695SN/A void initStage(); 125695SN/A 126695SN/A /** Sets CPU pointer for IEW, IQ, and LSQ. */ 127695SN/A void setCPU(FullCPU *cpu_ptr); 128695SN/A 129695SN/A /** Sets main time buffer used for backwards communication. */ 130695SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 131695SN/A 1321395SN/A /** Sets time buffer for getting instructions coming from rename. */ 133695SN/A void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 134695SN/A 135695SN/A /** Sets time buffer to pass on instructions to commit. */ 136695SN/A void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 137695SN/A 138695SN/A /** Sets pointer to list of active threads. */ 139695SN/A void setActiveThreads(std::list<unsigned> *at_ptr); 140695SN/A 141695SN/A /** Sets pointer to the scoreboard. */ 142720SN/A void setScoreboard(Scoreboard *sb_ptr); 143695SN/A 144695SN/A void switchOut(); 145695SN/A 146695SN/A void doSwitchOut(); 147695SN/A 148695SN/A void takeOverFrom(); 149695SN/A 150695SN/A bool isSwitchedOut() { return switchedOut; } 151695SN/A 152695SN/A /** Sets page table pointer within LSQ. */ 153695SN/A// void setPageTable(PageTable *pt_ptr); 154695SN/A 155695SN/A /** Squashes instructions in IEW for a specific thread. */ 156695SN/A void squash(unsigned tid); 157695SN/A 158695SN/A /** Wakes all dependents of a completed instruction. */ 159695SN/A void wakeDependents(DynInstPtr &inst); 160695SN/A 161695SN/A /** Tells memory dependence unit that a memory instruction needs to be 162695SN/A * rescheduled. It will re-execute once replayMemInst() is called. 163695SN/A */ 164695SN/A void rescheduleMemInst(DynInstPtr &inst); 165695SN/A 166695SN/A /** Re-executes all rescheduled memory instructions. */ 167695SN/A void replayMemInst(DynInstPtr &inst); 168695SN/A 169695SN/A /** Sends an instruction to commit through the time buffer. */ 170695SN/A void instToCommit(DynInstPtr &inst); 171695SN/A 172695SN/A /** Inserts unused instructions of a thread into the skid buffer. */ 173695SN/A void skidInsert(unsigned tid); 174695SN/A 175695SN/A /** Returns the max of the number of entries in all of the skid buffers. */ 176695SN/A int skidCount(); 177695SN/A 178695SN/A /** Returns if all of the skid buffers are empty. */ 179695SN/A bool skidsEmpty(); 180695SN/A 181695SN/A /** Updates overall IEW status based on all of the stages' statuses. */ 182695SN/A void updateStatus(); 183695SN/A 184695SN/A /** Resets entries of the IQ and the LSQ. */ 185695SN/A void resetEntries(); 186695SN/A 187695SN/A /** Tells the CPU to wakeup if it has descheduled itself due to no 188695SN/A * activity. Used mainly by the LdWritebackEvent. 189695SN/A */ 190695SN/A void wakeCPU(); 191695SN/A 192695SN/A /** Reports to the CPU that there is activity this cycle. */ 193695SN/A void activityThisCycle(); 194695SN/A 195695SN/A /** Tells CPU that the IEW stage is active and running. */ 196695SN/A inline void activateStage(); 197695SN/A 198695SN/A /** Tells CPU that the IEW stage is inactive and idle. */ 199695SN/A inline void deactivateStage(); 200695SN/A 201695SN/A /** Returns if the LSQ has any stores to writeback. */ 202695SN/A bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 203695SN/A 204695SN/A private: 205695SN/A /** Sends commit proper information for a squash due to a branch 206695SN/A * mispredict. 207695SN/A */ 208695SN/A void squashDueToBranch(DynInstPtr &inst, unsigned thread_id); 209695SN/A 210695SN/A /** Sends commit proper information for a squash due to a memory order 211695SN/A * violation. 212695SN/A */ 213695SN/A void squashDueToMemOrder(DynInstPtr &inst, unsigned thread_id); 214695SN/A 215695SN/A /** Sends commit proper information for a squash due to memory becoming 216695SN/A * blocked (younger issued instructions must be retried). 217695SN/A */ 218695SN/A void squashDueToMemBlocked(DynInstPtr &inst, unsigned thread_id); 219695SN/A 220695SN/A /** Sets Dispatch to blocked, and signals back to other stages to block. */ 221695SN/A void block(unsigned thread_id); 222695SN/A 223695SN/A /** Unblocks Dispatch if the skid buffer is empty, and signals back to 224695SN/A * other stages to unblock. 225695SN/A */ 226695SN/A void unblock(unsigned thread_id); 227695SN/A 228695SN/A /** Determines proper actions to take given Dispatch's status. */ 229695SN/A void dispatch(unsigned tid); 230695SN/A 231695SN/A /** Dispatches instructions to IQ and LSQ. */ 232695SN/A void dispatchInsts(unsigned tid); 233695SN/A 234695SN/A /** Executes instructions. In the case of memory operations, it informs the 235695SN/A * LSQ to execute the instructions. Also handles any redirects that occur 236695SN/A * due to the executed instructions. 237695SN/A */ 238695SN/A void executeInsts(); 239695SN/A 240695SN/A /** Writebacks instructions. In our model, the instruction's execute() 241695SN/A * function atomically reads registers, executes, and writes registers. 242695SN/A * Thus this writeback only wakes up dependent instructions, and informs 243695SN/A * the scoreboard of registers becoming ready. 244695SN/A */ 245695SN/A void writebackInsts(); 246695SN/A 247695SN/A /** Returns the number of valid, non-squashed instructions coming from 248695SN/A * rename to dispatch. 249695SN/A */ 250695SN/A unsigned validInstsFromRename(); 251695SN/A 252695SN/A /** Reads the stall signals. */ 253695SN/A void readStallSignals(unsigned tid); 254695SN/A 255695SN/A /** Checks if any of the stall conditions are currently true. */ 256695SN/A bool checkStall(unsigned tid); 257695SN/A 258695SN/A /** Processes inputs and changes state accordingly. */ 259695SN/A void checkSignalsAndUpdate(unsigned tid); 260695SN/A 261695SN/A /** Sorts instructions coming from rename into lists separated by thread. */ 262695SN/A void sortInsts(); 263695SN/A 264695SN/A public: 265695SN/A /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 266695SN/A * Writeback to run for one cycle. 267695SN/A */ 268695SN/A void tick(); 269695SN/A 270695SN/A private: 271695SN/A void updateExeInstStats(DynInstPtr &inst); 272695SN/A 273695SN/A /** Pointer to main time buffer used for backwards communication. */ 274695SN/A TimeBuffer<TimeStruct> *timeBuffer; 275695SN/A 276695SN/A /** Wire to write information heading to previous stages. */ 277695SN/A typename TimeBuffer<TimeStruct>::wire toFetch; 278695SN/A 279695SN/A /** Wire to get commit's output from backwards time buffer. */ 280695SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 281695SN/A 282695SN/A /** Wire to write information heading to previous stages. */ 283695SN/A typename TimeBuffer<TimeStruct>::wire toRename; 284695SN/A 285695SN/A /** Rename instruction queue interface. */ 286695SN/A TimeBuffer<RenameStruct> *renameQueue; 287695SN/A 288695SN/A /** Wire to get rename's output from rename queue. */ 289695SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 290695SN/A 291695SN/A /** Issue stage queue. */ 292729SN/A TimeBuffer<IssueStruct> issueToExecQueue; 293695SN/A 294695SN/A /** Wire to read information from the issue stage time queue. */ 295695SN/A typename TimeBuffer<IssueStruct>::wire fromIssue; 296695SN/A 297695SN/A /** 298695SN/A * IEW stage time buffer. Holds ROB indices of instructions that 299729SN/A * can be marked as completed. 300695SN/A */ 301695SN/A TimeBuffer<IEWStruct> *iewQueue; 302695SN/A 303695SN/A /** Wire to write infromation heading to commit. */ 304695SN/A typename TimeBuffer<IEWStruct>::wire toCommit; 305695SN/A 306695SN/A /** Queue of all instructions coming from rename this cycle. */ 307695SN/A std::queue<DynInstPtr> insts[Impl::MaxThreads]; 308695SN/A 309695SN/A /** Skid buffer between rename and IEW. */ 310695SN/A std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 311695SN/A 312695SN/A /** Scoreboard pointer. */ 313695SN/A Scoreboard* scoreboard; 314695SN/A 315695SN/A public: 316695SN/A /** Instruction queue. */ 317695SN/A IQ instQueue; 318695SN/A 319695SN/A /** Load / store queue. */ 320695SN/A LSQ ldstQueue; 321695SN/A 322695SN/A /** Pointer to the functional unit pool. */ 323695SN/A FUPool *fuPool; 324695SN/A 325695SN/A private: 326695SN/A /** CPU pointer. */ 327695SN/A FullCPU *cpu; 328695SN/A 329695SN/A /** Records if IEW has written to the time buffer this cycle, so that the 330695SN/A * CPU can deschedule itself if there is no activity. 331695SN/A */ 332695SN/A bool wroteToTimeBuffer; 333695SN/A 334695SN/A /** Source of possible stalls. */ 335695SN/A struct Stalls { 336695SN/A bool commit; 337695SN/A }; 338695SN/A 339695SN/A /** Stages that are telling IEW to stall. */ 340695SN/A Stalls stalls[Impl::MaxThreads]; 341695SN/A 342695SN/A /** Debug function to print instructions that are issued this cycle. */ 343695SN/A void printAvailableInsts(); 344695SN/A 345695SN/A public: 346695SN/A /** Records if the LSQ needs to be updated on the next cycle, so that 347695SN/A * IEW knows if there will be activity on the next cycle. 348695SN/A */ 349695SN/A bool updateLSQNextCycle; 350695SN/A 351695SN/A private: 352695SN/A /** Records if there is a fetch redirect on this cycle for each thread. */ 353695SN/A bool fetchRedirect[Impl::MaxThreads]; 354695SN/A 355695SN/A /** Used to track if all instructions have been dispatched this cycle. 356695SN/A * If they have not, then blocking must have occurred, and the instructions 357695SN/A * would already be added to the skid buffer. 358695SN/A * @todo: Fix this hack. 359695SN/A */ 360695SN/A bool dispatchedAllInsts; 361695SN/A 362695SN/A /** Records if the queues have been changed (inserted or issued insts), 363695SN/A * so that IEW knows to broadcast the updated amount of free entries. 364695SN/A */ 365695SN/A bool updatedQueues; 366695SN/A 367695SN/A /** Commit to IEW delay, in ticks. */ 368695SN/A unsigned commitToIEWDelay; 369695SN/A 370695SN/A /** Rename to IEW delay, in ticks. */ 371695SN/A unsigned renameToIEWDelay; 372695SN/A 373695SN/A /** 374695SN/A * Issue to execute delay, in ticks. What this actually represents is 375695SN/A * the amount of time it takes for an instruction to wake up, be 376695SN/A * scheduled, and sent to a FU for execution. 377695SN/A */ 378695SN/A unsigned issueToExecuteDelay; 379695SN/A 380695SN/A /** Width of issue's read path, in instructions. The read path is both 381695SN/A * the skid buffer and the rename instruction queue. 382695SN/A * Note to self: is this really different than issueWidth? 383695SN/A */ 384695SN/A unsigned issueReadWidth; 385695SN/A 386695SN/A /** Width of issue, in instructions. */ 387695SN/A unsigned issueWidth; 388695SN/A 389695SN/A /** Width of execute, in instructions. Might make more sense to break 390695SN/A * down into FP vs int. 391695SN/A */ 392695SN/A unsigned executeWidth; 393695SN/A 394695SN/A /** Index into queue of instructions being written back. */ 395695SN/A unsigned wbNumInst; 396695SN/A 397695SN/A /** Cycle number within the queue of instructions being written back. 398695SN/A * Used in case there are too many instructions writing back at the current 399695SN/A * cycle and writesbacks need to be scheduled for the future. See comments 400695SN/A * in instToCommit(). 401695SN/A */ 402695SN/A unsigned wbCycle; 403695SN/A 404695SN/A /** Number of active threads. */ 405695SN/A unsigned numThreads; 406695SN/A 407695SN/A /** Pointer to list of active threads. */ 408695SN/A std::list<unsigned> *activeThreads; 409695SN/A 410695SN/A /** Maximum size of the skid buffer. */ 411695SN/A unsigned skidBufferMax; 412695SN/A 413695SN/A bool switchedOut; 414695SN/A 415695SN/A /** Stat for total number of idle cycles. */ 416695SN/A Stats::Scalar<> iewIdleCycles; 417695SN/A /** Stat for total number of squashing cycles. */ 418695SN/A Stats::Scalar<> iewSquashCycles; 419695SN/A /** Stat for total number of blocking cycles. */ 420695SN/A Stats::Scalar<> iewBlockCycles; 421695SN/A /** Stat for total number of unblocking cycles. */ 422695SN/A Stats::Scalar<> iewUnblockCycles; 423695SN/A /** Stat for total number of instructions dispatched. */ 424695SN/A Stats::Scalar<> iewDispatchedInsts; 425695SN/A /** Stat for total number of squashed instructions dispatch skips. */ 426695SN/A Stats::Scalar<> iewDispSquashedInsts; 427695SN/A /** Stat for total number of dispatched load instructions. */ 428695SN/A Stats::Scalar<> iewDispLoadInsts; 429695SN/A /** Stat for total number of dispatched store instructions. */ 430695SN/A Stats::Scalar<> iewDispStoreInsts; 431695SN/A /** Stat for total number of dispatched non speculative instructions. */ 432695SN/A Stats::Scalar<> iewDispNonSpecInsts; 433695SN/A /** Stat for number of times the IQ becomes full. */ 434695SN/A Stats::Scalar<> iewIQFullEvents; 435695SN/A /** Stat for number of times the LSQ becomes full. */ 436695SN/A Stats::Scalar<> iewLSQFullEvents; 437695SN/A /** Stat for total number of executed instructions. */ 438695SN/A Stats::Scalar<> iewExecutedInsts; 439695SN/A /** Stat for total number of executed load instructions. */ 440695SN/A Stats::Vector<> iewExecLoadInsts; 441695SN/A /** Stat for total number of executed store instructions. */ 442695SN/A// Stats::Scalar<> iewExecStoreInsts; 443695SN/A /** Stat for total number of squashed instructions skipped at execute. */ 444695SN/A Stats::Scalar<> iewExecSquashedInsts; 445695SN/A /** Stat for total number of memory ordering violation events. */ 446695SN/A Stats::Scalar<> memOrderViolationEvents; 447695SN/A /** Stat for total number of incorrect predicted taken branches. */ 448695SN/A Stats::Scalar<> predictedTakenIncorrect; 449695SN/A /** Stat for total number of incorrect predicted not taken branches. */ 450695SN/A Stats::Scalar<> predictedNotTakenIncorrect; 451695SN/A /** Stat for total number of mispredicted branches detected at execute. */ 452695SN/A Stats::Formula branchMispredicts; 453695SN/A 454695SN/A Stats::Vector<> exeSwp; 455695SN/A Stats::Vector<> exeNop; 456695SN/A Stats::Vector<> exeRefs; 457695SN/A Stats::Vector<> exeBranches; 458695SN/A 459695SN/A// Stats::Vector<> issued_ops; 460695SN/A/* 461695SN/A Stats::Vector<> stat_fu_busy; 462695SN/A Stats::Vector2d<> stat_fuBusy; 463695SN/A Stats::Vector<> dist_unissued; 464695SN/A Stats::Vector2d<> stat_issued_inst_type; 465695SN/A*/ 466695SN/A Stats::Formula issueRate; 467695SN/A Stats::Formula iewExecStoreInsts; 468695SN/A// Stats::Formula issue_op_rate; 469695SN/A// Stats::Formula fu_busy_rate; 470695SN/A 471695SN/A Stats::Vector<> iewInstsToCommit; 472695SN/A Stats::Vector<> writebackCount; 473695SN/A Stats::Vector<> producerInst; 474695SN/A Stats::Vector<> consumerInst; 475695SN/A Stats::Vector<> wbPenalized; 476695SN/A 477695SN/A Stats::Formula wbRate; 478695SN/A Stats::Formula wbFanout; 479695SN/A Stats::Formula wbPenalizedRate; 480695SN/A}; 481695SN/A 482695SN/A#endif // __CPU_O3_IEW_HH__ 483695SN/A