iew.hh revision 2632:1bb2f91485ea 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29//Todo: Update with statuses.
30//Need to handle delaying writes to the writeback bus if it's full at the
31//given time.
32
33#ifndef __CPU_O3_CPU_SIMPLE_IEW_HH__
34#define __CPU_O3_CPU_SIMPLE_IEW_HH__
35
36#include <queue>
37
38#include "config/full_system.hh"
39#include "base/statistics.hh"
40#include "base/timebuf.hh"
41#include "cpu/o3/comm.hh"
42
43template<class Impl>
44class SimpleIEW
45{
46  private:
47    //Typedefs from Impl
48    typedef typename Impl::CPUPol CPUPol;
49    typedef typename Impl::DynInstPtr DynInstPtr;
50    typedef typename Impl::FullCPU FullCPU;
51    typedef typename Impl::Params Params;
52
53    typedef typename CPUPol::IQ IQ;
54    typedef typename CPUPol::RenameMap RenameMap;
55    typedef typename CPUPol::LDSTQ LDSTQ;
56
57    typedef typename CPUPol::TimeStruct TimeStruct;
58    typedef typename CPUPol::IEWStruct IEWStruct;
59    typedef typename CPUPol::RenameStruct RenameStruct;
60    typedef typename CPUPol::IssueStruct IssueStruct;
61
62    friend class Impl::FullCPU;
63  public:
64    enum Status {
65        Running,
66        Blocked,
67        Idle,
68        Squashing,
69        Unblocking
70    };
71
72  private:
73    Status _status;
74    Status _issueStatus;
75    Status _exeStatus;
76    Status _wbStatus;
77
78  public:
79    class WritebackEvent : public Event {
80      private:
81        DynInstPtr inst;
82        SimpleIEW<Impl> *iewStage;
83
84      public:
85        WritebackEvent(DynInstPtr &_inst, SimpleIEW<Impl> *_iew);
86
87        virtual void process();
88        virtual const char *description();
89    };
90
91  public:
92    SimpleIEW(Params &params);
93
94    void regStats();
95
96    void setCPU(FullCPU *cpu_ptr);
97
98    void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
99
100    void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
101
102    void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
103
104    void setRenameMap(RenameMap *rm_ptr);
105
106    void squash();
107
108    void squashDueToBranch(DynInstPtr &inst);
109
110    void squashDueToMem(DynInstPtr &inst);
111
112    void block();
113
114    inline void unblock();
115
116    void wakeDependents(DynInstPtr &inst);
117
118    void instToCommit(DynInstPtr &inst);
119
120  private:
121    void dispatchInsts();
122
123    void executeInsts();
124
125  public:
126    void tick();
127
128    void iew();
129
130    //Interfaces to objects inside and outside of IEW.
131    /** Time buffer interface. */
132    TimeBuffer<TimeStruct> *timeBuffer;
133
134    /** Wire to get commit's output from backwards time buffer. */
135    typename TimeBuffer<TimeStruct>::wire fromCommit;
136
137    /** Wire to write information heading to previous stages. */
138    typename TimeBuffer<TimeStruct>::wire toRename;
139
140    /** Rename instruction queue interface. */
141    TimeBuffer<RenameStruct> *renameQueue;
142
143    /** Wire to get rename's output from rename queue. */
144    typename TimeBuffer<RenameStruct>::wire fromRename;
145
146    /** Issue stage queue. */
147    TimeBuffer<IssueStruct> issueToExecQueue;
148
149    /** Wire to read information from the issue stage time queue. */
150    typename TimeBuffer<IssueStruct>::wire fromIssue;
151
152    /**
153     * IEW stage time buffer.  Holds ROB indices of instructions that
154     * can be marked as completed.
155     */
156    TimeBuffer<IEWStruct> *iewQueue;
157
158    /** Wire to write infromation heading to commit. */
159    typename TimeBuffer<IEWStruct>::wire toCommit;
160
161    //Will need internal queue to hold onto instructions coming from
162    //the rename stage in case of a stall.
163    /** Skid buffer between rename and IEW. */
164    std::queue<RenameStruct> skidBuffer;
165
166  protected:
167    /** Instruction queue. */
168    IQ instQueue;
169
170    LDSTQ ldstQueue;
171
172#if !FULL_SYSTEM
173  public:
174    void lsqWriteback();
175#endif
176
177  private:
178    /** Pointer to rename map.  Might not want this stage to directly
179     *  access this though...
180     */
181    RenameMap *renameMap;
182
183    /** CPU interface. */
184    FullCPU *cpu;
185
186  private:
187    /** Commit to IEW delay, in ticks. */
188    unsigned commitToIEWDelay;
189
190    /** Rename to IEW delay, in ticks. */
191    unsigned renameToIEWDelay;
192
193    /**
194     * Issue to execute delay, in ticks.  What this actually represents is
195     * the amount of time it takes for an instruction to wake up, be
196     * scheduled, and sent to a FU for execution.
197     */
198    unsigned issueToExecuteDelay;
199
200    /** Width of issue's read path, in instructions.  The read path is both
201     *  the skid buffer and the rename instruction queue.
202     *  Note to self: is this really different than issueWidth?
203     */
204    unsigned issueReadWidth;
205
206    /** Width of issue, in instructions. */
207    unsigned issueWidth;
208
209    /** Width of execute, in instructions.  Might make more sense to break
210     *  down into FP vs int.
211     */
212    unsigned executeWidth;
213
214    /** Number of cycles stage has been squashing.  Used so that the stage
215     *  knows when it can start unblocking, which is when the previous stage
216     *  has received the stall signal and clears up its outputs.
217     */
218    unsigned cyclesSquashing;
219
220    Stats::Scalar<> iewIdleCycles;
221    Stats::Scalar<> iewSquashCycles;
222    Stats::Scalar<> iewBlockCycles;
223    Stats::Scalar<> iewUnblockCycles;
224//    Stats::Scalar<> iewWBInsts;
225    Stats::Scalar<> iewDispatchedInsts;
226    Stats::Scalar<> iewDispSquashedInsts;
227    Stats::Scalar<> iewDispLoadInsts;
228    Stats::Scalar<> iewDispStoreInsts;
229    Stats::Scalar<> iewDispNonSpecInsts;
230    Stats::Scalar<> iewIQFullEvents;
231    Stats::Scalar<> iewExecutedInsts;
232    Stats::Scalar<> iewExecLoadInsts;
233    Stats::Scalar<> iewExecStoreInsts;
234    Stats::Scalar<> iewExecSquashedInsts;
235    Stats::Scalar<> memOrderViolationEvents;
236    Stats::Scalar<> predictedTakenIncorrect;
237};
238
239#endif // __CPU_O3_CPU_IEW_HH__
240