free_list.hh revision 8232
17405SAli.Saidi@ARM.com/* 28868SMatt.Horsnell@arm.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 37405SAli.Saidi@ARM.com * All rights reserved. 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147405SAli.Saidi@ARM.com * this software without specific prior written permission. 157405SAli.Saidi@ARM.com * 167405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277405SAli.Saidi@ARM.com * 287405SAli.Saidi@ARM.com * Authors: Kevin Lim 297405SAli.Saidi@ARM.com */ 307405SAli.Saidi@ARM.com 317405SAli.Saidi@ARM.com#ifndef __CPU_O3_FREE_LIST_HH__ 327405SAli.Saidi@ARM.com#define __CPU_O3_FREE_LIST_HH__ 337405SAli.Saidi@ARM.com 347405SAli.Saidi@ARM.com#include <iostream> 357405SAli.Saidi@ARM.com#include <queue> 367405SAli.Saidi@ARM.com 377405SAli.Saidi@ARM.com#include "arch/registers.hh" 387405SAli.Saidi@ARM.com#include "base/misc.hh" 397405SAli.Saidi@ARM.com#include "base/trace.hh" 407405SAli.Saidi@ARM.com#include "config/the_isa.hh" 417405SAli.Saidi@ARM.com#include "cpu/o3/comm.hh" 429050Schander.sudanthi@arm.com#include "debug/FreeList.hh" 438887Sgeoffrey.blake@arm.com 448232Snate@binkert.org/** 458232Snate@binkert.org * FreeList class that simply holds the list of free integer and floating 469384SAndreas.Sandberg@arm.com * point registers. Can request for a free register of either type, and 477678Sgblack@eecs.umich.edu * also send back free registers of either type. This is a very simple 488059SAli.Saidi@ARM.com * class, but it should be sufficient for most implementations. Like all 498284SAli.Saidi@ARM.com * other classes, it assumes that the indices for the floating point 507405SAli.Saidi@ARM.com * registers starts after the integer registers end. Hence the variable 517405SAli.Saidi@ARM.com * numPhysicalIntRegs is logically equivalent to the baseFP dependency. 527405SAli.Saidi@ARM.com * Note that while this most likely should be called FreeList, the name 537405SAli.Saidi@ARM.com * "FreeList" is used in a typedef within the CPU Policy, and therefore no 549384SAndreas.Sandberg@arm.com * class can be named simply "FreeList". 559384SAndreas.Sandberg@arm.com * @todo: Give a better name to the base FP dependency. 569384SAndreas.Sandberg@arm.com */ 579384SAndreas.Sandberg@arm.comclass SimpleFreeList 589384SAndreas.Sandberg@arm.com{ 599384SAndreas.Sandberg@arm.com private: 609384SAndreas.Sandberg@arm.com /** The list of free integer registers. */ 619384SAndreas.Sandberg@arm.com std::queue<PhysRegIndex> freeIntRegs; 629384SAndreas.Sandberg@arm.com 639384SAndreas.Sandberg@arm.com /** The list of free floating point registers. */ 649384SAndreas.Sandberg@arm.com std::queue<PhysRegIndex> freeFloatRegs; 659384SAndreas.Sandberg@arm.com 669384SAndreas.Sandberg@arm.com /** Number of logical integer registers. */ 679384SAndreas.Sandberg@arm.com int numLogicalIntRegs; 689384SAndreas.Sandberg@arm.com 697427Sgblack@eecs.umich.edu /** Number of physical integer registers. */ 707427Sgblack@eecs.umich.edu int numPhysicalIntRegs; 717427Sgblack@eecs.umich.edu 727427Sgblack@eecs.umich.edu /** Number of logical floating point registers. */ 738299Schander.sudanthi@arm.com int numLogicalFloatRegs; 747427Sgblack@eecs.umich.edu 757427Sgblack@eecs.umich.edu /** Number of physical floating point registers. */ 767427Sgblack@eecs.umich.edu int numPhysicalFloatRegs; 777427Sgblack@eecs.umich.edu 787427Sgblack@eecs.umich.edu /** Total number of physical registers. */ 797427Sgblack@eecs.umich.edu int numPhysicalRegs; 807427Sgblack@eecs.umich.edu 817604SGene.Wu@arm.com public: 827427Sgblack@eecs.umich.edu /** Constructs a free list. 837427Sgblack@eecs.umich.edu * @param activeThreads Number of active threads. 847427Sgblack@eecs.umich.edu * @param _numLogicalIntRegs Number of logical integer registers. 857427Sgblack@eecs.umich.edu * @param _numPhysicalIntRegs Number of physical integer registers. 867427Sgblack@eecs.umich.edu * @param _numLogicalFloatRegs Number of logical fp registers. 877427Sgblack@eecs.umich.edu * @param _numPhysicalFloatRegs Number of physical fp registers. 887427Sgblack@eecs.umich.edu */ 897427Sgblack@eecs.umich.edu SimpleFreeList(ThreadID activeThreads, 907427Sgblack@eecs.umich.edu unsigned _numLogicalIntRegs, 917427Sgblack@eecs.umich.edu unsigned _numPhysicalIntRegs, 929050Schander.sudanthi@arm.com unsigned _numLogicalFloatRegs, 938299Schander.sudanthi@arm.com unsigned _numPhysicalFloatRegs); 948299Schander.sudanthi@arm.com 957427Sgblack@eecs.umich.edu /** Gives the name of the freelist. */ 967427Sgblack@eecs.umich.edu std::string name() const; 977427Sgblack@eecs.umich.edu 987427Sgblack@eecs.umich.edu /** Gets a free integer register. */ 997427Sgblack@eecs.umich.edu inline PhysRegIndex getIntReg(); 1007427Sgblack@eecs.umich.edu 1017427Sgblack@eecs.umich.edu /** Gets a free fp register. */ 1027427Sgblack@eecs.umich.edu inline PhysRegIndex getFloatReg(); 1037427Sgblack@eecs.umich.edu 1047427Sgblack@eecs.umich.edu /** Adds a register back to the free list. */ 1057427Sgblack@eecs.umich.edu inline void addReg(PhysRegIndex freed_reg); 1067427Sgblack@eecs.umich.edu 1077427Sgblack@eecs.umich.edu /** Adds an integer register back to the free list. */ 1087427Sgblack@eecs.umich.edu inline void addIntReg(PhysRegIndex freed_reg); 1097427Sgblack@eecs.umich.edu 1107427Sgblack@eecs.umich.edu /** Adds a fp register back to the free list. */ 1117427Sgblack@eecs.umich.edu inline void addFloatReg(PhysRegIndex freed_reg); 1127427Sgblack@eecs.umich.edu 1137427Sgblack@eecs.umich.edu /** Checks if there are any free integer registers. */ 1147427Sgblack@eecs.umich.edu bool hasFreeIntRegs() 1157427Sgblack@eecs.umich.edu { return !freeIntRegs.empty(); } 1167427Sgblack@eecs.umich.edu 1177427Sgblack@eecs.umich.edu /** Checks if there are any free fp registers. */ 1187427Sgblack@eecs.umich.edu bool hasFreeFloatRegs() 1197427Sgblack@eecs.umich.edu { return !freeFloatRegs.empty(); } 1207427Sgblack@eecs.umich.edu 1217427Sgblack@eecs.umich.edu /** Returns the number of free integer registers. */ 1227436Sdam.sunwoo@arm.com int numFreeIntRegs() 1237436Sdam.sunwoo@arm.com { return freeIntRegs.size(); } 1247436Sdam.sunwoo@arm.com 1257436Sdam.sunwoo@arm.com /** Returns the number of free fp registers. */ 1267436Sdam.sunwoo@arm.com int numFreeFloatRegs() 1277436Sdam.sunwoo@arm.com { return freeFloatRegs.size(); } 1287436Sdam.sunwoo@arm.com}; 1297436Sdam.sunwoo@arm.com 1307436Sdam.sunwoo@arm.cominline PhysRegIndex 1317436Sdam.sunwoo@arm.comSimpleFreeList::getIntReg() 1327436Sdam.sunwoo@arm.com{ 1337436Sdam.sunwoo@arm.com DPRINTF(FreeList, "Trying to get free integer register.\n"); 1347436Sdam.sunwoo@arm.com 1357436Sdam.sunwoo@arm.com if (freeIntRegs.empty()) { 1367436Sdam.sunwoo@arm.com panic("No free integer registers!"); 1377436Sdam.sunwoo@arm.com } 1387436Sdam.sunwoo@arm.com 1397436Sdam.sunwoo@arm.com PhysRegIndex free_reg = freeIntRegs.front(); 1407436Sdam.sunwoo@arm.com 1417436Sdam.sunwoo@arm.com freeIntRegs.pop(); 1427436Sdam.sunwoo@arm.com 1437436Sdam.sunwoo@arm.com return(free_reg); 1447436Sdam.sunwoo@arm.com} 1457436Sdam.sunwoo@arm.com 1467436Sdam.sunwoo@arm.cominline PhysRegIndex 1477436Sdam.sunwoo@arm.comSimpleFreeList::getFloatReg() 1487436Sdam.sunwoo@arm.com{ 1497436Sdam.sunwoo@arm.com DPRINTF(FreeList, "Trying to get free float register.\n"); 1507436Sdam.sunwoo@arm.com 1517436Sdam.sunwoo@arm.com if (freeFloatRegs.empty()) { 1527436Sdam.sunwoo@arm.com panic("No free integer registers!"); 1537436Sdam.sunwoo@arm.com } 1547644Sali.saidi@arm.com 1557644Sali.saidi@arm.com PhysRegIndex free_reg = freeFloatRegs.front(); 1568147SAli.Saidi@ARM.com 1578147SAli.Saidi@ARM.com freeFloatRegs.pop(); 1588147SAli.Saidi@ARM.com 1598520SAli.Saidi@ARM.com return(free_reg); 1608147SAli.Saidi@ARM.com} 1618147SAli.Saidi@ARM.com 1628147SAli.Saidi@ARM.cominline void 1638147SAli.Saidi@ARM.comSimpleFreeList::addReg(PhysRegIndex freed_reg) 1648147SAli.Saidi@ARM.com{ 1658147SAli.Saidi@ARM.com DPRINTF(FreeList,"Freeing register %i.\n", freed_reg); 1667427Sgblack@eecs.umich.edu //Might want to add in a check for whether or not this register is 1677427Sgblack@eecs.umich.edu //already in there. A bit vector or something similar would be useful. 1687427Sgblack@eecs.umich.edu if (freed_reg < numPhysicalIntRegs) { 1697405SAli.Saidi@ARM.com if (freed_reg != TheISA::ZeroReg) 1707405SAli.Saidi@ARM.com freeIntRegs.push(freed_reg); 1717405SAli.Saidi@ARM.com } else if (freed_reg < numPhysicalRegs) { 1727405SAli.Saidi@ARM.com#if THE_ISA == ALPHA_ISA 1737614Sminkyu.jeong@arm.com if (freed_reg != (TheISA::ZeroReg + numPhysicalIntRegs)) 1747614Sminkyu.jeong@arm.com#endif 1757614Sminkyu.jeong@arm.com freeFloatRegs.push(freed_reg); 1767614Sminkyu.jeong@arm.com } 1777614Sminkyu.jeong@arm.com 1787614Sminkyu.jeong@arm.com // These assert conditions ensure that the number of free 1797614Sminkyu.jeong@arm.com // registers are not more than the # of total Physical Registers. 1807614Sminkyu.jeong@arm.com // If this were false, it would mean that registers 1817614Sminkyu.jeong@arm.com // have been freed twice, overflowing the free register 1827614Sminkyu.jeong@arm.com // pool and potentially crashing SMT workloads. 1837614Sminkyu.jeong@arm.com // ---- 1847405SAli.Saidi@ARM.com // Comment out for now so as to not potentially break 1857405SAli.Saidi@ARM.com // CMP and single-threaded workloads 1867405SAli.Saidi@ARM.com // ---- 1877405SAli.Saidi@ARM.com // assert(freeIntRegs.size() <= numPhysicalIntRegs); 1887405SAli.Saidi@ARM.com // assert(freeFloatRegs.size() <= numPhysicalFloatRegs); 1897405SAli.Saidi@ARM.com} 1909050Schander.sudanthi@arm.com 1919050Schander.sudanthi@arm.cominline void 1927405SAli.Saidi@ARM.comSimpleFreeList::addIntReg(PhysRegIndex freed_reg) 1937405SAli.Saidi@ARM.com{ 1947720Sgblack@eecs.umich.edu DPRINTF(FreeList,"Freeing int register %i.\n", freed_reg); 1957720Sgblack@eecs.umich.edu 1967720Sgblack@eecs.umich.edu freeIntRegs.push(freed_reg); 1977405SAli.Saidi@ARM.com} 1987405SAli.Saidi@ARM.com 1997757SAli.Saidi@ARM.cominline void 2007405SAli.Saidi@ARM.comSimpleFreeList::addFloatReg(PhysRegIndex freed_reg) 2017405SAli.Saidi@ARM.com{ 2027757SAli.Saidi@ARM.com DPRINTF(FreeList,"Freeing float register %i.\n", freed_reg); 2037405SAli.Saidi@ARM.com 2048284SAli.Saidi@ARM.com freeFloatRegs.push(freed_reg); 2059050Schander.sudanthi@arm.com} 2069050Schander.sudanthi@arm.com 2078873SAli.Saidi@ARM.com#endif // __CPU_O3_FREE_LIST_HH__ 2089050Schander.sudanthi@arm.com