free_list.hh revision 5364
12632Sstever@eecs.umich.edu/* 22632Sstever@eecs.umich.edu * Copyright (c) 2004-2005 The Regents of The University of Michigan 32632Sstever@eecs.umich.edu * All rights reserved. 42632Sstever@eecs.umich.edu * 52632Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62632Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 72632Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92632Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112632Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122632Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132632Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142632Sstever@eecs.umich.edu * this software without specific prior written permission. 152632Sstever@eecs.umich.edu * 162632Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172632Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182632Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192632Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202632Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212632Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222632Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232632Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242632Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252632Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262632Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272632Sstever@eecs.umich.edu * 282632Sstever@eecs.umich.edu * Authors: Kevin Lim 292632Sstever@eecs.umich.edu */ 302632Sstever@eecs.umich.edu 312632Sstever@eecs.umich.edu#ifndef __CPU_O3_FREE_LIST_HH__ 322632Sstever@eecs.umich.edu#define __CPU_O3_FREE_LIST_HH__ 332632Sstever@eecs.umich.edu 342632Sstever@eecs.umich.edu#include <iostream> 352632Sstever@eecs.umich.edu#include <queue> 362632Sstever@eecs.umich.edu 372632Sstever@eecs.umich.edu#include "arch/isa_traits.hh" 382632Sstever@eecs.umich.edu#include "base/misc.hh" 392632Sstever@eecs.umich.edu#include "base/trace.hh" 402632Sstever@eecs.umich.edu#include "base/traceflags.hh" 412632Sstever@eecs.umich.edu#include "cpu/o3/comm.hh" 422632Sstever@eecs.umich.edu 432632Sstever@eecs.umich.edu/** 442632Sstever@eecs.umich.edu * FreeList class that simply holds the list of free integer and floating 452632Sstever@eecs.umich.edu * point registers. Can request for a free register of either type, and 462632Sstever@eecs.umich.edu * also send back free registers of either type. This is a very simple 472632Sstever@eecs.umich.edu * class, but it should be sufficient for most implementations. Like all 482632Sstever@eecs.umich.edu * other classes, it assumes that the indices for the floating point 492632Sstever@eecs.umich.edu * registers starts after the integer registers end. Hence the variable 502632Sstever@eecs.umich.edu * numPhysicalIntRegs is logically equivalent to the baseFP dependency. 512632Sstever@eecs.umich.edu * Note that while this most likely should be called FreeList, the name 522632Sstever@eecs.umich.edu * "FreeList" is used in a typedef within the CPU Policy, and therefore no 532632Sstever@eecs.umich.edu * class can be named simply "FreeList". 542632Sstever@eecs.umich.edu * @todo: Give a better name to the base FP dependency. 552632Sstever@eecs.umich.edu */ 562632Sstever@eecs.umich.educlass SimpleFreeList 572632Sstever@eecs.umich.edu{ 582632Sstever@eecs.umich.edu private: 592632Sstever@eecs.umich.edu /** The list of free integer registers. */ 602632Sstever@eecs.umich.edu std::queue<PhysRegIndex> freeIntRegs; 612632Sstever@eecs.umich.edu 622632Sstever@eecs.umich.edu /** The list of free floating point registers. */ 632632Sstever@eecs.umich.edu std::queue<PhysRegIndex> freeFloatRegs; 642632Sstever@eecs.umich.edu 652632Sstever@eecs.umich.edu /** Number of logical integer registers. */ 662632Sstever@eecs.umich.edu int numLogicalIntRegs; 672632Sstever@eecs.umich.edu 68 /** Number of physical integer registers. */ 69 int numPhysicalIntRegs; 70 71 /** Number of logical floating point registers. */ 72 int numLogicalFloatRegs; 73 74 /** Number of physical floating point registers. */ 75 int numPhysicalFloatRegs; 76 77 /** Total number of physical registers. */ 78 int numPhysicalRegs; 79 80 public: 81 /** Constructs a free list. 82 * @param activeThreads Number of active threads. 83 * @param _numLogicalIntRegs Number of logical integer registers. 84 * @param _numPhysicalIntRegs Number of physical integer registers. 85 * @param _numLogicalFloatRegs Number of logical fp registers. 86 * @param _numPhysicalFloatRegs Number of physical fp registers. 87 */ 88 SimpleFreeList(unsigned activeThreads, 89 unsigned _numLogicalIntRegs, 90 unsigned _numPhysicalIntRegs, 91 unsigned _numLogicalFloatRegs, 92 unsigned _numPhysicalFloatRegs); 93 94 /** Gives the name of the freelist. */ 95 std::string name() const; 96 97 /** Gets a free integer register. */ 98 inline PhysRegIndex getIntReg(); 99 100 /** Gets a free fp register. */ 101 inline PhysRegIndex getFloatReg(); 102 103 /** Adds a register back to the free list. */ 104 inline void addReg(PhysRegIndex freed_reg); 105 106 /** Adds an integer register back to the free list. */ 107 inline void addIntReg(PhysRegIndex freed_reg); 108 109 /** Adds a fp register back to the free list. */ 110 inline void addFloatReg(PhysRegIndex freed_reg); 111 112 /** Checks if there are any free integer registers. */ 113 bool hasFreeIntRegs() 114 { return !freeIntRegs.empty(); } 115 116 /** Checks if there are any free fp registers. */ 117 bool hasFreeFloatRegs() 118 { return !freeFloatRegs.empty(); } 119 120 /** Returns the number of free integer registers. */ 121 int numFreeIntRegs() 122 { return freeIntRegs.size(); } 123 124 /** Returns the number of free fp registers. */ 125 int numFreeFloatRegs() 126 { return freeFloatRegs.size(); } 127}; 128 129inline PhysRegIndex 130SimpleFreeList::getIntReg() 131{ 132 DPRINTF(FreeList, "Trying to get free integer register.\n"); 133 134 if (freeIntRegs.empty()) { 135 panic("No free integer registers!"); 136 } 137 138 PhysRegIndex free_reg = freeIntRegs.front(); 139 140 freeIntRegs.pop(); 141 142 return(free_reg); 143} 144 145inline PhysRegIndex 146SimpleFreeList::getFloatReg() 147{ 148 DPRINTF(FreeList, "Trying to get free float register.\n"); 149 150 if (freeFloatRegs.empty()) { 151 panic("No free integer registers!"); 152 } 153 154 PhysRegIndex free_reg = freeFloatRegs.front(); 155 156 freeFloatRegs.pop(); 157 158 return(free_reg); 159} 160 161inline void 162SimpleFreeList::addReg(PhysRegIndex freed_reg) 163{ 164 DPRINTF(FreeList,"Freeing register %i.\n", freed_reg); 165 //Might want to add in a check for whether or not this register is 166 //already in there. A bit vector or something similar would be useful. 167 if (freed_reg < numPhysicalIntRegs) { 168 if (freed_reg != TheISA::ZeroReg) 169 freeIntRegs.push(freed_reg); 170 } else if (freed_reg < numPhysicalRegs) { 171#if THE_ISA == ALPHA_ISA 172 if (freed_reg != (TheISA::ZeroReg + numPhysicalIntRegs)) 173#endif 174 freeFloatRegs.push(freed_reg); 175 } 176 177 // These assert conditions ensure that the number of free 178 // registers are not more than the # of total Physical Registers. 179 // If this were false, it would mean that registers 180 // have been freed twice, overflowing the free register 181 // pool and potentially crashing SMT workloads. 182 // ---- 183 // Comment out for now so as to not potentially break 184 // CMP and single-threaded workloads 185 // ---- 186 // assert(freeIntRegs.size() <= numPhysicalIntRegs); 187 // assert(freeFloatRegs.size() <= numPhysicalFloatRegs); 188} 189 190inline void 191SimpleFreeList::addIntReg(PhysRegIndex freed_reg) 192{ 193 DPRINTF(FreeList,"Freeing int register %i.\n", freed_reg); 194 195 freeIntRegs.push(freed_reg); 196} 197 198inline void 199SimpleFreeList::addFloatReg(PhysRegIndex freed_reg) 200{ 201 DPRINTF(FreeList,"Freeing float register %i.\n", freed_reg); 202 203 freeFloatRegs.push(freed_reg); 204} 205 206#endif // __CPU_O3_FREE_LIST_HH__ 207