free_list.cc revision 2292
12810SN/A/*
22810SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
32810SN/A * All rights reserved.
42810SN/A *
52810SN/A * Redistribution and use in source and binary forms, with or without
62810SN/A * modification, are permitted provided that the following conditions are
72810SN/A * met: redistributions of source code must retain the above copyright
82810SN/A * notice, this list of conditions and the following disclaimer;
92810SN/A * redistributions in binary form must reproduce the above copyright
102810SN/A * notice, this list of conditions and the following disclaimer in the
112810SN/A * documentation and/or other materials provided with the distribution;
122810SN/A * neither the name of the copyright holders nor the names of its
132810SN/A * contributors may be used to endorse or promote products derived from
142810SN/A * this software without specific prior written permission.
152810SN/A *
162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272810SN/A */
282810SN/A
292810SN/A#include "base/trace.hh"
302810SN/A
312810SN/A#include "cpu/o3/free_list.hh"
322810SN/A
332810SN/ASimpleFreeList::SimpleFreeList(unsigned activeThreads,
342810SN/A                               unsigned _numLogicalIntRegs,
352810SN/A                               unsigned _numPhysicalIntRegs,
362810SN/A                               unsigned _numLogicalFloatRegs,
372810SN/A                               unsigned _numPhysicalFloatRegs)
382810SN/A    : numLogicalIntRegs(_numLogicalIntRegs),
392810SN/A      numPhysicalIntRegs(_numPhysicalIntRegs),
404666SN/A      numLogicalFloatRegs(_numLogicalFloatRegs),
412810SN/A      numPhysicalFloatRegs(_numPhysicalFloatRegs),
425338Sstever@gmail.com      numPhysicalRegs(numPhysicalIntRegs + numPhysicalFloatRegs)
434167SN/A{
442810SN/A    DPRINTF(FreeList, "Creating new free list object.\n");
452810SN/A
462810SN/A    // Put all of the extra physical registers onto the free list.  This
472810SN/A    // means excluding all of the base logical registers.
482810SN/A    for (PhysRegIndex i = numLogicalIntRegs * activeThreads;
492810SN/A         i < numPhysicalIntRegs; ++i)
502810SN/A    {
512810SN/A        freeIntRegs.push(i);
522810SN/A    }
532810SN/A
542813SN/A    // Put all of the extra physical registers onto the free list.  This
554903SN/A    // means excluding all of the base logical registers.  Because the
564903SN/A    // float registers' indices start where the physical registers end,
572810SN/A    // some math must be done to determine where the free registers start.
582810SN/A    PhysRegIndex i = numPhysicalIntRegs + (numLogicalFloatRegs * activeThreads);
594903SN/A
604903SN/A    for ( ; i < numPhysicalRegs; ++i)
614903SN/A    {
624903SN/A        freeFloatRegs.push(i);
634903SN/A    }
644903SN/A}
654903SN/A
664908SN/Astd::string
675875Ssteve.reinhardt@amd.comSimpleFreeList::name() const
684903SN/A{
695875Ssteve.reinhardt@amd.com    return "cpu.freelist";
704903SN/A}
714903SN/A