fetch.hh revision 9814:7ad2b0186a32 
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Kevin Lim
41 *          Korey Sewell
42 */
43
44#ifndef __CPU_O3_FETCH_HH__
45#define __CPU_O3_FETCH_HH__
46
47#include "arch/decoder.hh"
48#include "arch/utility.hh"
49#include "base/statistics.hh"
50#include "config/the_isa.hh"
51#include "cpu/pc_event.hh"
52#include "cpu/pred/bpred_unit.hh"
53#include "cpu/timebuf.hh"
54#include "cpu/translation.hh"
55#include "mem/packet.hh"
56#include "mem/port.hh"
57#include "sim/eventq.hh"
58
59struct DerivO3CPUParams;
60
61/**
62 * DefaultFetch class handles both single threaded and SMT fetch. Its
63 * width is specified by the parameters; each cycle it tries to fetch
64 * that many instructions. It supports using a branch predictor to
65 * predict direction and targets.
66 * It supports the idling functionality of the CPU by indicating to
67 * the CPU when it is active and inactive.
68 */
69template <class Impl>
70class DefaultFetch
71{
72  public:
73    /** Typedefs from Impl. */
74    typedef typename Impl::CPUPol CPUPol;
75    typedef typename Impl::DynInst DynInst;
76    typedef typename Impl::DynInstPtr DynInstPtr;
77    typedef typename Impl::O3CPU O3CPU;
78
79    /** Typedefs from the CPU policy. */
80    typedef typename CPUPol::FetchStruct FetchStruct;
81    typedef typename CPUPol::TimeStruct TimeStruct;
82
83    /** Typedefs from ISA. */
84    typedef TheISA::MachInst MachInst;
85    typedef TheISA::ExtMachInst ExtMachInst;
86
87    class FetchTranslation : public BaseTLB::Translation
88    {
89      protected:
90        DefaultFetch<Impl> *fetch;
91
92      public:
93        FetchTranslation(DefaultFetch<Impl> *_fetch)
94            : fetch(_fetch)
95        {}
96
97        void
98        markDelayed()
99        {}
100
101        void
102        finish(Fault fault, RequestPtr req, ThreadContext *tc,
103               BaseTLB::Mode mode)
104        {
105            assert(mode == BaseTLB::Execute);
106            fetch->finishTranslation(fault, req);
107            delete this;
108        }
109    };
110
111  private:
112    /* Event to delay delivery of a fetch translation result in case of
113     * a fault and the nop to carry the fault cannot be generated
114     * immediately */
115    class FinishTranslationEvent : public Event
116    {
117      private:
118        DefaultFetch<Impl> *fetch;
119        Fault fault;
120        RequestPtr req;
121
122      public:
123        FinishTranslationEvent(DefaultFetch<Impl> *_fetch)
124            : fetch(_fetch)
125        {}
126
127        void setFault(Fault _fault)
128        {
129            fault = _fault;
130        }
131
132        void setReq(RequestPtr _req)
133        {
134            req = _req;
135        }
136
137        /** Process the delayed finish translation */
138        void process()
139        {
140            assert(fetch->numInst < fetch->fetchWidth);
141            fetch->finishTranslation(fault, req);
142        }
143
144        const char *description() const
145        {
146            return "FullO3CPU FetchFinishTranslation";
147        }
148      };
149
150  public:
151    /** Overall fetch status. Used to determine if the CPU can
152     * deschedule itsef due to a lack of activity.
153     */
154    enum FetchStatus {
155        Active,
156        Inactive
157    };
158
159    /** Individual thread status. */
160    enum ThreadStatus {
161        Running,
162        Idle,
163        Squashing,
164        Blocked,
165        Fetching,
166        TrapPending,
167        QuiescePending,
168        ItlbWait,
169        IcacheWaitResponse,
170        IcacheWaitRetry,
171        IcacheAccessComplete,
172        NoGoodAddr
173    };
174
175    /** Fetching Policy, Add new policies here.*/
176    enum FetchPriority {
177        SingleThread,
178        RoundRobin,
179        Branch,
180        IQ,
181        LSQ
182    };
183
184  private:
185    /** Fetch status. */
186    FetchStatus _status;
187
188    /** Per-thread status. */
189    ThreadStatus fetchStatus[Impl::MaxThreads];
190
191    /** Fetch policy. */
192    FetchPriority fetchPolicy;
193
194    /** List that has the threads organized by priority. */
195    std::list<ThreadID> priorityList;
196
197  public:
198    /** DefaultFetch constructor. */
199    DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
200
201    /** Returns the name of fetch. */
202    std::string name() const;
203
204    /** Registers statistics. */
205    void regStats();
206
207    /** Sets the main backwards communication time buffer pointer. */
208    void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
209
210    /** Sets pointer to list of active threads. */
211    void setActiveThreads(std::list<ThreadID> *at_ptr);
212
213    /** Sets pointer to time buffer used to communicate to the next stage. */
214    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
215
216    /** Initialize stage. */
217    void startupStage();
218
219    /** Handles retrying the fetch access. */
220    void recvRetry();
221
222    /** Processes cache completion event. */
223    void processCacheCompletion(PacketPtr pkt);
224
225    /** Resume after a drain. */
226    void drainResume();
227
228    /** Perform sanity checks after a drain. */
229    void drainSanityCheck() const;
230
231    /** Has the stage drained? */
232    bool isDrained() const;
233
234    /** Takes over from another CPU's thread. */
235    void takeOverFrom();
236
237    /**
238     * Stall the fetch stage after reaching a safe drain point.
239     *
240     * The CPU uses this method to stop fetching instructions from a
241     * thread that has been drained. The drain stall is different from
242     * all other stalls in that it is signaled instantly from the
243     * commit stage (without the normal communication delay) when it
244     * has reached a safe point to drain from.
245     */
246    void drainStall(ThreadID tid);
247
248    /** Tells fetch to wake up from a quiesce instruction. */
249    void wakeFromQuiesce();
250
251  private:
252    /** Reset this pipeline stage */
253    void resetStage();
254
255    /** Changes the status of this stage to active, and indicates this
256     * to the CPU.
257     */
258    inline void switchToActive();
259
260    /** Changes the status of this stage to inactive, and indicates
261     * this to the CPU.
262     */
263    inline void switchToInactive();
264
265    /**
266     * Looks up in the branch predictor to see if the next PC should be
267     * either next PC+=MachInst or a branch target.
268     * @param next_PC Next PC variable passed in by reference.  It is
269     * expected to be set to the current PC; it will be updated with what
270     * the next PC will be.
271     * @param next_NPC Used for ISAs which use delay slots.
272     * @return Whether or not a branch was predicted as taken.
273     */
274    bool lookupAndUpdateNextPC(DynInstPtr &inst, TheISA::PCState &pc);
275
276    /**
277     * Fetches the cache line that contains fetch_PC.  Returns any
278     * fault that happened.  Puts the data into the class variable
279     * cacheData.
280     * @param vaddr The memory address that is being fetched from.
281     * @param ret_fault The fault reference that will be set to the result of
282     * the icache access.
283     * @param tid Thread id.
284     * @param pc The actual PC of the current instruction.
285     * @return Any fault that occured.
286     */
287    bool fetchCacheLine(Addr vaddr, ThreadID tid, Addr pc);
288    void finishTranslation(Fault fault, RequestPtr mem_req);
289
290
291    /** Check if an interrupt is pending and that we need to handle
292     */
293    bool
294    checkInterrupt(Addr pc)
295    {
296        return (interruptPending && (THE_ISA != ALPHA_ISA || !(pc & 0x3)));
297    }
298
299    /** Squashes a specific thread and resets the PC. */
300    inline void doSquash(const TheISA::PCState &newPC,
301                         const DynInstPtr squashInst, ThreadID tid);
302
303    /** Squashes a specific thread and resets the PC. Also tells the CPU to
304     * remove any instructions between fetch and decode that should be sqaushed.
305     */
306    void squashFromDecode(const TheISA::PCState &newPC,
307                          const DynInstPtr squashInst,
308                          const InstSeqNum seq_num, ThreadID tid);
309
310    /** Checks if a thread is stalled. */
311    bool checkStall(ThreadID tid) const;
312
313    /** Updates overall fetch stage status; to be called at the end of each
314     * cycle. */
315    FetchStatus updateFetchStatus();
316
317  public:
318    /** Squashes a specific thread and resets the PC. Also tells the CPU to
319     * remove any instructions that are not in the ROB. The source of this
320     * squash should be the commit stage.
321     */
322    void squash(const TheISA::PCState &newPC, const InstSeqNum seq_num,
323                DynInstPtr squashInst, ThreadID tid);
324
325    /** Ticks the fetch stage, processing all inputs signals and fetching
326     * as many instructions as possible.
327     */
328    void tick();
329
330    /** Checks all input signals and updates the status as necessary.
331     *  @return: Returns if the status has changed due to input signals.
332     */
333    bool checkSignalsAndUpdate(ThreadID tid);
334
335    /** Does the actual fetching of instructions and passing them on to the
336     * next stage.
337     * @param status_change fetch() sets this variable if there was a status
338     * change (ie switching to IcacheMissStall).
339     */
340    void fetch(bool &status_change);
341
342    /** Align a PC to the start of an I-cache block. */
343    Addr icacheBlockAlignPC(Addr addr)
344    {
345        return (addr & ~(cacheBlkMask));
346    }
347
348    /** The decoder. */
349    TheISA::Decoder *decoder[Impl::MaxThreads];
350
351  private:
352    DynInstPtr buildInst(ThreadID tid, StaticInstPtr staticInst,
353                         StaticInstPtr curMacroop, TheISA::PCState thisPC,
354                         TheISA::PCState nextPC, bool trace);
355
356    /** Returns the appropriate thread to fetch, given the fetch policy. */
357    ThreadID getFetchingThread(FetchPriority &fetch_priority);
358
359    /** Returns the appropriate thread to fetch using a round robin policy. */
360    ThreadID roundRobin();
361
362    /** Returns the appropriate thread to fetch using the IQ count policy. */
363    ThreadID iqCount();
364
365    /** Returns the appropriate thread to fetch using the LSQ count policy. */
366    ThreadID lsqCount();
367
368    /** Returns the appropriate thread to fetch using the branch count
369     * policy. */
370    ThreadID branchCount();
371
372    /** Pipeline the next I-cache access to the current one. */
373    void pipelineIcacheAccesses(ThreadID tid);
374
375    /** Profile the reasons of fetch stall. */
376    void profileStall(ThreadID tid);
377
378  private:
379    /** Pointer to the O3CPU. */
380    O3CPU *cpu;
381
382    /** Time buffer interface. */
383    TimeBuffer<TimeStruct> *timeBuffer;
384
385    /** Wire to get decode's information from backwards time buffer. */
386    typename TimeBuffer<TimeStruct>::wire fromDecode;
387
388    /** Wire to get rename's information from backwards time buffer. */
389    typename TimeBuffer<TimeStruct>::wire fromRename;
390
391    /** Wire to get iew's information from backwards time buffer. */
392    typename TimeBuffer<TimeStruct>::wire fromIEW;
393
394    /** Wire to get commit's information from backwards time buffer. */
395    typename TimeBuffer<TimeStruct>::wire fromCommit;
396
397    /** Internal fetch instruction queue. */
398    TimeBuffer<FetchStruct> *fetchQueue;
399
400    //Might be annoying how this name is different than the queue.
401    /** Wire used to write any information heading to decode. */
402    typename TimeBuffer<FetchStruct>::wire toDecode;
403
404    /** BPredUnit. */
405    BPredUnit *branchPred;
406
407    TheISA::PCState pc[Impl::MaxThreads];
408
409    Addr fetchOffset[Impl::MaxThreads];
410
411    StaticInstPtr macroop[Impl::MaxThreads];
412
413    /** Can the fetch stage redirect from an interrupt on this instruction? */
414    bool delayedCommit[Impl::MaxThreads];
415
416    /** Memory request used to access cache. */
417    RequestPtr memReq[Impl::MaxThreads];
418
419    /** Variable that tracks if fetch has written to the time buffer this
420     * cycle. Used to tell CPU if there is activity this cycle.
421     */
422    bool wroteToTimeBuffer;
423
424    /** Tracks how many instructions has been fetched this cycle. */
425    int numInst;
426
427    /** Source of possible stalls. */
428    struct Stalls {
429        bool decode;
430        bool rename;
431        bool iew;
432        bool commit;
433        bool drain;
434    };
435
436    /** Tracks which stages are telling fetch to stall. */
437    Stalls stalls[Impl::MaxThreads];
438
439    /** Decode to fetch delay. */
440    Cycles decodeToFetchDelay;
441
442    /** Rename to fetch delay. */
443    Cycles renameToFetchDelay;
444
445    /** IEW to fetch delay. */
446    Cycles iewToFetchDelay;
447
448    /** Commit to fetch delay. */
449    Cycles commitToFetchDelay;
450
451    /** The width of fetch in instructions. */
452    unsigned fetchWidth;
453
454    /** Is the cache blocked?  If so no threads can access it. */
455    bool cacheBlocked;
456
457    /** The packet that is waiting to be retried. */
458    PacketPtr retryPkt;
459
460    /** The thread that is waiting on the cache to tell fetch to retry. */
461    ThreadID retryTid;
462
463    /** Cache block size. */
464    unsigned int cacheBlkSize;
465
466    /** Mask to get a cache block's address. */
467    Addr cacheBlkMask;
468
469    /** The cache line being fetched. */
470    uint8_t *cacheData[Impl::MaxThreads];
471
472    /** The PC of the cacheline that has been loaded. */
473    Addr cacheDataPC[Impl::MaxThreads];
474
475    /** Whether or not the cache data is valid. */
476    bool cacheDataValid[Impl::MaxThreads];
477
478    /** Size of instructions. */
479    int instSize;
480
481    /** Icache stall statistics. */
482    Counter lastIcacheStall[Impl::MaxThreads];
483
484    /** List of Active Threads */
485    std::list<ThreadID> *activeThreads;
486
487    /** Number of threads. */
488    ThreadID numThreads;
489
490    /** Number of threads that are actively fetching. */
491    ThreadID numFetchingThreads;
492
493    /** Thread ID being fetched. */
494    ThreadID threadFetched;
495
496    /** Checks if there is an interrupt pending.  If there is, fetch
497     * must stop once it is not fetching PAL instructions.
498     */
499    bool interruptPending;
500
501    /** Set to true if a pipelined I-cache request should be issued. */
502    bool issuePipelinedIfetch[Impl::MaxThreads];
503
504    /** Event used to delay fault generation of translation faults */
505    FinishTranslationEvent finishTranslationEvent;
506
507    // @todo: Consider making these vectors and tracking on a per thread basis.
508    /** Stat for total number of cycles stalled due to an icache miss. */
509    Stats::Scalar icacheStallCycles;
510    /** Stat for total number of fetched instructions. */
511    Stats::Scalar fetchedInsts;
512    /** Total number of fetched branches. */
513    Stats::Scalar fetchedBranches;
514    /** Stat for total number of predicted branches. */
515    Stats::Scalar predictedBranches;
516    /** Stat for total number of cycles spent fetching. */
517    Stats::Scalar fetchCycles;
518    /** Stat for total number of cycles spent squashing. */
519    Stats::Scalar fetchSquashCycles;
520    /** Stat for total number of cycles spent waiting for translation */
521    Stats::Scalar fetchTlbCycles;
522    /** Stat for total number of cycles spent blocked due to other stages in
523     * the pipeline.
524     */
525    Stats::Scalar fetchIdleCycles;
526    /** Total number of cycles spent blocked. */
527    Stats::Scalar fetchBlockedCycles;
528    /** Total number of cycles spent in any other state. */
529    Stats::Scalar fetchMiscStallCycles;
530    /** Total number of cycles spent in waiting for drains. */
531    Stats::Scalar fetchPendingDrainCycles;
532    /** Total number of stall cycles caused by no active threads to run. */
533    Stats::Scalar fetchNoActiveThreadStallCycles;
534    /** Total number of stall cycles caused by pending traps. */
535    Stats::Scalar fetchPendingTrapStallCycles;
536    /** Total number of stall cycles caused by pending quiesce instructions. */
537    Stats::Scalar fetchPendingQuiesceStallCycles;
538    /** Total number of stall cycles caused by I-cache wait retrys. */
539    Stats::Scalar fetchIcacheWaitRetryStallCycles;
540    /** Stat for total number of fetched cache lines. */
541    Stats::Scalar fetchedCacheLines;
542    /** Total number of outstanding icache accesses that were dropped
543     * due to a squash.
544     */
545    Stats::Scalar fetchIcacheSquashes;
546    /** Total number of outstanding tlb accesses that were dropped
547     * due to a squash.
548     */
549    Stats::Scalar fetchTlbSquashes;
550    /** Distribution of number of instructions fetched each cycle. */
551    Stats::Distribution fetchNisnDist;
552    /** Rate of how often fetch was idle. */
553    Stats::Formula idleRate;
554    /** Number of branch fetches per cycle. */
555    Stats::Formula branchRate;
556    /** Number of instruction fetched per cycle. */
557    Stats::Formula fetchRate;
558};
559
560#endif //__CPU_O3_FETCH_HH__
561