fetch.hh revision 5606:6da7a58b0bc8 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "base/timebuf.hh"
39#include "cpu/pc_event.hh"
40#include "mem/packet.hh"
41#include "mem/port.hh"
42#include "sim/eventq.hh"
43
44class DerivO3CPUParams;
45
46/**
47 * DefaultFetch class handles both single threaded and SMT fetch. Its
48 * width is specified by the parameters; each cycle it tries to fetch
49 * that many instructions. It supports using a branch predictor to
50 * predict direction and targets.
51 * It supports the idling functionality of the CPU by indicating to
52 * the CPU when it is active and inactive.
53 */
54template <class Impl>
55class DefaultFetch
56{
57  public:
58    /** Typedefs from Impl. */
59    typedef typename Impl::CPUPol CPUPol;
60    typedef typename Impl::DynInst DynInst;
61    typedef typename Impl::DynInstPtr DynInstPtr;
62    typedef typename Impl::O3CPU O3CPU;
63
64    /** Typedefs from the CPU policy. */
65    typedef typename CPUPol::BPredUnit BPredUnit;
66    typedef typename CPUPol::FetchStruct FetchStruct;
67    typedef typename CPUPol::TimeStruct TimeStruct;
68
69    /** Typedefs from ISA. */
70    typedef TheISA::MachInst MachInst;
71    typedef TheISA::ExtMachInst ExtMachInst;
72
73    /** IcachePort class for DefaultFetch.  Handles doing the
74     * communication with the cache/memory.
75     */
76    class IcachePort : public Port
77    {
78      protected:
79        /** Pointer to fetch. */
80        DefaultFetch<Impl> *fetch;
81
82      public:
83        /** Default constructor. */
84        IcachePort(DefaultFetch<Impl> *_fetch)
85            : Port(_fetch->name() + "-iport", _fetch->cpu), fetch(_fetch)
86        { }
87
88        bool snoopRangeSent;
89
90        virtual void setPeer(Port *port);
91
92      protected:
93        /** Atomic version of receive.  Panics. */
94        virtual Tick recvAtomic(PacketPtr pkt);
95
96        /** Functional version of receive.  Panics. */
97        virtual void recvFunctional(PacketPtr pkt);
98
99        /** Receives status change.  Other than range changing, panics. */
100        virtual void recvStatusChange(Status status);
101
102        /** Returns the address ranges of this device. */
103        virtual void getDeviceAddressRanges(AddrRangeList &resp,
104                                            bool &snoop)
105        { resp.clear(); snoop = true; }
106
107        /** Timing version of receive.  Handles setting fetch to the
108         * proper status to start fetching. */
109        virtual bool recvTiming(PacketPtr pkt);
110
111        /** Handles doing a retry of a failed fetch. */
112        virtual void recvRetry();
113    };
114
115
116  public:
117    /** Overall fetch status. Used to determine if the CPU can
118     * deschedule itsef due to a lack of activity.
119     */
120    enum FetchStatus {
121        Active,
122        Inactive
123    };
124
125    /** Individual thread status. */
126    enum ThreadStatus {
127        Running,
128        Idle,
129        Squashing,
130        Blocked,
131        Fetching,
132        TrapPending,
133        QuiescePending,
134        SwitchOut,
135        IcacheWaitResponse,
136        IcacheWaitRetry,
137        IcacheAccessComplete
138    };
139
140    /** Fetching Policy, Add new policies here.*/
141    enum FetchPriority {
142        SingleThread,
143        RoundRobin,
144        Branch,
145        IQ,
146        LSQ
147    };
148
149  private:
150    /** Fetch status. */
151    FetchStatus _status;
152
153    /** Per-thread status. */
154    ThreadStatus fetchStatus[Impl::MaxThreads];
155
156    /** Fetch policy. */
157    FetchPriority fetchPolicy;
158
159    /** List that has the threads organized by priority. */
160    std::list<unsigned> priorityList;
161
162  public:
163    /** DefaultFetch constructor. */
164    DefaultFetch(O3CPU *_cpu, DerivO3CPUParams *params);
165
166    /** Returns the name of fetch. */
167    std::string name() const;
168
169    /** Registers statistics. */
170    void regStats();
171
172    /** Returns the icache port. */
173    Port *getIcachePort() { return icachePort; }
174
175    /** Sets the main backwards communication time buffer pointer. */
176    void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
177
178    /** Sets pointer to list of active threads. */
179    void setActiveThreads(std::list<unsigned> *at_ptr);
180
181    /** Sets pointer to time buffer used to communicate to the next stage. */
182    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
183
184    /** Initialize stage. */
185    void initStage();
186
187    /** Tells the fetch stage that the Icache is set. */
188    void setIcache();
189
190    /** Processes cache completion event. */
191    void processCacheCompletion(PacketPtr pkt);
192
193    /** Begins the drain of the fetch stage. */
194    bool drain();
195
196    /** Resumes execution after a drain. */
197    void resume();
198
199    /** Tells fetch stage to prepare to be switched out. */
200    void switchOut();
201
202    /** Takes over from another CPU's thread. */
203    void takeOverFrom();
204
205    /** Checks if the fetch stage is switched out. */
206    bool isSwitchedOut() { return switchedOut; }
207
208    /** Tells fetch to wake up from a quiesce instruction. */
209    void wakeFromQuiesce();
210
211  private:
212    /** Changes the status of this stage to active, and indicates this
213     * to the CPU.
214     */
215    inline void switchToActive();
216
217    /** Changes the status of this stage to inactive, and indicates
218     * this to the CPU.
219     */
220    inline void switchToInactive();
221
222    /**
223     * Looks up in the branch predictor to see if the next PC should be
224     * either next PC+=MachInst or a branch target.
225     * @param next_PC Next PC variable passed in by reference.  It is
226     * expected to be set to the current PC; it will be updated with what
227     * the next PC will be.
228     * @param next_NPC Used for ISAs which use delay slots.
229     * @return Whether or not a branch was predicted as taken.
230     */
231    bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC, Addr &next_MicroPC);
232
233    /**
234     * Fetches the cache line that contains fetch_PC.  Returns any
235     * fault that happened.  Puts the data into the class variable
236     * cacheData.
237     * @param fetch_PC The PC address that is being fetched from.
238     * @param ret_fault The fault reference that will be set to the result of
239     * the icache access.
240     * @param tid Thread id.
241     * @return Any fault that occured.
242     */
243    bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
244
245    /** Squashes a specific thread and resets the PC. */
246    inline void doSquash(const Addr &new_PC, const Addr &new_NPC,
247                         const Addr &new_MicroPC, unsigned tid);
248
249    /** Squashes a specific thread and resets the PC. Also tells the CPU to
250     * remove any instructions between fetch and decode that should be sqaushed.
251     */
252    void squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
253                          const Addr &new_MicroPC,
254                          const InstSeqNum &seq_num, unsigned tid);
255
256    /** Checks if a thread is stalled. */
257    bool checkStall(unsigned tid) const;
258
259    /** Updates overall fetch stage status; to be called at the end of each
260     * cycle. */
261    FetchStatus updateFetchStatus();
262
263  public:
264    /** Squashes a specific thread and resets the PC. Also tells the CPU to
265     * remove any instructions that are not in the ROB. The source of this
266     * squash should be the commit stage.
267     */
268    void squash(const Addr &new_PC, const Addr &new_NPC,
269                const Addr &new_MicroPC,
270                const InstSeqNum &seq_num, unsigned tid);
271
272    /** Ticks the fetch stage, processing all inputs signals and fetching
273     * as many instructions as possible.
274     */
275    void tick();
276
277    /** Checks all input signals and updates the status as necessary.
278     *  @return: Returns if the status has changed due to input signals.
279     */
280    bool checkSignalsAndUpdate(unsigned tid);
281
282    /** Does the actual fetching of instructions and passing them on to the
283     * next stage.
284     * @param status_change fetch() sets this variable if there was a status
285     * change (ie switching to IcacheMissStall).
286     */
287    void fetch(bool &status_change);
288
289    /** Align a PC to the start of an I-cache block. */
290    Addr icacheBlockAlignPC(Addr addr)
291    {
292        addr = TheISA::realPCToFetchPC(addr);
293        return (addr & ~(cacheBlkMask));
294    }
295
296  private:
297    /** Handles retrying the fetch access. */
298    void recvRetry();
299
300    /** Returns the appropriate thread to fetch, given the fetch policy. */
301    int getFetchingThread(FetchPriority &fetch_priority);
302
303    /** Returns the appropriate thread to fetch using a round robin policy. */
304    int roundRobin();
305
306    /** Returns the appropriate thread to fetch using the IQ count policy. */
307    int iqCount();
308
309    /** Returns the appropriate thread to fetch using the LSQ count policy. */
310    int lsqCount();
311
312    /** Returns the appropriate thread to fetch using the branch count policy. */
313    int branchCount();
314
315  private:
316    /** Pointer to the O3CPU. */
317    O3CPU *cpu;
318
319    /** Time buffer interface. */
320    TimeBuffer<TimeStruct> *timeBuffer;
321
322    /** Wire to get decode's information from backwards time buffer. */
323    typename TimeBuffer<TimeStruct>::wire fromDecode;
324
325    /** Wire to get rename's information from backwards time buffer. */
326    typename TimeBuffer<TimeStruct>::wire fromRename;
327
328    /** Wire to get iew's information from backwards time buffer. */
329    typename TimeBuffer<TimeStruct>::wire fromIEW;
330
331    /** Wire to get commit's information from backwards time buffer. */
332    typename TimeBuffer<TimeStruct>::wire fromCommit;
333
334    /** Internal fetch instruction queue. */
335    TimeBuffer<FetchStruct> *fetchQueue;
336
337    //Might be annoying how this name is different than the queue.
338    /** Wire used to write any information heading to decode. */
339    typename TimeBuffer<FetchStruct>::wire toDecode;
340
341    /** Icache interface. */
342    IcachePort *icachePort;
343
344    /** BPredUnit. */
345    BPredUnit branchPred;
346
347    /** Predecoder. */
348    TheISA::Predecoder predecoder;
349
350    /** Per-thread fetch PC. */
351    Addr PC[Impl::MaxThreads];
352
353    /** Per-thread fetch micro PC. */
354    Addr microPC[Impl::MaxThreads];
355
356    /** Per-thread next PC. */
357    Addr nextPC[Impl::MaxThreads];
358
359    /** Memory request used to access cache. */
360    RequestPtr memReq[Impl::MaxThreads];
361
362    /** Variable that tracks if fetch has written to the time buffer this
363     * cycle. Used to tell CPU if there is activity this cycle.
364     */
365    bool wroteToTimeBuffer;
366
367    /** Tracks how many instructions has been fetched this cycle. */
368    int numInst;
369
370    /** Source of possible stalls. */
371    struct Stalls {
372        bool decode;
373        bool rename;
374        bool iew;
375        bool commit;
376    };
377
378    /** Tracks which stages are telling fetch to stall. */
379    Stalls stalls[Impl::MaxThreads];
380
381    /** Decode to fetch delay, in ticks. */
382    unsigned decodeToFetchDelay;
383
384    /** Rename to fetch delay, in ticks. */
385    unsigned renameToFetchDelay;
386
387    /** IEW to fetch delay, in ticks. */
388    unsigned iewToFetchDelay;
389
390    /** Commit to fetch delay, in ticks. */
391    unsigned commitToFetchDelay;
392
393    /** The width of fetch in instructions. */
394    unsigned fetchWidth;
395
396    /** Is the cache blocked?  If so no threads can access it. */
397    bool cacheBlocked;
398
399    /** The packet that is waiting to be retried. */
400    PacketPtr retryPkt;
401
402    /** The thread that is waiting on the cache to tell fetch to retry. */
403    int retryTid;
404
405    /** Cache block size. */
406    int cacheBlkSize;
407
408    /** Mask to get a cache block's address. */
409    Addr cacheBlkMask;
410
411    /** The cache line being fetched. */
412    uint8_t *cacheData[Impl::MaxThreads];
413
414    /** The PC of the cacheline that has been loaded. */
415    Addr cacheDataPC[Impl::MaxThreads];
416
417    /** Whether or not the cache data is valid. */
418    bool cacheDataValid[Impl::MaxThreads];
419
420    /** Size of instructions. */
421    int instSize;
422
423    /** Icache stall statistics. */
424    Counter lastIcacheStall[Impl::MaxThreads];
425
426    /** List of Active Threads */
427    std::list<unsigned> *activeThreads;
428
429    /** Number of threads. */
430    unsigned numThreads;
431
432    /** Number of threads that are actively fetching. */
433    unsigned numFetchingThreads;
434
435    /** Thread ID being fetched. */
436    int threadFetched;
437
438    /** Checks if there is an interrupt pending.  If there is, fetch
439     * must stop once it is not fetching PAL instructions.
440     */
441    bool interruptPending;
442
443    /** Is there a drain pending. */
444    bool drainPending;
445
446    /** Records if fetch is switched out. */
447    bool switchedOut;
448
449    // @todo: Consider making these vectors and tracking on a per thread basis.
450    /** Stat for total number of cycles stalled due to an icache miss. */
451    Stats::Scalar<> icacheStallCycles;
452    /** Stat for total number of fetched instructions. */
453    Stats::Scalar<> fetchedInsts;
454    /** Total number of fetched branches. */
455    Stats::Scalar<> fetchedBranches;
456    /** Stat for total number of predicted branches. */
457    Stats::Scalar<> predictedBranches;
458    /** Stat for total number of cycles spent fetching. */
459    Stats::Scalar<> fetchCycles;
460    /** Stat for total number of cycles spent squashing. */
461    Stats::Scalar<> fetchSquashCycles;
462    /** Stat for total number of cycles spent blocked due to other stages in
463     * the pipeline.
464     */
465    Stats::Scalar<> fetchIdleCycles;
466    /** Total number of cycles spent blocked. */
467    Stats::Scalar<> fetchBlockedCycles;
468    /** Total number of cycles spent in any other state. */
469    Stats::Scalar<> fetchMiscStallCycles;
470    /** Stat for total number of fetched cache lines. */
471    Stats::Scalar<> fetchedCacheLines;
472    /** Total number of outstanding icache accesses that were dropped
473     * due to a squash.
474     */
475    Stats::Scalar<> fetchIcacheSquashes;
476    /** Distribution of number of instructions fetched each cycle. */
477    Stats::Distribution<> fetchNisnDist;
478    /** Rate of how often fetch was idle. */
479    Stats::Formula idleRate;
480    /** Number of branch fetches per cycle. */
481    Stats::Formula branchRate;
482    /** Number of instruction fetched per cycle. */
483    Stats::Formula fetchRate;
484};
485
486#endif //__CPU_O3_FETCH_HH__
487