fetch.hh revision 4636:afc8da9f526e 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "base/timebuf.hh"
39#include "cpu/pc_event.hh"
40#include "mem/packet.hh"
41#include "mem/port.hh"
42#include "sim/eventq.hh"
43
44/**
45 * DefaultFetch class handles both single threaded and SMT fetch. Its
46 * width is specified by the parameters; each cycle it tries to fetch
47 * that many instructions. It supports using a branch predictor to
48 * predict direction and targets.
49 * It supports the idling functionality of the CPU by indicating to
50 * the CPU when it is active and inactive.
51 */
52template <class Impl>
53class DefaultFetch
54{
55  public:
56    /** Typedefs from Impl. */
57    typedef typename Impl::CPUPol CPUPol;
58    typedef typename Impl::DynInst DynInst;
59    typedef typename Impl::DynInstPtr DynInstPtr;
60    typedef typename Impl::O3CPU O3CPU;
61    typedef typename Impl::Params Params;
62
63    /** Typedefs from the CPU policy. */
64    typedef typename CPUPol::BPredUnit BPredUnit;
65    typedef typename CPUPol::FetchStruct FetchStruct;
66    typedef typename CPUPol::TimeStruct TimeStruct;
67
68    /** Typedefs from ISA. */
69    typedef TheISA::MachInst MachInst;
70    typedef TheISA::ExtMachInst ExtMachInst;
71
72    /** IcachePort class for DefaultFetch.  Handles doing the
73     * communication with the cache/memory.
74     */
75    class IcachePort : public Port
76    {
77      protected:
78        /** Pointer to fetch. */
79        DefaultFetch<Impl> *fetch;
80
81      public:
82        /** Default constructor. */
83        IcachePort(DefaultFetch<Impl> *_fetch)
84            : Port(_fetch->name() + "-iport"), fetch(_fetch)
85        { }
86
87        bool snoopRangeSent;
88
89        virtual void setPeer(Port *port);
90
91      protected:
92        /** Atomic version of receive.  Panics. */
93        virtual Tick recvAtomic(PacketPtr pkt);
94
95        /** Functional version of receive.  Panics. */
96        virtual void recvFunctional(PacketPtr pkt);
97
98        /** Receives status change.  Other than range changing, panics. */
99        virtual void recvStatusChange(Status status);
100
101        /** Returns the address ranges of this device. */
102        virtual void getDeviceAddressRanges(AddrRangeList &resp,
103                                            AddrRangeList &snoop)
104        { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
105
106        /** Timing version of receive.  Handles setting fetch to the
107         * proper status to start fetching. */
108        virtual bool recvTiming(PacketPtr pkt);
109
110        /** Handles doing a retry of a failed fetch. */
111        virtual void recvRetry();
112    };
113
114
115  public:
116    /** Overall fetch status. Used to determine if the CPU can
117     * deschedule itsef due to a lack of activity.
118     */
119    enum FetchStatus {
120        Active,
121        Inactive
122    };
123
124    /** Individual thread status. */
125    enum ThreadStatus {
126        Running,
127        Idle,
128        Squashing,
129        Blocked,
130        Fetching,
131        TrapPending,
132        QuiescePending,
133        SwitchOut,
134        IcacheWaitResponse,
135        IcacheWaitRetry,
136        IcacheAccessComplete
137    };
138
139    /** Fetching Policy, Add new policies here.*/
140    enum FetchPriority {
141        SingleThread,
142        RoundRobin,
143        Branch,
144        IQ,
145        LSQ
146    };
147
148  private:
149    /** Fetch status. */
150    FetchStatus _status;
151
152    /** Per-thread status. */
153    ThreadStatus fetchStatus[Impl::MaxThreads];
154
155    /** Fetch policy. */
156    FetchPriority fetchPolicy;
157
158    /** List that has the threads organized by priority. */
159    std::list<unsigned> priorityList;
160
161  public:
162    /** DefaultFetch constructor. */
163    DefaultFetch(O3CPU *_cpu, Params *params);
164
165    /** Returns the name of fetch. */
166    std::string name() const;
167
168    /** Registers statistics. */
169    void regStats();
170
171    /** Returns the icache port. */
172    Port *getIcachePort() { return icachePort; }
173
174    /** Sets the main backwards communication time buffer pointer. */
175    void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
176
177    /** Sets pointer to list of active threads. */
178    void setActiveThreads(std::list<unsigned> *at_ptr);
179
180    /** Sets pointer to time buffer used to communicate to the next stage. */
181    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
182
183    /** Initialize stage. */
184    void initStage();
185
186    /** Tells the fetch stage that the Icache is set. */
187    void setIcache();
188
189    /** Processes cache completion event. */
190    void processCacheCompletion(PacketPtr pkt);
191
192    /** Begins the drain of the fetch stage. */
193    bool drain();
194
195    /** Resumes execution after a drain. */
196    void resume();
197
198    /** Tells fetch stage to prepare to be switched out. */
199    void switchOut();
200
201    /** Takes over from another CPU's thread. */
202    void takeOverFrom();
203
204    /** Checks if the fetch stage is switched out. */
205    bool isSwitchedOut() { return switchedOut; }
206
207    /** Tells fetch to wake up from a quiesce instruction. */
208    void wakeFromQuiesce();
209
210  private:
211    /** Changes the status of this stage to active, and indicates this
212     * to the CPU.
213     */
214    inline void switchToActive();
215
216    /** Changes the status of this stage to inactive, and indicates
217     * this to the CPU.
218     */
219    inline void switchToInactive();
220
221    /**
222     * Looks up in the branch predictor to see if the next PC should be
223     * either next PC+=MachInst or a branch target.
224     * @param next_PC Next PC variable passed in by reference.  It is
225     * expected to be set to the current PC; it will be updated with what
226     * the next PC will be.
227     * @param next_NPC Used for ISAs which use delay slots.
228     * @return Whether or not a branch was predicted as taken.
229     */
230    bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC, Addr &next_MicroPC);
231
232    /**
233     * Fetches the cache line that contains fetch_PC.  Returns any
234     * fault that happened.  Puts the data into the class variable
235     * cacheData.
236     * @param fetch_PC The PC address that is being fetched from.
237     * @param ret_fault The fault reference that will be set to the result of
238     * the icache access.
239     * @param tid Thread id.
240     * @return Any fault that occured.
241     */
242    bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
243
244    /** Squashes a specific thread and resets the PC. */
245    inline void doSquash(const Addr &new_PC, const Addr &new_NPC,
246                         const Addr &new_MicroPC, unsigned tid);
247
248    /** Squashes a specific thread and resets the PC. Also tells the CPU to
249     * remove any instructions between fetch and decode that should be sqaushed.
250     */
251    void squashFromDecode(const Addr &new_PC, const Addr &new_NPC,
252                          const Addr &new_MicroPC,
253                          const InstSeqNum &seq_num, unsigned tid);
254
255    /** Checks if a thread is stalled. */
256    bool checkStall(unsigned tid) const;
257
258    /** Updates overall fetch stage status; to be called at the end of each
259     * cycle. */
260    FetchStatus updateFetchStatus();
261
262  public:
263    /** Squashes a specific thread and resets the PC. Also tells the CPU to
264     * remove any instructions that are not in the ROB. The source of this
265     * squash should be the commit stage.
266     */
267    void squash(const Addr &new_PC, const Addr &new_NPC,
268                const Addr &new_MicroPC,
269                const InstSeqNum &seq_num, unsigned tid);
270
271    /** Ticks the fetch stage, processing all inputs signals and fetching
272     * as many instructions as possible.
273     */
274    void tick();
275
276    /** Checks all input signals and updates the status as necessary.
277     *  @return: Returns if the status has changed due to input signals.
278     */
279    bool checkSignalsAndUpdate(unsigned tid);
280
281    /** Does the actual fetching of instructions and passing them on to the
282     * next stage.
283     * @param status_change fetch() sets this variable if there was a status
284     * change (ie switching to IcacheMissStall).
285     */
286    void fetch(bool &status_change);
287
288    /** Align a PC to the start of an I-cache block. */
289    Addr icacheBlockAlignPC(Addr addr)
290    {
291        addr = TheISA::realPCToFetchPC(addr);
292        return (addr & ~(cacheBlkMask));
293    }
294
295  private:
296    /** Handles retrying the fetch access. */
297    void recvRetry();
298
299    /** Returns the appropriate thread to fetch, given the fetch policy. */
300    int getFetchingThread(FetchPriority &fetch_priority);
301
302    /** Returns the appropriate thread to fetch using a round robin policy. */
303    int roundRobin();
304
305    /** Returns the appropriate thread to fetch using the IQ count policy. */
306    int iqCount();
307
308    /** Returns the appropriate thread to fetch using the LSQ count policy. */
309    int lsqCount();
310
311    /** Returns the appropriate thread to fetch using the branch count policy. */
312    int branchCount();
313
314  private:
315    /** Pointer to the O3CPU. */
316    O3CPU *cpu;
317
318    /** Time buffer interface. */
319    TimeBuffer<TimeStruct> *timeBuffer;
320
321    /** Wire to get decode's information from backwards time buffer. */
322    typename TimeBuffer<TimeStruct>::wire fromDecode;
323
324    /** Wire to get rename's information from backwards time buffer. */
325    typename TimeBuffer<TimeStruct>::wire fromRename;
326
327    /** Wire to get iew's information from backwards time buffer. */
328    typename TimeBuffer<TimeStruct>::wire fromIEW;
329
330    /** Wire to get commit's information from backwards time buffer. */
331    typename TimeBuffer<TimeStruct>::wire fromCommit;
332
333    /** Internal fetch instruction queue. */
334    TimeBuffer<FetchStruct> *fetchQueue;
335
336    //Might be annoying how this name is different than the queue.
337    /** Wire used to write any information heading to decode. */
338    typename TimeBuffer<FetchStruct>::wire toDecode;
339
340    /** Icache interface. */
341    IcachePort *icachePort;
342
343    /** BPredUnit. */
344    BPredUnit branchPred;
345
346    /** Predecoder. */
347    TheISA::Predecoder predecoder;
348
349    /** Per-thread fetch PC. */
350    Addr PC[Impl::MaxThreads];
351
352    /** Per-thread fetch micro PC. */
353    Addr microPC[Impl::MaxThreads];
354
355    /** Per-thread next PC. */
356    Addr nextPC[Impl::MaxThreads];
357
358    /** Memory request used to access cache. */
359    RequestPtr memReq[Impl::MaxThreads];
360
361    /** Variable that tracks if fetch has written to the time buffer this
362     * cycle. Used to tell CPU if there is activity this cycle.
363     */
364    bool wroteToTimeBuffer;
365
366    /** Tracks how many instructions has been fetched this cycle. */
367    int numInst;
368
369    /** Source of possible stalls. */
370    struct Stalls {
371        bool decode;
372        bool rename;
373        bool iew;
374        bool commit;
375    };
376
377    /** Tracks which stages are telling fetch to stall. */
378    Stalls stalls[Impl::MaxThreads];
379
380    /** Decode to fetch delay, in ticks. */
381    unsigned decodeToFetchDelay;
382
383    /** Rename to fetch delay, in ticks. */
384    unsigned renameToFetchDelay;
385
386    /** IEW to fetch delay, in ticks. */
387    unsigned iewToFetchDelay;
388
389    /** Commit to fetch delay, in ticks. */
390    unsigned commitToFetchDelay;
391
392    /** The width of fetch in instructions. */
393    unsigned fetchWidth;
394
395    /** Is the cache blocked?  If so no threads can access it. */
396    bool cacheBlocked;
397
398    /** The packet that is waiting to be retried. */
399    PacketPtr retryPkt;
400
401    /** The thread that is waiting on the cache to tell fetch to retry. */
402    int retryTid;
403
404    /** Cache block size. */
405    int cacheBlkSize;
406
407    /** Mask to get a cache block's address. */
408    Addr cacheBlkMask;
409
410    /** The cache line being fetched. */
411    uint8_t *cacheData[Impl::MaxThreads];
412
413    /** The PC of the cacheline that has been loaded. */
414    Addr cacheDataPC[Impl::MaxThreads];
415
416    /** Whether or not the cache data is valid. */
417    bool cacheDataValid[Impl::MaxThreads];
418
419    /** Size of instructions. */
420    int instSize;
421
422    /** Icache stall statistics. */
423    Counter lastIcacheStall[Impl::MaxThreads];
424
425    /** List of Active Threads */
426    std::list<unsigned> *activeThreads;
427
428    /** Number of threads. */
429    unsigned numThreads;
430
431    /** Number of threads that are actively fetching. */
432    unsigned numFetchingThreads;
433
434    /** Thread ID being fetched. */
435    int threadFetched;
436
437    /** Checks if there is an interrupt pending.  If there is, fetch
438     * must stop once it is not fetching PAL instructions.
439     */
440    bool interruptPending;
441
442    /** Is there a drain pending. */
443    bool drainPending;
444
445    /** Records if fetch is switched out. */
446    bool switchedOut;
447
448    // @todo: Consider making these vectors and tracking on a per thread basis.
449    /** Stat for total number of cycles stalled due to an icache miss. */
450    Stats::Scalar<> icacheStallCycles;
451    /** Stat for total number of fetched instructions. */
452    Stats::Scalar<> fetchedInsts;
453    /** Total number of fetched branches. */
454    Stats::Scalar<> fetchedBranches;
455    /** Stat for total number of predicted branches. */
456    Stats::Scalar<> predictedBranches;
457    /** Stat for total number of cycles spent fetching. */
458    Stats::Scalar<> fetchCycles;
459    /** Stat for total number of cycles spent squashing. */
460    Stats::Scalar<> fetchSquashCycles;
461    /** Stat for total number of cycles spent blocked due to other stages in
462     * the pipeline.
463     */
464    Stats::Scalar<> fetchIdleCycles;
465    /** Total number of cycles spent blocked. */
466    Stats::Scalar<> fetchBlockedCycles;
467    /** Total number of cycles spent in any other state. */
468    Stats::Scalar<> fetchMiscStallCycles;
469    /** Stat for total number of fetched cache lines. */
470    Stats::Scalar<> fetchedCacheLines;
471    /** Total number of outstanding icache accesses that were dropped
472     * due to a squash.
473     */
474    Stats::Scalar<> fetchIcacheSquashes;
475    /** Distribution of number of instructions fetched each cycle. */
476    Stats::Distribution<> fetchNisnDist;
477    /** Rate of how often fetch was idle. */
478    Stats::Formula idleRate;
479    /** Number of branch fetches per cycle. */
480    Stats::Formula branchRate;
481    /** Number of instruction fetched per cycle. */
482    Stats::Formula fetchRate;
483};
484
485#endif //__CPU_O3_FETCH_HH__
486