fetch.hh revision 3647 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38#include "cpu/pc_event.hh"
39#include "mem/packet.hh"
40#include "mem/port.hh"
41#include "sim/eventq.hh"
42
43/**
44 * DefaultFetch class handles both single threaded and SMT fetch. Its
45 * width is specified by the parameters; each cycle it tries to fetch
46 * that many instructions. It supports using a branch predictor to
47 * predict direction and targets.
48 * It supports the idling functionality of the CPU by indicating to
49 * the CPU when it is active and inactive.
50 */
51template <class Impl>
52class DefaultFetch
53{
54  public:
55    /** Typedefs from Impl. */
56    typedef typename Impl::CPUPol CPUPol;
57    typedef typename Impl::DynInst DynInst;
58    typedef typename Impl::DynInstPtr DynInstPtr;
59    typedef typename Impl::O3CPU O3CPU;
60    typedef typename Impl::Params Params;
61
62    /** Typedefs from the CPU policy. */
63    typedef typename CPUPol::BPredUnit BPredUnit;
64    typedef typename CPUPol::FetchStruct FetchStruct;
65    typedef typename CPUPol::TimeStruct TimeStruct;
66
67    /** Typedefs from ISA. */
68    typedef TheISA::MachInst MachInst;
69    typedef TheISA::ExtMachInst ExtMachInst;
70
71    /** IcachePort class for DefaultFetch.  Handles doing the
72     * communication with the cache/memory.
73     */
74    class IcachePort : public Port
75    {
76      protected:
77        /** Pointer to fetch. */
78        DefaultFetch<Impl> *fetch;
79
80      public:
81        /** Default constructor. */
82        IcachePort(DefaultFetch<Impl> *_fetch)
83            : Port(_fetch->name() + "-iport"), fetch(_fetch)
84        { }
85
86        bool snoopRangeSent;
87
88      protected:
89        /** Atomic version of receive.  Panics. */
90        virtual Tick recvAtomic(PacketPtr pkt);
91
92        /** Functional version of receive.  Panics. */
93        virtual void recvFunctional(PacketPtr pkt);
94
95        /** Receives status change.  Other than range changing, panics. */
96        virtual void recvStatusChange(Status status);
97
98        /** Returns the address ranges of this device. */
99        virtual void getDeviceAddressRanges(AddrRangeList &resp,
100                                            AddrRangeList &snoop)
101        { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,-1)); }
102
103        /** Timing version of receive.  Handles setting fetch to the
104         * proper status to start fetching. */
105        virtual bool recvTiming(PacketPtr pkt);
106
107        /** Handles doing a retry of a failed fetch. */
108        virtual void recvRetry();
109    };
110
111
112  public:
113    /** Overall fetch status. Used to determine if the CPU can
114     * deschedule itsef due to a lack of activity.
115     */
116    enum FetchStatus {
117        Active,
118        Inactive
119    };
120
121    /** Individual thread status. */
122    enum ThreadStatus {
123        Running,
124        Idle,
125        Squashing,
126        Blocked,
127        Fetching,
128        TrapPending,
129        QuiescePending,
130        SwitchOut,
131        IcacheWaitResponse,
132        IcacheWaitRetry,
133        IcacheAccessComplete
134    };
135
136    /** Fetching Policy, Add new policies here.*/
137    enum FetchPriority {
138        SingleThread,
139        RoundRobin,
140        Branch,
141        IQ,
142        LSQ
143    };
144
145  private:
146    /** Fetch status. */
147    FetchStatus _status;
148
149    /** Per-thread status. */
150    ThreadStatus fetchStatus[Impl::MaxThreads];
151
152    /** Fetch policy. */
153    FetchPriority fetchPolicy;
154
155    /** List that has the threads organized by priority. */
156    std::list<unsigned> priorityList;
157
158  public:
159    /** DefaultFetch constructor. */
160    DefaultFetch(Params *params);
161
162    /** Returns the name of fetch. */
163    std::string name() const;
164
165    /** Registers statistics. */
166    void regStats();
167
168    /** Returns the icache port. */
169    Port *getIcachePort() { return icachePort; }
170
171    /** Sets CPU pointer. */
172    void setCPU(O3CPU *cpu_ptr);
173
174    /** Sets the main backwards communication time buffer pointer. */
175    void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
176
177    /** Sets pointer to list of active threads. */
178    void setActiveThreads(std::list<unsigned> *at_ptr);
179
180    /** Sets pointer to time buffer used to communicate to the next stage. */
181    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
182
183    /** Initialize stage. */
184    void initStage();
185
186    /** Processes cache completion event. */
187    void processCacheCompletion(PacketPtr pkt);
188
189    /** Begins the drain of the fetch stage. */
190    bool drain();
191
192    /** Resumes execution after a drain. */
193    void resume();
194
195    /** Tells fetch stage to prepare to be switched out. */
196    void switchOut();
197
198    /** Takes over from another CPU's thread. */
199    void takeOverFrom();
200
201    /** Checks if the fetch stage is switched out. */
202    bool isSwitchedOut() { return switchedOut; }
203
204    /** Tells fetch to wake up from a quiesce instruction. */
205    void wakeFromQuiesce();
206
207  private:
208    /** Changes the status of this stage to active, and indicates this
209     * to the CPU.
210     */
211    inline void switchToActive();
212
213    /** Changes the status of this stage to inactive, and indicates
214     * this to the CPU.
215     */
216    inline void switchToInactive();
217
218    /**
219     * Looks up in the branch predictor to see if the next PC should be
220     * either next PC+=MachInst or a branch target.
221     * @param next_PC Next PC variable passed in by reference.  It is
222     * expected to be set to the current PC; it will be updated with what
223     * the next PC will be.
224     * @param next_NPC Used for ISAs which use delay slots.
225     * @return Whether or not a branch was predicted as taken.
226     */
227    bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC, Addr &next_NPC);
228
229    /**
230     * Fetches the cache line that contains fetch_PC.  Returns any
231     * fault that happened.  Puts the data into the class variable
232     * cacheData.
233     * @param fetch_PC The PC address that is being fetched from.
234     * @param ret_fault The fault reference that will be set to the result of
235     * the icache access.
236     * @param tid Thread id.
237     * @return Any fault that occured.
238     */
239    bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
240
241    /** Squashes a specific thread and resets the PC. */
242    inline void doSquash(const Addr &new_PC, unsigned tid);
243
244    /** Squashes a specific thread and resets the PC. Also tells the CPU to
245     * remove any instructions between fetch and decode that should be sqaushed.
246     */
247    void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
248                          unsigned tid);
249
250    /** Checks if a thread is stalled. */
251    bool checkStall(unsigned tid) const;
252
253    /** Updates overall fetch stage status; to be called at the end of each
254     * cycle. */
255    FetchStatus updateFetchStatus();
256
257  public:
258    /** Squashes a specific thread and resets the PC. Also tells the CPU to
259     * remove any instructions that are not in the ROB. The source of this
260     * squash should be the commit stage.
261     */
262    void squash(const Addr &new_PC, const InstSeqNum &seq_num,
263                bool squash_delay_slot, unsigned tid);
264
265    /** Ticks the fetch stage, processing all inputs signals and fetching
266     * as many instructions as possible.
267     */
268    void tick();
269
270    /** Checks all input signals and updates the status as necessary.
271     *  @return: Returns if the status has changed due to input signals.
272     */
273    bool checkSignalsAndUpdate(unsigned tid);
274
275    /** Does the actual fetching of instructions and passing them on to the
276     * next stage.
277     * @param status_change fetch() sets this variable if there was a status
278     * change (ie switching to IcacheMissStall).
279     */
280    void fetch(bool &status_change);
281
282    /** Align a PC to the start of an I-cache block. */
283    Addr icacheBlockAlignPC(Addr addr)
284    {
285        addr = TheISA::realPCToFetchPC(addr);
286        return (addr & ~(cacheBlkMask));
287    }
288
289  private:
290    /** Handles retrying the fetch access. */
291    void recvRetry();
292
293    /** Returns the appropriate thread to fetch, given the fetch policy. */
294    int getFetchingThread(FetchPriority &fetch_priority);
295
296    /** Returns the appropriate thread to fetch using a round robin policy. */
297    int roundRobin();
298
299    /** Returns the appropriate thread to fetch using the IQ count policy. */
300    int iqCount();
301
302    /** Returns the appropriate thread to fetch using the LSQ count policy. */
303    int lsqCount();
304
305    /** Returns the appropriate thread to fetch using the branch count policy. */
306    int branchCount();
307
308  private:
309    /** Pointer to the O3CPU. */
310    O3CPU *cpu;
311
312    /** Time buffer interface. */
313    TimeBuffer<TimeStruct> *timeBuffer;
314
315    /** Wire to get decode's information from backwards time buffer. */
316    typename TimeBuffer<TimeStruct>::wire fromDecode;
317
318    /** Wire to get rename's information from backwards time buffer. */
319    typename TimeBuffer<TimeStruct>::wire fromRename;
320
321    /** Wire to get iew's information from backwards time buffer. */
322    typename TimeBuffer<TimeStruct>::wire fromIEW;
323
324    /** Wire to get commit's information from backwards time buffer. */
325    typename TimeBuffer<TimeStruct>::wire fromCommit;
326
327    /** Internal fetch instruction queue. */
328    TimeBuffer<FetchStruct> *fetchQueue;
329
330    //Might be annoying how this name is different than the queue.
331    /** Wire used to write any information heading to decode. */
332    typename TimeBuffer<FetchStruct>::wire toDecode;
333
334    /** Icache interface. */
335    IcachePort *icachePort;
336
337    /** BPredUnit. */
338    BPredUnit branchPred;
339
340    /** Per-thread fetch PC. */
341    Addr PC[Impl::MaxThreads];
342
343    /** Per-thread next PC. */
344    Addr nextPC[Impl::MaxThreads];
345
346    /** Per-thread next Next PC.
347     *  This is not a real register but is used for
348     *  architectures that use a branch-delay slot.
349     *  (such as MIPS or Sparc)
350     */
351    Addr nextNPC[Impl::MaxThreads];
352
353    /** Memory request used to access cache. */
354    RequestPtr memReq[Impl::MaxThreads];
355
356    /** Variable that tracks if fetch has written to the time buffer this
357     * cycle. Used to tell CPU if there is activity this cycle.
358     */
359    bool wroteToTimeBuffer;
360
361    /** Tracks how many instructions has been fetched this cycle. */
362    int numInst;
363
364    /** Tracks delay slot information for threads in ISAs which use
365     *	delay slots;
366     */
367    struct DelaySlotInfo {
368        InstSeqNum delaySlotSeqNum;
369        InstSeqNum branchSeqNum;
370        int numInsts;
371        Addr targetAddr;
372        bool targetReady;
373    };
374
375    DelaySlotInfo delaySlotInfo[Impl::MaxThreads];
376
377    /** Source of possible stalls. */
378    struct Stalls {
379        bool decode;
380        bool rename;
381        bool iew;
382        bool commit;
383    };
384
385    /** Tracks which stages are telling fetch to stall. */
386    Stalls stalls[Impl::MaxThreads];
387
388    /** Decode to fetch delay, in ticks. */
389    unsigned decodeToFetchDelay;
390
391    /** Rename to fetch delay, in ticks. */
392    unsigned renameToFetchDelay;
393
394    /** IEW to fetch delay, in ticks. */
395    unsigned iewToFetchDelay;
396
397    /** Commit to fetch delay, in ticks. */
398    unsigned commitToFetchDelay;
399
400    /** The width of fetch in instructions. */
401    unsigned fetchWidth;
402
403    /** Is the cache blocked?  If so no threads can access it. */
404    bool cacheBlocked;
405
406    /** The packet that is waiting to be retried. */
407    PacketPtr retryPkt;
408
409    /** The thread that is waiting on the cache to tell fetch to retry. */
410    int retryTid;
411
412    /** Cache block size. */
413    int cacheBlkSize;
414
415    /** Mask to get a cache block's address. */
416    Addr cacheBlkMask;
417
418    /** The cache line being fetched. */
419    uint8_t *cacheData[Impl::MaxThreads];
420
421    /** The PC of the cacheline that has been loaded. */
422    Addr cacheDataPC[Impl::MaxThreads];
423
424    /** Whether or not the cache data is valid. */
425    bool cacheDataValid[Impl::MaxThreads];
426
427    /** Size of instructions. */
428    int instSize;
429
430    /** Icache stall statistics. */
431    Counter lastIcacheStall[Impl::MaxThreads];
432
433    /** List of Active Threads */
434    std::list<unsigned> *activeThreads;
435
436    /** Number of threads. */
437    unsigned numThreads;
438
439    /** Number of threads that are actively fetching. */
440    unsigned numFetchingThreads;
441
442    /** Thread ID being fetched. */
443    int threadFetched;
444
445    /** Checks if there is an interrupt pending.  If there is, fetch
446     * must stop once it is not fetching PAL instructions.
447     */
448    bool interruptPending;
449
450    /** Is there a drain pending. */
451    bool drainPending;
452
453    /** Records if fetch is switched out. */
454    bool switchedOut;
455
456    // @todo: Consider making these vectors and tracking on a per thread basis.
457    /** Stat for total number of cycles stalled due to an icache miss. */
458    Stats::Scalar<> icacheStallCycles;
459    /** Stat for total number of fetched instructions. */
460    Stats::Scalar<> fetchedInsts;
461    /** Total number of fetched branches. */
462    Stats::Scalar<> fetchedBranches;
463    /** Stat for total number of predicted branches. */
464    Stats::Scalar<> predictedBranches;
465    /** Stat for total number of cycles spent fetching. */
466    Stats::Scalar<> fetchCycles;
467    /** Stat for total number of cycles spent squashing. */
468    Stats::Scalar<> fetchSquashCycles;
469    /** Stat for total number of cycles spent blocked due to other stages in
470     * the pipeline.
471     */
472    Stats::Scalar<> fetchIdleCycles;
473    /** Total number of cycles spent blocked. */
474    Stats::Scalar<> fetchBlockedCycles;
475    /** Total number of cycles spent in any other state. */
476    Stats::Scalar<> fetchMiscStallCycles;
477    /** Stat for total number of fetched cache lines. */
478    Stats::Scalar<> fetchedCacheLines;
479    /** Total number of outstanding icache accesses that were dropped
480     * due to a squash.
481     */
482    Stats::Scalar<> fetchIcacheSquashes;
483    /** Distribution of number of instructions fetched each cycle. */
484    Stats::Distribution<> fetchNisnDist;
485    /** Rate of how often fetch was idle. */
486    Stats::Formula idleRate;
487    /** Number of branch fetches per cycle. */
488    Stats::Formula branchRate;
489    /** Number of instruction fetched per cycle. */
490    Stats::Formula fetchRate;
491};
492
493#endif //__CPU_O3_FETCH_HH__
494