fetch.hh revision 2756:7bf0d6481df9 
1/*
2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 *          Korey Sewell
30 */
31
32#ifndef __CPU_O3_FETCH_HH__
33#define __CPU_O3_FETCH_HH__
34
35#include "arch/utility.hh"
36#include "base/statistics.hh"
37#include "base/timebuf.hh"
38#include "cpu/pc_event.hh"
39#include "mem/packet.hh"
40#include "mem/port.hh"
41#include "sim/eventq.hh"
42
43class Sampler;
44
45/**
46 * DefaultFetch class handles both single threaded and SMT fetch. Its
47 * width is specified by the parameters; each cycle it tries to fetch
48 * that many instructions. It supports using a branch predictor to
49 * predict direction and targets.
50 * It supports the idling functionality of the CPU by indicating to
51 * the CPU when it is active and inactive.
52 */
53template <class Impl>
54class DefaultFetch
55{
56  public:
57    /** Typedefs from Impl. */
58    typedef typename Impl::CPUPol CPUPol;
59    typedef typename Impl::DynInst DynInst;
60    typedef typename Impl::DynInstPtr DynInstPtr;
61    typedef typename Impl::FullCPU FullCPU;
62    typedef typename Impl::Params Params;
63
64    /** Typedefs from the CPU policy. */
65    typedef typename CPUPol::BPredUnit BPredUnit;
66    typedef typename CPUPol::FetchStruct FetchStruct;
67    typedef typename CPUPol::TimeStruct TimeStruct;
68
69    /** Typedefs from ISA. */
70    typedef TheISA::MachInst MachInst;
71    typedef TheISA::ExtMachInst ExtMachInst;
72
73    /** IcachePort class for DefaultFetch.  Handles doing the
74     * communication with the cache/memory.
75     */
76    class IcachePort : public Port
77    {
78      protected:
79        /** Pointer to fetch. */
80        DefaultFetch<Impl> *fetch;
81
82      public:
83        /** Default constructor. */
84        IcachePort(DefaultFetch<Impl> *_fetch)
85            : Port(_fetch->name() + "-iport"), fetch(_fetch)
86        { }
87
88      protected:
89        /** Atomic version of receive.  Panics. */
90        virtual Tick recvAtomic(PacketPtr pkt);
91
92        /** Functional version of receive.  Panics. */
93        virtual void recvFunctional(PacketPtr pkt);
94
95        /** Receives status change.  Other than range changing, panics. */
96        virtual void recvStatusChange(Status status);
97
98        /** Returns the address ranges of this device. */
99        virtual void getDeviceAddressRanges(AddrRangeList &resp,
100                                            AddrRangeList &snoop)
101        { resp.clear(); snoop.clear(); }
102
103        /** Timing version of receive.  Handles setting fetch to the
104         * proper status to start fetching. */
105        virtual bool recvTiming(PacketPtr pkt);
106
107        /** Handles doing a retry of a failed fetch. */
108        virtual void recvRetry();
109    };
110
111  public:
112    /** Overall fetch status. Used to determine if the CPU can
113     * deschedule itsef due to a lack of activity.
114     */
115    enum FetchStatus {
116        Active,
117        Inactive
118    };
119
120    /** Individual thread status. */
121    enum ThreadStatus {
122        Running,
123        Idle,
124        Squashing,
125        Blocked,
126        Fetching,
127        TrapPending,
128        QuiescePending,
129        SwitchOut,
130        IcacheWaitResponse,
131        IcacheWaitRetry,
132        IcacheAccessComplete
133    };
134
135    /** Fetching Policy, Add new policies here.*/
136    enum FetchPriority {
137        SingleThread,
138        RoundRobin,
139        Branch,
140        IQ,
141        LSQ
142    };
143
144  private:
145    /** Fetch status. */
146    FetchStatus _status;
147
148    /** Per-thread status. */
149    ThreadStatus fetchStatus[Impl::MaxThreads];
150
151    /** Fetch policy. */
152    FetchPriority fetchPolicy;
153
154    /** List that has the threads organized by priority. */
155    std::list<unsigned> priorityList;
156
157  public:
158    /** DefaultFetch constructor. */
159    DefaultFetch(Params *params);
160
161    /** Returns the name of fetch. */
162    std::string name() const;
163
164    /** Registers statistics. */
165    void regStats();
166
167    /** Sets CPU pointer. */
168    void setCPU(FullCPU *cpu_ptr);
169
170    /** Sets the main backwards communication time buffer pointer. */
171    void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer);
172
173    /** Sets pointer to list of active threads. */
174    void setActiveThreads(std::list<unsigned> *at_ptr);
175
176    /** Sets pointer to time buffer used to communicate to the next stage. */
177    void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
178
179    /** Initialize stage. */
180    void initStage();
181
182    /** Processes cache completion event. */
183    void processCacheCompletion(PacketPtr pkt);
184
185    /** Begins the switch out of the fetch stage. */
186    void switchOut();
187
188    /** Completes the switch out of the fetch stage. */
189    void doSwitchOut();
190
191    /** Takes over from another CPU's thread. */
192    void takeOverFrom();
193
194    /** Checks if the fetch stage is switched out. */
195    bool isSwitchedOut() { return switchedOut; }
196
197    /** Tells fetch to wake up from a quiesce instruction. */
198    void wakeFromQuiesce();
199
200  private:
201    /** Changes the status of this stage to active, and indicates this
202     * to the CPU.
203     */
204    inline void switchToActive();
205
206    /** Changes the status of this stage to inactive, and indicates
207     * this to the CPU.
208     */
209    inline void switchToInactive();
210
211    /**
212     * Looks up in the branch predictor to see if the next PC should be
213     * either next PC+=MachInst or a branch target.
214     * @param next_PC Next PC variable passed in by reference.  It is
215     * expected to be set to the current PC; it will be updated with what
216     * the next PC will be.
217     * @return Whether or not a branch was predicted as taken.
218     */
219    bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC);
220
221    /**
222     * Fetches the cache line that contains fetch_PC.  Returns any
223     * fault that happened.  Puts the data into the class variable
224     * cacheData.
225     * @param fetch_PC The PC address that is being fetched from.
226     * @param ret_fault The fault reference that will be set to the result of
227     * the icache access.
228     * @param tid Thread id.
229     * @return Any fault that occured.
230     */
231    bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid);
232
233    /** Squashes a specific thread and resets the PC. */
234    inline void doSquash(const Addr &new_PC, unsigned tid);
235
236    /** Squashes a specific thread and resets the PC. Also tells the CPU to
237     * remove any instructions between fetch and decode that should be sqaushed.
238     */
239    void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num,
240                          unsigned tid);
241
242    /** Checks if a thread is stalled. */
243    bool checkStall(unsigned tid) const;
244
245    /** Updates overall fetch stage status; to be called at the end of each
246     * cycle. */
247    FetchStatus updateFetchStatus();
248
249  public:
250    /** Squashes a specific thread and resets the PC. Also tells the CPU to
251     * remove any instructions that are not in the ROB. The source of this
252     * squash should be the commit stage.
253     */
254    void squash(const Addr &new_PC, unsigned tid);
255
256    /** Ticks the fetch stage, processing all inputs signals and fetching
257     * as many instructions as possible.
258     */
259    void tick();
260
261    /** Checks all input signals and updates the status as necessary.
262     *  @return: Returns if the status has changed due to input signals.
263     */
264    bool checkSignalsAndUpdate(unsigned tid);
265
266    /** Does the actual fetching of instructions and passing them on to the
267     * next stage.
268     * @param status_change fetch() sets this variable if there was a status
269     * change (ie switching to IcacheMissStall).
270     */
271    void fetch(bool &status_change);
272
273    /** Align a PC to the start of an I-cache block. */
274    Addr icacheBlockAlignPC(Addr addr)
275    {
276        addr = TheISA::realPCToFetchPC(addr);
277        return (addr & ~(cacheBlkMask));
278    }
279
280  private:
281    /** Handles retrying the fetch access. */
282    void recvRetry();
283
284    /** Returns the appropriate thread to fetch, given the fetch policy. */
285    int getFetchingThread(FetchPriority &fetch_priority);
286
287    /** Returns the appropriate thread to fetch using a round robin policy. */
288    int roundRobin();
289
290    /** Returns the appropriate thread to fetch using the IQ count policy. */
291    int iqCount();
292
293    /** Returns the appropriate thread to fetch using the LSQ count policy. */
294    int lsqCount();
295
296    /** Returns the appropriate thread to fetch using the branch count policy. */
297    int branchCount();
298
299  private:
300    /** Pointer to the FullCPU. */
301    FullCPU *cpu;
302
303    /** Time buffer interface. */
304    TimeBuffer<TimeStruct> *timeBuffer;
305
306    /** Wire to get decode's information from backwards time buffer. */
307    typename TimeBuffer<TimeStruct>::wire fromDecode;
308
309    /** Wire to get rename's information from backwards time buffer. */
310    typename TimeBuffer<TimeStruct>::wire fromRename;
311
312    /** Wire to get iew's information from backwards time buffer. */
313    typename TimeBuffer<TimeStruct>::wire fromIEW;
314
315    /** Wire to get commit's information from backwards time buffer. */
316    typename TimeBuffer<TimeStruct>::wire fromCommit;
317
318    /** Internal fetch instruction queue. */
319    TimeBuffer<FetchStruct> *fetchQueue;
320
321    //Might be annoying how this name is different than the queue.
322    /** Wire used to write any information heading to decode. */
323    typename TimeBuffer<FetchStruct>::wire toDecode;
324
325    MemObject *mem;
326
327    /** Icache interface. */
328    IcachePort *icachePort;
329
330    /** BPredUnit. */
331    BPredUnit branchPred;
332
333    /** Per-thread fetch PC. */
334    Addr PC[Impl::MaxThreads];
335
336    /** Per-thread next PC. */
337    Addr nextPC[Impl::MaxThreads];
338
339#if THE_ISA != ALPHA_ISA
340    /** Per-thread next Next PC.
341     *  This is not a real register but is used for
342     *  architectures that use a branch-delay slot.
343     *  (such as MIPS or Sparc)
344     */
345    Addr nextNPC[Impl::MaxThreads];
346#endif
347
348    /** Memory request used to access cache. */
349    RequestPtr memReq[Impl::MaxThreads];
350
351    /** Variable that tracks if fetch has written to the time buffer this
352     * cycle. Used to tell CPU if there is activity this cycle.
353     */
354    bool wroteToTimeBuffer;
355
356    /** Tracks how many instructions has been fetched this cycle. */
357    int numInst;
358
359    /** Source of possible stalls. */
360    struct Stalls {
361        bool decode;
362        bool rename;
363        bool iew;
364        bool commit;
365    };
366
367    /** Tracks which stages are telling fetch to stall. */
368    Stalls stalls[Impl::MaxThreads];
369
370    /** Decode to fetch delay, in ticks. */
371    unsigned decodeToFetchDelay;
372
373    /** Rename to fetch delay, in ticks. */
374    unsigned renameToFetchDelay;
375
376    /** IEW to fetch delay, in ticks. */
377    unsigned iewToFetchDelay;
378
379    /** Commit to fetch delay, in ticks. */
380    unsigned commitToFetchDelay;
381
382    /** The width of fetch in instructions. */
383    unsigned fetchWidth;
384
385    /** Is the cache blocked?  If so no threads can access it. */
386    bool cacheBlocked;
387
388    /** The packet that is waiting to be retried. */
389    PacketPtr retryPkt;
390
391    /** The thread that is waiting on the cache to tell fetch to retry. */
392    int retryTid;
393
394    /** Cache block size. */
395    int cacheBlkSize;
396
397    /** Mask to get a cache block's address. */
398    Addr cacheBlkMask;
399
400    /** The cache line being fetched. */
401    uint8_t *cacheData[Impl::MaxThreads];
402
403    /** Size of instructions. */
404    int instSize;
405
406    /** Icache stall statistics. */
407    Counter lastIcacheStall[Impl::MaxThreads];
408
409    /** List of Active Threads */
410    std::list<unsigned> *activeThreads;
411
412    /** Number of threads. */
413    unsigned numThreads;
414
415    /** Number of threads that are actively fetching. */
416    unsigned numFetchingThreads;
417
418    /** Thread ID being fetched. */
419    int threadFetched;
420
421    /** Checks if there is an interrupt pending.  If there is, fetch
422     * must stop once it is not fetching PAL instructions.
423     */
424    bool interruptPending;
425
426    /** Records if fetch is switched out. */
427    bool switchedOut;
428
429    // @todo: Consider making these vectors and tracking on a per thread basis.
430    /** Stat for total number of cycles stalled due to an icache miss. */
431    Stats::Scalar<> icacheStallCycles;
432    /** Stat for total number of fetched instructions. */
433    Stats::Scalar<> fetchedInsts;
434    /** Total number of fetched branches. */
435    Stats::Scalar<> fetchedBranches;
436    /** Stat for total number of predicted branches. */
437    Stats::Scalar<> predictedBranches;
438    /** Stat for total number of cycles spent fetching. */
439    Stats::Scalar<> fetchCycles;
440    /** Stat for total number of cycles spent squashing. */
441    Stats::Scalar<> fetchSquashCycles;
442    /** Stat for total number of cycles spent blocked due to other stages in
443     * the pipeline.
444     */
445    Stats::Scalar<> fetchIdleCycles;
446    /** Total number of cycles spent blocked. */
447    Stats::Scalar<> fetchBlockedCycles;
448    /** Total number of cycles spent in any other state. */
449    Stats::Scalar<> fetchMiscStallCycles;
450    /** Stat for total number of fetched cache lines. */
451    Stats::Scalar<> fetchedCacheLines;
452    /** Total number of outstanding icache accesses that were dropped
453     * due to a squash.
454     */
455    Stats::Scalar<> fetchIcacheSquashes;
456    /** Distribution of number of instructions fetched each cycle. */
457    Stats::Distribution<> fetchNisnDist;
458    /** Rate of how often fetch was idle. */
459    Stats::Formula idleRate;
460    /** Number of branch fetches per cycle. */
461    Stats::Formula branchRate;
462    /** Number of instruction fetched per cycle. */
463    Stats::Formula fetchRate;
464};
465
466#endif //__CPU_O3_FETCH_HH__
467