fetch.hh revision 2654:9559cfa91b9d
1/* 2 * Copyright (c) 2004-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#ifndef __CPU_O3_FETCH_HH__ 30#define __CPU_O3_FETCH_HH__ 31 32#include "base/statistics.hh" 33#include "base/timebuf.hh" 34#include "cpu/pc_event.hh" 35#include "mem/mem_interface.hh" 36#include "sim/eventq.hh" 37 38class Sampler; 39 40/** 41 * DefaultFetch class handles both single threaded and SMT fetch. Its 42 * width is specified by the parameters; each cycle it tries to fetch 43 * that many instructions. It supports using a branch predictor to 44 * predict direction and targets. 45 * It supports the idling functionalitiy of the CPU by indicating to 46 * the CPU when it is active and inactive. 47 */ 48template <class Impl> 49class DefaultFetch 50{ 51 public: 52 /** Typedefs from Impl. */ 53 typedef typename Impl::CPUPol CPUPol; 54 typedef typename Impl::DynInst DynInst; 55 typedef typename Impl::DynInstPtr DynInstPtr; 56 typedef typename Impl::FullCPU FullCPU; 57 typedef typename Impl::Params Params; 58 59 /** Typedefs from the CPU policy. */ 60 typedef typename CPUPol::BPredUnit BPredUnit; 61 typedef typename CPUPol::FetchStruct FetchStruct; 62 typedef typename CPUPol::TimeStruct TimeStruct; 63 64 /** Typedefs from ISA. */ 65 typedef TheISA::MachInst MachInst; 66 typedef TheISA::ExtMachInst ExtMachInst; 67 68 public: 69 /** Overall fetch status. Used to determine if the CPU can 70 * deschedule itsef due to a lack of activity. 71 */ 72 enum FetchStatus { 73 Active, 74 Inactive 75 }; 76 77 /** Individual thread status. */ 78 enum ThreadStatus { 79 Running, 80 Idle, 81 Squashing, 82 Blocked, 83 Fetching, 84 TrapPending, 85 QuiescePending, 86 SwitchOut, 87 IcacheMissStall, 88 IcacheMissComplete 89 }; 90 91 /** Fetching Policy, Add new policies here.*/ 92 enum FetchPriority { 93 SingleThread, 94 RoundRobin, 95 Branch, 96 IQ, 97 LSQ 98 }; 99 100 private: 101 /** Fetch status. */ 102 FetchStatus _status; 103 104 /** Per-thread status. */ 105 ThreadStatus fetchStatus[Impl::MaxThreads]; 106 107 /** Fetch policy. */ 108 FetchPriority fetchPolicy; 109 110 /** List that has the threads organized by priority. */ 111 std::list<unsigned> priorityList; 112 113 public: 114 class CacheCompletionEvent : public Event 115 { 116 private: 117 MemReqPtr req; 118 /** Pointer to fetch. */ 119 DefaultFetch *fetch; 120 /** Thread id. */ 121// unsigned threadId; 122 123 public: 124 /** Constructs a cache completion event, which tells fetch when the 125 * cache miss is complete. 126 */ 127 CacheCompletionEvent(MemReqPtr &_req, DefaultFetch *_fetch); 128 129 /** Processes cache completion event. */ 130 virtual void process(); 131 /** Returns the description of the cache completion event. */ 132 virtual const char *description(); 133 }; 134 135 public: 136 /** DefaultFetch constructor. */ 137 DefaultFetch(Params *params); 138 139 /** Returns the name of fetch. */ 140 std::string name() const; 141 142 /** Registers statistics. */ 143 void regStats(); 144 145 /** Sets CPU pointer. */ 146 void setCPU(FullCPU *cpu_ptr); 147 148 /** Sets the main backwards communication time buffer pointer. */ 149 void setTimeBuffer(TimeBuffer<TimeStruct> *time_buffer); 150 151 /** Sets pointer to list of active threads. */ 152 void setActiveThreads(std::list<unsigned> *at_ptr); 153 154 /** Sets pointer to time buffer used to communicate to the next stage. */ 155 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr); 156 157 /** Sets pointer to page table. */ 158// void setPageTable(PageTable *pt_ptr); 159 160 /** Initialize stage. */ 161 void initStage(); 162 163 /** Processes cache completion event. */ 164 void processCacheCompletion(MemReqPtr &req); 165 166 void switchOut(); 167 168 void doSwitchOut(); 169 170 void takeOverFrom(); 171 172 bool isSwitchedOut() { return switchedOut; } 173 174 void wakeFromQuiesce(); 175 176 private: 177 /** Changes the status of this stage to active, and indicates this 178 * to the CPU. 179 */ 180 inline void switchToActive(); 181 182 /** Changes the status of this stage to inactive, and indicates 183 * this to the CPU. 184 */ 185 inline void switchToInactive(); 186 187 /** 188 * Looks up in the branch predictor to see if the next PC should be 189 * either next PC+=MachInst or a branch target. 190 * @param next_PC Next PC variable passed in by reference. It is 191 * expected to be set to the current PC; it will be updated with what 192 * the next PC will be. 193 * @return Whether or not a branch was predicted as taken. 194 */ 195 bool lookupAndUpdateNextPC(DynInstPtr &inst, Addr &next_PC); 196 197 /** 198 * Fetches the cache line that contains fetch_PC. Returns any 199 * fault that happened. Puts the data into the class variable 200 * cacheData. 201 * @param fetch_PC The PC address that is being fetched from. 202 * @param ret_fault The fault reference that will be set to the result of 203 * the icache access. 204 * @param tid Thread id. 205 * @return Any fault that occured. 206 */ 207 bool fetchCacheLine(Addr fetch_PC, Fault &ret_fault, unsigned tid); 208 209 /** Squashes a specific thread and resets the PC. */ 210 inline void doSquash(const Addr &new_PC, unsigned tid); 211 212 /** Squashes a specific thread and resets the PC. Also tells the CPU to 213 * remove any instructions between fetch and decode that should be sqaushed. 214 */ 215 void squashFromDecode(const Addr &new_PC, const InstSeqNum &seq_num, 216 unsigned tid); 217 218 /** Checks if a thread is stalled. */ 219 bool checkStall(unsigned tid) const; 220 221 /** Updates overall fetch stage status; to be called at the end of each 222 * cycle. */ 223 FetchStatus updateFetchStatus(); 224 225 public: 226 /** Squashes a specific thread and resets the PC. Also tells the CPU to 227 * remove any instructions that are not in the ROB. The source of this 228 * squash should be the commit stage. 229 */ 230 void squash(const Addr &new_PC, unsigned tid); 231 232 /** Ticks the fetch stage, processing all inputs signals and fetching 233 * as many instructions as possible. 234 */ 235 void tick(); 236 237 /** Checks all input signals and updates the status as necessary. 238 * @return: Returns if the status has changed due to input signals. 239 */ 240 bool checkSignalsAndUpdate(unsigned tid); 241 242 /** Does the actual fetching of instructions and passing them on to the 243 * next stage. 244 * @param status_change fetch() sets this variable if there was a status 245 * change (ie switching to IcacheMissStall). 246 */ 247 void fetch(bool &status_change); 248 249 /** Align a PC to the start of an I-cache block. */ 250 Addr icacheBlockAlignPC(Addr addr) 251 { 252 addr = TheISA::realPCToFetchPC(addr); 253 return (addr & ~(cacheBlkMask)); 254 } 255 256 private: 257 /** Returns the appropriate thread to fetch, given the fetch policy. */ 258 int getFetchingThread(FetchPriority &fetch_priority); 259 260 /** Returns the appropriate thread to fetch using a round robin policy. */ 261 int roundRobin(); 262 263 /** Returns the appropriate thread to fetch using the IQ count policy. */ 264 int iqCount(); 265 266 /** Returns the appropriate thread to fetch using the LSQ count policy. */ 267 int lsqCount(); 268 269 /** Returns the appropriate thread to fetch using the branch count policy. */ 270 int branchCount(); 271 272 private: 273 /** Pointer to the FullCPU. */ 274 FullCPU *cpu; 275 276 /** Time buffer interface. */ 277 TimeBuffer<TimeStruct> *timeBuffer; 278 279 /** Wire to get decode's information from backwards time buffer. */ 280 typename TimeBuffer<TimeStruct>::wire fromDecode; 281 282 /** Wire to get rename's information from backwards time buffer. */ 283 typename TimeBuffer<TimeStruct>::wire fromRename; 284 285 /** Wire to get iew's information from backwards time buffer. */ 286 typename TimeBuffer<TimeStruct>::wire fromIEW; 287 288 /** Wire to get commit's information from backwards time buffer. */ 289 typename TimeBuffer<TimeStruct>::wire fromCommit; 290 291 /** Internal fetch instruction queue. */ 292 TimeBuffer<FetchStruct> *fetchQueue; 293 294 //Might be annoying how this name is different than the queue. 295 /** Wire used to write any information heading to decode. */ 296 typename TimeBuffer<FetchStruct>::wire toDecode; 297 298 /** Icache interface. */ 299 MemInterface *icacheInterface; 300 301 /** BPredUnit. */ 302 BPredUnit branchPred; 303 304 Addr PC[Impl::MaxThreads]; 305 306 Addr nextPC[Impl::MaxThreads]; 307 308 /** Memory request used to access cache. */ 309 MemReqPtr memReq[Impl::MaxThreads]; 310 311 /** Variable that tracks if fetch has written to the time buffer this 312 * cycle. Used to tell CPU if there is activity this cycle. 313 */ 314 bool wroteToTimeBuffer; 315 316 /** Tracks how many instructions has been fetched this cycle. */ 317 int numInst; 318 319 /** Source of possible stalls. */ 320 struct Stalls { 321 bool decode; 322 bool rename; 323 bool iew; 324 bool commit; 325 }; 326 327 /** Tracks which stages are telling fetch to stall. */ 328 Stalls stalls[Impl::MaxThreads]; 329 330 /** Decode to fetch delay, in ticks. */ 331 unsigned decodeToFetchDelay; 332 333 /** Rename to fetch delay, in ticks. */ 334 unsigned renameToFetchDelay; 335 336 /** IEW to fetch delay, in ticks. */ 337 unsigned iewToFetchDelay; 338 339 /** Commit to fetch delay, in ticks. */ 340 unsigned commitToFetchDelay; 341 342 /** The width of fetch in instructions. */ 343 unsigned fetchWidth; 344 345 /** Cache block size. */ 346 int cacheBlkSize; 347 348 /** Mask to get a cache block's address. */ 349 Addr cacheBlkMask; 350 351 /** The cache line being fetched. */ 352 uint8_t *cacheData[Impl::MaxThreads]; 353 354 /** Size of instructions. */ 355 int instSize; 356 357 /** Icache stall statistics. */ 358 Counter lastIcacheStall[Impl::MaxThreads]; 359 360 /** List of Active Threads */ 361 std::list<unsigned> *activeThreads; 362 363 /** Number of threads. */ 364 unsigned numThreads; 365 366 /** Number of threads that are actively fetching. */ 367 unsigned numFetchingThreads; 368 369 /** Thread ID being fetched. */ 370 int threadFetched; 371 372 bool interruptPending; 373 374 bool switchedOut; 375 376#if !FULL_SYSTEM 377 /** Page table pointer. */ 378// PageTable *pTable; 379#endif 380 381 // @todo: Consider making these vectors and tracking on a per thread basis. 382 /** Stat for total number of cycles stalled due to an icache miss. */ 383 Stats::Scalar<> icacheStallCycles; 384 /** Stat for total number of fetched instructions. */ 385 Stats::Scalar<> fetchedInsts; 386 Stats::Scalar<> fetchedBranches; 387 /** Stat for total number of predicted branches. */ 388 Stats::Scalar<> predictedBranches; 389 /** Stat for total number of cycles spent fetching. */ 390 Stats::Scalar<> fetchCycles; 391 /** Stat for total number of cycles spent squashing. */ 392 Stats::Scalar<> fetchSquashCycles; 393 /** Stat for total number of cycles spent blocked due to other stages in 394 * the pipeline. 395 */ 396 Stats::Scalar<> fetchIdleCycles; 397 Stats::Scalar<> fetchBlockedCycles; 398 399 Stats::Scalar<> fetchMiscStallCycles; 400 /** Stat for total number of fetched cache lines. */ 401 Stats::Scalar<> fetchedCacheLines; 402 403 Stats::Scalar<> fetchIcacheSquashes; 404 /** Distribution of number of instructions fetched each cycle. */ 405 Stats::Distribution<> fetchNisnDist; 406 Stats::Formula idleRate; 407 Stats::Formula branchRate; 408 Stats::Formula fetchRate; 409}; 410 411#endif //__CPU_O3_FETCH_HH__ 412